1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc. 24 * All rights reserved. 25 */ 26 27#ifndef _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 28#define _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32/* 33 * hci1394_descriptors.h 34 * 1394 Open HCI command descriptors. 35 * These are DMA commands chained together to form packets. 36 */ 37 38#ifdef __cplusplus 39extern "C" { 40#endif 41 42#include <sys/note.h> 43 44/* 45 * There are 2 different 1394 Open HCI entities defined in this file. 46 * The HCI DMA descriptors (aka context descriptors or descriptor 47 * commands), and the packet formats. 48 * 49 * Packet formats are used within descriptors for transmit and 50 * are available in buffers for receive. EACH PACKET TYPE 51 * (such as read_quadlet_request) may have a different format 52 * depending on whether it is to be transmitted or whether it 53 * is being received. 54 * 55 * In general, fields within a packet remain in the same location 56 * within a quadlet either way. However, the location of the 57 * quadlets themselves may be different. 58 * 59 * In an attempt to clarify what is used for what, Macros used 60 * for setting up packets within a descriptor (an "Immediate" command) 61 * shall have "DESC" in their name. Macros used for reading packets 62 * from an input buffer shall have "PKT" in their name. 63 * 64 * For more information, see OpenHCI 1.00 chapters 7 (Asynch Transmit), 65 * 8 (Asynch Receive), 9 (Isoch Transmit) and 10 (Isoch Receive). 66 * Each chapter shows the DMA descriptors at the beginning, and 67 * the packet formats at the end. 68 * Also see chapter 11 (Self ID). 69 */ 70 71 72/* 73 * hci1394_desc is the basic format used for the following descriptor commands: 74 * OUTPUT_MORE, OUTPUT_LAST, INPUT_MORE and INPUT_LAST 75 */ 76typedef struct hci1394_desc_s { 77 uint32_t hdr; 78 uint32_t data_addr; 79 uint32_t branch; /* branch or skip address (& Z) */ 80 uint32_t status; /* status and/or (timestamp or rescount) */ 81} hci1394_desc_t; 82 83_NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_s)) 84 85/* 86 * hci1394_desc_imm is the basic format used for the "immediate" descriptor 87 * commands: OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. 88 */ 89typedef struct hci1394_desc_imm_s { 90 uint32_t hdr; 91 uint32_t data_addr; 92 uint32_t branch; 93 uint32_t status; 94 uint32_t q1; 95 uint32_t q2; 96 uint32_t q3; 97 uint32_t q4; 98} hci1394_desc_imm_t; 99 100_NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_desc_imm_s)) 101 102/* 103 * hci1394_desc_hdr contains the immediate packet header quadlets 104 * for OUTPUT_MORE_IMMEDIATE and OUTPUT_LAST_IMMEDIATE. A packet header 105 * has up to 4 quadlets of data which are specific to the individual operation 106 * and operation type (i.e. this data would be different between a quadlet read 107 * and quadlet write). 108 */ 109typedef struct hci1394_desc_hdr_s { 110 uint32_t q1; 111 uint32_t q2; 112 uint32_t q3; 113 uint32_t q4; 114} hci1394_desc_hdr_t; 115 116 117/* typedefs for each descriptor command */ 118typedef hci1394_desc_imm_t hci1394_output_more_imm_t; 119typedef hci1394_desc_t hci1394_output_more_t; 120typedef hci1394_desc_imm_t hci1394_output_last_imm_t; 121typedef hci1394_desc_t hci1394_output_last_t; 122typedef hci1394_desc_t hci1394_input_more_t; 123typedef hci1394_desc_t hci1394_input_last_t; 124 125/* 126 * maximum number of 16-byte components comprising a descriptor block. 127 * Note that "immediate" descriptors take up 32-bytes and therefore are 128 * 2 Z counts. Refer to OHCI 1.00 sections 3.1.2, 7.1.5.1, 8.3.1, 9.2.1, 129 * and table 10-2 for context specific info about Z. 130 */ 131#define HCI1394_DESC_MAX_Z 8 132 133 134/* 135 * There are two sets of defines below. The first set includes 136 * definitions for the descriptor header. Namely hdr, branch, and stat. 137 * The second set includes definitions for the different packet header 138 * formats that have to be placed in the immediate q1-q4 fields 139 * of a descriptor. 140 */ 141 142 143/* General descriptor HDR quadlet defs */ 144#define DESC_HDR_STAT_ENBL 0x08000000 /* AR, IT & IR only */ 145#define DESC_HDR_STAT_DSABL 0x00000000 /* AR, IT & IR only */ 146#define DESC_HDR_PING_ENBL 0x00800000 /* AT only */ 147#define DESC_HDR_REQCOUNT_MASK 0x0000FFFF /* IR only */ 148#define DESC_HDR_REQCOUNT_SHIFT 0 149#define DESC_HDR_STVAL_MASK 0x0000FFFF /* IT STORE only */ 150#define DESC_HDR_STVAL_SHIFT 0 151#define DESC_GET_HDR_REQCOUNT(DESCP) \ 152 (((DESCP)->hdr & DESC_HDR_REQCOUNT_MASK) >> DESC_HDR_REQCOUNT_SHIFT) 153 154/* CMD_TYPE values */ 155#define DESC_TY_OUTPUT_MORE 0x00000000 /* AT & IT */ 156#define DESC_TY_OUTPUT_LAST 0x10000000 /* AT & IT */ 157#define DESC_TY_INPUT_MORE 0x20000000 /* AR & IR */ 158#define DESC_TY_INPUT_LAST 0x30000000 /* IR only */ 159#define DESC_TY_STORE 0x80000000 /* IT only */ 160 161/* CMD_KEY values */ 162#define DESC_KEY_REF 0x00000000 /* reference ptr to data */ 163#define DESC_KEY_IMMED 0x02000000 /* immediate data */ 164#define DESC_KEY_STORE 0x06000000 /* store data */ 165 166/* CMD_BR and CMD_INT values - two bits */ 167#define DESC_INTR_DSABL 0x00000000 168#define DESC_INTR_ENBL 0x00300000 169#define DESC_BR_DSABL 0x00000000 170#define DESC_BR_ENBL 0x000C0000 171#define DESC_W_DSABL 0x00000000 172#define DESC_W_ENBL 0x00030000 173 174/* 175 * Shortcuts for AT Descriptor types. We will always interrupt upon command 176 * completion for AT OL, OLI, and IM. 177 */ 178#define DESC_AT_OM DESC_TY_OUTPUT_MORE 179#define DESC_AT_OMI (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED) 180#define DESC_AT_OL (DESC_TY_OUTPUT_LAST | DESC_INTR_ENBL | DESC_BR_ENBL) 181#define DESC_AT_OLI (DESC_AT_OL | DESC_KEY_IMMED) 182#define DESC_AR_IM (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 183 DESC_INTR_ENBL | DESC_BR_ENBL) 184 185/* 186 * descriptor BRANCH field defs 187 * Branch addresses are 16-byte aligned. the low order 4-bits are 188 * used for the Z value. 189 */ 190#define DESC_BRANCH_MASK 0xFFFFFFF0 191#define DESC_Z_MASK 0x0000000F 192 193#define HCI1394_SET_BRANCH(DESCP, ADDR, Z) ((DESCP)->branch = 0 | \ 194 ((ADDR) & DESC_BRANCH_MASK) | ((Z) & DESC_Z_MASK)) 195 196#define HCI1394_GET_BRANCH_ADDR(DESCP) ((DESCP)->branch & ~DESC_Z_MASK) 197#define HCI1394_GET_BRANCH_Z(DESCP) ((DESCP)->branch & DESC_Z_MASK) 198 199/* 200 * descriptor STATUS field defs. comprised of xfer status and either 201 * a timestamp or a residual count (rescount) 202 */ 203#define DESC_ST_XFER_STAT_MASK 0xFFFF0000 204#define DESC_ST_XFER_STAT_SHIFT 16 205#define DESC_ST_RESCOUNT_MASK 0x0000FFFF /* AR, IR only */ 206#define DESC_ST_RESCOUNT_SHIFT 0 207#define DESC_ST_TIMESTAMP_MASK 0x0000FFFF /* AT, IT only */ 208#define DESC_ST_TIMESTAMP_SHIFT 0 209 210#define HCI1394_DESC_RESCOUNT_GET(data) ((data) & DESC_ST_RESCOUNT_MASK) 211#define HCI1394_DESC_TIMESTAMP_GET(data) ((data) & DESC_ST_TIMESTAMP_MASK) 212 213/* 214 * XFER status fields are the same as the context control fields. 215 * but in the high 16 bits 216 */ 217#define DESC_XFER_RUN_MASK (OHCI_CC_RUN_MASK << DESC_ST_XFER_STAT_SHIFT) 218#define DESC_XFER_WAKE_MASK (OHCI_CC_WAKE_MASK << DESC_ST_XFER_STAT_SHIFT) 219#define DESC_XFER_DEAD_MASK (OHCI_CC_DEAD_MASK << DESC_ST_XFER_STAT_SHIFT) 220#define DESC_XFER_ACTIVE_MASK (OHCI_CC_ACTIVE_MASK << DESC_ST_XFER_STAT_SHIFT) 221 222#define DESC_AT_SPD_MASK 0x7 223#define DESC_AT_SPD_SHIFT 16 224#define DESC_AR_SPD_MASK 0x00E00000 225#define DESC_AR_SPD_SHIFT 21 226#define DESC_AR_EVT_MASK 0x001F0000 227#define DESC_AR_EVT_SHIFT 16 228 229#define HCI1394_DESC_EVT_GET(data) \ 230 (((data) & DESC_AR_EVT_MASK) >> DESC_AR_EVT_SHIFT) 231#define HCI1394_DESC_AR_SPD_GET(data) \ 232 (((data) & DESC_AR_SPD_MASK) >> DESC_AR_SPD_SHIFT) 233#define HCI1394_DESC_AT_SPD_SET(data) \ 234 (((data) & DESC_AT_SPD_MASK) << DESC_AT_SPD_SHIFT) 235 236 237/* 238 * XferStatus events are as follows 239 */ 240#define DESC_EVT_NO_STATUS 0x00 /* AT, AR, IT, IR */ 241#define DESC_EVT_LONG_PKT 0x02 /* IR */ 242#define DESC_EVT_MISSING_ACK 0x03 /* AT */ 243#define DESC_EVT_UNDERRUN 0x04 /* AT, IT */ 244#define DESC_EVT_OVERRUN 0x05 /* IR */ 245#define DESC_EVT_DESC_READ 0x06 /* AT, AR, IT, IR */ 246#define DESC_EVT_DATA_READ 0x07 /* AT, IT */ 247#define DESC_EVT_DATA_WRITE 0x08 /* AR, IR */ 248#define DESC_EVT_BUS_RESET 0x09 /* AR */ 249#define DESC_EVT_TIMEOUT 0x0A /* AT */ 250#define DESC_EVT_TCODE_ERR 0x0B /* AT, IT */ 251 252#define DESC_ACK_COMPLETE 0x11 /* AT, AR, IT, IR */ 253#define DESC_ACK_PENDING 0x12 /* AT, AR */ 254#define DESC_ACK_BUSY_X 0x14 /* AT */ 255#define DESC_ACK_BUSY_A 0x15 /* AT */ 256#define DESC_ACK_BUSY_B 0x16 /* AT */ 257#define DESC_ACK_TARDY 0x1B /* AT */ 258#define DESC_ACK_DATA_ERR 0x1D /* AT IR */ 259#define DESC_ACK_TYPE_ERR 0x1E /* AT, AR */ 260 261/* 262 * Response packet response codes 263 */ 264#define DESC_RESP_COMPLETE 0x0 265#define DESC_RESP_CONFLICT_ERR 0x4 266#define DESC_RESP_DATA_ERR 0x5 267#define DESC_RESP_TYPE_ERR 0x6 268#define DESC_RESP_ADDR_ERR 0x7 269 270 271/* 272 * Context dependent MACROs used to set up the command headers and 273 * Caller provides only the necessary variables. 274 */ 275 276/* 277 * Isochronous Transmit Descriptors 278 */ 279#define HCI1394_INIT_IT_OMORE(DESCP, REQCOUNT) ((DESCP)->hdr = 0 | \ 280 (DESC_TY_OUTPUT_MORE | DESC_KEY_REF | DESC_BR_DSABL | \ 281 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 282 283#define HCI1394_INIT_IT_OMORE_IMM(DESCP) ((DESCP)->hdr = 0 | \ 284 (DESC_TY_OUTPUT_MORE | DESC_KEY_IMMED | DESC_BR_DSABL | \ 285 (8 << DESC_HDR_REQCOUNT_SHIFT))) 286 287#define HCI1394_INIT_IT_OLAST(DESCP, STAT, INTR, REQCOUNT) ((DESCP)->hdr = 0 |\ 288 (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_REF | (INTR) | \ 289 DESC_BR_ENBL | ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT))) 290 291#define HCI1394_INIT_IT_OLAST_IMM(DESCP, STAT, INTR) ((DESCP)->hdr = 0 | \ 292 (DESC_TY_OUTPUT_LAST | (STAT) | DESC_KEY_IMMED | (INTR) | \ 293 DESC_BR_ENBL | (8 << DESC_HDR_REQCOUNT_SHIFT))) 294 295#define HCI1394_INIT_IT_STORE(DESCP, VAL) ((DESCP)->hdr = 0 | \ 296 (DESC_TY_STORE | DESC_KEY_STORE | ((VAL) << DESC_HDR_STVAL_SHIFT))) 297 298/* 299 * Isochronous Receive Descriptors 300 * PPB is Packet-Per-Buffer mode, BF is Buffer-Fill mode 301 */ 302#define HCI1394_INIT_IR_PPB_IMORE(DESCP, WAIT, REQCOUNT) (DESCP)->hdr = 0 | \ 303 (DESC_TY_INPUT_MORE | DESC_HDR_STAT_DSABL | DESC_KEY_REF | \ 304 DESC_INTR_DSABL | DESC_BR_DSABL | (WAIT) | \ 305 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 306 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 307 DESC_ST_RESCOUNT_MASK); 308 309#define HCI1394_INIT_IR_PPB_ILAST(DESCP, STAT, INTR, WAIT, REQCOUNT) \ 310 (DESCP)->hdr = 0 | (DESC_TY_INPUT_LAST | (STAT) | DESC_KEY_REF | \ 311 (INTR) | DESC_BR_ENBL | (WAIT) | \ 312 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 313 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 314 DESC_ST_RESCOUNT_MASK); 315 316#define HCI1394_INIT_IR_BF_IMORE(DESCP, INT, WAIT, REQCOUNT) \ 317 (DESCP)->hdr = 0 | (DESC_TY_INPUT_MORE | DESC_HDR_STAT_ENBL | \ 318 DESC_KEY_REF | (INT) | DESC_BR_ENBL | (WAIT) | \ 319 ((REQCOUNT) << DESC_HDR_REQCOUNT_SHIFT)); \ 320 (DESCP)->status = 0 | (((REQCOUNT) << DESC_ST_RESCOUNT_SHIFT) & \ 321 DESC_ST_RESCOUNT_MASK); 322 323/* 324 * Packet Formats 325 * 326 * HCI packet formats typically comprise 2-4 quadlets for transmit 327 * and 3-5 quadlets for receive. Although particular quadlets 328 * may be in different parts of the 1394 header, the fields within 329 * the quadlets remain in a consistent location. 330 */ 331typedef struct hci1394_basic_packet { 332 uint32_t q1; /* (HCI format) packet header w/tcode */ 333 uint32_t q2; 334 uint32_t q3; 335 uint32_t q4; 336 uint32_t q5; /* xferstatus/rescount for AR/IR */ 337} hci1394_basic_pkt_t; 338 339 340/* defs for the # of bytes are used in building the immediate descriptors */ 341/* These are used to set REQCOUNT in the HDR etc... */ 342#define DESC_FIVE_QUADS 20 343#define DESC_FOUR_QUADS 16 344#define DESC_THREE_QUADS 12 345#define DESC_TWO_QUADS 8 346#define DESC_ONE_QUAD 4 347#define DESC_ONE_OCTLET 8 348#define DESC_TWO_OCTLETS 16 349 350#define DESC_PKT_HDRLEN_AT_READQUAD DESC_THREE_QUADS 351#define DESC_PKT_HDRLEN_AT_WRITEQUAD DESC_FOUR_QUADS 352#define DESC_PKT_HDRLEN_AT_READBLOCK DESC_FOUR_QUADS 353#define DESC_PKT_HDRLEN_AT_WRITEBLOCK DESC_FOUR_QUADS 354#define DESC_PKT_HDRLEN_AT_LOCK DESC_FOUR_QUADS 355#define DESC_PKT_HDRLEN_AT_PHY DESC_THREE_QUADS 356#define DESC_PKT_HDRLEN_AT_WRITE_RESP DESC_THREE_QUADS 357#define DESC_PKT_HDRLEN_AT_READQUAD_RESP DESC_FOUR_QUADS 358#define DESC_PKT_HDRLEN_AT_READBLOCK_RESP DESC_FOUR_QUADS 359#define DESC_PKT_HDRLEN_AT_LOCK_RESP DESC_FOUR_QUADS 360#define DESC_PKT_HDRLEN_AT_STREAM DESC_TWO_QUADS 361#define DESC_PKT_HDRLEN_AT_ISOCH DESC_PKT_HDRLEN_AT_STREAM 362 363/* q1 shortcuts for ASYNC processing */ 364#define DESC_AT_SRCBUSID 0x00800000 365#define DESC_ATREQ_Q1_PHY 0x000000E0 366#define DESC_ATREQ_Q1_QWR 0x00000100 367#define DESC_ATREQ_Q1_BWR 0x00000110 368#define DESC_ATREQ_Q1_QRD 0x00000140 369#define DESC_ATREQ_Q1_BRD 0x00000150 370#define DESC_ATREQ_Q1_LCK 0x00000190 371#define DESC_ATRESP_Q1_WR 0x00000120 372#define DESC_ATRESP_Q1_QRD 0x00000160 373#define DESC_ATRESP_Q1_BRD 0x00000170 374#define DESC_ATRESP_Q1_LCK 0x000001B0 375 376/* q1 - definitions for the asynch packet first quadlet */ 377#define DESC_PKT_SRCBUSID_SHIFT 23 378#define DESC_PKT_SRCBUSID_MASK 0x00800000 379#define DESC_PKT_SPD_SHIFT 16 /* asynch and isoch */ 380#define DESC_PKT_SPD_MASK 0x00070000 381#define DESC_PKT_TLABEL_SHIFT 10 /* asynch and isoch */ 382#define DESC_PKT_TLABEL_MASK 0x0000FC00 383#define DESC_PKT_RT_SHIFT 8 384#define DESC_PKT_RT_MASK 0x00000300 385#define DESC_PKT_TCODE_SHIFT 4 /* asynch and isoch */ 386#define DESC_PKT_TCODE_MASK 0x000000F0 387#define DESC_RT_RETRYX 0x1 388 389/* q1 - definitions for the isoch first quadlet (see q1 async above for spd) */ 390#define DESC_PKT_TAG_SHIFT 14 391#define DESC_PKT_TAG_MASK 0x0000C000 392#define DESC_PKT_CHAN_SHIFT 8 393#define DESC_PKT_CHAN_MASK 0x00003F00 394#define DESC_PKT_SY_SHIFT 0 395#define DESC_PKT_SY_MASK 0x0000000F 396 397/* q2 - definitions for the asynch second quadlet */ 398#define DESC_PKT_DESTID_SHIFT 16 /* 1st quadlet for AR */ 399#define DESC_PKT_DESTID_MASK 0xFFFF0000 400#define DESC_PKT_SRCID_SHIFT 16 /* asynch recv only */ 401#define DESC_PKT_SRCID_MASK 0xFFFF0000 402#define DESC_PKT_DESTOFFHI_SHIFT 0 403#define DESC_PKT_DESTOFFHI_MASK 0x0000FFFF 404 405#define DESC_PKT_BUSID_SHIFT 22 /* in srcid or destid */ 406#define DESC_PKT_BUSID_MASK 0xFFC00000 /* in srcid or destid */ 407#define DESC_PKT_NODENUM_SHIFT 16 /* in srcid or destid */ 408#define DESC_PKT_NODENUM_MASK 0x003F0000 /* in srcid or destid */ 409#define DESC_PKT_RC_SHIFT 12 /* AT/AR read respnse */ 410#define DESC_PKT_RC_MASK 0x0000F000 /* AT/AR read respnse */ 411 412/* q3 - definitions for the asynch third quadlet */ 413#define DESC_PKT_DESTOFFLO_SHIFT 0 414#define DESC_PKT_DESTOFFLO_MASK 0xFFFFFFFF 415#define DESC_PKT_PHYGEN_SHIFT 16 416#define DESC_PKT_PHYGEN_MASK 0x00FF0000 417 418/* q4 - definitions for the fourth quadlet */ 419#define DESC_PKT_QDATA_SHIFT 0 /* at_wr_quad, at_rd_resp_quad */ 420#define DESC_PKT_QDATA_MASK 0xFFFFFFFF 421#define DESC_PKT_DATALEN_SHIFT 16 /* at_rd_blk, at_wr_blk, isoch (q2), */ 422#define DESC_PKT_DATALEN_MASK 0xFFFF0000 /* at_rd_resp_blk, at_lock_resp, */ 423 /* ar_rd_blk, ar_wr_blk, ar_lock, */ 424 /* ar_rd_resp, ar_lock_resp */ 425#define DESC_PKT_EXTTCODE_MASK 0x0000FFFF 426 427/* 428 * MACROS for getting and setting HCI packet fields 429 */ 430 431/* ASYNCHRONOUS */ 432#define HCI1394_DESC_TCODE_GET(data) \ 433 (((data) & DESC_PKT_TCODE_MASK) >> DESC_PKT_TCODE_SHIFT) 434#define HCI1394_DESC_TLABEL_GET(data) \ 435 (((data) & DESC_PKT_TLABEL_MASK) >> DESC_PKT_TLABEL_SHIFT) 436#define HCI1394_DESC_RCODE_GET(data) \ 437 (((data) & DESC_PKT_RC_MASK) >> DESC_PKT_RC_SHIFT) 438#define HCI1394_DESC_DESTID_GET(data) \ 439 (((data) & DESC_PKT_DESTID_MASK) >> DESC_PKT_DESTID_SHIFT) 440#define HCI1394_DESC_SRCID_GET(data) \ 441 (((data) & DESC_PKT_SRCID_MASK) >> DESC_PKT_SRCID_SHIFT) 442#define HCI1394_DESC_DATALEN_GET(data) \ 443 (((data) & DESC_PKT_DATALEN_MASK) >> DESC_PKT_DATALEN_SHIFT) 444#define HCI1394_DESC_EXTTCODE_GET(data) \ 445 ((data) & DESC_PKT_EXTTCODE_MASK) 446#define HCI1394_DESC_PHYGEN_GET(data) \ 447 (((data) & DESC_PKT_PHYGEN_MASK) >> DESC_PKT_PHYGEN_SHIFT) 448 449#define HCI1394_DESC_TLABEL_SET(data) \ 450 (((data) << DESC_PKT_TLABEL_SHIFT) & DESC_PKT_TLABEL_MASK) 451#define HCI1394_DESC_RCODE_SET(data) \ 452 (((data) << DESC_PKT_RC_SHIFT) & DESC_PKT_RC_MASK) 453#define HCI1394_DESC_DESTID_SET(data) \ 454 (((data) << DESC_PKT_DESTID_SHIFT) & DESC_PKT_DESTID_MASK) 455#define HCI1394_DESC_DATALEN_SET(data) \ 456 (((data) << DESC_PKT_DATALEN_SHIFT) & DESC_PKT_DATALEN_MASK) 457#define HCI1394_DESC_EXTTCODE_SET(data) \ 458 ((data) & DESC_PKT_EXTTCODE_MASK) 459 460 461/* ISOCHRONOUS */ 462/* 463 * note: the GET macros for isoch take the actual quadlet as an arg because 464 * the location of the IR header quadlet varies depending on the mode. 465 * SETs are expected to be done only for isochronous transmit. 466 */ 467#define HCI1394_GETTAG(Q) (((Q) & DESC_TAG_MASK) >> DESC_TAG_SHIFT) 468 469#define HCI1394_SETTAG(PKT, VAL) ((PKT)->q1 = (((PKT)->q1) & \ 470 ~DESC_PKT_TAG_MASK) | (((VAL) << DESC_PKT_TAG_SHIFT) & \ 471 DESC_PKT_TAG_MASK)) 472 473#define HCI1394_GETCHAN(Q) (((Q) & PKT_CHAN_MASK) >> \ 474 DESC_PKT_CHAN_SHIFT) 475 476#define HCI1394_SETCHAN(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 477 ~DESC_PKT_CHAN_MASK) | (((VAL) << DESC_PKT_CHAN_SHIFT) & \ 478 DESC_PKT_CHAN_MASK)) 479 480#define HCI1394_GETSY(Q) (((Q) & DESC_PKT_SY_MASK) >> \ 481 DESC_PKT_SY_SHIFT) 482 483#define HCI1394_SETSY(PKT, VAL) ((PKT)->q1 = ((PKT)->q1) & \ 484 ~DESC_PKT_SY_MASK) | (((VAL) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 485 486#define HCI1394_GET_ILEN(Q) (((Q) & DESC_DATALEN_MASK) >> \ 487 DESC_DATALEN_SHIFT) 488 489#define HCI1394_SET_ILEN(PKT, VAL) ((PKT)->q2 = (((PKT)->q1) & \ 490 ~DESC_PKT_DATALEN_MASK) | (((VAL) << DESC_PKT_DATALEN_SHIFT) & \ 491 DESC_PKT_DATALEN_MASK)) 492 493#define HCI1394_IT_SET_HDR_Q1(PKT, SPD, TAG, CH, TC, SY) ((PKT)->q1 = 0 | \ 494 (((SPD) << DESC_PKT_SPD_SHIFT) & DESC_PKT_SPD_MASK) | \ 495 (((TAG) << DESC_PKT_TAG_SHIFT) & DESC_PKT_TAG_MASK) | \ 496 (((CH) << DESC_PKT_CH_SHIFT) & DESC_PKT_CH_MASK) | \ 497 (((TC) << DESC_PKT_TCODE_SHIFT) & DESC_PKT_TCODE_MASK) | \ 498 (((SY) << DESC_PKT_SY_SHIFT) & DESC_PKT_SY_MASK)) 499 500/* 501 * OpenHCI Packet format sizes (header only) 502 */ 503#define DESC_SZ_AR_WRITEQUAD_REQ DESC_FIVE_QUADS 504#define DESC_SZ_AR_WRITEBLOCK_REQ DESC_FIVE_QUADS /* add data_len */ 505#define DESC_SZ_AR_WRITE_RESP DESC_FOUR_QUADS 506#define DESC_SZ_AR_READQUAD_REQ DESC_FOUR_QUADS 507#define DESC_SZ_AR_READBLOCK_REQ DESC_FIVE_QUADS 508#define DESC_SZ_AR_READQUAD_RESP DESC_FIVE_QUADS 509#define DESC_SZ_AR_READ_BLOCK_RESP DESC_FIVE_QUADS /* add data_len */ 510#define DESC_SZ_AR_PHY DESC_FOUR_QUADS 511#define DESC_SZ_AR_LOCK_REQ DESC_FIVE_QUADS /* add data_len */ 512#define DESC_SZ_AR_LOCK_RESP DESC_FIVE_QUADS /* add data_len */ 513 514#ifdef __cplusplus 515} 516#endif 517 518#endif /* _SYS_1394_ADAPTERS_HCI1394_DESCRIPTORS_H */ 519