1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright (c) 2002-2006 Neterion, Inc. 22 */ 23 24#ifndef XGE_HAL_MGMT_H 25#define XGE_HAL_MGMT_H 26 27#include "xge-os-pal.h" 28#include "xge-debug.h" 29#include "xgehal-types.h" 30#include "xgehal-config.h" 31#include "xgehal-stats.h" 32#include "xgehal-regs.h" 33#include "xgehal-device.h" 34 35__EXTERN_BEGIN_DECLS 36 37/** 38 * struct xge_hal_mgmt_about_info_t - About info. 39 * @vendor: PCI Vendor ID. 40 * @device: PCI Device ID. 41 * @subsys_vendor: PCI Subsystem Vendor ID. 42 * @subsys_device: PCI Subsystem Device ID. 43 * @board_rev: PCI Board revision, e.g. 3 - for Xena 3. 44 * @vendor_name: Neterion, Inc. 45 * @chip_name: Xframe. 46 * @media: Fiber, copper. 47 * @hal_major: HAL major version number. 48 * @hal_minor: HAL minor version number. 49 * @hal_fix: HAL fix number. 50 * @hal_build: HAL build number. 51 * @ll_major: Link-layer ULD major version number. 52 * @ll_minor: Link-layer ULD minor version number. 53 * @ll_fix: Link-layer ULD fix version number. 54 * @ll_build: Link-layer ULD build number. 55 * @transponder_temperature: TODO 56 */ 57typedef struct xge_hal_mgmt_about_info_t { 58 u16 vendor; 59 u16 device; 60 u16 subsys_vendor; 61 u16 subsys_device; 62 u8 board_rev; 63 char vendor_name[16]; 64 char chip_name[16]; 65 char media[16]; 66 char hal_major[4]; 67 char hal_minor[4]; 68 char hal_fix[4]; 69 char hal_build[16]; 70 char ll_major[4]; 71 char ll_minor[4]; 72 char ll_fix[4]; 73 char ll_build[16]; 74 u32 transponder_temperature; 75} xge_hal_mgmt_about_info_t; 76 77typedef xge_hal_stats_hw_info_t xge_hal_mgmt_hw_stats_t; 78typedef xge_hal_stats_pcim_info_t xge_hal_mgmt_pcim_stats_t; 79typedef xge_hal_stats_sw_err_t xge_hal_mgmt_sw_stats_t; 80typedef xge_hal_stats_device_info_t xge_hal_mgmt_device_stats_t; 81typedef xge_hal_stats_channel_info_t xge_hal_mgmt_channel_stats_t; 82typedef xge_hal_device_config_t xge_hal_mgmt_device_config_t; 83typedef xge_hal_driver_config_t xge_hal_mgmt_driver_config_t; 84typedef xge_hal_pci_config_t xge_hal_mgmt_pci_config_t; 85 86xge_hal_status_e 87xge_hal_mgmt_about(xge_hal_device_h devh, xge_hal_mgmt_about_info_t *about_info, 88 int size); 89 90xge_hal_status_e 91xge_hal_mgmt_hw_stats(xge_hal_device_h devh, xge_hal_mgmt_hw_stats_t *hw_stats, 92 int size); 93 94xge_hal_status_e 95xge_hal_mgmt_hw_stats_off(xge_hal_device_h devh, int off, int size, char *out); 96 97xge_hal_status_e 98xge_hal_mgmt_pcim_stats(xge_hal_device_h devh, 99 xge_hal_mgmt_pcim_stats_t *pcim_stats, int size); 100 101xge_hal_status_e 102xge_hal_mgmt_pcim_stats_off(xge_hal_device_h devh, int off, int size, 103 char *out); 104 105xge_hal_status_e 106xge_hal_mgmt_sw_stats(xge_hal_device_h devh, xge_hal_mgmt_sw_stats_t *hw_stats, 107 int size); 108 109xge_hal_status_e 110xge_hal_mgmt_device_stats(xge_hal_device_h devh, 111 xge_hal_mgmt_device_stats_t *device_stats, int size); 112 113xge_hal_status_e 114xge_hal_mgmt_channel_stats(xge_hal_channel_h channelh, 115 xge_hal_mgmt_channel_stats_t *channel_stats, int size); 116 117xge_hal_status_e 118xge_hal_mgmt_reg_read(xge_hal_device_h devh, int bar_id, unsigned int offset, 119 u64 *value); 120 121xge_hal_status_e 122xge_hal_mgmt_reg_write(xge_hal_device_h devh, int bar_id, unsigned int offset, 123 u64 value); 124 125xge_hal_status_e 126xge_hal_mgmt_pcireg_read(xge_hal_device_h devh, unsigned int offset, 127 int bits, u32 *value); 128 129xge_hal_status_e 130xge_hal_mgmt_device_config(xge_hal_device_h devh, 131 xge_hal_mgmt_device_config_t *dev_config, int size); 132 133xge_hal_status_e 134xge_hal_mgmt_driver_config(xge_hal_mgmt_driver_config_t *drv_config, 135 int size); 136 137xge_hal_status_e 138xge_hal_mgmt_pci_config(xge_hal_device_h devh, 139 xge_hal_mgmt_pci_config_t *pci_config, int size); 140 141xge_hal_status_e 142xge_hal_pma_loopback( xge_hal_device_h devh, int enable ); 143 144xge_hal_status_e 145xge_hal_rldram_test(xge_hal_device_h devh, u64 * data); 146 147u16 148xge_hal_mdio_read( xge_hal_device_h devh, u32 mmd_type, u64 addr ); 149 150xge_hal_status_e 151xge_hal_mdio_write( xge_hal_device_h devh, u32 mmd_type, u64 addr, u32 value ); 152 153u32 154xge_hal_read_xfp_current_temp(xge_hal_device_h devh); 155 156xge_hal_status_e 157xge_hal_read_eeprom(xge_hal_device_h devh, int off, u32* data); 158 159xge_hal_status_e 160xge_hal_write_eeprom(xge_hal_device_h devh, int off, u32 data, int cnt); 161 162xge_hal_status_e 163xge_hal_register_test(xge_hal_device_h devh, u64 *data); 164 165xge_hal_status_e 166xge_hal_eeprom_test(xge_hal_device_h devh, u64 *data); 167 168xge_hal_status_e 169xge_hal_bist_test(xge_hal_device_h devh, u64 *data); 170 171xge_hal_status_e 172xge_hal_link_test(xge_hal_device_h devh, u64 *data); 173 174int 175xge_hal_setpause_data(xge_hal_device_h devh, int tx, int rx); 176 177void 178xge_hal_getpause_data(xge_hal_device_h devh, int *tx, int *rx); 179 180void 181__hal_updt_stats_xpak(xge_hal_device_t *hldev); 182 183void 184__hal_chk_xpak_counter(xge_hal_device_t *hldev, int type, u32 value); 185 186#ifdef XGE_TRACE_INTO_CIRCULAR_ARR 187xge_hal_status_e 188xge_hal_mgmt_trace_read(char *buffer, unsigned buf_size, unsigned *offset, 189 unsigned *read_length); 190#endif 191 192void 193xge_hal_restore_link_led(xge_hal_device_h devh); 194 195 196void 197xge_hal_flick_link_led(xge_hal_device_h devh); 198 199/* 200 * Some set of Xena3 Cards were known to have some link LED 201 * Problems. This macro identifies if the card is among them 202 * given its Sub system ID. 203 */ 204#define CARDS_WITH_FAULTY_LINK_INDICATORS(subid) \ 205 ((((subid >= 0x600B) && (subid <= 0x600D)) || \ 206 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) 207#define CHECKBIT(value, nbit) (value & (1 << nbit)) 208 209#ifdef XGE_HAL_USE_MGMT_AUX 210#include "xgehal-mgmtaux.h" 211#endif 212 213__EXTERN_END_DECLS 214 215#endif /* XGE_HAL_MGMT_H */ 216