1/* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6/* 7 * Copyright (c) 2006 8 * Damien Bergamini <damien.bergamini@free.fr> 9 * Copyright (c) 2006 Sam Leffler, Errno Consulting 10 * 11 * Permission to use, copy, modify, and distribute this software for any 12 * purpose with or without fee is hereby granted, provided that the above 13 * copyright notice and this permission notice appear in all copies. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 22 */ 23 24 25#ifndef _UATH_REG_H 26#define _UATH_REG_H 27 28#ifdef __cplusplus 29extern "C" { 30#endif 31 32/* Location in the endpoint descriptor tree used by the device */ 33#define UATH_CONFIG_NO 1 34#define UATH_IFACE_INDEX 0 35#define UATH_ALT_IF_INDEX 0 36 37/* all fields are big endian */ 38#pragma pack(1) 39struct uath_fwblock { 40 uint32_t flags; 41#define UATH_WRITE_BLOCK (1 << 4) 42 uint32_t len; 43#define UATH_MAX_FWBLOCK_SIZE 2048 44 uint32_t total; 45 uint32_t remain; 46 uint32_t rxtotal; 47 uint32_t pad[123]; 48}; 49#pragma pack() 50 51#define UATH_MAX_CMDSZ 512 52 53/* 54 * Messages are passed in Target Endianness. All fixed-size 55 * fields of a WDS Control Message are treated as 32-bit 56 * values and Control Msgs are guaranteed to be 32-bit aligned. 57 * 58 * The format of a WDS Control Message is as follows: 59 * Message Length 32 bits 60 * Message Opcode 32 bits 61 * Message ID 32 bits 62 * parameter 1 63 * parameter 2 64 * ... 65 * 66 * A variable-length parameter, or a parmeter that is larger than 67 * 32 bits is passed as <length, data> pair, where length is a 68 * 32-bit quantity and data is padded to 32 bits. 69 */ 70#pragma pack(1) 71struct uath_cmd_hdr { 72 uint32_t len; /* msg length including header */ 73 uint32_t code; /* operation code */ 74/* NB: these are defined for rev 1.5 firmware; rev 1.6 is different */ 75/* messages from Host -> Target */ 76#define WDCMSG_HOST_AVAILABLE 0x01 77#define WDCMSG_BIND 0x02 78#define WDCMSG_TARGET_RESET 0x03 79#define WDCMSG_TARGET_GET_CAPABILITY 0x04 80#define WDCMSG_TARGET_SET_CONFIG 0x05 81#define WDCMSG_TARGET_GET_STATUS 0x06 82#define WDCMSG_TARGET_GET_STATS 0x07 83#define WDCMSG_TARGET_START 0x08 84#define WDCMSG_TARGET_STOP 0x09 85#define WDCMSG_TARGET_ENABLE 0x0a 86#define WDCMSG_TARGET_DISABLE 0x0b 87#define WDCMSG_CREATE_CONNECTION 0x0c 88#define WDCMSG_UPDATE_CONNECT_ATTR 0x0d 89#define WDCMSG_DELETE_CONNECT 0x0e 90#define WDCMSG_SEND 0x0f 91#define WDCMSG_FLUSH 0x10 92/* messages from Target -> Host */ 93#define WDCMSG_STATS_UPDATE 0x11 94#define WDCMSG_BMISS 0x12 95#define WDCMSG_DEVICE_AVAIL 0x13 96#define WDCMSG_SEND_COMPLETE 0x14 97#define WDCMSG_DATA_AVAIL 0x15 98#define WDCMSG_SET_PWR_MODE 0x16 99#define WDCMSG_BMISS_ACK 0x17 100#define WDCMSG_SET_LED_STEADY 0x18 101#define WDCMSG_SET_LED_BLINK 0x19 102/* more messages */ 103#define WDCMSG_SETUP_BEACON_DESC 0x1a 104#define WDCMSG_BEACON_INIT 0x1b 105#define WDCMSG_RESET_KEY_CACHE 0x1c 106#define WDCMSG_RESET_KEY_CACHE_ENTRY 0x1d 107#define WDCMSG_SET_KEY_CACHE_ENTRY 0x1e 108#define WDCMSG_SET_DECOMP_MASK 0x1f 109#define WDCMSG_SET_REGULATORY_DOMAIN 0x20 110#define WDCMSG_SET_LED_STATE 0x21 111#define WDCMSG_WRITE_ASSOCID 0x22 112#define WDCMSG_SET_STA_BEACON_TIMERS 0x23 113#define WDCMSG_GET_TSF 0x24 114#define WDCMSG_RESET_TSF 0x25 115#define WDCMSG_SET_ADHOC_MODE 0x26 116#define WDCMSG_SET_BASIC_RATE 0x27 117#define WDCMSG_MIB_CONTROL 0x28 118#define WDCMSG_GET_CHANNEL_DATA 0x29 119#define WDCMSG_GET_CUR_RSSI 0x2a 120#define WDCMSG_SET_ANTENNA_SWITCH 0x2b 121#define WDCMSG_USE_SHORT_SLOT_TIME 0x2f 122#define WDCMSG_SET_POWER_MODE 0x30 123#define WDCMSG_SETUP_PSPOLL_DESC 0x31 124#define WDCMSG_SET_RX_MULTICAST_FILTER 0x32 125#define WDCMSG_RX_FILTER 0x33 126#define WDCMSG_PER_CALIBRATION 0x34 127#define WDCMSG_RESET 0x35 128#define WDCMSG_DISABLE 0x36 129#define WDCMSG_PHY_DISABLE 0x37 130#define WDCMSG_SET_TX_POWER_LIMIT 0x38 131#define WDCMSG_SET_TX_QUEUE_PARAMS 0x39 132#define WDCMSG_SETUP_TX_QUEUE 0x3a 133#define WDCMSG_RELEASE_TX_QUEUE 0x3b 134#define WDCMSG_SET_DEFAULT_KEY 0x43 135 uint32_t msgid; /* msg id (supplied by host) */ 136 uint32_t magic; /* response desired/target status */ 137 uint32_t debug[4]; /* debug data area */ 138 /* msg data follows */ 139}; 140#pragma pack() 141 142#define UATH_RX_DUMMYSIZE 4 143 144#pragma pack(1) 145struct uath_chunk { 146 uint8_t seqnum; /* sequence number for ordering */ 147 uint8_t flags; 148#define UATH_CFLAGS_FINAL 0x01 /* final chunk of a msg */ 149#define UATH_CFLAGS_RXMSG 0x02 /* chunk contains rx completion */ 150#define UATH_CFLAGS_DEBUG 0x04 /* for debugging */ 151 uint16_t length; /* chunk size in bytes */ 152 /* chunk data follows */ 153}; 154#pragma pack() 155 156/* 157 * Message format for a WDCMSG_DATA_AVAIL message from Target to Host. 158 */ 159#pragma pack(1) 160struct uath_rx_desc { 161 uint32_t len; /* msg length including header */ 162 uint32_t code; /* WDCMSG_DATA_AVAIL */ 163 uint32_t gennum; /* generation number */ 164 uint32_t status; /* start of RECEIVE_INFO */ 165#define UATH_STATUS_OK 0 166#define UATH_STATUS_STOP_IN_PROGRESS 1 167#define UATH_STATUS_CRC_ERR 2 168#define UATH_STATUS_PHY_ERR 3 169#define UATH_STATUS_DECRYPT_CRC_ERR 4 170#define UATH_STATUS_DECRYPT_MIC_ERR 5 171#define UATH_STATUS_DECOMP_ERR 6 172#define UATH_STATUS_KEY_ERR 7 173#define UATH_STATUS_ERR 8 174 uint32_t tstamp_low; /* low-order 32-bits of rx timestamp */ 175 uint32_t tstamp_high; /* high-order 32-bits of rx timestamp */ 176 uint32_t framelen; /* frame length */ 177 uint32_t rate; /* rx rate code */ 178 uint32_t antenna; 179 int32_t rssi; 180 uint32_t channel; 181 uint32_t phyerror; 182 uint32_t connix; /* key table ix for bss traffic */ 183 uint32_t decrypterror; 184 uint32_t keycachemiss; 185 uint32_t pad; /* XXX? */ 186}; 187#pragma pack() 188 189#pragma pack(1) 190struct uath_tx_desc { 191 uint32_t msglen; 192 uint32_t msgid; /* msg id (supplied by host) */ 193 uint32_t type; /* opcode: WDMSG_SEND or WDCMSG_FLUSH */ 194 uint32_t txqid; /* tx queue id and flags */ 195#define UATH_TXQID_MASK 0x0f 196#define UATH_TXQID_MINRATE 0x10 /* use min tx rate */ 197#define UATH_TXQID_FF 0x20 /* content is fast frame */ 198 uint32_t connid; /* tx connection id */ 199#define UATH_ID_INVALID 0xffffffff /* for sending prior to connection */ 200 uint32_t flags; /* non-zero if response desired */ 201#define UATH_TX_NOTIFY (1 << 24) /* f/w will send a UATH_NOTIF_TX */ 202 uint32_t buflen; /* payload length */ 203}; 204#pragma pack() 205 206#pragma pack(1) 207struct uath_cmd_host_available { 208 uint32_t sw_ver_major; 209 uint32_t sw_ver_minor; 210 uint32_t sw_ver_patch; 211 uint32_t sw_ver_build; 212}; 213#pragma pack() 214 215#define ATH_SW_VER_MAJOR 1 216#define ATH_SW_VER_MINOR 5 217#define ATH_SW_VER_PATCH 0 218#define ATH_SW_VER_BUILD 9999 219 220 221/* structure for command UATH_CMD_WRITE_MAC */ 222#pragma pack(1) 223struct uath_write_mac { 224 uint32_t reg; 225 uint32_t len; 226 uint8_t data[32]; 227}; 228#pragma pack() 229 230#pragma pack(1) 231struct uath_cmd_ledsteady { /* WDCMSG_SET_LED_STEADY */ 232 uint32_t lednum; 233#define UATH_LED_LINK 0 234#define UATH_LED_ACTIVITY 1 235 uint32_t ledmode; 236#define UATH_LED_OFF 0 237#define UATH_LED_ON 1 238}; 239#pragma pack() 240 241#pragma pack(1) 242struct uath_cmd_ledblink { /* WDCMSG_SET_LED_BLINK */ 243 uint32_t lednum; 244 uint32_t ledmode; 245 uint32_t blinkrate; 246 uint32_t slowmode; 247}; 248#pragma pack() 249 250/* structure for command WDCMSG_RESET */ 251#pragma pack(1) 252struct uath_cmd_reset { 253 uint32_t flags; /* channel flags */ 254#define UATH_CHAN_TURBO 0x0100 255#define UATH_CHAN_CCK 0x0200 256#define UATH_CHAN_OFDM 0x0400 257#define UATH_CHAN_2GHZ 0x1000 258#define UATH_CHAN_5GHZ 0x2000 259 uint32_t freq; /* channel frequency */ 260 uint32_t maxrdpower; 261 uint32_t cfgctl; 262 uint32_t twiceantennareduction; 263 uint32_t channelchange; 264 uint32_t keeprccontent; 265}; 266#pragma pack() 267 268#pragma pack(1) 269struct uath_cmd_rateset { 270 uint8_t length; 271#define UATH_MAX_NRATES 32 272 uint8_t set[UATH_MAX_NRATES]; 273}; 274#pragma pack() 275 276#pragma pack(1) 277/* structure for command WDCMSG_SET_BASIC_RATE */ 278struct uath_cmd_rates { 279 uint32_t connid; 280 uint32_t keeprccontent; 281 uint32_t size; 282 struct uath_cmd_rateset rateset; 283}; 284#pragma pack() 285 286enum { 287 WLAN_MODE_NONE = 0, 288 WLAN_MODE_11b, 289 WLAN_MODE_11a, 290 WLAN_MODE_11g, 291 WLAN_MODE_11a_TURBO, 292 WLAN_MODE_11g_TURBO, 293 WLAN_MODE_11a_TURBO_PRIME, 294 WLAN_MODE_11g_TURBO_PRIME, 295 WLAN_MODE_11a_XR, 296 WLAN_MODE_11g_XR, 297}; 298 299#pragma pack(1) 300struct uath_cmd_connection_attr { 301 uint32_t longpreambleonly; 302 struct uath_cmd_rateset rateset; 303 uint32_t wlanmode; 304}; 305#pragma pack() 306 307#pragma pack(1) 308/* structure for command WDCMSG_CREATE_CONNECTION */ 309struct uath_cmd_create_connection { 310 uint32_t connid; 311 uint32_t bssid; 312 uint32_t size; 313 struct uath_cmd_connection_attr connattr; 314}; 315#pragma pack() 316 317#pragma pack(1) 318struct uath_cmd_txq_attr { 319 uint32_t priority; 320 uint32_t aifs; 321 uint32_t logcwmin; 322 uint32_t logcwmax; 323 uint32_t bursttime; 324 uint32_t mode; 325 uint32_t qflags; 326}; 327#pragma pack() 328 329#pragma pack(1) 330struct uath_cmd_txq_setup { /* WDCMSG_SETUP_TX_QUEUE */ 331 uint32_t qid; 332 uint32_t len; 333 struct uath_cmd_txq_attr attr; 334}; 335#pragma pack() 336 337#pragma pack(1) 338struct uath_cmd_rx_filter { /* WDCMSG_RX_FILTER */ 339 uint32_t bits; 340#define UATH_FILTER_RX_UCAST 0x00000001 341#define UATH_FILTER_RX_MCAST 0x00000002 342#define UATH_FILTER_RX_BCAST 0x00000004 343#define UATH_FILTER_RX_CONTROL 0x00000008 344#define UATH_FILTER_RX_BEACON 0x00000010 /* beacon frames */ 345#define UATH_FILTER_RX_PROM 0x00000020 /* promiscuous mode */ 346#define UATH_FILTER_RX_PHY_ERR 0x00000040 /* phy errors */ 347#define UATH_FILTER_RX_PHY_RADAR 0x00000080 /* radar phy errors */ 348#define UATH_FILTER_RX_XR_POOL 0x00000400 /* XR group polls */ 349#define UATH_FILTER_RX_PROBE_REQ 0x00000800 350 uint32_t op; 351#define UATH_FILTER_OP_INIT 0x0 352#define UATH_FILTER_OP_SET 0x1 353#define UATH_FILTER_OP_CLEAR 0x2 354#define UATH_FILTER_OP_TEMP 0x3 355#define UATH_FILTER_OP_RESTORE 0x4 356}; 357#pragma pack() 358 359#pragma pack(1) 360struct uath_cmd_set_associd { /* WDCMSG_WRITE_ASSOCID */ 361 uint32_t defaultrateix; 362 uint32_t associd; 363 uint32_t timoffset; 364 uint32_t turboprime; 365 uint32_t bssid[2]; 366}; 367#pragma pack() 368 369enum { 370 CFG_NONE, /* Sentinal to indicate "no config" */ 371 CFG_REG_DOMAIN, /* Regulatory Domain */ 372 CFG_RATE_CONTROL_ENABLE, 373 CFG_DEF_XMIT_DATA_RATE, /* NB: if rate control is not enabled */ 374 CFG_HW_TX_RETRIES, 375 CFG_SW_TX_RETRIES, 376 CFG_SLOW_CLOCK_ENABLE, 377 CFG_COMP_PROC, 378 CFG_USER_RTS_THRESHOLD, 379 CFG_XR2NORM_RATE_THRESHOLD, 380 CFG_XRMODE_SWITCH_COUNT, 381 CFG_PROTECTION_TYPE, 382 CFG_BURST_SEQ_THRESHOLD, 383 CFG_ABOLT, 384 CFG_IQ_LOG_COUNT_MAX, 385 CFG_MODE_CTS, 386 CFG_WME_ENABLED, 387 CFG_GPRS_CBR_PERIOD, 388 CFG_SERVICE_TYPE, 389 /* MAC Address to use. Overrides EEPROM */ 390 CFG_MAC_ADDR, 391 CFG_DEBUG_EAR, 392 CFG_INIT_REGS, 393 /* An ID for use in error & debug messages */ 394 CFG_DEBUG_ID, 395 CFG_COMP_WIN_SZ, 396 CFG_DIVERSITY_CTL, 397 CFG_TP_SCALE, 398 CFG_TPC_HALF_DBM5, 399 CFG_TPC_HALF_DBM2, 400 CFG_OVERRD_TX_POWER, 401 CFG_USE_32KHZ_CLOCK, 402 CFG_GMODE_PROTECTION, 403 CFG_GMODE_PROTECT_RATE_INDEX, 404 CFG_GMODE_NON_ERP_PREAMBLE, 405 CFG_WDC_TRANSPORT_CHUNK_SIZE, 406}; 407 408enum { 409 /* Sentinal to indicate "no capability" */ 410 CAP_NONE, 411 CAP_ALL, /* ALL capabilities */ 412 CAP_TARGET_VERSION, 413 CAP_TARGET_REVISION, 414 CAP_MAC_VERSION, 415 CAP_MAC_REVISION, 416 CAP_PHY_REVISION, 417 CAP_ANALOG_5GHz_REVISION, 418 CAP_ANALOG_2GHz_REVISION, 419 /* Target supports WDC message debug features */ 420 CAP_DEBUG_WDCMSG_SUPPORT, 421 422 CAP_REG_DOMAIN, 423 CAP_COUNTRY_CODE, 424 CAP_REG_CAP_BITS, 425 426 CAP_WIRELESS_MODES, 427 CAP_CHAN_SPREAD_SUPPORT, 428 CAP_SLEEP_AFTER_BEACON_BROKEN, 429 CAP_COMPRESS_SUPPORT, 430 CAP_BURST_SUPPORT, 431 CAP_FAST_FRAMES_SUPPORT, 432 CAP_CHAP_TUNING_SUPPORT, 433 CAP_TURBOG_SUPPORT, 434 CAP_TURBO_PRIME_SUPPORT, 435 CAP_DEVICE_TYPE, 436 CAP_XR_SUPPORT, 437 CAP_WME_SUPPORT, 438 CAP_TOTAL_QUEUES, 439 CAP_CONNECTION_ID_MAX, /* Should absorb CAP_KEY_CACHE_SIZE */ 440 441 CAP_LOW_5GHZ_CHAN, 442 CAP_HIGH_5GHZ_CHAN, 443 CAP_LOW_2GHZ_CHAN, 444 CAP_HIGH_2GHZ_CHAN, 445 446 CAP_MIC_AES_CCM, 447 CAP_MIC_CKIP, 448 CAP_MIC_TKIP, 449 CAP_MIC_TKIP_WME, 450 CAP_CIPHER_AES_CCM, 451 CAP_CIPHER_CKIP, 452 CAP_CIPHER_TKIP, 453 454 CAP_TWICE_ANTENNAGAIN_5G, 455 CAP_TWICE_ANTENNAGAIN_2G, 456}; 457 458enum { 459 ST_NONE, /* Sentinal to indicate "no status" */ 460 ST_ALL, 461 ST_SERVICE_TYPE, 462 ST_WLAN_MODE, 463 ST_FREQ, 464 ST_BAND, 465 ST_LAST_RSSI, 466 ST_PS_FRAMES_DROPPED, 467 ST_CACHED_DEF_ANT, 468 ST_COUNT_OTHER_RX_ANT, 469 ST_USE_FAST_DIVERSITY, 470 ST_MAC_ADDR, 471 ST_RX_GENERATION_NUM, 472 ST_TX_QUEUE_DEPTH, 473 ST_SERIAL_NUMBER, 474 ST_WDC_TRANSPORT_CHUNK_SIZE, 475}; 476 477enum { 478 TARGET_DEVICE_AWAKE, 479 TARGET_DEVICE_SLEEP, 480 TARGET_DEVICE_PWRDN, 481 TARGET_DEVICE_PWRSAVE, 482 TARGET_DEVICE_SUSPEND, 483 TARGET_DEVICE_RESUME, 484}; 485 486#define UATH_MAX_TXBUFSZ \ 487 (sizeof (struct uath_chunk) + sizeof (struct uath_tx_desc) + \ 488 IEEE80211_MAX_LEN) 489 490/* 491 * it's not easy to measure how the chunk is passed into the host if the target 492 * passed the multi-chunks so just we check a minimal size we can imagine. 493 */ 494#define UATH_MIN_RXBUFSZ (sizeof (struct uath_chunk)) 495 496#define USB_VENDOR_ACCTON 0x083a /* Accton Technology */ 497#define USB_VENDOR_ATHEROS 0x168c /* Atheros Communications */ 498#define USB_VENDOR_ATHEROS2 0x0cf3 /* Atheros Communications */ 499#define USB_VENDOR_CONCEPTRONIC 0x0d8e /* Conceptronic */ 500#define USB_VENDOR_DLINK 0x2001 /* D-Link */ 501#define USB_VENDOR_GIGASET 0x1690 /* Gigaset */ 502#define USB_VENDOR_GLOBALSUN 0x16ab /* Global Sun Technology */ 503#define USB_VENDOR_IODATA 0x04bb /* I/O Data */ 504#define USB_VENDOR_MELCO 0x0411 /* Melco */ 505#define USB_VENDOR_NETGEAR 0x0846 /* BayNETGEAR */ 506#define USB_VENDOR_NETGEAR3 0x1385 /* Netgear */ 507#define USB_VENDOR_PHILIPS 0x0471 /* Philips */ 508#define USB_VENDOR_UMEDIA 0x157e /* U-MEDIA Communications */ 509#define USB_VENDOR_WISTRONNEWEB 0x1435 /* Wistron NeWeb */ 510#define USB_VENDOR_ZCOM 0x0cde /* Z-Com */ 511 512#define USB_PRODUCT_ACCTON_SMCWUSBTG2 0x4506 /* SMCWUSBT-G2 */ 513#define USB_PRODUCT_ACCTON_SMCWUSBTG2_NF 0x4507 /* SMCWUSBT-G2 */ 514#define USB_PRODUCT_ATHEROS_AR5523 0x0001 /* AR5523 */ 515#define USB_PRODUCT_ATHEROS_AR5523_NF 0x0002 /* AR5523 */ 516#define USB_PRODUCT_ATHEROS2_AR5523_1 0x0003 /* AR5523 */ 517#define USB_PRODUCT_ATHEROS2_AR5523_1_NF 0x0002 /* AR5523 */ 518#define USB_PRODUCT_ATHEROS2_AR5523_2 0x0005 /* AR5523 */ 519#define USB_PRODUCT_ATHEROS2_AR5523_2_NF 0x0004 /* AR5523 */ 520#define USB_PRODUCT_ATHEROS2_AR5523_3 0x0007 /* AR5523 */ 521#define USB_PRODUCT_ATHEROS2_AR5523_3_NF 0x0006 /* AR5523 */ 522#define USB_PRODUCT_CONCEPTRONIC_AR5523_1 0x7801 /* AR5523 */ 523#define USB_PRODUCT_CONCEPTRONIC_AR5523_1_NF 0x7802 /* AR5523 */ 524#define USB_PRODUCT_CONCEPTRONIC_AR5523_2 0x7811 /* AR5523 */ 525#define USB_PRODUCT_CONCEPTRONIC_AR5523_2_NF 0x7812 /* AR5523 */ 526#define USB_PRODUCT_DLINK_DWLAG122 0x3a04 /* DWL-AG122 */ 527#define USB_PRODUCT_DLINK_DWLAG122_NF 0x3a05 /* DWL-AG122 */ 528#define USB_PRODUCT_DLINK_DWLAG132 0x3a00 /* DWL-AG132 */ 529#define USB_PRODUCT_DLINK_DWLAG132_NF 0x3a01 /* DWL-AG132 */ 530#define USB_PRODUCT_DLINK_DWLG132 0x3a02 /* DWL-G132 */ 531#define USB_PRODUCT_DLINK_DWLG132_NF 0x3a03 /* DWL-G132 */ 532#define USB_PRODUCT_GIGASET_AR5523 0x0712 /* AR5523 */ 533#define USB_PRODUCT_GIGASET_AR5523_NF 0x0713 /* AR5523 */ 534#define USB_PRODUCT_GIGASET_SMCWUSBTG 0x0710 /* SMCWUSBT-G */ 535#define USB_PRODUCT_GIGASET_SMCWUSBTG_NF 0x0711 /* SMCWUSBT-G */ 536#define USB_PRODUCT_GLOBALSUN_AR5523_1 0x7801 /* AR5523 */ 537#define USB_PRODUCT_GLOBALSUN_AR5523_1_NF 0x7802 /* AR5523 */ 538#define USB_PRODUCT_GLOBALSUN_AR5523_2 0x7811 /* AR5523 */ 539#define USB_PRODUCT_GLOBALSUN_AR5523_2_NF 0x7812 /* AR5523 */ 540#define USB_PRODUCT_IODATA_USBWNG54US 0x0928 /* USB WN-G54/US */ 541#define USB_PRODUCT_IODATA_USBWNG54US_NF 0x0929 /* USB WN-G54/US */ 542#define USB_PRODUCT_MELCO_WLIU2KAMG54 0x0091 /* WLI-U2-KAMG54 */ 543#define USB_PRODUCT_MELCO_WLIU2KAMG54_NF 0x0092 /* WLI-U2-KAMG54 */ 544#define USB_PRODUCT_NETGEAR_WG111U 0x4300 /* WG111U */ 545#define USB_PRODUCT_NETGEAR_WG111U_NF 0x4301 /* WG111U */ 546#define USB_PRODUCT_NETGEAR3_WG111T 0x4252 /* WG111T */ 547#define USB_PRODUCT_NETGEAR3_WG111T_NF 0x4251 /* WG111T */ 548#define USB_PRODUCT_NETGEAR3_WPN111 0x5f00 /* WPN111 */ 549#define USB_PRODUCT_NETGEAR3_WPN111_NF 0x5f01 /* WPN111 */ 550#define USB_PRODUCT_PHILIPS_SNU6500 0x1232 /* SNU6500 */ 551#define USB_PRODUCT_PHILIPS_SNU6500_NF 0x1233 /* SNU6500 */ 552#define USB_PRODUCT_UMEDIA_AR5523_2 0x3205 /* AR5523 */ 553#define USB_PRODUCT_UMEDIA_AR5523_2_NF 0x3206 /* AR5523 */ 554#define USB_PRODUCT_UMEDIA_TEW444UBEU 0x3006 /* TEW-444UB EU */ 555#define USB_PRODUCT_UMEDIA_TEW444UBEU_NF 0x3007 /* TEW-444UB EU */ 556#define USB_PRODUCT_WISTRONNEWEB_AR5523_1 0x0826 /* AR5523 */ 557#define USB_PRODUCT_WISTRONNEWEB_AR5523_1_NF 0x0827 /* AR5523 */ 558#define USB_PRODUCT_WISTRONNEWEB_AR5523_2 0x082a /* AR5523 */ 559#define USB_PRODUCT_WISTRONNEWEB_AR5523_2_NF 0x0829 /* AR5523 */ 560#define USB_PRODUCT_ZCOM_AR5523 0x0012 /* AR5523 */ 561#define USB_PRODUCT_ZCOM_AR5523_NF 0x0013 /* AR5523 */ 562 563#ifdef __cplusplus 564} 565#endif 566 567#endif /* _UATH_REG_H */ 568