1/* 2 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5/* 6 * Copyright (c) 2004, 2005 David Young. All rights reserved. 7 * 8 * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of David Young may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 23 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 24 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 25 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 26 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 27 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 28 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 * OF SUCH DAMAGE. 34 */ 35#ifndef _RTWVAR_H_ 36#define _RTWVAR_H_ 37 38#ifdef __cplusplus 39extern "C" { 40#endif 41 42#include <sys/list.h> 43#include <sys/net80211.h> 44 45#ifndef __func__ 46#define __func__ "" 47#endif 48 49extern void rtw_dbg(uint32_t dbg_flags, const int8_t *fmt, ...); 50 51#define RTW_DEBUG_TUNE 0x000001 52#define RTW_DEBUG_PKTFILT 0x000002 53#define RTW_DEBUG_XMIT 0x000004 54#define RTW_DEBUG_DMA 0x000008 55#define RTW_DEBUG_NODE 0x000010 56#define RTW_DEBUG_PWR 0x000020 57#define RTW_DEBUG_ATTACH 0x000040 58#define RTW_DEBUG_REGDUMP 0x000080 59#define RTW_DEBUG_ACCESS 0x000100 60#define RTW_DEBUG_RESET 0x000200 61#define RTW_DEBUG_INIT 0x000400 62#define RTW_DEBUG_PKTDUMP 0x000800 63#define RTW_DEBUG_RECV 0x001000 64#define RTW_DEBUG_RECV_DESC 0x002000 65#define RTW_DEBUG_IOSTATE 0x004000 66#define RTW_DEBUG_INTR 0x008000 67#define RTW_DEBUG_PHY 0x010000 68#define RTW_DEBUG_PHYIO 0x020000 69#define RTW_DEBUG_PHYBITIO 0x040000 70#define RTW_DEBUG_TIMEOUT 0x080000 71#define RTW_DEBUG_BUGS 0x100000 72#define RTW_DEBUG_BEACON 0x200000 73#define RTW_DEBUG_WIFICFG 0x400000 74#define RTW_DEBUG_80211 0x800000 75#define RTW_DEBUG_MAX 0xffffff 76 77#ifdef DEBUG 78#define RTW_DPRINTF \ 79 rtw_dbg 80#else /* DEBUG */ 81#define RTW_DPRINTF 82#endif /* DEBUG */ 83 84enum rtw_locale { 85 RTW_LOCALE_USA = 0, 86 RTW_LOCALE_EUROPE, 87 RTW_LOCALE_JAPAN, 88 RTW_LOCALE_UNKNOWN 89}; 90 91enum rtw_rfchipid { 92 RTW_RFCHIPID_RESERVED = 0, 93 RTW_RFCHIPID_INTERSIL = 1, 94 RTW_RFCHIPID_RFMD = 2, 95 RTW_RFCHIPID_PHILIPS = 3, 96 RTW_RFCHIPID_MAXIM = 4, 97 RTW_RFCHIPID_GCT = 5 98}; 99 100/* 101 * sc_flags 102 */ 103#define RTW_F_ENABLED 0x00000001 /* chip is enabled */ 104#define RTW_F_DIGPHY 0x00000002 /* digital PHY */ 105#define RTW_F_DFLANTB 0x00000004 /* B antenna is default */ 106#define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */ 107#define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */ 108#define RTW_F_SLEEP 0x00000040 /* chip is asleep */ 109#define RTW_F_INVALID 0x00000080 /* chip is absent */ 110#define RTW_F_SUSPEND 0x00000100 /* driver is suspended */ 111#define RTW_F_PLUMBED 0x00000200 /* driver is plumbed */ 112#define RTW_F_ATTACHED 0x01000000 /* driver is attached */ 113/* 114 * all PHY flags 115 */ 116#define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV) 117 118enum rtw_access {RTW_ACCESS_NONE = 0, 119 RTW_ACCESS_CONFIG = 1, 120 RTW_ACCESS_ANAPARM = 2}; 121 122struct rtw_regs { 123 ddi_acc_handle_t r_handle; 124 caddr_t r_base; 125 enum rtw_access r_access; 126}; 127 128#define RTW_SR_GET(sr, ofs) \ 129 (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff) 130 131#define RTW_SR_GET16(sr, ofs) \ 132 (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8)) 133 134struct rtw_srom { 135 uint16_t *sr_content; 136 uint16_t sr_size; 137}; 138 139 140#define RTW_NTXPRI 4 /* number of Tx priorities */ 141#define RTW_TXPRILO 0 142#define RTW_TXPRIMD 1 143#define RTW_TXPRIHI 2 144#define RTW_TXPRIBCN 3 /* beacon priority */ 145 146#define RTW_MAXPKTSEGS 64 /* Max 64 segments per Tx packet */ 147 148/* 149 * Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT 150 * boundaries. I allocate them consecutively from one buffer, so 151 * just round up. 152 */ 153#define RTW_TXQLENLO 64 /* low-priority queue length */ 154#define RTW_TXQLENMD 64 /* medium-priority */ 155#define RTW_TXQLENHI 64 /* high-priority */ 156#define RTW_TXQLENBCN 2 /* beacon */ 157 158#define RTW_NTXDESCLO RTW_TXQLENLO 159#define RTW_NTXDESCMD RTW_TXQLENMD 160#define RTW_NTXDESCHI RTW_TXQLENHI 161#define RTW_NTXDESCBCN RTW_TXQLENBCN 162 163#define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \ 164 RTW_NTXDESCHI + RTW_NTXDESCBCN) 165 166#define RTW_RXQLEN 64 167#define RTW_DMA_SYNC(area, flag) ((void) ddi_dma_sync((area).dma_hdl,\ 168 (area).offset, (area).alength, (flag))) 169 170#define RTW_DMA_SYNC_DESC(area, offset, len, flag) \ 171 ((void) ddi_dma_sync((area).dma_hdl, offset, len, (flag))) 172 173#define RTW_MINC(x, y) (x) = ((x + 1) % y) 174#define list_empty(a) ((a)->list_head.list_next == &(a)->list_head) 175 176typedef struct dma_area { 177 ddi_acc_handle_t acc_hdl; /* handle for memory */ 178 caddr_t mem_va; /* CPU VA of memory */ 179 uint32_t nslots; /* number of slots */ 180 uint32_t size; /* size per slot */ 181 size_t alength; /* allocated size */ 182 /* >= product of above */ 183 184 ddi_dma_handle_t dma_hdl; /* DMA handle */ 185 offset_t offset; /* relative to handle */ 186 ddi_dma_cookie_t cookie; /* associated cookie */ 187 uint32_t ncookies; /* must be 1 */ 188 uint32_t token; /* arbitrary identifier */ 189} dma_area_t; /* 0x50 (80) bytes */ 190 191struct rtw_txbuf { 192 struct rtw_txdesc *txdesc; /* virtual addr of desc */ 193 uint32_t bf_daddr; /* physical addr of desc */ 194 uint32_t next_bf_daddr; /* physical addr of next desc */ 195 dma_area_t bf_dma; /* dma area for buf */ 196 struct ieee80211_node *bf_in; /* pointer to the node */ 197 list_node_t bf_node; 198 uint32_t order; 199}; 200 201struct rtw_rxbuf { 202 struct rtw_rxdesc *rxdesc; /* virtual addr of desc */ 203 uint32_t bf_daddr; /* physical addr of desc */ 204 dma_area_t bf_dma; /* dma area for buf */ 205}; 206 207struct rtw_txq { 208 struct rtw_txdesc *txdesc_h; 209 struct rtw_txbuf *txbuf_h; 210 uint32_t tx_prod; 211 uint32_t tx_cons; 212 uint32_t tx_nfree; 213 kmutex_t txbuf_lock; 214 list_t tx_free_list; 215 list_t tx_dirty_list; 216}; 217 218struct rtw_descs { 219 struct rtw_txdesc hd_txlo[RTW_NTXDESCLO]; 220 struct rtw_txdesc hd_txmd[RTW_NTXDESCMD]; 221 struct rtw_txdesc hd_txhi[RTW_NTXDESCHI]; 222 struct rtw_rxdesc hd_rx[RTW_RXQLEN]; 223 struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN]; 224}; 225#define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i]) 226#define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0) 227#define RTW_RING_BASE(baseaddr0, ring) \ 228 (baseaddr0 + RTW_RING_OFFSET(ring)) 229 230/* 231 * One Time Unit (TU) is 1Kus = 1024 microseconds. 232 */ 233#define IEEE80211_DUR_TU 1024 234 235/* 236 * IEEE 802.11b durations for DSSS PHY in microseconds 237 */ 238#define IEEE80211_DUR_DS_LONG_PREAMBLE 144 239#define IEEE80211_DUR_DS_SHORT_PREAMBLE 72 240 241#define IEEE80211_DUR_DS_SLOW_PLCPHDR 48 242#define IEEE80211_DUR_DS_FAST_PLCPHDR 24 243#define IEEE80211_DUR_DS_SLOW_ACK 112 244#define IEEE80211_DUR_DS_FAST_ACK 56 245#define IEEE80211_DUR_DS_SLOW_CTS 112 246#define IEEE80211_DUR_DS_FAST_CTS 56 247 248#define IEEE80211_DUR_DS_SLOT 20 249#define IEEE80211_DUR_DS_SIFS 10 250#define IEEE80211_DUR_DS_PIFS (IEEE80211_DUR_DS_SIFS + IEEE80211_DUR_DS_SLOT) 251#define IEEE80211_DUR_DS_DIFS (IEEE80211_DUR_DS_SIFS + \ 252 2 * IEEE80211_DUR_DS_SLOT) 253#define IEEE80211_DUR_DS_EIFS (IEEE80211_DUR_DS_SIFS + \ 254 IEEE80211_DUR_DS_SLOW_ACK + \ 255 IEEE80211_DUR_DS_LONG_PREAMBLE + \ 256 IEEE80211_DUR_DS_SLOW_PLCPHDR + \ 257 IEEE80211_DUR_DIFS) 258 259/* 260 * 802.11 frame duration definitions. 261 */ 262struct rtw_ieee80211_duration { 263 uint16_t d_rts_dur; 264 uint16_t d_data_dur; 265 uint16_t d_plcp_len; 266 uint8_t d_residue; /* unused octets in time slot */ 267 uint8_t resv; 268}; 269 270 271#ifdef RTW_RADIOTAP 272/* 273 * Radio capture format for RTL8180. 274 */ 275 276#define RTW_RX_RADIOTAP_PRESENT \ 277 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 278 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 279 (1 << IEEE80211_RADIOTAP_RATE) | \ 280 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 281 (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ 282 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 283 0) 284 285struct rtw_rx_radiotap_header { 286 struct ieee80211_radiotap_header rr_ihdr; 287 uint64_t rr_tsft; 288 uint8_t rr_flags; 289 uint8_t rr_rate; 290 uint16_t rr_chan_freq; 291 uint16_t rr_chan_flags; 292 uint16_t rr_barker_lock; 293 uint8_t rr_antsignal; 294} __attribute__((__packed__)); 295 296#define RTW_TX_RADIOTAP_PRESENT \ 297 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 298 (1 << IEEE80211_RADIOTAP_RATE) | \ 299 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 300 0) 301 302struct rtw_tx_radiotap_header { 303 struct ieee80211_radiotap_header rt_ihdr; 304 uint8_t rt_flags; 305 uint8_t rt_rate; 306 uint16_t rt_chan_freq; 307 uint16_t rt_chan_flags; 308} __attribute__((__packed__)); 309#endif 310 311enum rtw_attach_state {FINISHED, FINISH_DESCMAP_LOAD, FINISH_DESCMAP_CREATE, 312 FINISH_DESC_MAP, FINISH_DESC_ALLOC, FINISH_RXMAPS_CREATE, 313 FINISH_TXMAPS_CREATE, FINISH_RESET, FINISH_READ_SROM, FINISH_PARSE_SROM, 314 FINISH_RF_ATTACH, FINISH_ID_STA, FINISH_TXDESCBLK_SETUP, 315 FINISH_TXCTLBLK_SETUP, DETACHED}; 316 317struct rtw_hooks { 318 void *rh_shutdown; /* shutdown hook */ 319 void *rh_power; /* power management hook */ 320}; 321 322enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON }; 323 324typedef void (*rtw_continuous_tx_cb_t)(void *arg, int); 325 326struct rtw_phy { 327 struct rtw_rf *p_rf; 328 struct rtw_regs *p_regs; 329}; 330 331struct rtw_bbpset { 332 uint_t bb_antatten; 333 uint_t bb_chestlim; 334 uint_t bb_chsqlim; 335 uint_t bb_ifagcdet; 336 uint_t bb_ifagcini; 337 uint_t bb_ifagclimit; 338 uint_t bb_lnadet; 339 uint_t bb_sys1; 340 uint_t bb_sys2; 341 uint_t bb_sys3; 342 uint_t bb_trl; 343 uint_t bb_txagc; 344}; 345 346struct rtw_rf { 347 void (*rf_destroy)(struct rtw_rf *); 348 /* 349 * args: frequency, txpower, power state 350 */ 351 int (*rf_init)(struct rtw_rf *, uint_t, uint8_t, enum rtw_pwrstate); 352 /* 353 * arg: power state 354 */ 355 int (*rf_pwrstate)(struct rtw_rf *, enum rtw_pwrstate); 356 /* 357 * arg: frequency 358 */ 359 int (*rf_tune)(struct rtw_rf *, uint_t); 360 /* 361 * arg: txpower 362 */ 363 int (*rf_txpower)(struct rtw_rf *, uint8_t); 364 rtw_continuous_tx_cb_t rf_continuous_tx_cb; 365 void *rf_continuous_tx_arg; 366 struct rtw_bbpset rf_bbpset; 367}; 368 369typedef int (*rtw_rf_write_t)(struct rtw_regs *, enum rtw_rfchipid, uint_t, 370 uint32_t); 371 372struct rtw_rfbus { 373 struct rtw_regs *b_regs; 374 rtw_rf_write_t b_write; 375}; 376 377struct rtw_max2820 { 378 struct rtw_rf mx_rf; 379 struct rtw_rfbus mx_bus; 380 int mx_is_a; /* 1: MAX2820A/MAX2821A */ 381}; 382 383struct rtw_sa2400 { 384 struct rtw_rf sa_rf; 385 struct rtw_rfbus sa_bus; 386 int sa_digphy; /* 1: digital PHY */ 387}; 388 389typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int); 390 391union rtw_keys { 392 uint8_t rk_keys[4][16]; 393 uint32_t rk_words[16]; 394}; 395 396#define RTW_LED_SLOW_TICKS MAX(1, hz/2) 397#define RTW_LED_FAST_TICKS MAX(1, hz/10) 398 399struct rtw_led_state { 400#define RTW_LED0 0x1 401#define RTW_LED1 0x2 402 uint8_t ls_slowblink:2; 403 uint8_t ls_actblink:2; 404 uint8_t ls_default:2; 405 uint8_t ls_state; 406 uint8_t ls_event; 407#define RTW_LED_S_RX 0x1 408#define RTW_LED_S_TX 0x2 409#define RTW_LED_S_SLOW 0x4 410}; 411 412typedef struct rtw_softc { 413 ieee80211com_t sc_ic; /* IEEE 802.11 common */ 414 dev_info_t *sc_dev; /* back pointer to dev_info_t */ 415 kmutex_t sc_genlock; 416 struct rtw_regs sc_regs; 417 ddi_acc_handle_t sc_cfg_handle; 418 caddr_t sc_cfg_base; 419 enum ieee80211_phymode sc_curmode; 420 uint32_t sc_flags; 421 uint32_t sc_invalid; 422 ddi_iblock_cookie_t sc_iblock; 423 uint32_t sc_need_reschedule; 424 uint16_t sc_cachelsz; /* cache line size */ 425 uchar_t sc_macaddr[6]; 426 427 enum rtw_rfchipid sc_rfchipid; 428 enum rtw_locale sc_locale; 429 uint8_t sc_phydelay; 430 431 uint32_t sc_dmabuf_size; 432 dma_area_t sc_desc_dma; 433 434 struct rtw_txq sc_txq[RTW_NTXPRI]; 435 436 struct rtw_rxdesc *rxdesc_h; 437 struct rtw_rxbuf *rxbuf_h; 438 uint32_t rx_next; 439 kmutex_t rxbuf_lock; 440 kmutex_t sc_txlock; 441 442 struct rtw_srom sc_srom; 443 enum rtw_pwrstate sc_pwrstate; 444 rtw_pwrstate_t sc_pwrstate_cb; 445 struct rtw_rf *sc_rf; 446 447 uint16_t sc_inten; 448 449 void (*sc_intr_ack)(struct rtw_regs *); 450 451 int (*sc_enable)(struct rtw_softc *); 452 void (*sc_disable)(struct rtw_softc *); 453 void (*sc_power)(struct rtw_softc *, int); 454 struct rtw_hooks sc_hooks; 455 456 uint_t sc_cur_chan; 457 458 uint32_t sc_tsfth; /* most significant TSFT bits */ 459 uint32_t sc_rcr; /* RTW_RCR */ 460 uint8_t sc_csthr; /* carrier-sense threshold */ 461 462 uint8_t sc_rev; /* PCI/Cardbus revision */ 463 464 uint32_t sc_anaparm; /* register RTW_ANAPARM */ 465#ifdef RTW_RADIOTAP 466 union { 467 struct rtw_rx_radiotap_header tap; 468 uint8_t pad[64]; 469 } sc_rxtapu; 470 union { 471 struct rtw_tx_radiotap_header tap; 472 uint8_t pad[64]; 473 } sc_txtapu; 474#endif 475 union rtw_keys sc_keys; 476 int sc_txkey; 477 struct rtw_led_state sc_led_state; 478 int sc_hwverid; 479 480 int (*sc_newstate)(ieee80211com_t *, 481 enum ieee80211_state, int); 482 483 timeout_id_t sc_scan_id; 484 timeout_id_t sc_ratectl_id; 485 uint32_t sc_tx_ok; 486 uint32_t sc_tx_err; 487 uint32_t sc_tx_retr; 488 uint32_t sc_xmtretry; 489 uint32_t sc_noxmtbuf; 490 uint32_t sc_norcvbuf; 491 uint32_t sc_bytexmt64; 492 uint32_t sc_bytercv64; 493 uint32_t sc_pktxmt64; 494 uint32_t sc_pktrcv64; 495 uint32_t sc_intr; 496 uint32_t sc_ioerror; 497 uint32_t hw_start; 498 uint32_t hw_go; 499} rtw_softc_t; 500 501#define RTW_SC(ic) ((rtw_softc_t *)ic) 502#ifdef __cplusplus 503} 504#endif 505 506#endif /* _RTWVAR_H_ */ 507