1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _RGE_HW_H 27#define _RGE_HW_H 28 29#ifdef __cplusplus 30extern "C" { 31#endif 32 33#include <sys/types.h> 34 35 36/* 37 * First section: 38 * Identification of the various Realtek GigE chips 39 */ 40 41/* 42 * Driver support device 43 */ 44#define VENDOR_ID_REALTECK 0x10EC 45#define DEVICE_ID_8169 0x8169 /* PCI */ 46#define DEVICE_ID_8110 0x8169 /* PCI */ 47#define DEVICE_ID_8168 0x8168 /* PCI-E */ 48#define DEVICE_ID_8111 0x8168 /* PCI-E */ 49#define DEVICE_ID_8169SC 0x8167 /* PCI */ 50#define DEVICE_ID_8110SC 0x8167 /* PCI */ 51#define DEVICE_ID_8101E 0x8136 /* 10/100M PCI-E */ 52 53#define RGE_REGISTER_MAX 0x0100 54 55 56/* 57 * Second section: 58 * Offsets of important registers & definitions for bits therein 59 */ 60/* 61 * MAC address register, initial value is autoloaded from the 62 * EEPROM EthernetID field 63 */ 64#define ID_0_REG 0x0000 65#define ID_1_REG 0x0001 66#define ID_2_REG 0x0002 67#define ID_3_REG 0x0003 68#define ID_4_REG 0x0004 69#define ID_5_REG 0x0005 70 71/* 72 * Multicast register 73 */ 74#define MULTICAST_0_REG 0x0008 75#define MULTICAST_1_REG 0x0009 76#define MULTICAST_2_REG 0x000a 77#define MULTICAST_3_REG 0x000b 78#define MULTICAST_4_REG 0x000c 79#define MULTICAST_5_REG 0x000d 80#define MULTICAST_6_REG 0x000e 81#define MULTICAST_7_REG 0x000f 82#define RGE_MCAST_NUM 8 /* total 8 registers: MAR0 - MAR7 */ 83 84/* 85 * Dump Tally Counter Command register 86 */ 87#define DUMP_COUNTER_REG_0 0x0010 88#define DUMP_COUNTER_REG_RESV 0x00000037 89#define DUMP_START 0x00000008 90#define DUMP_COUNTER_REG_1 0x0014 91 92/* 93 * Register for start address of transmit descriptors 94 */ 95#define NORMAL_TX_RING_ADDR_LO_REG 0x0020 96#define NORMAL_TX_RING_ADDR_HI_REG 0x0024 97#define HIGH_TX_RING_ADDR_LO_REG 0x0028 98#define HIGH_TX_RING_ADDR_HI_REG 0x002c 99 100/* 101 * Commond register 102 */ 103#define RT_COMMAND_REG 0x0037 104#define RT_COMMAND_RESV 0xe3 105#define RT_COMMAND_RESET 0x10 106#define RT_COMMAND_RX_ENABLE 0x08 107#define RT_COMMAND_TX_ENABLE 0x04 108 109/* 110 * Transmit priority polling register 111 */ 112#define TX_RINGS_POLL_REG 0x0038 113#define HIGH_TX_RING_POLL 0x80 114#define NORMAL_TX_RING_POLL 0x40 115#define FORCE_SW_INT 0x01 116 117/* 118 * Interrupt mask & status register 119 */ 120#define INT_MASK_REG 0x003c 121#define INT_STATUS_REG 0x003e 122#define SYS_ERR_INT 0x8000 123#define TIME_OUT_INT 0x4000 124#define SW_INT 0x0100 125#define NO_TXDESC_INT 0x0080 126#define RX_FIFO_OVERFLOW_INT 0x0040 127#define LINK_CHANGE_INT 0x0020 128#define NO_RXDESC_INT 0x0010 129#define TX_ERR_INT 0x0008 130#define TX_OK_INT 0x0004 131#define RX_ERR_INT 0x0002 132#define RX_OK_INT 0x0001 133 134#define INT_REG_RESV 0x3e00 135#define INT_MASK_ALL 0xffff 136#define INT_MASK_NONE 0x0000 137#define RGE_RX_INT (RX_OK_INT | RX_ERR_INT | \ 138 NO_RXDESC_INT) 139#define RGE_INT_MASK (TX_OK_INT | TX_ERR_INT | \ 140 RGE_RX_INT | LINK_CHANGE_INT | \ 141 TIME_OUT_INT | SYS_ERR_INT) 142 143/* 144 * Transmit configuration register 145 */ 146#define TX_CONFIG_REG 0x0040 147#define TX_CONFIG_REG_RESV 0x8070f8ff 148#define HW_VERSION_ID_0 0x7c000000 149#define INTER_FRAME_GAP_BITS 0x03080000 150#define TX_INTERFRAME_GAP_802_3 0x03000000 151#define HW_VERSION_ID_1 0x00800000 152#define MAC_LOOPBACK_ENABLE 0x00060000 153#define CRC_APPEND_ENABLE 0x00010000 154#define TX_DMA_BURST_BITS 0x00000700 155 156#define TX_DMA_BURST_UNLIMIT 0x00000700 157#define TX_DMA_BURST_1024B 0x00000600 158#define TX_DMA_BURST_512B 0x00000500 159#define TX_DMA_BURST_256B 0x00000400 160#define TX_DMA_BURST_128B 0x00000300 161#define TX_DMA_BURST_64B 0x00000200 162#define TX_DMA_BURST_32B 0x00000100 163#define TX_DMA_BURST_16B 0x00000000 164 165#define MAC_VER_8169 0x00000000 166#define MAC_VER_8169S_D 0x00800000 167#define MAC_VER_8169S_E 0x04000000 168#define MAC_VER_8169SB 0x10000000 169#define MAC_VER_8169SC 0x18000000 170#define MAC_VER_8168 0x20000000 171#define MAC_VER_8168B_B 0x30000000 172#define MAC_VER_8168B_C 0x38000000 173#define MAC_VER_8168C 0x3c000000 174#define MAC_VER_8101E 0x34000000 175#define MAC_VER_8101E_B 0x24800000 176#define MAC_VER_8101E_C 0x34800000 177 178#define TX_CONFIG_DEFAULT (TX_INTERFRAME_GAP_802_3 | \ 179 TX_DMA_BURST_1024B) 180/* 181 * Receive configuration register 182 */ 183#define RX_CONFIG_REG 0x0044 184#define RX_CONFIG_REG_RESV 0xfffe1880 185#define RX_RER8_ENABLE 0x00010000 186#define RX_FIFO_THRESHOLD_BITS 0x0000e000 187#define RX_FIFO_THRESHOLD_NONE 0x0000e000 188#define RX_FIFO_THRESHOLD_1024B 0x0000c000 189#define RX_FIFO_THRESHOLD_512B 0x0000a000 190#define RX_FIFO_THRESHOLD_256B 0x00008000 191#define RX_FIFO_THRESHOLD_128B 0x00006000 192#define RX_FIFO_THRESHOLD_64B 0x00004000 193#define RX_DMA_BURST_BITS 0x00000700 194#define RX_DMA_BURST_UNLIMITED 0x00000700 195#define RX_DMA_BURST_1024B 0x00000600 196#define RX_DMA_BURST_512B 0x00000500 197#define RX_DMA_BURST_256B 0x00000400 198#define RX_DMA_BURST_128B 0x00000300 199#define RX_DMA_BURST_64B 0x00000200 200#define RX_EEPROM_9356 0x00000040 201#define RX_ACCEPT_ERR_PKT 0x00000020 202#define RX_ACCEPT_RUNT_PKT 0x00000010 203#define RX_ACCEPT_BROADCAST_PKT 0x000000008 204#define RX_ACCEPT_MULTICAST_PKT 0x000000004 205#define RX_ACCEPT_MAC_MATCH_PKT 0x000000002 206#define RX_ACCEPT_ALL_PKT 0x000000001 207 208#define RX_CONFIG_DEFAULT (RX_FIFO_THRESHOLD_NONE | \ 209 RX_DMA_BURST_1024B | \ 210 RX_ACCEPT_BROADCAST_PKT | \ 211 RX_ACCEPT_MULTICAST_PKT | \ 212 RX_ACCEPT_MAC_MATCH_PKT) 213 214/* 215 * Timer count register 216 */ 217#define TIMER_COUNT_REG 0x0048 218#define TIMER_CLK_PCIE (125*1000*1000) 219#define TIMER_CLK_PCI (33*1000*1000) 220 221/* 222 * Missed packet counter: indicates the number of packets 223 * discarded due to Rx FIFO overflow 224 */ 225#define RX_PKT_MISS_COUNT_REG 0x004c 226 227/* 228 * 93c46(93c56) commond register: 229 */ 230#define RT_93c46_COMMOND_REG 0x0050 231#define RT_93c46_MODE_BITS 0xc0 232#define RT_93c46_MODE_NORMAL 0x00 233#define RT_93c46_MODE_AUTOLOAD 0x40 234#define RT_93c46_MODE_PROGRAM 0x80 235#define RT_93c46_MODE_CONFIG 0xc0 236 237#define RT_93c46_EECS 0x08 238#define RT_93c46_EESK 0x04 239#define RT_93c46_EEDI 0x02 240#define RT_93c46_EEDO 0x01 241 242/* 243 * Configuration registers 244 */ 245#define RT_CONFIG_0_REG 0x0051 246#define RT_CONFIG_1_REG 0x0052 247#define RT_CONFIG_2_REG 0x0053 248#define RT_CONFIG_3_REG 0x0054 249#define RT_CONFIG_4_REG 0x0055 250#define RT_CONFIG_5_REG 0x0056 251 252/* 253 * Config 5 Register Bits 254 */ 255#define RT_UNI_WAKE_FRAME 0x10 256#define RT_MUL_WAKE_FRAME 0x20 257#define RT_BRO_WAKE_FRAME 0x40 258 259/* 260 * Timer interrupt register 261 */ 262#define TIMER_INT_REG 0x0058 263#define TIMER_INT_NONE 0x00000000 264 265/* 266 * PHY access register 267 */ 268#define PHY_ACCESS_REG 0x0060 269#define PHY_ACCESS_WR_FLAG 0x80000000 270#define PHY_ACCESS_REG_BITS 0x001f0000 271#define PHY_ACCESS_DATA_BITS 0x0000ffff 272#define PHY_DATA_MASK 0xffff 273#define PHY_REG_MASK 0x1f 274#define PHY_REG_SHIFT 16 275 276/* 277 * CSI data register (for PCIE chipset) 278 */ 279#define RT_CSI_DATA_REG 0x0064 280 281/* 282 * CSI access register (for PCIE chipset) 283 */ 284#define RT_CSI_ACCESS_REG 0x0068 285 286/* 287 * PHY status register 288 */ 289#define PHY_STATUS_REG 0x006c 290#define PHY_STATUS_TBI 0x80 291#define PHY_STATUS_TX_FLOW 0x40 292#define PHY_STATUS_RX_FLOW 0x20 293#define PHY_STATUS_1000MF 0x10 294#define PHY_STATUS_100M 0x08 295#define PHY_STATUS_10M 0x04 296#define PHY_STATUS_LINK_UP 0x02 297#define PHY_STATUS_DUPLEX_FULL 0x01 298 299#define RGE_SPEED_1000M 1000 300#define RGE_SPEED_100M 100 301#define RGE_SPEED_10M 10 302#define RGE_SPEED_UNKNOWN 0 303 304/* 305 * EPHY access register (for PCIE chipset) 306 */ 307#define EPHY_ACCESS_REG 0x0080 308#define EPHY_ACCESS_WR_FLAG 0x80000000 309#define EPHY_ACCESS_REG_BITS 0x001f0000 310#define EPHY_ACCESS_DATA_BITS 0x0000ffff 311#define EPHY_DATA_MASK 0xffff 312#define EPHY_REG_MASK 0x1f 313#define EPHY_REG_SHIFT 16 314 315/* 316 * Receive packet maximum size register 317 * -- the maximum rx size supported is (16K - 1) bytes 318 */ 319#define RX_MAX_PKTSIZE_REG 0x00da 320#define RX_PKTSIZE_JUMBO 0x1bfa /* 7K bytes */ 321#define RX_PKTSIZE_STD 0x05fa /* 1530 bytes */ 322#define RX_PKTSIZE_STD_8101E 0x3fff 323 324/* 325 * C+ command register 326 */ 327#define CPLUS_COMMAND_REG 0x00e0 328#define CPLUS_RESERVE 0xfd87 329#define CPLUS_BIT14 0x4000 330#define CPLUS_BIG_ENDIAN 0x0400 331#define RX_VLAN_DETAG 0x0040 332#define RX_CKSM_OFFLOAD 0x0020 333#define DUAL_PCI_CYCLE 0x0010 334#define MUL_PCI_RW_ENABLE 0x0008 335 336/* 337 * Receive descriptor start address 338 */ 339#define RX_RING_ADDR_LO_REG 0x00e4 340#define RX_RING_ADDR_HI_REG 0x00e8 341 342/* 343 * Max transmit packet size register 344 */ 345#define TX_MAX_PKTSIZE_REG 0x00ec 346#define TX_MAX_PKTSIZE_REG_RESV 0xc0 347#define TX_PKTSIZE_JUMBO 0x3b /* Realtek suggested value */ 348#define TX_PKTSIZE_STD 0x32 /* document suggested value */ 349#define TX_PKTSIZE_STD_8101E 0x3f 350 351#define RESV_82_REG 0x0082 352#define RESV_E2_REG 0x00e2 353 354/* 355 * PHY registers 356 */ 357/* 358 * Basic mode control register 359 */ 360#define PHY_BMCR_REG 0x00 361#define PHY_RESET 0x8000 362#define PHY_LOOPBACK 0x4000 363#define PHY_SPEED_0 0x2000 364#define PHY_SPEED_1 0x0040 365#define PHY_SPEED_BITS (PHY_SPEED_0 | PHY_SPEED_1) 366#define PHY_SPEED_1000M PHY_SPEED_1 367#define PHY_SPEED_100M PHY_SPEED_0 368#define PHY_SPEED_10M 0x0000 369#define PHY_SPEED_RES (PHY_SPEED_0 | PHY_SPEED_1) 370#define PHY_AUTO_NEGO 0x1000 371#define PHY_RESTART_ANTO_NEGO 0x0200 372#define PHY_DUPLEX_FULL 0x0100 373#define PHY_BMCR_CLEAR 0xff40 374 375/* 376 * Basic mode status register 377 */ 378#define PHY_BMSR_REG 0x01 379#define PHY_100BASE_T4 0x8000 380#define PHY_100BASE_TX_FULL 0x4000 381#define PHY_100BASE_TX_HALF 0x2000 382#define PHY_10BASE_T_FULL 0x1000 383#define PHY_10BASE_T_HALF 0x0800 384#define PHY_100BASE_T2_FULL 0x0400 385#define PHY_100BASE_T2_HALF 0x0200 386#define PHY_1000BASE_T_EXT 0x0100 387#define PHY_AUTO_NEGO_END 0x0020 388#define PHY_REMOTE_FAULT 0x0010 389#define PHY_AUTO_NEGO_ABLE 0x0008 390#define PHY_LINK_UP 0x0004 391#define PHY_JABBER_DETECT 0x0002 392#define PHY_EXT_ABLE 0x0001 393 394/* 395 * PHY identifier register 396 */ 397#define PHY_ID_REG_1 0x02 398#define PHY_ID_REG_2 0x03 399#define PHY_VER_MASK 0x000f 400#define PHY_VER_S 0x0000 401#define PHY_VER_SB 0x0010 402 403/* 404 * Auto-negotiation advertising register 405 */ 406#define PHY_ANAR_REG 0x04 407#define ANAR_NEXT_PAGE 0x8000 408#define ANAR_REMOTE_FAULT 0x2000 409#define ANAR_ASY_PAUSE 0x0800 410#define ANAR_PAUSE 0x0400 411#define ANAR_100BASE_T4 0x0200 412#define ANAR_100BASE_TX_FULL 0x0100 413#define ANAR_100BASE_TX_HALF 0x0080 414#define ANAR_10BASE_T_FULL 0x0040 415#define ANAR_10BASE_T_HALF 0x0020 416#define ANAR_RESV_BITS 0x501f 417 418/* 419 * Auto-negotiation link partner ability register 420 */ 421#define PHY_ANLPAR_REG 0x05 422 423/* 424 * Auto-negotiation expansion register 425 */ 426#define PHY_ANER_REG 0x06 427 428/* 429 * Auto-negotiation next page transmit register 430 */ 431#define PHY_ANNPTR_REG 0x07 432 433/* 434 * Auto-negotiation next page receive register 435 */ 436#define PHY_ANNPRR_REG 0x08 437 438/* 439 * 1000Base-T control register 440 */ 441#define PHY_GBCR_REG 0x09 442#define GBCR_MODE_JITTER 0x2000 443#define GBCR_MODE_MASTER 0x4000 444#define GBCR_MODE_SLAVE 0x6000 445#define GBCR_1000BASE_T_FULL 0x0200 446#define GBCR_1000BASE_T_HALF 0x0100 447#define GBCR_DEFAULT 0x273a 448 449/* 450 * 1000Base-T status register 451 */ 452#define PHY_GBSR_REG 0x0a 453#define LP_1000BASE_T_FULL 0x0800 454#define LP_1000BASE_T_HALF 0x0400 455 456/* 457 * 1000Base-T extended status register 458 */ 459#define PHY_GBESR_REG 0x0f 460 461#define PHY_1F_REG 0x1f 462#define PHY_1D_REG 0x1d 463#define PHY_1C_REG 0x1c 464#define PHY_1B_REG 0x1b 465#define PHY_18_REG 0x18 466#define PHY_15_REG 0x15 467#define PHY_13_REG 0x13 468#define PHY_12_REG 0x12 469#define PHY_0E_REG 0x0e 470#define PHY_0C_REG 0x0c 471#define PHY_0B_REG 0x0b 472 473/* 474 * MII (PHY) registers, beyond those already defined in <sys/miiregs.h> 475 */ 476 477#define MII_AN_LPNXTPG 8 478#define MII_1000BASE_T_CONTROL 9 479#define MII_1000BASE_T_STATUS 10 480#define MII_IEEE_EXT_STATUS 15 481 482/* 483 * Bits in the MII_1000BASE_T_CONTROL register 484 * 485 * The MASTER_CFG bit enables manual configuration of Master/Slave mode 486 * (otherwise, roles are automatically negotiated). When this bit is set, 487 * the MASTER_SEL bit forces Master mode, otherwise Slave mode is forced. 488 */ 489#define MII_1000BT_CTL_MASTER_CFG 0x1000 /* enable role select */ 490#define MII_1000BT_CTL_MASTER_SEL 0x0800 /* role select bit */ 491#define MII_1000BT_CTL_ADV_FDX 0x0200 492#define MII_1000BT_CTL_ADV_HDX 0x0100 493 494/* 495 * Vendor-specific MII registers 496 */ 497#define MII_EXT_CONTROL MII_VENDOR(0) 498#define MII_EXT_STATUS MII_VENDOR(1) 499#define MII_RCV_ERR_COUNT MII_VENDOR(2) 500#define MII_FALSE_CARR_COUNT MII_VENDOR(3) 501#define MII_RCV_NOT_OK_COUNT MII_VENDOR(4) 502#define MII_AUX_CONTROL MII_VENDOR(8) 503#define MII_AUX_STATUS MII_VENDOR(9) 504#define MII_INTR_STATUS MII_VENDOR(10) 505#define MII_INTR_MASK MII_VENDOR(11) 506#define MII_HCD_STATUS MII_VENDOR(13) 507 508#define MII_MAXREG MII_VENDOR(15) /* 31, 0x1f */ 509 510/* 511 * Bits in the MII_AUX_STATUS register 512 */ 513#define MII_AUX_STATUS_MODE_MASK 0x0700 514#define MII_AUX_STATUS_MODE_1000_F 0x0700 515#define MII_AUX_STATUS_MODE_1000_H 0x0600 516#define MII_AUX_STATUS_MODE_100_F 0x0500 517#define MII_AUX_STATUS_MODE_100_4 0x0400 518#define MII_AUX_STATUS_MODE_100_H 0x0300 519#define MII_AUX_STATUS_MODE_10_F 0x0200 520#define MII_AUX_STATUS_MODE_10_H 0x0100 521#define MII_AUX_STATUS_MODE_NONE 0x0000 522#define MII_AUX_STATUS_MODE_SHIFT 8 523 524#define MII_AUX_STATUS_PAR_FAULT 0x0080 525#define MII_AUX_STATUS_REM_FAULT 0x0040 526#define MII_AUX_STATUS_LP_ANEG_ABLE 0x0010 527#define MII_AUX_STATUS_LP_NP_ABLE 0x0008 528 529#define MII_AUX_STATUS_LINKUP 0x0004 530#define MII_AUX_STATUS_RX_PAUSE 0x0002 531#define MII_AUX_STATUS_TX_PAUSE 0x0001 532 533/* 534 * Third section: 535 * Hardware-defined data structures 536 * 537 * Note that the chip is naturally little-endian, so, for a little-endian 538 * host, the structures defined below match those descibed in the PRM. 539 * For big-endian hosts, some structures have to be swapped around. 540 */ 541 542#if !defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) 543#error Host endianness not defined 544#endif 545 546/* 547 * Architectural constants: absolute maximum numbers of each type of ring 548 */ 549 550#define RGE_SEND_SLOTS 1024 551#define RGE_RECV_SLOTS 1024 552#define RGE_BUFF_SIZE_STD 1536 /* 1536 bytes */ 553#define RGE_BUFF_SIZE_JUMBO 7168 /* maximum 7K */ 554#define RGE_JUMBO_SIZE 7014 555#define RGE_JUMBO_MTU 7000 556#define RGE_STATS_DUMP_SIZE 64 557 558typedef struct rge_bd { 559 volatile uint32_t flags_len; 560 volatile uint32_t vlan_tag; 561 volatile uint32_t host_buf_addr; 562 volatile uint32_t host_buf_addr_hi; 563} rge_bd_t; 564 565#define BD_FLAG_HW_OWN 0x80000000 566#define BD_FLAG_EOR 0x40000000 567#define BD_FLAG_PKT_START 0x20000000 568#define BD_FLAG_PKT_END 0x10000000 569 570#define RBD_FLAG_MULTICAST 0x08000000 571#define RBD_FLAG_UNICAST 0x04000000 572#define RBD_FLAG_BROADCAST 0x02000000 573#define RBD_FLAG_PKT_4096 0x00400000 574#define RBD_FLAG_ERROR 0x00200000 575#define RBD_FLAG_RUNT 0x00100000 576#define RBD_FLAG_CRC_ERR 0x00080000 577#define RBD_FLAG_PROTOCOL 0x00060000 578#define RBD_FLAG_IP 0x00060000 579#define RBD_FLAG_UDP 0x00040000 580#define RBD_FLAG_TCP 0x00020000 581#define RBD_FLAG_NONE_IP 0x00000000 582#define RBD_IP_CKSUM_ERR 0x00010000 583#define RBD_UDP_CKSUM_ERR 0x00008000 584#define RBD_TCP_CKSUM_ERR 0x00004000 585#define RBD_CKSUM_ERR 0x0001c000 586#define RBD_FLAGS_MASK 0xffffc000 587#define RBD_LEN_MASK 0x00003fff 588 589#define RBD_VLAN_PKT 0x00010000 590#define RBD_VLAN_TAG 0x0000ffff 591 592 593#define SBD_FLAG_LARGE_SEND 0x08000000 594#define SBD_FLAG_SEG_MAX 0x07ff0000 595#define SBD_FLAG_IP_CKSUM 0x00040000 596#define SBD_FLAG_UDP_CKSUM 0x00020000 597#define SBD_FLAG_TCP_CKSUM 0x00010000 598#define SBD_FLAG_TCP_UDP_CKSUM 0x00030000 599#define SBD_LEN_MASK 0x0000ffff 600 601#define SBD_VLAN_PKT 0x00020000 602#define SBD_VLAN_TAG 0x0000ffff 603 604#define SBD_FLAG_TX_PKT (BD_FLAG_HW_OWN | BD_FLAG_PKT_START | \ 605 BD_FLAG_PKT_END) 606 607/* 608 * Chip VLAN TCI format 609 * bit0-3: VIDH The high 4 bits of a 12-bit VLAN ID 610 * bit4: CFI Canonical format indicator 611 * bit5-7: 3-bit 8-level priority 612 * bit8-15: The low 8 bits of a 12-bit VLAN ID 613 */ 614#define TCI_OS2CHIP(tci) (((tci & 0xff) << 8) | (tci >> 8)) 615#define TCI_CHIP2OS(tci) (((tci & 0xff00) >> 8) | (tci << 8)) 616 617/* 618 * Hardware-defined Status Block 619 */ 620typedef struct rge_hw_stats { 621 uint64_t xmt_ok; 622 uint64_t rcv_ok; 623 uint64_t xmt_err; 624 uint32_t rcv_err; 625 uint16_t in_discards; 626 uint16_t frame_err; 627 uint32_t xmt_1col; 628 uint32_t xmt_mcol; 629 uint64_t unicast_rcv; 630 uint64_t brdcst_rcv; 631 uint32_t multi_rcv; 632 uint16_t xmt_abt; 633 uint16_t xmt_undrn; 634} rge_hw_stats_t; /* total 64 bytes */ 635 636#ifdef __cplusplus 637} 638#endif 639 640#endif /* _RGE_HW_H */ 641