1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _NPI_RX_WR64_H 27#define _NPI_RX_WR64_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#include <npi.h> 36 37/* 38 * RXDMA_REG_WRITE64 39 * 40 * Write a 64-bit value to a DMC register. 41 * 42 * This is the old, rather convoluted, macro. 43 * 44 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \ 45 * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 46 * channel)), (data)) \ 47 * 48 * There are 3 versions of NXGE_REG_WR64: 49 * ------------------------------------------------------------- 50 * #if defined(REG_TRACE) 51 * #define NXGE_REG_WR64(handle, offset, val) { \ 52 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val)); \ 53 * npi_rtrace_update(handle, B_TRUE, &npi_rtracebuf, (uint32_t)offset, \ 54 * (uint64_t)(val)); \ 55 * } 56 * #elif defined(REG_SHOW) 57 * #define NXGE_REG_WR64(handle, offset, val) {\ 58 * NXGE_NPI_PIO_WRITE64(handle, offset, (val));\ 59 * rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, (uint64_t)(val));\ 60 * } 61 * #else 62 * #define NXGE_REG_WR64(handle, offset, val) {\ 63 * NXGE_NPI_PIO_WRITE64(handle, (offset), (val));\ 64 * } 65 * #endif 66 * 67 * There are 2 versions of NXGE_NPI_PIO_WRITE64: 68 * ------------------------------------------------------------- 69 * #if defined(__i386) 70 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 71 * (ddi_put64(NPI_REGH(npi_handle), \ 72 * (uint64_t *)(NPI_REGP(npi_handle) + (uint32_t)offset), data)) 73 * #else 74 * #define NXGE_NPI_PIO_WRITE64(npi_handle, offset, data) \ 75 * (ddi_put64(NPI_REGH(npi_handle), \ 76 * (uint64_t *)(NPI_REGP(npi_handle) + offset), data)) 77 * #endif 78 * 79 * ------------------------------------------------------------- 80 * #define NPI_REGH(npi_handle) (npi_handle.regh) 81 * #define NPI_REGP(npi_handle) (npi_handle.regp) 82 * 83 * Now let's tackle NXGE_RXDMA_OFFSET 84 * ------------------------------------------------------------- 85 * #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \ 86 * (!v ? DMC_OFFSET(channel) : \ 87 * RDMC_PIOVADDR_OFFSET(channel))) 88 * 89 * ------------------------------------------------------------- 90 * #define DMC_OFFSET(channel) (DMA_CSR_SIZE * channel) 91 * 92 * #define TDMC_PIOVADDR_OFFSET(channel) (2 * DMA_CSR_SIZE * channel) 93 * ------------------------------------------------------------- 94 * #define RDMC_PIOVADDR_OFFSET(channel) \ 95 * (TDMC_OFFSET(channel) + DMA_CSR_SIZE) 96 * ------------------------------------------------------------- 97 * #define DMA_CSR_SIZE 512 98 * 99 * #define TDMC_OFFSET(channel) (TX_RNG_CFIG + DMA_CSR_SIZE * channel) 100 * #define TX_RNG_CFIG (DMC + 0x40000) 101 * ------------------------------------------------------------- 102 * This definition is clearly wrong! I think this was intended: 103 * 104 * #define RDMC_PIOVADDR_OFFSET(channel) \ 105 * (TDMC_PIOVADDR__OFFSET(channel) + DMA_CSR_SIZE) 106 * ------------------------------------------------------------- 107 * 108 * Finally, we have the full macro: 109 * ------------------------------------------------------------- 110 * #define RXDMA_REG_WRITE64(handle, reg, channel, data) { \ 111 * NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 112 * channel)), (data)) \ 113 * 114 * ddi_put64(handle.regh, (uint64_t*)(handle.regp + ((0x600000 + 0x00000) + 115 * (!handle.is_vraddr ? 116 * (512 * channel) : 117 * (0x600000 + 0x40000 + 512 * channel + 512))), data); 118 */ 119 120static void RXDMA_REG_WRITE64(npi_handle_t, uint64_t, int, uint64_t); 121#pragma inline(RXDMA_REG_WRITE64) 122 123/* 124 * RXDMA_REG_WRITE64 125 * 126 * Write a 64-bit value to a DMC register. 127 * 128 * Arguments: 129 * handle The NPI handle to use. 130 * offset The offset into the DMA CSR (the register). 131 * channel The channel, which is used as a multiplicand. 132 * value The 64-bit value to write. 133 * 134 * Notes: 135 * If handle.regp is a virtual address (the address of a VR), 136 * we have to subtract the value DMC right off the bat. DMC 137 * is defined as 0x600000, which works in a non-virtual address 138 * space, but not in a VR. In a VR, a DMA CSR's space begins 139 * at zero (0). So, since every call to RXMDA_REG_READ64 uses 140 * a register macro which adds in DMC, we have to subtract it. 141 * 142 * The rest of it is pretty straighforward. In a VR, a channel is 143 * logical, not absolute; and every DMA CSR is 512 bytes big; 144 * furthermore, a subpage of a VR is always ordered with the 145 * transmit CSRs first, followed by the receive CSRs. That is, 146 * a 512 byte space of Tx CSRs, followed by a 512 byte space of 147 * Rx CSRs. Hence this calculation: 148 * 149 * offset += ((channel << 1) + 1) << DMA_CSR_SLL; 150 * 151 * Here's an example: 152 * 153 * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value); 154 * Let's say channel is 3 155 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070) 156 * offset = 0x600070 157 * offset &= 0xff = 0x70 158 * offset += ((3 << 1) + 1) << 9 159 * 3 << 1 = 6 160 * 6 + 1 = 7 161 * 7 << 9 = 0xe00 162 * offset += 0xe00 = 0xe70 163 * 164 * Therefore, our register's (virtual) PIO address is 0xe70. 165 * 166 * cf. Table 10-6 on page 181 of the Neptune PRM, v 1.4: 167 * 168 * E00 - FFF CSRs for bound logical receive DMA channel 3. 169 * 170 * In a non-virtual environment, you simply multiply the absolute 171 * channel number by 512 bytes, and get the correct offset to 172 * the register you're looking for. That is, the RX_DMA_CTL_STAT CSR, 173 * is, as are all of these registers, in a table where each channel 174 * is offset 512 bytes from the previous channel (count 16 step 512). 175 * 176 * offset += (channel << DMA_CSR_SLL); // channel<<9 = channel*512 177 * 178 * Here's an example: 179 * 180 * RXDMA_REG_WRITE64(handle, RX_DMA_CTL_STAT_REG, channel, value); 181 * Let's say channel is 3 182 * #define RX_DMA_CTL_STAT_REG (DMC + 0x00070) 183 * offset = 0x600070 184 * offset += (3 << 9) 185 * 3 << 9 = 0x600 186 * offset += 0x600 = 0x600670 187 * 188 * Therefore, our register's PIO address is 0x600670. 189 * 190 * cf. Table 12-42 on page 234 of the Neptune PRM, v 1.4: 191 * RX_DMA_CTL_STAT (DMC + [0x]00070) (count 16 step [0x]200) 192 * 193 * Context: 194 * Any domain 195 * 196 */ 197extern const char *nxge_rx2str(int); 198 199void 200RXDMA_REG_WRITE64( 201 npi_handle_t handle, 202 uint64_t offset, 203 int channel, 204 uint64_t value) 205{ 206#if defined(NPI_REG_TRACE) 207 const char *name = nxge_rx2str((int)offset); 208#endif 209 if (handle.is_vraddr) { 210 offset &= DMA_CSR_MASK; 211 offset += (((channel << 1) + 1) << DMA_CSR_SLL); 212 } else { 213 offset += (channel << DMA_CSR_SLL); 214 } 215 216#if defined(__i386) 217 ddi_put64(handle.regh, 218 (uint64_t *)(handle.regp + (uint32_t)offset), value); 219#else 220 ddi_put64(handle.regh, 221 (uint64_t *)(handle.regp + offset), value); 222#endif 223 224#if defined(NPI_REG_TRACE) 225 npi_trace_update(handle, B_TRUE, &npi_rtracebuf, 226 name, (uint32_t)offset, value); 227#elif defined(REG_SHOW) 228 /* 229 * Since we don't have a valid RTBUF index to show, send 0xBADBAD. 230 */ 231 rt_show_reg(0xbadbad, B_TRUE, (uint32_t)offset, value); 232#endif 233} 234 235#ifdef __cplusplus 236} 237#endif 238 239#endif /* _NPI_RX_WR64_H */ 240