1/*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21
22/*
23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved.
24 */
25
26/*
27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved.
28 */
29
30#ifndef	_IXGBE_OSDEP_H
31#define	_IXGBE_OSDEP_H
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37#include <sys/types.h>
38#include <sys/byteorder.h>
39#include <sys/conf.h>
40#include <sys/debug.h>
41#include <sys/stropts.h>
42#include <sys/stream.h>
43#include <sys/strlog.h>
44#include <sys/kmem.h>
45#include <sys/stat.h>
46#include <sys/kstat.h>
47#include <sys/modctl.h>
48#include <sys/errno.h>
49#include <sys/ddi.h>
50#include <sys/dditypes.h>
51#include <sys/sunddi.h>
52#include <sys/pci.h>
53#include <sys/atomic.h>
54#include <sys/note.h>
55#include "ixgbe_debug.h"
56
57/* function declarations */
58struct ixgbe_hw;
59uint16_t ixgbe_read_pci_cfg(struct ixgbe_hw *, uint32_t);
60void ixgbe_write_pci_cfg(struct ixgbe_hw *, uint32_t, uint32_t);
61
62#define	usec_delay(x)		drv_usecwait(x)
63#define	msec_delay(x)		drv_usecwait(x * 1000)
64
65#define	OS_DEP(hw)		((struct ixgbe_osdep *)((hw)->back))
66
67#define	false		B_FALSE
68#define	true		B_TRUE
69
70#define	IXGBE_READ_PCIE_WORD 	ixgbe_read_pci_cfg
71#define	IXGBE_WRITE_PCIE_WORD 	ixgbe_write_pci_cfg
72#define	CMD_MEM_WRT_INVALIDATE	0x0010	/* BIT_4 */
73#define	PCI_COMMAND_REGISTER	0x04
74#define	PCI_EX_CONF_CAP		0xE0
75#define	SPEED_10GB		10000
76#define	SPEED_1GB		1000
77#define	SPEED_100		100
78#define	FULL_DUPLEX		2
79
80#define	IXGBE_WRITE_FLUSH(a)	(void) IXGBE_READ_REG(a, IXGBE_STATUS)
81
82#define	IXGBE_WRITE_REG(a, reg, value)	\
83	ddi_put32((OS_DEP(a))->reg_handle, \
84	    (uint32_t *)((uintptr_t)(a)->hw_addr + reg), (value))
85
86#define	IXGBE_WRITE_REG_ARRAY(a, reg, index, value)	\
87	IXGBE_WRITE_REG(a, ((reg) + ((index) << 2)), (value))
88
89#define	IXGBE_READ_REG(a, reg)	\
90	ddi_get32((OS_DEP(a))->reg_handle, \
91	    (uint32_t *)((uintptr_t)(a)->hw_addr + reg))
92
93#define	IXGBE_READ_REG_ARRAY(a, reg, index)	\
94	IXGBE_READ_REG(a, ((reg) + ((index) << 2)))
95
96#define	IXGBE_WRITE_REG64(hw, reg, value)	\
97	do {								\
98		IXGBE_WRITE_REG(hw, reg, (u32) value);			\
99		IXGBE_WRITE_REG(hw, reg + 4, (u32) (value >> 32));	\
100		_NOTE(CONSTCOND)					\
101	} while (0)
102
103#define	msec_delay_irq	msec_delay
104#define	IXGBE_HTONL	htonl
105
106#define	UNREFERENCED_PARAMETER(x)	_NOTE(ARGUNUSED(x))
107
108typedef	int8_t		s8;
109typedef	int16_t		s16;
110typedef	int32_t		s32;
111typedef	int64_t		s64;
112typedef uint8_t		u8;
113typedef	uint16_t 	u16;
114typedef	uint32_t	u32;
115typedef	uint64_t	u64;
116typedef boolean_t	bool;
117
118struct ixgbe_osdep {
119	ddi_acc_handle_t reg_handle;
120	ddi_acc_handle_t cfg_handle;
121	struct ixgbe *ixgbe;
122};
123
124#ifdef __cplusplus
125}
126#endif
127
128#endif	/* _IXGBE_OSDEP_H */
129