1/*
2 * Sun elects to have this file available under and governed by the BSD license
3 * (see below for full license text).  However, the following notice
4 * accompanied the original version of this file:
5 */
6
7/*
8 * Copyright (c) 2009, Intel Corporation
9 * All rights reserved.
10 */
11
12/*
13 * This file is provided under a dual BSD/GPLv2 license.  When using or
14 * redistributing this file, you may do so under either license.
15 *
16 * GPL LICENSE SUMMARY
17 *
18 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of version 2 of the GNU General Public License as
22 * published by the Free Software Foundation.
23 *
24 * This program is distributed in the hope that it will be useful, but
25 * WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
27 * General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
32 * USA
33 *
34 * The full GNU General Public License is included in this distribution
35 * in the file called LICENSE.GPL.
36 *
37 * Contact Information:
38 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
39 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
40 *
41 * BSD LICENSE
42 *
43 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
44 * All rights reserved.
45 *
46 * Redistribution and use in source and binary forms, with or without
47 * modification, are permitted provided that the following conditions
48 * are met:
49 *
50 *  * Redistributions of source code must retain the above copyright
51 *    notice, this list of conditions and the following disclaimer.
52 *  * Redistributions in binary form must reproduce the above copyright
53 *    notice, this list of conditions and the following disclaimer in
54 *    the documentation and/or other materials provided with the
55 *    distribution.
56 *  * Neither the name Intel Corporation nor the names of its
57 *    contributors may be used to endorse or promote products derived
58 *    from this software without specific prior written permission.
59 *
60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
61 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
62 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
63 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
64 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
65 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
66 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
67 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
68 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
69 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
71 */
72
73#ifndef _IWP_EEPROM_H_
74#define	_IWP_EEPROM_H_
75
76/*
77 * This file defines EEPROM related constants, enums, and inline functions.
78 */
79
80/*
81 * EEPROM field values
82 */
83#define	ANTENNA_SWITCH_NORMAL		0
84#define	ANTENNA_SWITCH_INVERSE		1
85
86enum {
87	EEPROM_CHANNEL_VALID = (1 << 0),	/* usable for this SKU/geo */
88	EEPROM_CHANNEL_IBSS = (1 << 1),	/* usable as an IBSS channel */
89	/* Bit 2 Reserved */
90	EEPROM_CHANNEL_ACTIVE = (1 << 3),	/* active scanning allowed */
91	EEPROM_CHANNEL_RADAR = (1 << 4),	/* radar detection required */
92	EEPROM_CHANNEL_WIDE = (1 << 5),
93	EEPROM_CHANNEL_NARROW = (1 << 6),
94	EEPROM_CHANNEL_DFS = (1 << 7),	/* dynamic freq selection candidate */
95};
96
97/*
98 * EEPROM field lengths
99 */
100#define	EEPROM_BOARD_PBA_NUMBER_LENGTH		11
101
102/*
103 * EEPROM field lengths
104 */
105#define	EEPROM_BOARD_PBA_NUMBER_LENGTH		11
106#define	EEPROM_REGULATORY_SKU_ID_LENGTH		4
107#define	EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH	14
108#define	EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH	13
109#define	EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH	12
110#define	EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH	11
111#define	EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH	6
112
113
114#define	EEPROM_REGULATORY_NUMBER_OF_BANDS	5
115
116/*
117 * SKU Capabilities
118 */
119#define	EEPROM_SKU_CAP_SW_RF_KILL_ENABLE	(1 << 0)
120#define	EEPROM_SKU_CAP_HW_RF_KILL_ENABLE	(1 << 1)
121#define	EEPROM_SKU_CAP_OP_MODE_MRC		(1 << 7)
122
123/*
124 * *regulatory* channel data from eeprom, one for each channel
125 */
126struct iwl_eeprom_channel {
127	uint8_t flags;		/* flags copied from EEPROM */
128	int8_t max_power_avg;	/* max power (dBm) on this chnl, limit 31 */
129};
130
131/*
132 * Mapping of a Tx power level, at factory calibration temperature,
133 *   to a radio/DSP gain table index.
134 * One for each of 5 "sample" power levels in each band.
135 * v_det is measured at the factory, using the 3945's built-in power amplifier
136 *   (PA) output voltage detector.  This same detector is used during Tx of
137 *   long packets in normal operation to provide feedback as to proper output
138 *   level.
139 * Data copied from EEPROM.
140 */
141struct iwl_eeprom_txpower_sample {
142	uint8_t gain_index;	/* index into power (gain) setup table ... */
143	int8_t power;		/* ... for this pwr level for this chnl group */
144	uint16_t v_det;		/* PA output voltage */
145};
146
147/*
148 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
149 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
150 * Tx power setup code interpolates between the 5 "sample" power levels
151 *    to determine the nominal setup for a requested power level.
152 * Data copied from EEPROM.
153 * DO NOT ALTER THIS STRUCTURE!!!
154 */
155struct iwl_eeprom_txpower_group {
156	/* 5 power levels */
157	struct iwl_eeprom_txpower_sample samples[5];
158	/* coefficients for voltage->power formula (signed) */
159	uint32_t a, b, c, d, e;
160	/* these modify coeffs based on frequency (signed) */
161	uint32_t Fa, Fb, Fc, Fd, Fe;
162	/* highest power possible by h/w in this * band */
163	int8_t saturation_power;
164	/* "representative" channel # in this band */
165	uint8_t group_channel;
166	/* h/w temperature at factory calib this band (signed) */
167	uint16_t temperature;
168};
169
170/*
171 * Temperature-based Tx-power compensation data, not band-specific.
172 * These coefficients are use to modify a/b/c/d/e coeffs based on
173 *   difference between current temperature and factory calib temperature.
174 * Data copied from EEPROM.
175 */
176struct iwl_eeprom_temperature_corr {
177	uint32_t Ta;
178	uint32_t Tb;
179	uint32_t Tc;
180	uint32_t Td;
181	uint32_t Te;
182};
183
184
185/*
186 * eeprom map
187 */
188#define	EEP_MAC_ADDRESS	42	/* chipset's MAC address 6 bytes */
189#define	EEP_VERSION	136	/* eeprom version 2 bytes */
190#define	EEP_SP_RADIO_CONFIGURATION	144	/* SP's radio configuration */
191
192
193
194#define	CSR_EEPROM_REG			(CSR_BASE+0x02c)
195#define	CSR_EEPROM_GP			(CSR_BASE+0x030)
196#define	CSR_EEPROM_GP_VALID_MSK		0x00000007
197#define	CSR_EEPROM_GP_BAD_SIGNATURE	0x00000000
198#define	IWP_SP_EEPROM_SIZE	2048
199
200#define	IWP_READ_EEP_SHORT(sc, addr)	((((uint16_t)sc->sc_eep_map[addr + 1])\
201					    << 8) |\
202					    ((uint16_t)sc->sc_eep_map[addr]))
203
204#define	SP_RADIO_TYPE_3x3	(0)
205#define	SP_RADIO_TYPE_2x2	(1)
206#define	SP_RADIO_TYPE_1x2	(2)
207#define	SP_RADIO_TYPE_MAX	(3)
208
209#define	SP_RADIO_TYPE_MSK(x)	(x & 3)
210#define	SP_RADIO_STEP_MSK(x)	((x>>2) & 3)
211#define	SP_RADIO_DASH_MSK(x)	((x>>4) & 3)
212#define	SP_RADIO_PNUM_MSK(x)	((x>>6) & 3)
213#define	SP_RADIO_TX_CHAIN_MSK(x)	((x>>8) & 0xf)
214#define	SP_RADIO_RX_CHAIN_MSK(x)	((x>>12) & 0xf)
215
216#define	ADDRESS_MSK		0x0000ffff
217#define	INDIRECT_TYPE_MSK	0x000f0000
218#define	INDIRECT_HOST		0x00010000
219#define	INDIRECT_GENERAL	0x00020000
220#define	INDIRECT_REGULATORY	0x00030000
221#define	INDIRECT_CALIBRATION	0x00040000
222#define	INDIRECT_PROCESS_ADJST	0x00050000
223#define	INDIRECT_OTHERS		0x00060000
224#define	INDIRECT_ADDRESS	0x00100000
225
226#define	EEP_LINK_HOST		(200)
227#define	EEP_LINK_GENERAL	(202)
228#define	EEP_LINK_REGULATORY	(204)
229#define	EEP_LINK_CALIBRATION	(206)
230#define	EEP_LINK_PROCESS_ADJST	(208)
231#define	EEP_LINK_OTHERS		(210)
232
233#define	EEP_CALIBRATION		((0x00) | INDIRECT_ADDRESS |\
234				    INDIRECT_CALIBRATION)
235
236#define	EEP_TX_POWER_TX_CHAINS	(3)
237#define	EEP_RXIQ_CAL_CHANNELS	(7)
238#define	EEP_CAL_CHANNEL_GROUP	(7)
239#define	EEP_RXIQ_DRIVER_MODES	(12)
240
241
242
243#endif /* _IWP_EEPROM_H_ */
244