1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright(c) 2007-2010 Intel Corporation. All rights reserved. 24 */ 25 26/* 27 * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 28 */ 29 30/* IntelVersion: 1.108 v3_3_14_3_BHSW1 */ 31 32#include "igb_api.h" 33 34static s32 e1000_set_default_fc_generic(struct e1000_hw *hw); 35static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw); 36static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw); 37static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw); 38static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw); 39 40/* 41 * e1000_init_mac_ops_generic - Initialize MAC function pointers 42 * @hw: pointer to the HW structure 43 * 44 * Setups up the function pointers to no-op functions 45 */ 46void 47e1000_init_mac_ops_generic(struct e1000_hw *hw) 48{ 49 struct e1000_mac_info *mac = &hw->mac; 50 DEBUGFUNC("e1000_init_mac_ops_generic"); 51 52 /* General Setup */ 53 mac->ops.init_params = e1000_null_ops_generic; 54 mac->ops.init_hw = e1000_null_ops_generic; 55 mac->ops.reset_hw = e1000_null_ops_generic; 56 mac->ops.setup_physical_interface = e1000_null_ops_generic; 57 mac->ops.get_bus_info = e1000_null_ops_generic; 58 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; 59 mac->ops.read_mac_addr = e1000_read_mac_addr_generic; 60 mac->ops.config_collision_dist = e1000_config_collision_dist_generic; 61 mac->ops.clear_hw_cntrs = e1000_null_mac_generic; 62 /* LED */ 63 mac->ops.cleanup_led = e1000_null_ops_generic; 64 mac->ops.setup_led = e1000_null_ops_generic; 65 mac->ops.blink_led = e1000_null_ops_generic; 66 mac->ops.led_on = e1000_null_ops_generic; 67 mac->ops.led_off = e1000_null_ops_generic; 68 /* LINK */ 69 mac->ops.setup_link = e1000_null_ops_generic; 70 mac->ops.get_link_up_info = e1000_null_link_info; 71 mac->ops.check_for_link = e1000_null_ops_generic; 72 mac->ops.wait_autoneg = e1000_wait_autoneg_generic; 73 /* Management */ 74 mac->ops.check_mng_mode = e1000_null_mng_mode; 75 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic; 76 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic; 77 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic; 78 /* VLAN, MC, etc. */ 79 mac->ops.update_mc_addr_list = e1000_null_update_mc; 80 mac->ops.clear_vfta = e1000_null_mac_generic; 81 mac->ops.write_vfta = e1000_null_write_vfta; 82 mac->ops.mta_set = e1000_null_mta_set; 83 mac->ops.rar_set = e1000_rar_set_generic; 84 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic; 85} 86 87/* 88 * e1000_null_ops_generic - No-op function, returns 0 89 * @hw: pointer to the HW structure 90 */ 91s32 92e1000_null_ops_generic(struct e1000_hw *hw) 93{ 94 DEBUGFUNC("e1000_null_ops_generic"); 95 UNREFERENCED_1PARAMETER(hw); 96 return (E1000_SUCCESS); 97} 98 99/* 100 * e1000_null_mac_generic - No-op function, return void 101 * @hw: pointer to the HW structure 102 */ 103void 104e1000_null_mac_generic(struct e1000_hw *hw) 105{ 106 DEBUGFUNC("e1000_null_mac_generic"); 107 UNREFERENCED_1PARAMETER(hw); 108} 109 110/* 111 * e1000_null_link_info - No-op function, return 0 112 * @hw: pointer to the HW structure 113 */ 114s32 115e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d) 116{ 117 DEBUGFUNC("e1000_null_link_info"); 118 UNREFERENCED_3PARAMETER(hw, s, d); 119 return (E1000_SUCCESS); 120} 121 122/* 123 * e1000_null_mng_mode - No-op function, return false 124 * @hw: pointer to the HW structure 125 */ 126bool 127e1000_null_mng_mode(struct e1000_hw *hw) 128{ 129 DEBUGFUNC("e1000_null_mng_mode"); 130 UNREFERENCED_1PARAMETER(hw); 131 return (false); 132} 133 134/* 135 * e1000_null_update_mc - No-op function, return void 136 * @hw: pointer to the HW structure 137 */ 138void 139e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a) 140{ 141 DEBUGFUNC("e1000_null_update_mc"); 142 UNREFERENCED_3PARAMETER(hw, h, a); 143} 144 145/* 146 * e1000_null_write_vfta - No-op function, return void 147 * @hw: pointer to the HW structure 148 */ 149void 150e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b) 151{ 152 DEBUGFUNC("e1000_null_write_vfta"); 153 UNREFERENCED_3PARAMETER(hw, a, b); 154} 155 156/* 157 * e1000_null_set_mta - No-op function, return void 158 * @hw: pointer to the HW structure 159 */ 160void 161e1000_null_mta_set(struct e1000_hw *hw, u32 a) 162{ 163 DEBUGFUNC("e1000_null_mta_set"); 164 UNREFERENCED_2PARAMETER(hw, a); 165} 166 167/* 168 * e1000_null_rar_set - No-op function, return void 169 * @hw: pointer to the HW structure 170 */ 171void 172e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a) 173{ 174 DEBUGFUNC("e1000_null_rar_set"); 175 UNREFERENCED_3PARAMETER(hw, h, a); 176} 177 178/* 179 * e1000_get_bus_info_pcie_generic - Get PCIe bus information 180 * @hw: pointer to the HW structure 181 * 182 * Determines and stores the system bus information for a particular 183 * network interface. The following bus information is determined and stored: 184 * bus speed, bus width, type (PCIe), and PCIe function. 185 */ 186s32 187e1000_get_bus_info_pcie_generic(struct e1000_hw *hw) 188{ 189 struct e1000_mac_info *mac = &hw->mac; 190 struct e1000_bus_info *bus = &hw->bus; 191 s32 ret_val; 192 u16 pcie_link_status; 193 194 DEBUGFUNC("e1000_get_bus_info_pcie_generic"); 195 196 bus->type = e1000_bus_type_pci_express; 197 bus->speed = e1000_bus_speed_2500; 198 199 ret_val = e1000_read_pcie_cap_reg(hw, 200 PCIE_LINK_STATUS, &pcie_link_status); 201 if (ret_val) 202 bus->width = e1000_bus_width_unknown; 203 else 204 bus->width = (enum e1000_bus_width)((pcie_link_status & 205 PCIE_LINK_WIDTH_MASK) >> PCIE_LINK_WIDTH_SHIFT); 206 207 mac->ops.set_lan_id(hw); 208 209 return (E1000_SUCCESS); 210} 211 212/* 213 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 214 * 215 * @hw: pointer to the HW structure 216 * 217 * Determines the LAN function id by reading memory-mapped registers 218 * and swaps the port value if requested. 219 */ 220static void 221e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 222{ 223 struct e1000_bus_info *bus = &hw->bus; 224 u32 reg; 225 226 /* 227 * The status register reports the correct function number 228 * for the device regardless of function swap state. 229 */ 230 reg = E1000_READ_REG(hw, E1000_STATUS); 231 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 232} 233 234/* 235 * e1000_set_lan_id_single_port - Set LAN id for a single port device 236 * @hw: pointer to the HW structure 237 * 238 * Sets the LAN function id to zero for a single port device. 239 */ 240void 241e1000_set_lan_id_single_port(struct e1000_hw *hw) 242{ 243 struct e1000_bus_info *bus = &hw->bus; 244 245 bus->func = 0; 246} 247 248/* 249 * e1000_clear_vfta_generic - Clear VLAN filter table 250 * @hw: pointer to the HW structure 251 * 252 * Clears the register array which contains the VLAN filter table by 253 * setting all the values to 0. 254 */ 255void 256e1000_clear_vfta_generic(struct e1000_hw *hw) 257{ 258 u32 offset; 259 260 DEBUGFUNC("e1000_clear_vfta_generic"); 261 262 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 263 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 264 E1000_WRITE_FLUSH(hw); 265 } 266} 267 268/* 269 * e1000_write_vfta_generic - Write value to VLAN filter table 270 * @hw: pointer to the HW structure 271 * @offset: register offset in VLAN filter table 272 * @value: register value written to VLAN filter table 273 * 274 * Writes value at the given offset in the register array which stores 275 * the VLAN filter table. 276 */ 277void 278e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 279{ 280 DEBUGFUNC("e1000_write_vfta_generic"); 281 282 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 283 E1000_WRITE_FLUSH(hw); 284} 285 286/* 287 * e1000_init_rx_addrs_generic - Initialize receive address's 288 * @hw: pointer to the HW structure 289 * @rar_count: receive address registers 290 * 291 * Setups the receive address registers by setting the base receive address 292 * register to the devices MAC address and clearing all the other receive 293 * address registers to 0. 294 */ 295void 296e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count) 297{ 298 u32 i; 299 u8 mac_addr[ETH_ADDR_LEN] = {0}; 300 301 DEBUGFUNC("e1000_init_rx_addrs_generic"); 302 303 /* Setup the receive address */ 304 DEBUGOUT("Programming MAC Address into RAR[0]\n"); 305 306 hw->mac.ops.rar_set(hw, hw->mac.addr, 0); 307 308 /* Zero out the other (rar_entry_count - 1) receive addresses */ 309 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1); 310 for (i = 1; i < rar_count; i++) 311 hw->mac.ops.rar_set(hw, mac_addr, i); 312} 313 314/* 315 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 316 * @hw: pointer to the HW structure 317 * 318 * Checks the nvm for an alternate MAC address. An alternate MAC address 319 * can be setup by pre-boot software and must be treated like a permanent 320 * address and must override the actual permanent MAC address. If an 321 * alternate MAC address is found it is programmed into RAR0, replacing 322 * the permanent address that was installed into RAR0 by the Si on reset. 323 * This function will return SUCCESS unless it encounters an error while 324 * reading the EEPROM. 325 */ 326s32 327e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 328{ 329 u32 i; 330 s32 ret_val = E1000_SUCCESS; 331 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 332 u8 alt_mac_addr[ETH_ADDR_LEN]; 333 334 DEBUGFUNC("e1000_check_alt_mac_addr_generic"); 335 336 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1, 337 &nvm_alt_mac_addr_offset); 338 if (ret_val) { 339 DEBUGOUT("NVM Read Error\n"); 340 goto out; 341 } 342 343 if (nvm_alt_mac_addr_offset == 0xFFFF) { 344 /* There is no Alternate MAC Address */ 345 goto out; 346 } 347 348 if (hw->bus.func == E1000_FUNC_1) 349 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 350 if (hw->bus.func == E1000_FUNC_2) 351 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2; 352 if (hw->bus.func == E1000_FUNC_3) 353 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3; 354 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 355 offset = nvm_alt_mac_addr_offset + (i >> 1); 356 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 357 if (ret_val) { 358 DEBUGOUT("NVM Read Error\n"); 359 goto out; 360 } 361 362 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 363 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 364 } 365 366 /* if multicast bit is set, the alternate address will not be used */ 367 if (alt_mac_addr[0] & 0x01) { 368 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n"); 369 goto out; 370 } 371 372 /* 373 * We have a valid alternate MAC address, and we want to treat it the 374 * same as the normal permanent MAC address stored by the HW into the 375 * RAR. Do this by mapping this address into RAR0. 376 */ 377 hw->mac.ops.rar_set(hw, alt_mac_addr, 0); 378 379out: 380 return (ret_val); 381} 382 383/* 384 * e1000_rar_set_generic - Set receive address register 385 * @hw: pointer to the HW structure 386 * @addr: pointer to the receive address 387 * @index: receive address array register 388 * 389 * Sets the receive address array register at index to the address passed 390 * in by addr. 391 */ 392void 393e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index) 394{ 395 u32 rar_low, rar_high; 396 397 DEBUGFUNC("e1000_rar_set_generic"); 398 399 /* 400 * HW expects these in little endian so we reverse the byte order 401 * from network order (big endian) to little endian 402 */ 403 rar_low = ((u32) addr[0] | 404 ((u32) addr[1] << 8) | 405 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 406 407 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 408 409 /* If MAC address zero, no need to set the AV bit */ 410 if (rar_low || rar_high) 411 rar_high |= E1000_RAH_AV; 412 413 /* 414 * Some bridges will combine consecutive 32-bit writes into 415 * a single burst write, which will malfunction on some parts. 416 * The flushes avoid this. 417 */ 418 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low); 419 E1000_WRITE_FLUSH(hw); 420 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high); 421 E1000_WRITE_FLUSH(hw); 422} 423 424/* 425 * e1000_mta_set_generic - Set multicast filter table address 426 * @hw: pointer to the HW structure 427 * @hash_value: determines the MTA register and bit to set 428 * 429 * The multicast table address is a register array of 32-bit registers. 430 * The hash_value is used to determine what register the bit is in, the 431 * current value is read, the new bit is OR'd in and the new value is 432 * written back into the register. 433 */ 434void 435e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value) 436{ 437 u32 hash_bit, hash_reg, mta; 438 439 DEBUGFUNC("e1000_mta_set_generic"); 440 /* 441 * The MTA is a register array of 32-bit registers. It is 442 * treated like an array of (32*mta_reg_count) bits. We want to 443 * set bit BitArray[hash_value]. So we figure out what register 444 * the bit is in, read it, OR in the new bit, then write 445 * back the new value. The (hw->mac.mta_reg_count - 1) serves as a 446 * mask to bits 31:5 of the hash value which gives us the 447 * register we're modifying. The hash bit within that register 448 * is determined by the lower 5 bits of the hash value. 449 */ 450 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 451 hash_bit = hash_value & 0x1F; 452 453 mta = E1000_READ_REG_ARRAY(hw, E1000_MTA, hash_reg); 454 455 mta |= (1 << hash_bit); 456 457 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, hash_reg, mta); 458 E1000_WRITE_FLUSH(hw); 459} 460 461/* 462 * e1000_update_mc_addr_list_generic - Update Multicast addresses 463 * @hw: pointer to the HW structure 464 * @mc_addr_list: array of multicast addresses to program 465 * @mc_addr_count: number of multicast addresses to program 466 * 467 * Updates the Multicast Table Array. 468 * The caller must have a packed mc_addr_list of multicast addresses. 469 */ 470void 471e1000_update_mc_addr_list_generic(struct e1000_hw *hw, 472 u8 *mc_addr_list, u32 mc_addr_count) 473{ 474 u32 hash_value, hash_bit, hash_reg; 475 int i; 476 477 DEBUGFUNC("e1000_update_mc_addr_list_generic"); 478 479 /* clear mta_shadow */ 480 (void) memset(&hw->mac.mta_shadow, 0, sizeof (hw->mac.mta_shadow)); 481 482 /* update mta_shadow from mc_addr_list */ 483 for (i = 0; (u32) i < mc_addr_count; i++) { 484 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list); 485 486 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 487 hash_bit = hash_value & 0x1F; 488 489 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 490 mc_addr_list += (ETH_ADDR_LEN); 491 } 492 493 /* replace the entire MTA table */ 494 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 495 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 496 E1000_WRITE_FLUSH(hw); 497} 498 499/* 500 * e1000_hash_mc_addr_generic - Generate a multicast hash value 501 * @hw: pointer to the HW structure 502 * @mc_addr: pointer to a multicast address 503 * 504 * Generates a multicast address hash value which is used to determine 505 * the multicast filter table array address and new table value. See 506 * e1000_mta_set_generic() 507 */ 508u32 509e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr) 510{ 511 u32 hash_value, hash_mask; 512 u8 bit_shift = 0; 513 514 DEBUGFUNC("e1000_hash_mc_addr_generic"); 515 516 /* Register count multiplied by bits per register */ 517 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 518 519 /* 520 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 521 * where 0xFF would still fall within the hash mask. 522 */ 523 while (hash_mask >> bit_shift != 0xFF) 524 bit_shift++; 525 526 /* 527 * The portion of the address that is used for the hash table 528 * is determined by the mc_filter_type setting. 529 * The algorithm is such that there is a total of 8 bits of shifting. 530 * The bit_shift for a mc_filter_type of 0 represents the number of 531 * left-shifts where the MSB of mc_addr[5] would still fall within 532 * the hash_mask. Case 0 does this exactly. Since there are a total 533 * of 8 bits of shifting, then mc_addr[4] will shift right the 534 * remaining number of bits. Thus 8 - bit_shift. The rest of the 535 * cases are a variation of this algorithm...essentially raising the 536 * number of bits to shift mc_addr[5] left, while still keeping the 537 * 8-bit shifting total. 538 * 539 * For example, given the following Destination MAC Address and an 540 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 541 * we can see that the bit_shift for case 0 is 4. These are the hash 542 * values resulting from each mc_filter_type... 543 * [0] [1] [2] [3] [4] [5] 544 * 01 AA 00 12 34 56 545 * LSB MSB 546 * 547 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 548 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 549 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 550 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 551 */ 552 switch (hw->mac.mc_filter_type) { 553 default: 554 case 0: 555 break; 556 case 1: 557 bit_shift += 1; 558 break; 559 case 2: 560 bit_shift += 2; 561 break; 562 case 3: 563 bit_shift += 4; 564 break; 565 } 566 567 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 568 (((u16) mc_addr[5]) << bit_shift))); 569 570 return (hash_value); 571} 572 573/* 574 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters 575 * @hw: pointer to the HW structure 576 * 577 * Clears the base hardware counters by reading the counter registers. 578 */ 579void 580e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw) 581{ 582 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic"); 583 584 (void) E1000_READ_REG(hw, E1000_CRCERRS); 585 (void) E1000_READ_REG(hw, E1000_SYMERRS); 586 (void) E1000_READ_REG(hw, E1000_MPC); 587 (void) E1000_READ_REG(hw, E1000_SCC); 588 (void) E1000_READ_REG(hw, E1000_ECOL); 589 (void) E1000_READ_REG(hw, E1000_MCC); 590 (void) E1000_READ_REG(hw, E1000_LATECOL); 591 (void) E1000_READ_REG(hw, E1000_COLC); 592 (void) E1000_READ_REG(hw, E1000_DC); 593 (void) E1000_READ_REG(hw, E1000_SEC); 594 (void) E1000_READ_REG(hw, E1000_RLEC); 595 (void) E1000_READ_REG(hw, E1000_XONRXC); 596 (void) E1000_READ_REG(hw, E1000_XONTXC); 597 (void) E1000_READ_REG(hw, E1000_XOFFRXC); 598 (void) E1000_READ_REG(hw, E1000_XOFFTXC); 599 (void) E1000_READ_REG(hw, E1000_FCRUC); 600 (void) E1000_READ_REG(hw, E1000_GPRC); 601 (void) E1000_READ_REG(hw, E1000_BPRC); 602 (void) E1000_READ_REG(hw, E1000_MPRC); 603 (void) E1000_READ_REG(hw, E1000_GPTC); 604 (void) E1000_READ_REG(hw, E1000_GORCL); 605 (void) E1000_READ_REG(hw, E1000_GORCH); 606 (void) E1000_READ_REG(hw, E1000_GOTCL); 607 (void) E1000_READ_REG(hw, E1000_GOTCH); 608 (void) E1000_READ_REG(hw, E1000_RNBC); 609 (void) E1000_READ_REG(hw, E1000_RUC); 610 (void) E1000_READ_REG(hw, E1000_RFC); 611 (void) E1000_READ_REG(hw, E1000_ROC); 612 (void) E1000_READ_REG(hw, E1000_RJC); 613 (void) E1000_READ_REG(hw, E1000_TORL); 614 (void) E1000_READ_REG(hw, E1000_TORH); 615 (void) E1000_READ_REG(hw, E1000_TOTL); 616 (void) E1000_READ_REG(hw, E1000_TOTH); 617 (void) E1000_READ_REG(hw, E1000_TPR); 618 (void) E1000_READ_REG(hw, E1000_TPT); 619 (void) E1000_READ_REG(hw, E1000_MPTC); 620 (void) E1000_READ_REG(hw, E1000_BPTC); 621} 622 623/* 624 * e1000_check_for_copper_link_generic - Check for link (Copper) 625 * @hw: pointer to the HW structure 626 * 627 * Checks to see of the link status of the hardware has changed. If a 628 * change in link status has been detected, then we read the PHY registers 629 * to get the current speed/duplex if link exists. 630 */ 631s32 632e1000_check_for_copper_link_generic(struct e1000_hw *hw) 633{ 634 struct e1000_mac_info *mac = &hw->mac; 635 s32 ret_val; 636 bool link; 637 638 DEBUGFUNC("e1000_check_for_copper_link"); 639 640 /* 641 * We only want to go out to the PHY registers to see if Auto-Neg 642 * has completed and/or if our link status has changed. The 643 * get_link_status flag is set upon receiving a Link Status 644 * Change or Rx Sequence Error interrupt. 645 */ 646 if (!mac->get_link_status) { 647 ret_val = E1000_SUCCESS; 648 goto out; 649 } 650 651 /* 652 * First we want to see if the MII Status Register reports 653 * link. If so, then we want to get the current speed/duplex 654 * of the PHY. 655 */ 656 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 657 if (ret_val) 658 goto out; 659 660 if (!link) 661 goto out; /* No link detected */ 662 663 mac->get_link_status = false; 664 665 /* 666 * Check if there was DownShift, must be checked 667 * immediately after link-up 668 */ 669 (void) e1000_check_downshift_generic(hw); 670 671 /* 672 * If we are forcing speed/duplex, then we simply return since 673 * we have already determined whether we have link or not. 674 */ 675 if (!mac->autoneg) { 676 ret_val = -E1000_ERR_CONFIG; 677 goto out; 678 } 679 680 /* 681 * Auto-Neg is enabled. Auto Speed Detection takes care 682 * of MAC speed/duplex configuration. So we only need to 683 * configure Collision Distance in the MAC. 684 */ 685 e1000_config_collision_dist_generic(hw); 686 687 /* 688 * Configure Flow Control now that Auto-Neg has completed. 689 * First, we need to restore the desired flow control 690 * settings because we may have had to re-autoneg with a 691 * different link partner. 692 */ 693 ret_val = e1000_config_fc_after_link_up_generic(hw); 694 if (ret_val) 695 DEBUGOUT("Error configuring flow control\n"); 696 697out: 698 return (ret_val); 699} 700 701/* 702 * e1000_check_for_fiber_link_generic - Check for link (Fiber) 703 * @hw: pointer to the HW structure 704 * 705 * Checks for link up on the hardware. If link is not up and we have 706 * a signal, then we need to force link up. 707 */ 708s32 709e1000_check_for_fiber_link_generic(struct e1000_hw *hw) 710{ 711 struct e1000_mac_info *mac = &hw->mac; 712 u32 rxcw; 713 u32 ctrl; 714 u32 status; 715 s32 ret_val = E1000_SUCCESS; 716 717 DEBUGFUNC("e1000_check_for_fiber_link_generic"); 718 719 ctrl = E1000_READ_REG(hw, E1000_CTRL); 720 status = E1000_READ_REG(hw, E1000_STATUS); 721 rxcw = E1000_READ_REG(hw, E1000_RXCW); 722 723 /* 724 * If we don't have link (auto-negotiation failed or link partner 725 * cannot auto-negotiate), the cable is plugged in (we have signal), 726 * and our link partner is not trying to auto-negotiate with us (we 727 * are receiving idles or data), we need to force link up. We also 728 * need to give auto-negotiation time to complete, in case the cable 729 * was just plugged in. The autoneg_failed flag does this. 730 */ 731 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 732 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) && 733 (!(rxcw & E1000_RXCW_C))) { 734 if (mac->autoneg_failed == 0) { 735 mac->autoneg_failed = 1; 736 goto out; 737 } 738 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 739 740 /* Disable auto-negotiation in the TXCW register */ 741 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 742 743 /* Force link-up and also force full-duplex. */ 744 ctrl = E1000_READ_REG(hw, E1000_CTRL); 745 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 746 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 747 748 /* Configure Flow Control after forcing link up. */ 749 ret_val = e1000_config_fc_after_link_up_generic(hw); 750 if (ret_val) { 751 DEBUGOUT("Error configuring flow control\n"); 752 goto out; 753 } 754 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 755 /* 756 * If we are forcing link and we are receiving /C/ ordered 757 * sets, re-enable auto-negotiation in the TXCW register 758 * and disable forced link in the Device Control register 759 * in an attempt to auto-negotiate with our link partner. 760 */ 761 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 762 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 763 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 764 765 mac->serdes_has_link = true; 766 } 767 768out: 769 return (ret_val); 770} 771 772/* 773 * e1000_check_for_serdes_link_generic - Check for link (Serdes) 774 * @hw: pointer to the HW structure 775 * 776 * Checks for link up on the hardware. If link is not up and we have 777 * a signal, then we need to force link up. 778 */ 779s32 780e1000_check_for_serdes_link_generic(struct e1000_hw *hw) 781{ 782 struct e1000_mac_info *mac = &hw->mac; 783 u32 rxcw; 784 u32 ctrl; 785 u32 status; 786 s32 ret_val = E1000_SUCCESS; 787 788 DEBUGFUNC("e1000_check_for_serdes_link_generic"); 789 790 ctrl = E1000_READ_REG(hw, E1000_CTRL); 791 status = E1000_READ_REG(hw, E1000_STATUS); 792 rxcw = E1000_READ_REG(hw, E1000_RXCW); 793 794 /* 795 * If we don't have link (auto-negotiation failed or link partner 796 * cannot auto-negotiate), and our link partner is not trying to 797 * auto-negotiate with us (we are receiving idles or data), 798 * we need to force link up. We also need to give auto-negotiation 799 * time to complete. 800 */ 801 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 802 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) { 803 if (mac->autoneg_failed == 0) { 804 mac->autoneg_failed = 1; 805 goto out; 806 } 807 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n"); 808 809 /* Disable auto-negotiation in the TXCW register */ 810 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 811 812 /* Force link-up and also force full-duplex. */ 813 ctrl = E1000_READ_REG(hw, E1000_CTRL); 814 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 815 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 816 817 /* Configure Flow Control after forcing link up. */ 818 ret_val = e1000_config_fc_after_link_up_generic(hw); 819 if (ret_val) { 820 DEBUGOUT("Error configuring flow control\n"); 821 goto out; 822 } 823 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 824 /* 825 * If we are forcing link and we are receiving /C/ ordered 826 * sets, re-enable auto-negotiation in the TXCW register 827 * and disable forced link in the Device Control register 828 * in an attempt to auto-negotiate with our link partner. 829 */ 830 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n"); 831 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw); 832 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU)); 833 834 mac->serdes_has_link = true; 835 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) { 836 /* 837 * If we force link for non-auto-negotiation switch, check 838 * link status based on MAC synchronization for internal 839 * serdes media type. 840 */ 841 /* SYNCH bit and IV bit are sticky. */ 842 usec_delay(10); 843 rxcw = E1000_READ_REG(hw, E1000_RXCW); 844 if (rxcw & E1000_RXCW_SYNCH) { 845 if (!(rxcw & E1000_RXCW_IV)) { 846 mac->serdes_has_link = true; 847 DEBUGOUT("SERDES: Link up - forced.\n"); 848 } 849 } else { 850 mac->serdes_has_link = false; 851 DEBUGOUT("SERDES: Link down - force failed.\n"); 852 } 853 } 854 855 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) { 856 status = E1000_READ_REG(hw, E1000_STATUS); 857 if (status & E1000_STATUS_LU) { 858 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 859 usec_delay(10); 860 rxcw = E1000_READ_REG(hw, E1000_RXCW); 861 if (rxcw & E1000_RXCW_SYNCH) { 862 if (!(rxcw & E1000_RXCW_IV)) { 863 mac->serdes_has_link = true; 864 DEBUGOUT("SERDES: Link up - autoneg " 865 "completed sucessfully.\n"); 866 } else { 867 mac->serdes_has_link = false; 868 DEBUGOUT("SERDES: Link down - invalid" 869 "codewords detected in autoneg.\n"); 870 } 871 } else { 872 mac->serdes_has_link = false; 873 DEBUGOUT("SERDES: Link down - no sync.\n"); 874 } 875 } else { 876 mac->serdes_has_link = false; 877 DEBUGOUT("SERDES: Link down - autoneg failed\n"); 878 } 879 } 880 881out: 882 return (ret_val); 883} 884 885/* 886 * e1000_setup_link_generic - Setup flow control and link settings 887 * @hw: pointer to the HW structure 888 * 889 * Determines which flow control settings to use, then configures flow 890 * control. Calls the appropriate media-specific link configuration 891 * function. Assuming the adapter has a valid link partner, a valid link 892 * should be established. Assumes the hardware has previously been reset 893 * and the transmitter and receiver are not enabled. 894 */ 895s32 896e1000_setup_link_generic(struct e1000_hw *hw) 897{ 898 s32 ret_val = E1000_SUCCESS; 899 900 DEBUGFUNC("e1000_setup_link_generic"); 901 902 /* 903 * In the case of the phy reset being blocked, we already have a link. 904 * We do not need to set it up again. 905 */ 906 if (hw->phy.ops.check_reset_block) 907 if (hw->phy.ops.check_reset_block(hw)) 908 goto out; 909 910 /* 911 * If requested flow control is set to default, set flow control 912 * based on the EEPROM flow control settings. 913 */ 914 if (hw->fc.requested_mode == e1000_fc_default) { 915 ret_val = e1000_set_default_fc_generic(hw); 916 if (ret_val) 917 goto out; 918 } 919 920 /* 921 * Save off the requested flow control mode for use later. Depending 922 * on the link partner's capabilities, we may or may not use this mode. 923 */ 924 hw->fc.current_mode = hw->fc.requested_mode; 925 926 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 927 hw->fc.current_mode); 928 929 /* Call the necessary media_type subroutine to configure the link. */ 930 ret_val = hw->mac.ops.setup_physical_interface(hw); 931 if (ret_val) 932 goto out; 933 934 /* 935 * Initialize the flow control address, type, and PAUSE timer 936 * registers to their default values. This is done even if flow 937 * control is disabled, because it does not hurt anything to 938 * initialize these registers. 939 */ 940 DEBUGOUT("Initializing the Flow Control address,type and timer regs\n"); 941 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 942 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 943 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 944 945 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 946 947 ret_val = e1000_set_fc_watermarks_generic(hw); 948 949out: 950 return (ret_val); 951} 952 953/* 954 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes 955 * @hw: pointer to the HW structure 956 * 957 * Configures collision distance and flow control for fiber and serdes 958 * links. Upon successful setup, poll for link. 959 */ 960s32 961e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw) 962{ 963 u32 ctrl; 964 s32 ret_val = E1000_SUCCESS; 965 966 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic"); 967 968 ctrl = E1000_READ_REG(hw, E1000_CTRL); 969 970 /* Take the link out of reset */ 971 ctrl &= ~E1000_CTRL_LRST; 972 973 e1000_config_collision_dist_generic(hw); 974 975 ret_val = e1000_commit_fc_settings_generic(hw); 976 if (ret_val) 977 goto out; 978 979 /* 980 * Since auto-negotiation is enabled, take the link out of reset (the 981 * link will be in reset, because we previously reset the chip). This 982 * will restart auto-negotiation. If auto-negotiation is successful 983 * then the link-up status bit will be set and the flow control enable 984 * bits (RFCE and TFCE) will be set according to their negotiated value. 985 */ 986 DEBUGOUT("Auto-negotiation enabled\n"); 987 988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 989 E1000_WRITE_FLUSH(hw); 990 msec_delay(1); 991 992 /* 993 * For these adapters, the SW definable pin 1 is set when the optics 994 * detect a signal. If we have a signal, then poll for a "Link-Up" 995 * indication. 996 */ 997 if (hw->phy.media_type == e1000_media_type_internal_serdes || 998 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) { 999 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 1000 } else { 1001 DEBUGOUT("No signal detected\n"); 1002 } 1003 1004out: 1005 return (ret_val); 1006} 1007 1008/* 1009 * e1000_config_collision_dist_generic - Configure collision distance 1010 * @hw: pointer to the HW structure 1011 * 1012 * Configures the collision distance to the default value and is used 1013 * during link setup. Currently no func pointer exists and all 1014 * implementations are handled in the generic version of this function. 1015 */ 1016void 1017e1000_config_collision_dist_generic(struct e1000_hw *hw) 1018{ 1019 u32 tctl; 1020 1021 DEBUGFUNC("e1000_config_collision_dist_generic"); 1022 1023 tctl = E1000_READ_REG(hw, E1000_TCTL); 1024 1025 tctl &= ~E1000_TCTL_COLD; 1026 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 1027 1028 E1000_WRITE_REG(hw, E1000_TCTL, tctl); 1029 E1000_WRITE_FLUSH(hw); 1030} 1031 1032/* 1033 * e1000_poll_fiber_serdes_link_generic - Poll for link up 1034 * @hw: pointer to the HW structure 1035 * 1036 * Polls for link up by reading the status register, if link fails to come 1037 * up with auto-negotiation, then the link is forced if a signal is detected. 1038 */ 1039s32 1040e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 1041{ 1042 struct e1000_mac_info *mac = &hw->mac; 1043 u32 i, status; 1044 s32 ret_val = E1000_SUCCESS; 1045 1046 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic"); 1047 1048 /* 1049 * If we have a signal (the cable is plugged in, or assumed true for 1050 * serdes media) then poll for a "Link-Up" indication in the Device 1051 * Status Register. Time-out if a link isn't seen in 500 milliseconds 1052 * seconds (Auto-negotiation should complete in less than 500 1053 * milliseconds even if the other end is doing it in SW). 1054 */ 1055 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 1056 msec_delay(10); 1057 status = E1000_READ_REG(hw, E1000_STATUS); 1058 if (status & E1000_STATUS_LU) 1059 break; 1060 } 1061 if (i == FIBER_LINK_UP_LIMIT) { 1062 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); 1063 mac->autoneg_failed = 1; 1064 /* 1065 * AutoNeg failed to achieve a link, so we'll call 1066 * mac->check_for_link. This routine will force the 1067 * link up if we detect a signal. This will allow us to 1068 * communicate with non-autonegotiating link partners. 1069 */ 1070 ret_val = hw->mac.ops.check_for_link(hw); 1071 if (ret_val) { 1072 DEBUGOUT("Error while checking for link\n"); 1073 goto out; 1074 } 1075 mac->autoneg_failed = 0; 1076 } else { 1077 mac->autoneg_failed = 0; 1078 DEBUGOUT("Valid Link Found\n"); 1079 } 1080 1081out: 1082 return (ret_val); 1083} 1084 1085/* 1086 * e1000_commit_fc_settings_generic - Configure flow control 1087 * @hw: pointer to the HW structure 1088 * 1089 * Write the flow control settings to the Transmit Config Word Register (TXCW) 1090 * base on the flow control settings in e1000_mac_info. 1091 */ 1092s32 1093e1000_commit_fc_settings_generic(struct e1000_hw *hw) 1094{ 1095 struct e1000_mac_info *mac = &hw->mac; 1096 u32 txcw; 1097 s32 ret_val = E1000_SUCCESS; 1098 1099 DEBUGFUNC("e1000_commit_fc_settings_generic"); 1100 1101 /* 1102 * Check for a software override of the flow control settings, and 1103 * setup the device accordingly. If auto-negotiation is enabled, then 1104 * software will have to set the "PAUSE" bits to the correct value in 1105 * the Transmit Config Word Register (TXCW) and re-start auto- 1106 * negotiation. However, if auto-negotiation is disabled, then 1107 * software will have to manually configure the two flow control enable 1108 * bits in the CTRL register. 1109 * 1110 * The possible values of the "fc" parameter are: 1111 * 0: Flow control is completely disabled 1112 * 1: Rx flow control is enabled (we can receive pause frames, 1113 * but not send pause frames). 1114 * 2: Tx flow control is enabled (we can send pause frames but we 1115 * do not support receiving pause frames). 1116 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1117 */ 1118 switch (hw->fc.current_mode) { 1119 case e1000_fc_none: 1120 /* Flow control completely disabled by a software over-ride. */ 1121 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 1122 break; 1123 case e1000_fc_rx_pause: 1124 /* 1125 * Rx Flow control is enabled and Tx Flow control is disabled 1126 * by a software over-ride. Since there really isn't a way to 1127 * advertise that we are capable of Rx Pause ONLY, we will 1128 * advertise that we support both symmetric and asymmetric RX 1129 * PAUSE. Later, we will disable the adapter's ability to send 1130 * PAUSE frames. 1131 */ 1132 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1133 break; 1134 case e1000_fc_tx_pause: 1135 /* 1136 * Tx Flow control is enabled, and Rx Flow control is disabled, 1137 * by a software over-ride. 1138 */ 1139 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 1140 break; 1141 case e1000_fc_full: 1142 /* 1143 * Flow control (both Rx and Tx) is enabled by a software 1144 * over-ride. 1145 */ 1146 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 1147 break; 1148 default: 1149 DEBUGOUT("Flow control param set incorrectly\n"); 1150 ret_val = -E1000_ERR_CONFIG; 1151 goto out; 1152 } 1153 1154 E1000_WRITE_REG(hw, E1000_TXCW, txcw); 1155 mac->txcw = txcw; 1156 1157out: 1158 return (ret_val); 1159} 1160 1161/* 1162 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks 1163 * @hw: pointer to the HW structure 1164 * 1165 * Sets the flow control high/low threshold (watermark) registers. If 1166 * flow control XON frame transmission is enabled, then set XON frame 1167 * transmission as well. 1168 */ 1169s32 1170e1000_set_fc_watermarks_generic(struct e1000_hw *hw) 1171{ 1172 s32 ret_val = E1000_SUCCESS; 1173 u32 fcrtl = 0, fcrth = 0; 1174 1175 DEBUGFUNC("e1000_set_fc_watermarks_generic"); 1176 1177 /* 1178 * Set the flow control receive threshold registers. Normally, 1179 * these registers will be set to a default threshold that may be 1180 * adjusted later by the driver's runtime code. However, if the 1181 * ability to transmit pause frames is not enabled, then these 1182 * registers will be set to 0. 1183 */ 1184 if (hw->fc.current_mode & e1000_fc_tx_pause) { 1185 /* 1186 * We need to set up the Receive Threshold high and low water 1187 * marks as well as (optionally) enabling the transmission of 1188 * XON frames. 1189 */ 1190 fcrtl = hw->fc.low_water; 1191 if (hw->fc.send_xon) 1192 fcrtl |= E1000_FCRTL_XONE; 1193 1194 fcrth = hw->fc.high_water; 1195 } 1196 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl); 1197 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth); 1198 1199 return (ret_val); 1200} 1201 1202/* 1203 * e1000_set_default_fc_generic - Set flow control default values 1204 * @hw: pointer to the HW structure 1205 * 1206 * Read the EEPROM for the default values for flow control and store the 1207 * values. 1208 */ 1209s32 1210e1000_set_default_fc_generic(struct e1000_hw *hw) 1211{ 1212 s32 ret_val = E1000_SUCCESS; 1213 u16 nvm_data; 1214 1215 DEBUGFUNC("e1000_set_default_fc_generic"); 1216 1217 /* 1218 * Read and store word 0x0F of the EEPROM. This word contains bits 1219 * that determine the hardware's default PAUSE (flow control) mode, 1220 * a bit that determines whether the HW defaults to enabling or 1221 * disabling auto-negotiation, and the direction of the 1222 * SW defined pins. If there is no SW over-ride of the flow 1223 * control setting, then the variable hw->fc will 1224 * be initialized based on a value in the EEPROM. 1225 */ 1226 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 1227 1228 if (ret_val) { 1229 DEBUGOUT("NVM Read Error\n"); 1230 goto out; 1231 } 1232 1233 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 1234 hw->fc.requested_mode = e1000_fc_none; 1235 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 1236 NVM_WORD0F_ASM_DIR) 1237 hw->fc.requested_mode = e1000_fc_tx_pause; 1238 else 1239 hw->fc.requested_mode = e1000_fc_full; 1240 1241out: 1242 return (ret_val); 1243} 1244 1245/* 1246 * e1000_force_mac_fc_generic - Force the MAC's flow control settings 1247 * @hw: pointer to the HW structure 1248 * 1249 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 1250 * device control register to reflect the adapter settings. TFCE and RFCE 1251 * need to be explicitly set by software when a copper PHY is used because 1252 * autonegotiation is managed by the PHY rather than the MAC. Software must 1253 * also configure these bits when link is forced on a fiber connection. 1254 */ 1255s32 1256e1000_force_mac_fc_generic(struct e1000_hw *hw) 1257{ 1258 u32 ctrl; 1259 s32 ret_val = E1000_SUCCESS; 1260 1261 DEBUGFUNC("e1000_force_mac_fc_generic"); 1262 1263 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1264 1265 /* 1266 * Because we didn't get link via the internal auto-negotiation 1267 * mechanism (we either forced link or we got link via PHY 1268 * auto-neg), we have to manually enable/disable transmit an 1269 * receive flow control. 1270 * 1271 * The "Case" statement below enables/disable flow control 1272 * according to the "hw->fc.current_mode" parameter. 1273 * 1274 * The possible values of the "fc" parameter are: 1275 * 0: Flow control is completely disabled 1276 * 1: Rx flow control is enabled (we can receive pause 1277 * frames but not send pause frames). 1278 * 2: Tx flow control is enabled (we can send pause frames 1279 * frames but we do not receive pause frames). 1280 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1281 * other: No other values should be possible at this point. 1282 */ 1283 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1284 1285 switch (hw->fc.current_mode) { 1286 case e1000_fc_none: 1287 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1288 break; 1289 case e1000_fc_rx_pause: 1290 ctrl &= (~E1000_CTRL_TFCE); 1291 ctrl |= E1000_CTRL_RFCE; 1292 break; 1293 case e1000_fc_tx_pause: 1294 ctrl &= (~E1000_CTRL_RFCE); 1295 ctrl |= E1000_CTRL_TFCE; 1296 break; 1297 case e1000_fc_full: 1298 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1299 break; 1300 default: 1301 DEBUGOUT("Flow control param set incorrectly\n"); 1302 ret_val = -E1000_ERR_CONFIG; 1303 goto out; 1304 } 1305 1306 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1307 1308out: 1309 return (ret_val); 1310} 1311 1312/* 1313 * e1000_config_fc_after_link_up_generic - Configures flow control after link 1314 * @hw: pointer to the HW structure 1315 * 1316 * Checks the status of auto-negotiation after link up to ensure that the 1317 * speed and duplex were not forced. If the link needed to be forced, then 1318 * flow control needs to be forced also. If auto-negotiation is enabled 1319 * and did not fail, then we configure flow control based on our link 1320 * partner. 1321 */ 1322s32 1323e1000_config_fc_after_link_up_generic(struct e1000_hw *hw) 1324{ 1325 struct e1000_mac_info *mac = &hw->mac; 1326 s32 ret_val = E1000_SUCCESS; 1327 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1328 u16 speed, duplex; 1329 1330 DEBUGFUNC("e1000_config_fc_after_link_up_generic"); 1331 1332 /* 1333 * Check for the case where we have fiber media and auto-neg failed 1334 * so we had to force link. In this case, we need to force the 1335 * configuration of the MAC to match the "fc" parameter. 1336 */ 1337 if (mac->autoneg_failed) { 1338 if (hw->phy.media_type == e1000_media_type_fiber || 1339 hw->phy.media_type == e1000_media_type_internal_serdes) 1340 ret_val = e1000_force_mac_fc_generic(hw); 1341 } else { 1342 if (hw->phy.media_type == e1000_media_type_copper) 1343 ret_val = e1000_force_mac_fc_generic(hw); 1344 } 1345 1346 if (ret_val) { 1347 DEBUGOUT("Error forcing flow control settings\n"); 1348 goto out; 1349 } 1350 1351 /* 1352 * Check for the case where we have copper media and auto-neg is 1353 * enabled. In this case, we need to check and see if Auto-Neg 1354 * has completed, and if so, how the PHY and link partner has 1355 * flow control configured. 1356 */ 1357 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1358 /* 1359 * Read the MII Status Register and check to see if AutoNeg 1360 * has completed. We read this twice because this reg has 1361 * some "sticky" (latched) bits. 1362 */ 1363 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1364 if (ret_val) 1365 goto out; 1366 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg); 1367 if (ret_val) 1368 goto out; 1369 1370 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1371 DEBUGOUT("Copper PHY and Auto Neg " 1372 "has not completed.\n"); 1373 goto out; 1374 } 1375 1376 /* 1377 * The AutoNeg process has completed, so we now need to 1378 * read both the Auto Negotiation Advertisement 1379 * Register (Address 4) and the Auto_Negotiation Base 1380 * Page Ability Register (Address 5) to determine how 1381 * flow control was negotiated. 1382 */ 1383 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV, 1384 &mii_nway_adv_reg); 1385 if (ret_val) 1386 goto out; 1387 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY, 1388 &mii_nway_lp_ability_reg); 1389 if (ret_val) 1390 goto out; 1391 1392 /* 1393 * Two bits in the Auto Negotiation Advertisement Register 1394 * (Address 4) and two bits in the Auto Negotiation Base 1395 * Page Ability Register (Address 5) determine flow control 1396 * for both the PHY and the link partner. The following 1397 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1398 * 1999, describes these PAUSE resolution bits and how flow 1399 * control is determined based upon these settings. 1400 * NOTE: DC = Don't Care 1401 * 1402 * LOCAL DEVICE | LINK PARTNER 1403 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1404 * ------|---------|-------|---------|-------------------- 1405 * 0 | 0 | DC | DC | e1000_fc_none 1406 * 0 | 1 | 0 | DC | e1000_fc_none 1407 * 0 | 1 | 1 | 0 | e1000_fc_none 1408 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1409 * 1 | 0 | 0 | DC | e1000_fc_none 1410 * 1 | DC | 1 | DC | e1000_fc_full 1411 * 1 | 1 | 0 | 0 | e1000_fc_none 1412 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1413 * 1414 * Are both PAUSE bits set to 1? If so, this implies 1415 * Symmetric Flow Control is enabled at both ends. The 1416 * ASM_DIR bits are irrelevant per the spec. 1417 * 1418 * For Symmetric Flow Control: 1419 * 1420 * LOCAL DEVICE | LINK PARTNER 1421 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1422 * ------|---------|-------|---------|-------------------- 1423 * 1 | DC | 1 | DC | E1000_fc_full 1424 * 1425 */ 1426 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1427 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1428 /* 1429 * Now we need to check if the user selected Rx ONLY 1430 * of pause frames. In this case, we had to advertise 1431 * FULL flow control because we could not advertise RX 1432 * ONLY. Hence, we must now check to see if we need to 1433 * turn OFF the TRANSMISSION of PAUSE frames. 1434 */ 1435 if (hw->fc.requested_mode == e1000_fc_full) { 1436 hw->fc.current_mode = e1000_fc_full; 1437 DEBUGOUT("Flow Control = FULL.\r\n"); 1438 } else { 1439 hw->fc.current_mode = e1000_fc_rx_pause; 1440 DEBUGOUT("Flow Control = " 1441 "RX PAUSE frames only.\r\n"); 1442 } 1443 } 1444 /* 1445 * For receiving PAUSE frames ONLY. 1446 * 1447 * LOCAL DEVICE | LINK PARTNER 1448 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1449 * ------|---------|-------|---------|-------------------- 1450 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1451 */ 1452 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1453 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1454 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1455 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1456 hw->fc.current_mode = e1000_fc_tx_pause; 1457 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n"); 1458 } 1459 /* 1460 * For transmitting PAUSE frames ONLY. 1461 * 1462 * LOCAL DEVICE | LINK PARTNER 1463 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1464 * ------|---------|-------|---------|-------------------- 1465 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1466 */ 1467 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1468 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1469 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1470 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1471 hw->fc.current_mode = e1000_fc_rx_pause; 1472 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n"); 1473 } else { 1474 /* 1475 * Per the IEEE spec, at this point flow control 1476 * should be disabled. 1477 */ 1478 hw->fc.current_mode = e1000_fc_none; 1479 DEBUGOUT("Flow Control = NONE.\r\n"); 1480 } 1481 1482 /* 1483 * Now we need to do one last check... If we auto- 1484 * negotiated to HALF DUPLEX, flow control should not be 1485 * enabled per IEEE 802.3 spec. 1486 */ 1487 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1488 if (ret_val) { 1489 DEBUGOUT("Error getting link speed and duplex\n"); 1490 goto out; 1491 } 1492 1493 if (duplex == HALF_DUPLEX) 1494 hw->fc.current_mode = e1000_fc_none; 1495 1496 /* 1497 * Now we call a subroutine to actually force the MAC 1498 * controller to use the correct flow control settings. 1499 */ 1500 ret_val = e1000_force_mac_fc_generic(hw); 1501 if (ret_val) { 1502 DEBUGOUT("Error forcing flow control settings\n"); 1503 goto out; 1504 } 1505 } 1506 1507out: 1508 return (ret_val); 1509} 1510 1511/* 1512 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex 1513 * @hw: pointer to the HW structure 1514 * @speed: stores the current speed 1515 * @duplex: stores the current duplex 1516 * 1517 * Read the status register for the current speed/duplex and store the current 1518 * speed and duplex for copper connections. 1519 */ 1520s32 1521e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed, 1522 u16 *duplex) 1523{ 1524 u32 status; 1525 1526 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic"); 1527 1528 status = E1000_READ_REG(hw, E1000_STATUS); 1529 if (status & E1000_STATUS_SPEED_1000) { 1530 *speed = SPEED_1000; 1531 DEBUGOUT("1000 Mbs, "); 1532 } else if (status & E1000_STATUS_SPEED_100) { 1533 *speed = SPEED_100; 1534 DEBUGOUT("100 Mbs, "); 1535 } else { 1536 *speed = SPEED_10; 1537 DEBUGOUT("10 Mbs, "); 1538 } 1539 1540 if (status & E1000_STATUS_FD) { 1541 *duplex = FULL_DUPLEX; 1542 DEBUGOUT("Full Duplex\n"); 1543 } else { 1544 *duplex = HALF_DUPLEX; 1545 DEBUGOUT("Half Duplex\n"); 1546 } 1547 1548 return (E1000_SUCCESS); 1549} 1550 1551/* 1552 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex 1553 * @hw: pointer to the HW structure 1554 * @speed: stores the current speed 1555 * @duplex: stores the current duplex 1556 * 1557 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1558 * for fiber/serdes links. 1559 */ 1560s32 1561e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw, 1562 u16 *speed, u16 *duplex) 1563{ 1564 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic"); 1565 UNREFERENCED_1PARAMETER(hw); 1566 1567 *speed = SPEED_1000; 1568 *duplex = FULL_DUPLEX; 1569 1570 return (E1000_SUCCESS); 1571} 1572 1573/* 1574 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore 1575 * @hw: pointer to the HW structure 1576 * 1577 * Acquire the HW semaphore to access the PHY or NVM 1578 */ 1579s32 1580e1000_get_hw_semaphore_generic(struct e1000_hw *hw) 1581{ 1582 u32 swsm; 1583 s32 ret_val = E1000_SUCCESS; 1584 s32 timeout = hw->nvm.word_size + 1; 1585 s32 i = 0; 1586 1587 DEBUGFUNC("e1000_get_hw_semaphore_generic"); 1588 1589 /* Get the SW semaphore */ 1590 while (i < timeout) { 1591 swsm = E1000_READ_REG(hw, E1000_SWSM); 1592 if (!(swsm & E1000_SWSM_SMBI)) 1593 break; 1594 1595 usec_delay(50); 1596 i++; 1597 } 1598 1599 if (i == timeout) { 1600 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); 1601 ret_val = -E1000_ERR_NVM; 1602 goto out; 1603 } 1604 1605 /* Get the FW semaphore. */ 1606 for (i = 0; i < timeout; i++) { 1607 swsm = E1000_READ_REG(hw, E1000_SWSM); 1608 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI); 1609 1610 /* Semaphore acquired if bit latched */ 1611 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI) 1612 break; 1613 1614 usec_delay(50); 1615 } 1616 1617 if (i == timeout) { 1618 /* Release semaphores */ 1619 e1000_put_hw_semaphore_generic(hw); 1620 DEBUGOUT("Driver can't access the NVM\n"); 1621 ret_val = -E1000_ERR_NVM; 1622 goto out; 1623 } 1624 1625out: 1626 return (ret_val); 1627} 1628 1629/* 1630 * e1000_put_hw_semaphore_generic - Release hardware semaphore 1631 * @hw: pointer to the HW structure 1632 * 1633 * Release hardware semaphore used to access the PHY or NVM 1634 */ 1635void 1636e1000_put_hw_semaphore_generic(struct e1000_hw *hw) 1637{ 1638 u32 swsm; 1639 1640 DEBUGFUNC("e1000_put_hw_semaphore_generic"); 1641 1642 swsm = E1000_READ_REG(hw, E1000_SWSM); 1643 1644 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1645 1646 E1000_WRITE_REG(hw, E1000_SWSM, swsm); 1647} 1648 1649/* 1650 * e1000_get_auto_rd_done_generic - Check for auto read completion 1651 * @hw: pointer to the HW structure 1652 * 1653 * Check EEPROM for Auto Read done bit. 1654 */ 1655s32 1656e1000_get_auto_rd_done_generic(struct e1000_hw *hw) 1657{ 1658 s32 i = 0; 1659 s32 ret_val = E1000_SUCCESS; 1660 1661 DEBUGFUNC("e1000_get_auto_rd_done_generic"); 1662 1663 while (i < AUTO_READ_DONE_TIMEOUT) { 1664 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD) 1665 break; 1666 msec_delay(1); 1667 i++; 1668 } 1669 1670 if (i == AUTO_READ_DONE_TIMEOUT) { 1671 DEBUGOUT("Auto read by HW from NVM has not completed.\n"); 1672 ret_val = -E1000_ERR_RESET; 1673 goto out; 1674 } 1675 1676out: 1677 return (ret_val); 1678} 1679 1680/* 1681 * e1000_valid_led_default_generic - Verify a valid default LED config 1682 * @hw: pointer to the HW structure 1683 * @data: pointer to the NVM (EEPROM) 1684 * 1685 * Read the EEPROM for the current default LED configuration. If the 1686 * LED configuration is not valid, set to a valid LED configuration. 1687 */ 1688s32 1689e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data) 1690{ 1691 s32 ret_val; 1692 1693 DEBUGFUNC("e1000_valid_led_default_generic"); 1694 1695 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data); 1696 if (ret_val) { 1697 DEBUGOUT("NVM Read Error\n"); 1698 goto out; 1699 } 1700 1701 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1702 *data = ID_LED_DEFAULT; 1703 1704out: 1705 return (ret_val); 1706} 1707 1708/* 1709 * e1000_id_led_init_generic - 1710 * @hw: pointer to the HW structure 1711 * 1712 */ 1713s32 1714e1000_id_led_init_generic(struct e1000_hw *hw) 1715{ 1716 struct e1000_mac_info *mac = &hw->mac; 1717 s32 ret_val; 1718 const u32 ledctl_mask = 0x000000FF; 1719 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1720 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1721 u16 data, i, temp; 1722 const u16 led_mask = 0x0F; 1723 1724 DEBUGFUNC("e1000_id_led_init_generic"); 1725 1726 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1727 if (ret_val) 1728 goto out; 1729 1730 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL); 1731 mac->ledctl_mode1 = mac->ledctl_default; 1732 mac->ledctl_mode2 = mac->ledctl_default; 1733 1734 for (i = 0; i < 4; i++) { 1735 temp = (data >> (i << 2)) & led_mask; 1736 switch (temp) { 1737 case ID_LED_ON1_DEF2: 1738 case ID_LED_ON1_ON2: 1739 case ID_LED_ON1_OFF2: 1740 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1741 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1742 break; 1743 case ID_LED_OFF1_DEF2: 1744 case ID_LED_OFF1_ON2: 1745 case ID_LED_OFF1_OFF2: 1746 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1747 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1748 break; 1749 default: 1750 /* Do nothing */ 1751 break; 1752 } 1753 switch (temp) { 1754 case ID_LED_DEF1_ON2: 1755 case ID_LED_ON1_ON2: 1756 case ID_LED_OFF1_ON2: 1757 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1758 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1759 break; 1760 case ID_LED_DEF1_OFF2: 1761 case ID_LED_ON1_OFF2: 1762 case ID_LED_OFF1_OFF2: 1763 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1764 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1765 break; 1766 default: 1767 /* Do nothing */ 1768 break; 1769 } 1770 } 1771 1772out: 1773 return (ret_val); 1774} 1775 1776/* 1777 * e1000_setup_led_generic - Configures SW controllable LED 1778 * @hw: pointer to the HW structure 1779 * 1780 * This prepares the SW controllable LED for use and saves the current state 1781 * of the LED so it can be later restored. 1782 */ 1783s32 1784e1000_setup_led_generic(struct e1000_hw *hw) 1785{ 1786 u32 ledctl; 1787 s32 ret_val = E1000_SUCCESS; 1788 1789 DEBUGFUNC("e1000_setup_led_generic"); 1790 1791 if (hw->mac.ops.setup_led != e1000_setup_led_generic) { 1792 ret_val = -E1000_ERR_CONFIG; 1793 goto out; 1794 } 1795 1796 if (hw->phy.media_type == e1000_media_type_fiber) { 1797 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 1798 hw->mac.ledctl_default = ledctl; 1799 /* Turn off LED0 */ 1800 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | 1801 E1000_LEDCTL_LED0_BLINK | 1802 E1000_LEDCTL_LED0_MODE_MASK); 1803 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1804 E1000_LEDCTL_LED0_MODE_SHIFT); 1805 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 1806 } else if (hw->phy.media_type == e1000_media_type_copper) { 1807 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1808 } 1809 1810out: 1811 return (ret_val); 1812} 1813 1814/* 1815 * e1000_cleanup_led_generic - Set LED config to default operation 1816 * @hw: pointer to the HW structure 1817 * 1818 * Remove the current LED configuration and set the LED configuration 1819 * to the default value, saved from the EEPROM. 1820 */ 1821s32 1822e1000_cleanup_led_generic(struct e1000_hw *hw) 1823{ 1824 s32 ret_val = E1000_SUCCESS; 1825 1826 DEBUGFUNC("e1000_cleanup_led_generic"); 1827 1828 if (hw->mac.ops.cleanup_led != e1000_cleanup_led_generic) { 1829 ret_val = -E1000_ERR_CONFIG; 1830 goto out; 1831 } 1832 1833 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1834 1835out: 1836 return (ret_val); 1837} 1838 1839/* 1840 * e1000_blink_led_generic - Blink LED 1841 * @hw: pointer to the HW structure 1842 * 1843 * Blink the LEDs which are set to be on. 1844 */ 1845s32 1846e1000_blink_led_generic(struct e1000_hw *hw) 1847{ 1848 u32 ledctl_blink = 0; 1849 u32 i; 1850 1851 DEBUGFUNC("e1000_blink_led_generic"); 1852 1853 if (hw->phy.media_type == e1000_media_type_fiber) { 1854 /* always blink LED0 for PCI-E fiber */ 1855 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1856 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1857 } else { 1858 /* 1859 * set the blink bit for each LED that's "on" (0x0E) 1860 * in ledctl_mode2 1861 */ 1862 ledctl_blink = hw->mac.ledctl_mode2; 1863 for (i = 0; i < 4; i++) 1864 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1865 E1000_LEDCTL_MODE_LED_ON) 1866 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1867 (i * 8)); 1868 } 1869 1870 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink); 1871 1872 return (E1000_SUCCESS); 1873} 1874 1875/* 1876 * e1000_led_on_generic - Turn LED on 1877 * @hw: pointer to the HW structure 1878 * 1879 * Turn LED on. 1880 */ 1881s32 1882e1000_led_on_generic(struct e1000_hw *hw) 1883{ 1884 u32 ctrl; 1885 1886 DEBUGFUNC("e1000_led_on_generic"); 1887 1888 switch (hw->phy.media_type) { 1889 case e1000_media_type_fiber: 1890 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1891 ctrl &= ~E1000_CTRL_SWDPIN0; 1892 ctrl |= E1000_CTRL_SWDPIO0; 1893 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1894 break; 1895 case e1000_media_type_copper: 1896 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2); 1897 break; 1898 default: 1899 break; 1900 } 1901 1902 return (E1000_SUCCESS); 1903} 1904 1905/* 1906 * e1000_led_off_generic - Turn LED off 1907 * @hw: pointer to the HW structure 1908 * 1909 * Turn LED off. 1910 */ 1911s32 1912e1000_led_off_generic(struct e1000_hw *hw) 1913{ 1914 u32 ctrl; 1915 1916 DEBUGFUNC("e1000_led_off_generic"); 1917 1918 switch (hw->phy.media_type) { 1919 case e1000_media_type_fiber: 1920 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1921 ctrl |= E1000_CTRL_SWDPIN0; 1922 ctrl |= E1000_CTRL_SWDPIO0; 1923 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1924 break; 1925 case e1000_media_type_copper: 1926 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1927 break; 1928 default: 1929 break; 1930 } 1931 1932 return (E1000_SUCCESS); 1933} 1934 1935/* 1936 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities 1937 * @hw: pointer to the HW structure 1938 * @no_snoop: bitmap of snoop events 1939 * 1940 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1941 */ 1942void 1943e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop) 1944{ 1945 u32 gcr; 1946 1947 DEBUGFUNC("e1000_set_pcie_no_snoop_generic"); 1948 1949 if (hw->bus.type != e1000_bus_type_pci_express) 1950 return; 1951 1952 if (no_snoop) { 1953 gcr = E1000_READ_REG(hw, E1000_GCR); 1954 gcr &= ~(PCIE_NO_SNOOP_ALL); 1955 gcr |= no_snoop; 1956 E1000_WRITE_REG(hw, E1000_GCR, gcr); 1957 } 1958} 1959 1960/* 1961 * e1000_disable_pcie_master_generic - Disables PCI-express master access 1962 * @hw: pointer to the HW structure 1963 * 1964 * Returns 0 (E1000_SUCCESS) if successful, else returns -10 1965 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1966 * the master requests to be disabled. 1967 * 1968 * Disables PCI-Express master access and verifies there are no pending 1969 * requests. 1970 */ 1971s32 1972e1000_disable_pcie_master_generic(struct e1000_hw *hw) 1973{ 1974 u32 ctrl; 1975 s32 timeout = MASTER_DISABLE_TIMEOUT; 1976 s32 ret_val = E1000_SUCCESS; 1977 1978 DEBUGFUNC("e1000_disable_pcie_master_generic"); 1979 1980 if (hw->bus.type != e1000_bus_type_pci_express) 1981 goto out; 1982 1983 ctrl = E1000_READ_REG(hw, E1000_CTRL); 1984 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1985 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 1986 1987 while (timeout) { 1988 if (!(E1000_READ_REG(hw, E1000_STATUS) & 1989 E1000_STATUS_GIO_MASTER_ENABLE)) 1990 break; 1991 usec_delay(100); 1992 timeout--; 1993 } 1994 1995 if (!timeout) { 1996 DEBUGOUT("Master requests are pending.\n"); 1997 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING; 1998 goto out; 1999 } 2000 2001out: 2002 return (ret_val); 2003} 2004 2005/* 2006 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing 2007 * @hw: pointer to the HW structure 2008 * 2009 * Reset the Adaptive Interframe Spacing throttle to default values. 2010 */ 2011void 2012e1000_reset_adaptive_generic(struct e1000_hw *hw) 2013{ 2014 struct e1000_mac_info *mac = &hw->mac; 2015 2016 DEBUGFUNC("e1000_reset_adaptive_generic"); 2017 2018 if (!mac->adaptive_ifs) { 2019 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2020 return; 2021 } 2022 2023 mac->current_ifs_val = 0; 2024 mac->ifs_min_val = IFS_MIN; 2025 mac->ifs_max_val = IFS_MAX; 2026 mac->ifs_step_size = IFS_STEP; 2027 mac->ifs_ratio = IFS_RATIO; 2028 2029 mac->in_ifs_mode = false; 2030 E1000_WRITE_REG(hw, E1000_AIT, 0); 2031} 2032 2033/* 2034 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing 2035 * @hw: pointer to the HW structure 2036 * 2037 * Update the Adaptive Interframe Spacing Throttle value based on the 2038 * time between transmitted packets and time between collisions. 2039 */ 2040void 2041e1000_update_adaptive_generic(struct e1000_hw *hw) 2042{ 2043 struct e1000_mac_info *mac = &hw->mac; 2044 2045 DEBUGFUNC("e1000_update_adaptive_generic"); 2046 2047 if (!mac->adaptive_ifs) { 2048 DEBUGOUT("Not in Adaptive IFS mode!\n"); 2049 return; 2050 } 2051 2052 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 2053 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 2054 mac->in_ifs_mode = true; 2055 if (mac->current_ifs_val < mac->ifs_max_val) { 2056 if (!mac->current_ifs_val) 2057 mac->current_ifs_val = mac->ifs_min_val; 2058 else 2059 mac->current_ifs_val += 2060 mac->ifs_step_size; 2061 E1000_WRITE_REG(hw, E1000_AIT, 2062 mac->current_ifs_val); 2063 } 2064 } 2065 } else { 2066 if (mac->in_ifs_mode && 2067 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 2068 mac->current_ifs_val = 0; 2069 mac->in_ifs_mode = false; 2070 E1000_WRITE_REG(hw, E1000_AIT, 0); 2071 } 2072 } 2073} 2074 2075/* 2076 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings 2077 * @hw: pointer to the HW structure 2078 * 2079 * Verify that when not using auto-negotiation that MDI/MDIx is correctly 2080 * set, which is forced to MDI mode only. 2081 */ 2082static s32 2083e1000_validate_mdi_setting_generic(struct e1000_hw *hw) 2084{ 2085 s32 ret_val = E1000_SUCCESS; 2086 2087 DEBUGFUNC("e1000_validate_mdi_setting_generic"); 2088 2089 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) { 2090 DEBUGOUT("Invalid MDI setting detected\n"); 2091 hw->phy.mdix = 1; 2092 ret_val = -E1000_ERR_CONFIG; 2093 goto out; 2094 } 2095 2096out: 2097 return (ret_val); 2098} 2099 2100/* 2101 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register 2102 * @hw: pointer to the HW structure 2103 * @reg: 32bit register offset such as E1000_SCTL 2104 * @offset: register offset to write to 2105 * @data: data to write at register offset 2106 * 2107 * Writes an address/data control type register. There are several of these 2108 * and they all have the format address << 8 | data and bit 31 is polled for 2109 * completion. 2110 */ 2111s32 2112e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg, 2113 u32 offset, u8 data) 2114{ 2115 u32 i, regvalue = 0; 2116 s32 ret_val = E1000_SUCCESS; 2117 2118 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic"); 2119 2120 /* Set up the address and data */ 2121 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT); 2122 E1000_WRITE_REG(hw, reg, regvalue); 2123 2124 /* Poll the ready bit to see if the MDI read completed */ 2125 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) { 2126 usec_delay(5); 2127 regvalue = E1000_READ_REG(hw, reg); 2128 if (regvalue & E1000_GEN_CTL_READY) 2129 break; 2130 } 2131 if (!(regvalue & E1000_GEN_CTL_READY)) { 2132 DEBUGOUT1("Reg %08x did not indicate ready\n", reg); 2133 ret_val = -E1000_ERR_PHY; 2134 goto out; 2135 } 2136 2137out: 2138 return (ret_val); 2139} 2140