hxge_vmac_hw.h revision 6349:b4971e04f83d
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _HXGE_VMAC_HW_H 27#define _HXGE_VMAC_HW_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#define VMAC_BASE_ADDR 0X00100000 36 37#define VMAC_RST (VMAC_BASE_ADDR + 0x0) 38#define VMAC_TX_CFG (VMAC_BASE_ADDR + 0x8) 39#define VMAC_RX_CFG (VMAC_BASE_ADDR + 0x10) 40#define VMAC_TX_STAT (VMAC_BASE_ADDR + 0x20) 41#define VMAC_TX_MSK (VMAC_BASE_ADDR + 0x28) 42#define VMAC_RX_STAT (VMAC_BASE_ADDR + 0x30) 43#define VMAC_RX_MSK (VMAC_BASE_ADDR + 0x38) 44#define VMAC_TX_STAT_MIRROR (VMAC_BASE_ADDR + 0x40) 45#define VMAC_RX_STAT_MIRROR (VMAC_BASE_ADDR + 0x48) 46#define VMAC_TX_FRAME_CNT (VMAC_BASE_ADDR + 0x100) 47#define VMAC_TX_BYTE_CNT (VMAC_BASE_ADDR + 0x108) 48#define VMAC_RX_FRAME_CNT (VMAC_BASE_ADDR + 0x120) 49#define VMAC_RX_BYTE_CNT (VMAC_BASE_ADDR + 0x128) 50#define VMAC_RX_DROP_FR_CNT (VMAC_BASE_ADDR + 0x130) 51#define VMAC_RX_DROP_BYTE_CNT (VMAC_BASE_ADDR + 0x138) 52#define VMAC_RX_CRC_CNT (VMAC_BASE_ADDR + 0x140) 53#define VMAC_RX_PAUSE_CNT (VMAC_BASE_ADDR + 0x148) 54#define VMAC_RX_BCAST_FR_CNT (VMAC_BASE_ADDR + 0x150) 55#define VMAC_RX_MCAST_FR_CNT (VMAC_BASE_ADDR + 0x158) 56 57 58/* 59 * Register: VmacRst 60 * VMAC Software Reset Command 61 * Description: 62 * Fields: 63 * Write a '1' to reset Rx VMAC; auto clears. This brings rx vmac 64 * to power on reset state. 65 * Write a '1' to reset Tx VMAC; auto clears. This brings tx vmac 66 * to power on reset state. 67 */ 68typedef union { 69 uint64_t value; 70 struct { 71#if defined(_BIG_ENDIAN) 72 uint64_t rsrvd:55; 73 uint64_t rx_reset:1; 74 uint64_t rsrvd1:7; 75 uint64_t tx_reset:1; 76#else 77 uint64_t tx_reset:1; 78 uint64_t rsrvd1:7; 79 uint64_t rx_reset:1; 80 uint64_t rsrvd:55; 81#endif 82 } bits; 83} vmac_rst_t; 84 85 86/* 87 * Register: VmacTxCfg 88 * Tx VMAC Configuration 89 * Description: 90 * Fields: 91 * Maximum length of any total transfer gathered by Tx VMAC, 92 * including packet data, header, crc, transmit header and any 93 * pad bytes. Default value of 0x2422 represents 9220 bytes of 94 * packet data, ethernet header, and crc, 14 bytes maximum pad, 95 * and 16 bytes transmit header = 9250 (0x2422). 96 * Enable padding of short packet to meet minimum frame length of 97 * 64 bytes. Software should note that if txPad functionality is 98 * used to pad runt packets to minimum length, that crcInsert 99 * functionality (below) must also be used to provide the packet 100 * with correct L2 crc. 101 * 1: Enable generation and appending of FCS to the packets. 0: 102 * Disable generation and appending of FCS to the packets. 103 * Enable Tx VMAC. Write a '1' to enable Tx VMAC; write a '0' to 104 * disable it. This bit also propagates as vmacTdcEn to the TDC 105 * block. In TDC, the vmacTdcEn bit disables the RTab state 106 * machine. Hence, the transmission from that blade would be 107 * stopped and be queued, but no packets would be dropped. Thus, 108 * the VMAC can only be enabled/disabled at packet boundary. The 109 * VMAC will not send out portion of a packet. The currently 110 * processed packet will continue to be sent out when Tx VMAC is 111 * disabled. 112 */ 113typedef union { 114 uint64_t value; 115 struct { 116#if defined(_BIG_ENDIAN) 117 uint64_t rsrvd:32; 118 uint64_t tx_max_frame_length:14; 119 uint64_t rsrvd1:15; 120 uint64_t tx_pad:1; 121 uint64_t crc_insert:1; 122 uint64_t tx_en:1; 123#else 124 uint64_t tx_en:1; 125 uint64_t crc_insert:1; 126 uint64_t tx_pad:1; 127 uint64_t rsrvd1:15; 128 uint64_t tx_max_frame_length:14; 129 uint64_t rsrvd:32; 130#endif 131 } bits; 132} vmac_tx_cfg_t; 133 134 135/* 136 * Register: VmacRxCfg 137 * Rx VMAC Configuration 138 * Description: MAC address and length in Type/Length field are 139 * checked in PFC. 140 * Fields: 141 * Maximum length of a frame accepted by Rx/Tx VMAC. Only packets 142 * with length between 64 bytes and maxFrameLength will be 143 * accepted by Rx/Tx VMAC. This length indicates just the packet 144 * length excluding the packet header, crc, and any pad bytes. 145 * Maximum value is 9K (9*1024) 146 * enable packets from the same blade to loopback 147 * Enable acceptance of all Unicast packets for L2 destination 148 * address, ie, allow all Unicast packets to pass the L2 149 * filtering. 150 * Enable acceptance of all multi-cast packets, ie, allow all 151 * multi-cast packets to pass the L2 filtering. 152 * Enable the passing through of flow control frames. 153 * Enable the stripping of FCS field in the packets. 154 * Disable of FCS checking. When enable, packets with incorrect 155 * FCS value are dropped by Rx VMAC. 156 * Enable rx VMAC. Write a '1' to enable rx VMAC; write a '0' to 157 * disable it. The VMAC will begin to accept packet at the 158 * detection of the SOP (start of packet). When disable, the 159 * currently processed packet will continue to be accepted. 160 */ 161typedef union { 162 uint64_t value; 163 struct { 164#if defined(_BIG_ENDIAN) 165 uint64_t rsrvd:32; 166 uint64_t rx_max_frame_length:14; 167 uint64_t reserved:11; 168 uint64_t loopback:1; 169 uint64_t promiscuous_mode:1; 170 uint64_t promiscuous_group:1; 171 uint64_t pass_flow_ctrl_fr:1; 172 uint64_t strip_crc:1; 173 uint64_t crc_check_disable:1; 174 uint64_t rx_en:1; 175#else 176 uint64_t rx_en:1; 177 uint64_t crc_check_disable:1; 178 uint64_t strip_crc:1; 179 uint64_t pass_flow_ctrl_fr:1; 180 uint64_t promiscuous_group:1; 181 uint64_t promiscuous_mode:1; 182 uint64_t loopback:1; 183 uint64_t reserved:11; 184 uint64_t rx_max_frame_length:14; 185 uint64_t rsrvd:32; 186#endif 187 } bits; 188} vmac_rx_cfg_t; 189 190 191/* 192 * Register: VmacTxStat 193 * Tx VMAC Status Register 194 * Description: A new interrupt will be generated only if Tx VMAC is 195 * enabled by vmacTxCfg::txEn=1. Disabling Tx VMAC does not affect 196 * currently-existing Ldf state. Writing this register affects 197 * vmacTxStatMirror register bits also the same way. 198 * Fields: 199 * Indicates that counter of byte transmitted has exceeded the 200 * max value. 201 * Indicates that counter of frame transmitted has exceeded the 202 * max value. 203 * A frame has been successfully transmitted. 204 */ 205typedef union { 206 uint64_t value; 207 struct { 208#if defined(_BIG_ENDIAN) 209 uint64_t rsrvd:61; 210 uint64_t tx_byte_cnt_overflow:1; 211 uint64_t tx_frame_cnt_overflow:1; 212 uint64_t frame_tx:1; 213#else 214 uint64_t frame_tx:1; 215 uint64_t tx_frame_cnt_overflow:1; 216 uint64_t tx_byte_cnt_overflow:1; 217 uint64_t rsrvd:61; 218#endif 219 } bits; 220} vmac_tx_stat_t; 221 222 223/* 224 * Register: VmacTxMsk 225 * Tx VMAC Status Mask 226 * Description: masking vmacTxStat from interrupt. 227 * Fields: 228 * 1: mask interrupt due to overflow of counter of byte 229 * transmitted 230 * 1: mask interrupt due to overflow of counter of frame 231 * transmitted 232 * 1: mask interrupt due to successful transmition of frame. 233 */ 234typedef union { 235 uint64_t value; 236 struct { 237#if defined(_BIG_ENDIAN) 238 uint64_t rsrvd:61; 239 uint64_t tx_byte_cnt_overflow_msk:1; 240 uint64_t tx_frame_cnt_overflow_msk:1; 241 uint64_t frame_tx_msk:1; 242#else 243 uint64_t frame_tx_msk:1; 244 uint64_t tx_frame_cnt_overflow_msk:1; 245 uint64_t tx_byte_cnt_overflow_msk:1; 246 uint64_t rsrvd:61; 247#endif 248 } bits; 249} vmac_tx_msk_t; 250 251 252/* 253 * Register: VmacRxStat 254 * Rx VMAC Status Register 255 * Description: Overflow indicators are read-only registers; Read off 256 * the counters to clear. A new interrupt will be generated only if 257 * Rx VMAC is enabled by vmacRxCfg::rxEn=1. Disabling Rx VMAC does 258 * not affect currently-existing Ldf state. Writing this register 259 * affects vmacRxStatMirror register bits also the same way. 260 * Fields: 261 * Indicates that the counter for broadcast packets has exceeded 262 * the max value. 263 * Indicates that the counter for multicast packets has exceeded 264 * the max value. 265 * Indicates that the counter for pause packets has exceeded the 266 * max value. 267 * Indicates that the counter for packets with mismatched FCS has 268 * exceeded the max value. 269 * Indicates that counter of dropped byte has exceeded the max 270 * value. 271 * Indicates that counter of dropped frame has exceeded the max 272 * value. 273 * Indicates that counter of byte received has exceeded the max 274 * value. 275 * Indicates that counter of frame received has exceeded the max 276 * value. 277 * A valid frame has been successfully received. 278 */ 279typedef union { 280 uint64_t value; 281 struct { 282#if defined(_BIG_ENDIAN) 283 uint64_t rsrvd:55; 284 uint64_t bcast_cnt_overflow:1; 285 uint64_t mcast_cnt_overflow:1; 286 uint64_t pause_cnt_overflow:1; 287 uint64_t crc_err_cnt_overflow:1; 288 uint64_t rx_drop_byte_cnt_overflow:1; 289 uint64_t rx_drop_frame_cnt_overflow:1; 290 uint64_t rx_byte_cnt_overflow:1; 291 uint64_t rx_frame_cnt_overflow:1; 292 uint64_t frame_rx:1; 293#else 294 uint64_t frame_rx:1; 295 uint64_t rx_frame_cnt_overflow:1; 296 uint64_t rx_byte_cnt_overflow:1; 297 uint64_t rx_drop_frame_cnt_overflow:1; 298 uint64_t rx_drop_byte_cnt_overflow:1; 299 uint64_t crc_err_cnt_overflow:1; 300 uint64_t pause_cnt_overflow:1; 301 uint64_t mcast_cnt_overflow:1; 302 uint64_t bcast_cnt_overflow:1; 303 uint64_t rsrvd:55; 304#endif 305 } bits; 306} vmac_rx_stat_t; 307 308 309/* 310 * Register: VmacRxMsk 311 * Rx VMAC Status Mask 312 * Description: 313 * Fields: 314 * 1: mask interrupt due to overflow of the counter for broadcast 315 * packets 316 * 1: mask interrupt due to overflow of the counter for multicast 317 * packets 318 * 1: mask interrupt due to overflow of the counter for pause 319 * packets 320 * 1: mask interrupt due to overflow of the counter for packets 321 * with mismatched FCS the max value. 322 * 1: mask interrupt due to overflow of dropped byte counter 323 * 1: mask interrupt due to overflow of dropped frame counter 324 * 1: mask interrupt due to overflow of received byte counter 325 * 1: mask interrupt due to overflow of received frame counter 326 * 1: mask interrupt due to a valid frame has been successfully 327 * received. 328 */ 329typedef union { 330 uint64_t value; 331 struct { 332#if defined(_BIG_ENDIAN) 333 uint64_t rsrvd:55; 334 uint64_t bcast_cnt_overflow_msk:1; 335 uint64_t mcast_cnt_overflow_msk:1; 336 uint64_t pause_cnt_overflow_msk:1; 337 uint64_t crc_err_cnt_overflow_msk:1; 338 uint64_t rx_drop_byte_cnt_overflow_msk:1; 339 uint64_t rx_drop_frame_cnt_overflow_msk:1; 340 uint64_t rx_byte_cnt_overflow_msk:1; 341 uint64_t rx_frame_cnt_overflow_msk:1; 342 uint64_t frame_rx_msk:1; 343#else 344 uint64_t frame_rx_msk:1; 345 uint64_t rx_frame_cnt_overflow_msk:1; 346 uint64_t rx_byte_cnt_overflow_msk:1; 347 uint64_t rx_drop_frame_cnt_overflow_msk:1; 348 uint64_t rx_drop_byte_cnt_overflow_msk:1; 349 uint64_t crc_err_cnt_overflow_msk:1; 350 uint64_t pause_cnt_overflow_msk:1; 351 uint64_t mcast_cnt_overflow_msk:1; 352 uint64_t bcast_cnt_overflow_msk:1; 353 uint64_t rsrvd:55; 354#endif 355 } bits; 356} vmac_rx_msk_t; 357 358 359/* 360 * Register: VmacTxStatMirror 361 * Tx VMAC Status Mirror Register 362 * Description: Write a 1 to this register to force the corresponding 363 * interrupt. Reading this register returns the current Tx interrupt 364 * status which would be the same as reading the vmacTxStat register. 365 * The bits are cleared by writing 1 to the corresponding register 366 * bit in the vmacTxStat register. ie, bit 0 of this register is 367 * cleared by writing 1 to bit 0 in the vmacTxStat register. 368 * 369 * Fields: 370 * 1 : Force tx byte counter overflow interrupt generation 371 * 1 : Force tx frame counter overflow interrupt generation 372 * 1 : Force frame transmitted interrupt generation 373 */ 374typedef union { 375 uint64_t value; 376 struct { 377#if defined(_BIG_ENDIAN) 378 uint64_t rsrvd:61; 379 uint64_t force_tx_byte_cnt_overflow:1; 380 uint64_t force_tx_frame_cnt_overflow:1; 381 uint64_t force_frame_tx:1; 382#else 383 uint64_t force_frame_tx:1; 384 uint64_t force_tx_frame_cnt_overflow:1; 385 uint64_t force_tx_byte_cnt_overflow:1; 386 uint64_t rsrvd:61; 387#endif 388 } bits; 389} vmac_tx_stat_mirror_t; 390 391 392/* 393 * Register: VmacRxStatMirror 394 * Rx VMAC Status Mirror Register 395 * Description: Write a 1 to this register to force the corresponding 396 * interrupt. Reading this register returns the current Rx interrupt 397 * status which would be the same as reading the vmacRxStat register. 398 * The bits are cleared by writing 1 to the corresponding register 399 * bit in the vmacRxStat register. ie, bit 0 of this register is 400 * cleared by writing 1 to bit 0 in the vmacRxStat register. 401 * Fields: 402 * 1 : Force broadcast frame counter overflow interrupt 403 * generation 404 * 1 : Force multicast frame counter overflow interrupt 405 * generation 406 * 1 : Force pause frame counter overflow interrupt generation 407 * 1 : Force crc error counter overflow interrupt generation 408 * 1 : Force dropped frames byte counter overflow interrupt 409 * generation 410 * 1 : Force dropped frame counter overflow interrupt generation 411 * 1 : Force rx byte counter overflow interrupt generation 412 * 1 : Force rx frame counter overflow interrupt generation 413 * 1 : Force frame received interrupt generation 414 */ 415typedef union { 416 uint64_t value; 417 struct { 418#if defined(_BIG_ENDIAN) 419 uint64_t rsrvd:55; 420 uint64_t force_bcast_cnt_overflow:1; 421 uint64_t force_mcast_cnt_overflow:1; 422 uint64_t force_pause_cnt_overflow:1; 423 uint64_t force_crc_err_cnt_overflow:1; 424 uint64_t force_rx_drop_byte_cnt_overflow:1; 425 uint64_t force_rx_drop_frame_cnt_overflow:1; 426 uint64_t force_rx_byte_cnt_overflow:1; 427 uint64_t force_rx_frame_cnt_overflow:1; 428 uint64_t force_frame_rx:1; 429#else 430 uint64_t force_frame_rx:1; 431 uint64_t force_rx_frame_cnt_overflow:1; 432 uint64_t force_rx_byte_cnt_overflow:1; 433 uint64_t force_rx_drop_frame_cnt_overflow:1; 434 uint64_t force_rx_drop_byte_cnt_overflow:1; 435 uint64_t force_crc_err_cnt_overflow:1; 436 uint64_t force_pause_cnt_overflow:1; 437 uint64_t force_mcast_cnt_overflow:1; 438 uint64_t force_bcast_cnt_overflow:1; 439 uint64_t rsrvd:55; 440#endif 441 } bits; 442} vmac_rx_stat_mirror_t; 443 444 445/* 446 * Register: VmacTxFrameCnt 447 * VMAC transmitted frame counter 448 * Description: 449 * Fields: 450 * Indicates the number of frames transmitted by Tx VMAC. The 451 * counter will saturate at max value. The counter is stalled 452 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 453 */ 454typedef union { 455 uint64_t value; 456 struct { 457#if defined(_BIG_ENDIAN) 458 uint64_t rsrvd:32; 459 uint64_t tx_frame_cnt:32; 460#else 461 uint64_t tx_frame_cnt:32; 462 uint64_t rsrvd:32; 463#endif 464 } bits; 465} vmac_tx_frame_cnt_t; 466 467 468/* 469 * Register: VmacTxByteCnt 470 * VMAC transmitted byte counter 471 * Description: 472 * Fields: 473 * Indicates the number of byte (octet) of data transmitted by Tx 474 * VMAC. This counter counts all the bytes of the incoming data 475 * including packet header, packet data, crc, and pad bytes. The 476 * counter will saturate at max value. The counter is stalled 477 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 478 */ 479typedef union { 480 uint64_t value; 481 struct { 482#if defined(_BIG_ENDIAN) 483 uint64_t rsrvd:32; 484 uint64_t tx_byte_cnt:32; 485#else 486 uint64_t tx_byte_cnt:32; 487 uint64_t rsrvd:32; 488#endif 489 } bits; 490} vmac_tx_byte_cnt_t; 491 492 493/* 494 * Register: VmacRxFrameCnt 495 * VMAC received frame counter 496 * Description: 497 * Fields: 498 * Indicates the number of frame received by Rx VMAC. The counter 499 * will saturate at max value. The counter is stalled when Rx 500 * VMAC is disabled by vmacRxCfg::rxEn=0. 501 */ 502typedef union { 503 uint64_t value; 504 struct { 505#if defined(_BIG_ENDIAN) 506 uint64_t rsrvd:32; 507 uint64_t rx_frame_cnt:32; 508#else 509 uint64_t rx_frame_cnt:32; 510 uint64_t rsrvd:32; 511#endif 512 } bits; 513} vmac_rx_frame_cnt_t; 514 515 516/* 517 * Register: VmacRxByteCnt 518 * VMAC received byte counter 519 * Description: 520 * Fields: 521 * Indicates the number of bytes (octet) of data received by Rx 522 * VMAC including any error frames. The counter will saturate at 523 * max value. The counter is stalled when Rx VMAC is disabled by 524 * vmacRxCfg::rxEn=0. 525 */ 526typedef union { 527 uint64_t value; 528 struct { 529#if defined(_BIG_ENDIAN) 530 uint64_t rsrvd:32; 531 uint64_t rx_byte_cnt:32; 532#else 533 uint64_t rx_byte_cnt:32; 534 uint64_t rsrvd:32; 535#endif 536 } bits; 537} vmac_rx_byte_cnt_t; 538 539 540/* 541 * Register: VmacRxDropFrCnt 542 * VMAC dropped frame counter 543 * Description: 544 * Fields: 545 * Indicates the number of frame dropped by Rx VMAC. The counter 546 * will This counter increments for every frame dropped for the 547 * following: - crc mismatch & crc check is enabled - failed the 548 * L2 address match & Vmac is not in promiscuous mode - pause 549 * packet & Vmac is not programmed to pass these frames The 550 * counter will saturate at max value. The counter is stalled 551 * when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 552 */ 553typedef union { 554 uint64_t value; 555 struct { 556#if defined(_BIG_ENDIAN) 557 uint64_t rsrvd:32; 558 uint64_t rx_drop_frame_cnt:32; 559#else 560 uint64_t rx_drop_frame_cnt:32; 561 uint64_t rsrvd:32; 562#endif 563 } bits; 564} vmac_rx_drop_fr_cnt_t; 565 566 567/* 568 * Register: VmacRxDropByteCnt 569 * VMAC dropped byte counter 570 * Description: 571 * Fields: 572 * Indicates the number of byte of data dropped by Rx VMAC. 573 * Frames are dropped for one of the follg conditions : - crc 574 * mismatch & crc check is enabled - failed the L2 address match 575 * & Vmac is not in promiscuous mode - pause packet & Vmac is not 576 * programmed to pass these frames The counter will saturate at 577 * max value. The counter is stalled when Rx VMAC is disabled by 578 * vmacRxCfg::rxEn=0. 579 */ 580typedef union { 581 uint64_t value; 582 struct { 583#if defined(_BIG_ENDIAN) 584 uint64_t rsrvd:32; 585 uint64_t rx_drop_byte_cnt:32; 586#else 587 uint64_t rx_drop_byte_cnt:32; 588 uint64_t rsrvd:32; 589#endif 590 } bits; 591} vmac_rx_drop_byte_cnt_t; 592 593 594/* 595 * Register: VmacRxCrcCnt 596 * VMAC received CRC error frame counter 597 * Description: 598 * Fields: 599 * Indicates the number of frames with invalid CRC. When NMAC 600 * truncates a packet, it asserts crcError indication to VMAC 601 * which then counts it towards CRC error. Thus the VMAC crc 602 * error counter reflects the CRC mismatches on all the packets 603 * going out of RxMAC while the NMAC crc error counter reflects 604 * the CRC mismatches on all the packets coming into RxMAC. The 605 * counter will saturate at max value The counter is stalled when 606 * Rx VMAC is disabled by vmacRxCfg::rxEn=0. 607 */ 608typedef union { 609 uint64_t value; 610 struct { 611#if defined(_BIG_ENDIAN) 612 uint64_t rsrvd:32; 613 uint64_t rx_crc_cnt:32; 614#else 615 uint64_t rx_crc_cnt:32; 616 uint64_t rsrvd:32; 617#endif 618 } bits; 619} vmac_rx_crc_cnt_t; 620 621 622/* 623 * Register: VmacRxPauseCnt 624 * VMAC received pause frame counter 625 * Description: 626 * Fields: 627 * Count the number of pause frames received by Rx VMAC. The 628 * counter is stalled when Rx VMAC is disabled by 629 * vmacRxCfg::rxEn=0. 630 */ 631typedef union { 632 uint64_t value; 633 struct { 634#if defined(_BIG_ENDIAN) 635 uint64_t rsrvd:32; 636 uint64_t rx_pause_cnt:32; 637#else 638 uint64_t rx_pause_cnt:32; 639 uint64_t rsrvd:32; 640#endif 641 } bits; 642} vmac_rx_pause_cnt_t; 643 644 645/* 646 * Register: VmacRxBcastFrCnt 647 * VMAC received broadcast frame counter 648 * Description: 649 * Fields: 650 * Indicates the number of broadcast frames received The counter 651 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 652 */ 653typedef union { 654 uint64_t value; 655 struct { 656#if defined(_BIG_ENDIAN) 657 uint64_t rsrvd:32; 658 uint64_t rx_bcast_fr_cnt:32; 659#else 660 uint64_t rx_bcast_fr_cnt:32; 661 uint64_t rsrvd:32; 662#endif 663 } bits; 664} vmac_rx_bcast_fr_cnt_t; 665 666 667/* 668 * Register: VmacRxMcastFrCnt 669 * VMAC received multicast frame counter 670 * Description: 671 * Fields: 672 * Indicates the number of multicast frames received The counter 673 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 674 */ 675typedef union { 676 uint64_t value; 677 struct { 678#if defined(_BIG_ENDIAN) 679 uint64_t rsrvd:32; 680 uint64_t rx_mcast_fr_cnt:32; 681#else 682 uint64_t rx_mcast_fr_cnt:32; 683 uint64_t rsrvd:32; 684#endif 685 } bits; 686} vmac_rx_mcast_fr_cnt_t; 687 688 689#ifdef __cplusplus 690} 691#endif 692 693#endif /* _HXGE_VMAC_HW_H */ 694