1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _HXGE_VMAC_HW_H 27#define _HXGE_VMAC_HW_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35#define VMAC_BASE_ADDR 0X00100000 36 37#define VMAC_RST (VMAC_BASE_ADDR + 0x0) 38#define VMAC_TX_CFG (VMAC_BASE_ADDR + 0x8) 39#define VMAC_RX_CFG (VMAC_BASE_ADDR + 0x10) 40#define VMAC_TX_STAT (VMAC_BASE_ADDR + 0x20) 41#define VMAC_TX_MSK (VMAC_BASE_ADDR + 0x28) 42#define VMAC_RX_STAT (VMAC_BASE_ADDR + 0x30) 43#define VMAC_RX_MSK (VMAC_BASE_ADDR + 0x38) 44#define VMAC_TX_STAT_MIRROR (VMAC_BASE_ADDR + 0x40) 45#define VMAC_RX_STAT_MIRROR (VMAC_BASE_ADDR + 0x48) 46#define VMAC_TX_FRAME_CNT (VMAC_BASE_ADDR + 0x100) 47#define VMAC_TX_BYTE_CNT (VMAC_BASE_ADDR + 0x108) 48#define VMAC_RX_FRAME_CNT (VMAC_BASE_ADDR + 0x120) 49#define VMAC_RX_BYTE_CNT (VMAC_BASE_ADDR + 0x128) 50#define VMAC_RX_DROP_FR_CNT (VMAC_BASE_ADDR + 0x130) 51#define VMAC_RX_DROP_BYTE_CNT (VMAC_BASE_ADDR + 0x138) 52#define VMAC_RX_CRC_CNT (VMAC_BASE_ADDR + 0x140) 53#define VMAC_RX_PAUSE_CNT (VMAC_BASE_ADDR + 0x148) 54#define VMAC_RX_BCAST_FR_CNT (VMAC_BASE_ADDR + 0x150) 55#define VMAC_RX_MCAST_FR_CNT (VMAC_BASE_ADDR + 0x158) 56 57 58/* 59 * Register: VmacRst 60 * VMAC Software Reset Command 61 * Description: 62 * Fields: 63 * Write a '1' to reset Rx VMAC; auto clears. This brings rx vmac 64 * to power on reset state. 65 * Write a '1' to reset Tx VMAC; auto clears. This brings tx vmac 66 * to power on reset state. 67 */ 68typedef union { 69 uint64_t value; 70 struct { 71#if defined(_BIG_ENDIAN) 72 uint32_t rsrvd:32; 73 uint32_t rsrvd_l:23; 74 uint32_t rx_reset:1; 75 uint32_t rsrvd1:7; 76 uint32_t tx_reset:1; 77#else 78 uint32_t tx_reset:1; 79 uint32_t rsrvd1:7; 80 uint32_t rx_reset:1; 81 uint32_t rsrvd_l:23; 82 uint32_t rsrvd:32; 83#endif 84 } bits; 85} vmac_rst_t; 86 87 88/* 89 * Register: VmacTxCfg 90 * Tx VMAC Configuration 91 * Description: 92 * Fields: 93 * Maximum length of any total transfer gathered by Tx VMAC, 94 * including packet data, header, crc, transmit header and any 95 * pad bytes. Default value of 0x2422 represents 9220 bytes of 96 * packet data, ethernet header, and crc, 14 bytes maximum pad, 97 * and 16 bytes transmit header = 9250 (0x2422). 98 * Enable padding of short packet to meet minimum frame length of 99 * 64 bytes. Software should note that if txPad functionality is 100 * used to pad runt packets to minimum length, that crcInsert 101 * functionality (below) must also be used to provide the packet 102 * with correct L2 crc. 103 * 1: Enable generation and appending of FCS to the packets. 0: 104 * Disable generation and appending of FCS to the packets. 105 * Enable Tx VMAC. Write a '1' to enable Tx VMAC; write a '0' to 106 * disable it. This bit also propagates as vmacTdcEn to the TDC 107 * block. In TDC, the vmacTdcEn bit disables the RTab state 108 * machine. Hence, the transmission from that blade would be 109 * stopped and be queued, but no packets would be dropped. Thus, 110 * the VMAC can only be enabled/disabled at packet boundary. The 111 * VMAC will not send out portion of a packet. The currently 112 * processed packet will continue to be sent out when Tx VMAC is 113 * disabled. 114 */ 115typedef union { 116 uint64_t value; 117 struct { 118#if defined(_BIG_ENDIAN) 119 uint32_t rsrvd:32; 120 uint32_t tx_max_frame_length:14; 121 uint32_t rsrvd1:15; 122 uint32_t tx_pad:1; 123 uint32_t crc_insert:1; 124 uint32_t tx_en:1; 125#else 126 uint32_t tx_en:1; 127 uint32_t crc_insert:1; 128 uint32_t tx_pad:1; 129 uint32_t rsrvd1:15; 130 uint32_t tx_max_frame_length:14; 131 uint32_t rsrvd:32; 132#endif 133 } bits; 134} vmac_tx_cfg_t; 135 136 137/* 138 * Register: VmacRxCfg 139 * Rx VMAC Configuration 140 * Description: MAC address and length in Type/Length field are 141 * checked in PFC. 142 * Fields: 143 * Maximum length of a frame accepted by Rx/Tx VMAC. Only packets 144 * with length between 64 bytes and maxFrameLength will be 145 * accepted by Rx/Tx VMAC. This length indicates just the packet 146 * length excluding the packet header, crc, and any pad bytes. 147 * Maximum value is 9K (9*1024) 148 * enable packets from the same blade to loopback 149 * Enable acceptance of all Unicast packets for L2 destination 150 * address, ie, allow all Unicast packets to pass the L2 151 * filtering. 152 * Enable acceptance of all multi-cast packets, ie, allow all 153 * multi-cast packets to pass the L2 filtering. 154 * Enable the passing through of flow control frames. 155 * Enable the stripping of FCS field in the packets. 156 * Disable of FCS checking. When enable, packets with incorrect 157 * FCS value are dropped by Rx VMAC. 158 * Enable rx VMAC. Write a '1' to enable rx VMAC; write a '0' to 159 * disable it. The VMAC will begin to accept packet at the 160 * detection of the SOP (start of packet). When disable, the 161 * currently processed packet will continue to be accepted. 162 */ 163typedef union { 164 uint64_t value; 165 struct { 166#if defined(_BIG_ENDIAN) 167 uint32_t rsrvd:32; 168 uint32_t rx_max_frame_length:14; 169 uint32_t reserved:11; 170 uint32_t loopback:1; 171 uint32_t promiscuous_mode:1; 172 uint32_t promiscuous_group:1; 173 uint32_t pass_flow_ctrl_fr:1; 174 uint32_t strip_crc:1; 175 uint32_t crc_check_disable:1; 176 uint32_t rx_en:1; 177#else 178 uint32_t rx_en:1; 179 uint32_t crc_check_disable:1; 180 uint32_t strip_crc:1; 181 uint32_t pass_flow_ctrl_fr:1; 182 uint32_t promiscuous_group:1; 183 uint32_t promiscuous_mode:1; 184 uint32_t loopback:1; 185 uint32_t reserved:11; 186 uint32_t rx_max_frame_length:14; 187 uint32_t rsrvd:32; 188#endif 189 } bits; 190} vmac_rx_cfg_t; 191 192 193/* 194 * Register: VmacTxStat 195 * Tx VMAC Status Register 196 * Description: A new interrupt will be generated only if Tx VMAC is 197 * enabled by vmacTxCfg::txEn=1. Disabling Tx VMAC does not affect 198 * currently-existing Ldf state. Writing this register affects 199 * vmacTxStatMirror register bits also the same way. 200 * Fields: 201 * Indicates that counter of byte transmitted has exceeded the 202 * max value. 203 * Indicates that counter of frame transmitted has exceeded the 204 * max value. 205 * A frame has been successfully transmitted. 206 */ 207typedef union { 208 uint64_t value; 209 struct { 210#if defined(_BIG_ENDIAN) 211 uint32_t rsrvd:32; 212 uint32_t rsrvd_l:29; 213 uint32_t tx_byte_cnt_overflow:1; 214 uint32_t tx_frame_cnt_overflow:1; 215 uint32_t frame_tx:1; 216#else 217 uint32_t frame_tx:1; 218 uint32_t tx_frame_cnt_overflow:1; 219 uint32_t tx_byte_cnt_overflow:1; 220 uint32_t rsrvd_l:29; 221 uint32_t rsrvd:32; 222#endif 223 } bits; 224} vmac_tx_stat_t; 225 226 227/* 228 * Register: VmacTxMsk 229 * Tx VMAC Status Mask 230 * Description: masking vmacTxStat from interrupt. 231 * Fields: 232 * 1: mask interrupt due to overflow of counter of byte 233 * transmitted 234 * 1: mask interrupt due to overflow of counter of frame 235 * transmitted 236 * 1: mask interrupt due to successful transmition of frame. 237 */ 238typedef union { 239 uint64_t value; 240 struct { 241#if defined(_BIG_ENDIAN) 242 uint32_t rsrvd:32; 243 uint32_t rsrvd_l:29; 244 uint32_t tx_byte_cnt_overflow_msk:1; 245 uint32_t tx_frame_cnt_overflow_msk:1; 246 uint32_t frame_tx_msk:1; 247#else 248 uint32_t frame_tx_msk:1; 249 uint32_t tx_frame_cnt_overflow_msk:1; 250 uint32_t tx_byte_cnt_overflow_msk:1; 251 uint32_t rsrvd_l:29; 252 uint32_t rsrvd:32; 253#endif 254 } bits; 255} vmac_tx_msk_t; 256 257 258/* 259 * Register: VmacRxStat 260 * Rx VMAC Status Register 261 * Description: Overflow indicators are read-only registers; Read off 262 * the counters to clear. A new interrupt will be generated only if 263 * Rx VMAC is enabled by vmacRxCfg::rxEn=1. Disabling Rx VMAC does 264 * not affect currently-existing Ldf state. Writing this register 265 * affects vmacRxStatMirror register bits also the same way. 266 * Fields: 267 * Indicates that the counter for broadcast packets has exceeded 268 * the max value. 269 * Indicates that the counter for multicast packets has exceeded 270 * the max value. 271 * Indicates that the counter for pause packets has exceeded the 272 * max value. 273 * Indicates that the counter for packets with mismatched FCS has 274 * exceeded the max value. 275 * Indicates that counter of dropped byte has exceeded the max 276 * value. 277 * Indicates that counter of dropped frame has exceeded the max 278 * value. 279 * Indicates that counter of byte received has exceeded the max 280 * value. 281 * Indicates that counter of frame received has exceeded the max 282 * value. 283 * A valid frame has been successfully received. 284 */ 285typedef union { 286 uint64_t value; 287 struct { 288#if defined(_BIG_ENDIAN) 289 uint32_t rsrvd:32; 290 uint32_t rsrvd_l:23; 291 uint32_t bcast_cnt_overflow:1; 292 uint32_t mcast_cnt_overflow:1; 293 uint32_t pause_cnt_overflow:1; 294 uint32_t crc_err_cnt_overflow:1; 295 uint32_t rx_drop_byte_cnt_overflow:1; 296 uint32_t rx_drop_frame_cnt_overflow:1; 297 uint32_t rx_byte_cnt_overflow:1; 298 uint32_t rx_frame_cnt_overflow:1; 299 uint32_t frame_rx:1; 300#else 301 uint32_t frame_rx:1; 302 uint32_t rx_frame_cnt_overflow:1; 303 uint32_t rx_byte_cnt_overflow:1; 304 uint32_t rx_drop_frame_cnt_overflow:1; 305 uint32_t rx_drop_byte_cnt_overflow:1; 306 uint32_t crc_err_cnt_overflow:1; 307 uint32_t pause_cnt_overflow:1; 308 uint32_t mcast_cnt_overflow:1; 309 uint32_t bcast_cnt_overflow:1; 310 uint32_t rsrvd_l:23; 311 uint32_t rsrvd:32; 312#endif 313 } bits; 314} vmac_rx_stat_t; 315 316 317/* 318 * Register: VmacRxMsk 319 * Rx VMAC Status Mask 320 * Description: 321 * Fields: 322 * 1: mask interrupt due to overflow of the counter for broadcast 323 * packets 324 * 1: mask interrupt due to overflow of the counter for multicast 325 * packets 326 * 1: mask interrupt due to overflow of the counter for pause 327 * packets 328 * 1: mask interrupt due to overflow of the counter for packets 329 * with mismatched FCS the max value. 330 * 1: mask interrupt due to overflow of dropped byte counter 331 * 1: mask interrupt due to overflow of dropped frame counter 332 * 1: mask interrupt due to overflow of received byte counter 333 * 1: mask interrupt due to overflow of received frame counter 334 * 1: mask interrupt due to a valid frame has been successfully 335 * received. 336 */ 337typedef union { 338 uint64_t value; 339 struct { 340#if defined(_BIG_ENDIAN) 341 uint32_t rsrvd:32; 342 uint32_t rsrvd_l:23; 343 uint32_t bcast_cnt_overflow_msk:1; 344 uint32_t mcast_cnt_overflow_msk:1; 345 uint32_t pause_cnt_overflow_msk:1; 346 uint32_t crc_err_cnt_overflow_msk:1; 347 uint32_t rx_drop_byte_cnt_overflow_msk:1; 348 uint32_t rx_drop_frame_cnt_overflow_msk:1; 349 uint32_t rx_byte_cnt_overflow_msk:1; 350 uint32_t rx_frame_cnt_overflow_msk:1; 351 uint32_t frame_rx_msk:1; 352#else 353 uint32_t frame_rx_msk:1; 354 uint32_t rx_frame_cnt_overflow_msk:1; 355 uint32_t rx_byte_cnt_overflow_msk:1; 356 uint32_t rx_drop_frame_cnt_overflow_msk:1; 357 uint32_t rx_drop_byte_cnt_overflow_msk:1; 358 uint32_t crc_err_cnt_overflow_msk:1; 359 uint32_t pause_cnt_overflow_msk:1; 360 uint32_t mcast_cnt_overflow_msk:1; 361 uint32_t bcast_cnt_overflow_msk:1; 362 uint32_t rsrvd_l:23; 363 uint32_t rsrvd:32; 364#endif 365 } bits; 366} vmac_rx_msk_t; 367 368 369/* 370 * Register: VmacTxStatMirror 371 * Tx VMAC Status Mirror Register 372 * Description: Write a 1 to this register to force the corresponding 373 * interrupt. Reading this register returns the current Tx interrupt 374 * status which would be the same as reading the vmacTxStat register. 375 * The bits are cleared by writing 1 to the corresponding register 376 * bit in the vmacTxStat register. ie, bit 0 of this register is 377 * cleared by writing 1 to bit 0 in the vmacTxStat register. 378 * 379 * Fields: 380 * 1 : Force tx byte counter overflow interrupt generation 381 * 1 : Force tx frame counter overflow interrupt generation 382 * 1 : Force frame transmitted interrupt generation 383 */ 384typedef union { 385 uint64_t value; 386 struct { 387#if defined(_BIG_ENDIAN) 388 uint32_t rsrvd:32; 389 uint32_t rsrvd_l:29; 390 uint32_t force_tx_byte_cnt_overflow:1; 391 uint32_t force_tx_frame_cnt_overflow:1; 392 uint32_t force_frame_tx:1; 393#else 394 uint32_t force_frame_tx:1; 395 uint32_t force_tx_frame_cnt_overflow:1; 396 uint32_t force_tx_byte_cnt_overflow:1; 397 uint32_t rsrvd_l:29; 398 uint32_t rsrvd:32; 399#endif 400 } bits; 401} vmac_tx_stat_mirror_t; 402 403 404/* 405 * Register: VmacRxStatMirror 406 * Rx VMAC Status Mirror Register 407 * Description: Write a 1 to this register to force the corresponding 408 * interrupt. Reading this register returns the current Rx interrupt 409 * status which would be the same as reading the vmacRxStat register. 410 * The bits are cleared by writing 1 to the corresponding register 411 * bit in the vmacRxStat register. ie, bit 0 of this register is 412 * cleared by writing 1 to bit 0 in the vmacRxStat register. 413 * Fields: 414 * 1 : Force broadcast frame counter overflow interrupt 415 * generation 416 * 1 : Force multicast frame counter overflow interrupt 417 * generation 418 * 1 : Force pause frame counter overflow interrupt generation 419 * 1 : Force crc error counter overflow interrupt generation 420 * 1 : Force dropped frames byte counter overflow interrupt 421 * generation 422 * 1 : Force dropped frame counter overflow interrupt generation 423 * 1 : Force rx byte counter overflow interrupt generation 424 * 1 : Force rx frame counter overflow interrupt generation 425 * 1 : Force frame received interrupt generation 426 */ 427typedef union { 428 uint64_t value; 429 struct { 430#if defined(_BIG_ENDIAN) 431 uint32_t rsrvd:32; 432 uint32_t rsrvd_l:23; 433 uint32_t force_bcast_cnt_overflow:1; 434 uint32_t force_mcast_cnt_overflow:1; 435 uint32_t force_pause_cnt_overflow:1; 436 uint32_t force_crc_err_cnt_overflow:1; 437 uint32_t force_rx_drop_byte_cnt_overflow:1; 438 uint32_t force_rx_drop_frame_cnt_overflow:1; 439 uint32_t force_rx_byte_cnt_overflow:1; 440 uint32_t force_rx_frame_cnt_overflow:1; 441 uint32_t force_frame_rx:1; 442#else 443 uint32_t force_frame_rx:1; 444 uint32_t force_rx_frame_cnt_overflow:1; 445 uint32_t force_rx_byte_cnt_overflow:1; 446 uint32_t force_rx_drop_frame_cnt_overflow:1; 447 uint32_t force_rx_drop_byte_cnt_overflow:1; 448 uint32_t force_crc_err_cnt_overflow:1; 449 uint32_t force_pause_cnt_overflow:1; 450 uint32_t force_mcast_cnt_overflow:1; 451 uint32_t force_bcast_cnt_overflow:1; 452 uint32_t rsrvd_l:23; 453 uint32_t rsrvd:32; 454#endif 455 } bits; 456} vmac_rx_stat_mirror_t; 457 458 459/* 460 * Register: VmacTxFrameCnt 461 * VMAC transmitted frame counter 462 * Description: 463 * Fields: 464 * Indicates the number of frames transmitted by Tx VMAC. The 465 * counter will saturate at max value. The counter is stalled 466 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 467 */ 468typedef union { 469 uint64_t value; 470 struct { 471#if defined(_BIG_ENDIAN) 472 uint32_t rsrvd:32; 473 uint32_t tx_frame_cnt:32; 474#else 475 uint32_t tx_frame_cnt:32; 476 uint32_t rsrvd:32; 477#endif 478 } bits; 479} vmac_tx_frame_cnt_t; 480 481 482/* 483 * Register: VmacTxByteCnt 484 * VMAC transmitted byte counter 485 * Description: 486 * Fields: 487 * Indicates the number of byte (octet) of data transmitted by Tx 488 * VMAC. This counter counts all the bytes of the incoming data 489 * including packet header, packet data, crc, and pad bytes. The 490 * counter will saturate at max value. The counter is stalled 491 * when Tx VMAC is disabled by vmacTxCfg::txEn=0 492 */ 493typedef union { 494 uint64_t value; 495 struct { 496#if defined(_BIG_ENDIAN) 497 uint32_t rsrvd:32; 498 uint32_t tx_byte_cnt:32; 499#else 500 uint32_t tx_byte_cnt:32; 501 uint32_t rsrvd:32; 502#endif 503 } bits; 504} vmac_tx_byte_cnt_t; 505 506 507/* 508 * Register: VmacRxFrameCnt 509 * VMAC received frame counter 510 * Description: 511 * Fields: 512 * Indicates the number of frame received by Rx VMAC. The counter 513 * will saturate at max value. The counter is stalled when Rx 514 * VMAC is disabled by vmacRxCfg::rxEn=0. 515 */ 516typedef union { 517 uint64_t value; 518 struct { 519#if defined(_BIG_ENDIAN) 520 uint32_t rsrvd:32; 521 uint32_t rx_frame_cnt:32; 522#else 523 uint32_t rx_frame_cnt:32; 524 uint32_t rsrvd:32; 525#endif 526 } bits; 527} vmac_rx_frame_cnt_t; 528 529 530/* 531 * Register: VmacRxByteCnt 532 * VMAC received byte counter 533 * Description: 534 * Fields: 535 * Indicates the number of bytes (octet) of data received by Rx 536 * VMAC including any error frames. The counter will saturate at 537 * max value. The counter is stalled when Rx VMAC is disabled by 538 * vmacRxCfg::rxEn=0. 539 */ 540typedef union { 541 uint64_t value; 542 struct { 543#if defined(_BIG_ENDIAN) 544 uint32_t rsrvd:32; 545 uint32_t rx_byte_cnt:32; 546#else 547 uint32_t rx_byte_cnt:32; 548 uint32_t rsrvd:32; 549#endif 550 } bits; 551} vmac_rx_byte_cnt_t; 552 553 554/* 555 * Register: VmacRxDropFrCnt 556 * VMAC dropped frame counter 557 * Description: 558 * Fields: 559 * Indicates the number of frame dropped by Rx VMAC. The counter 560 * will This counter increments for every frame dropped for the 561 * following: - crc mismatch & crc check is enabled - failed the 562 * L2 address match & Vmac is not in promiscuous mode - pause 563 * packet & Vmac is not programmed to pass these frames The 564 * counter will saturate at max value. The counter is stalled 565 * when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 566 */ 567typedef union { 568 uint64_t value; 569 struct { 570#if defined(_BIG_ENDIAN) 571 uint32_t rsrvd:32; 572 uint32_t rx_drop_frame_cnt:32; 573#else 574 uint32_t rx_drop_frame_cnt:32; 575 uint32_t rsrvd:32; 576#endif 577 } bits; 578} vmac_rx_drop_fr_cnt_t; 579 580 581/* 582 * Register: VmacRxDropByteCnt 583 * VMAC dropped byte counter 584 * Description: 585 * Fields: 586 * Indicates the number of byte of data dropped by Rx VMAC. 587 * Frames are dropped for one of the follg conditions : - crc 588 * mismatch & crc check is enabled - failed the L2 address match 589 * & Vmac is not in promiscuous mode - pause packet & Vmac is not 590 * programmed to pass these frames The counter will saturate at 591 * max value. The counter is stalled when Rx VMAC is disabled by 592 * vmacRxCfg::rxEn=0. 593 */ 594typedef union { 595 uint64_t value; 596 struct { 597#if defined(_BIG_ENDIAN) 598 uint32_t rsrvd:32; 599 uint32_t rx_drop_byte_cnt:32; 600#else 601 uint32_t rx_drop_byte_cnt:32; 602 uint32_t rsrvd:32; 603#endif 604 } bits; 605} vmac_rx_drop_byte_cnt_t; 606 607 608/* 609 * Register: VmacRxCrcCnt 610 * VMAC received CRC error frame counter 611 * Description: 612 * Fields: 613 * Indicates the number of frames with invalid CRC. When NMAC 614 * truncates a packet, it asserts crcError indication to VMAC 615 * which then counts it towards CRC error. Thus the VMAC crc 616 * error counter reflects the CRC mismatches on all the packets 617 * going out of RxMAC while the NMAC crc error counter reflects 618 * the CRC mismatches on all the packets coming into RxMAC. The 619 * counter will saturate at max value The counter is stalled when 620 * Rx VMAC is disabled by vmacRxCfg::rxEn=0. 621 */ 622typedef union { 623 uint64_t value; 624 struct { 625#if defined(_BIG_ENDIAN) 626 uint32_t rsrvd:32; 627 uint32_t rx_crc_cnt:32; 628#else 629 uint32_t rx_crc_cnt:32; 630 uint32_t rsrvd:32; 631#endif 632 } bits; 633} vmac_rx_crc_cnt_t; 634 635 636/* 637 * Register: VmacRxPauseCnt 638 * VMAC received pause frame counter 639 * Description: 640 * Fields: 641 * Count the number of pause frames received by Rx VMAC. The 642 * counter is stalled when Rx VMAC is disabled by 643 * vmacRxCfg::rxEn=0. 644 */ 645typedef union { 646 uint64_t value; 647 struct { 648#if defined(_BIG_ENDIAN) 649 uint32_t rsrvd:32; 650 uint32_t rx_pause_cnt:32; 651#else 652 uint32_t rx_pause_cnt:32; 653 uint32_t rsrvd:32; 654#endif 655 } bits; 656} vmac_rx_pause_cnt_t; 657 658 659/* 660 * Register: VmacRxBcastFrCnt 661 * VMAC received broadcast frame counter 662 * Description: 663 * Fields: 664 * Indicates the number of broadcast frames received The counter 665 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 666 */ 667typedef union { 668 uint64_t value; 669 struct { 670#if defined(_BIG_ENDIAN) 671 uint32_t rsrvd:32; 672 uint32_t rx_bcast_fr_cnt:32; 673#else 674 uint32_t rx_bcast_fr_cnt:32; 675 uint32_t rsrvd:32; 676#endif 677 } bits; 678} vmac_rx_bcast_fr_cnt_t; 679 680 681/* 682 * Register: VmacRxMcastFrCnt 683 * VMAC received multicast frame counter 684 * Description: 685 * Fields: 686 * Indicates the number of multicast frames received The counter 687 * is stalled when Rx VMAC is disabled by vmacRxCfg::rxEn=0. 688 */ 689typedef union { 690 uint64_t value; 691 struct { 692#if defined(_BIG_ENDIAN) 693 uint32_t rsrvd:32; 694 uint32_t rx_mcast_fr_cnt:32; 695#else 696 uint32_t rx_mcast_fr_cnt:32; 697 uint32_t rsrvd:32; 698#endif 699 } bits; 700} vmac_rx_mcast_fr_cnt_t; 701 702 703#ifdef __cplusplus 704} 705#endif 706 707#endif /* _HXGE_VMAC_HW_H */ 708