1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright (c) 2002, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25#ifndef HME_MAC_H 26#define HME_MAC_H 27 28/* 29 * HOST MEMORY DATA STRUCTURES 30 */ 31 32/* The pointers to the Descriptor Ring base Addresses must be 2K-byte aligned */ 33 34#define HME_HMDALIGN (2048) 35 36/* 37 * The transmit and receiver Descriptor Rings are organized as "wrap-around 38 * descriptors of programmable size. 39 */ 40#define HME_TMDMAX (64) /* Transmit descriptor ring size */ 41#define HME_RMDMAX (64) /* Receive descriptor ring size */ 42 43/* Transmit descriptor structure */ 44 45struct hme_tmd { 46 uint_t tmd_flags; /* OWN, SOP, EOP, cksum ctl and bufize */ 47 uint_t tmd_addr; /* 8-bye aligned buffer address */ 48}; 49 50/* fields in the tmd_flags */ 51 52#define HMETMD_BUFSIZE (0x3fff << 0) /* 0-13 : Tx Data buffer size */ 53#define HMETMD_CSSTART (0x3f << 14) /* 14-19 : Checksum start offset */ 54#define HMETMD_CSSTUFF (0xff << 20) /* 20-27 : Checksum stuff offset */ 55#define HMETMD_CSENABL (1 << 28) /* 28 : Enable checksum computation */ 56#define HMETMD_EOP (1 << 29) /* 29 : End Of Packet flag */ 57#define HMETMD_SOP (1 << 30) /* 30 : Start Of Packet flag */ 58#define HMETMD_OWN (0x80000000) /* 31 : Ownership flag */ 59 /* 0 - owned by software */ 60 /* 1 - owned by hardware */ 61 62#define HMETMD_CSSTART_MAX 0x3f /* Maximum checksum start offset */ 63#define HMETMD_CSSTUFF_MAX 0xff /* Maximum checksum stuff offset */ 64#define HMETMD_CSSTART_SHIFT 14 /* checksum start bit position */ 65#define HMETMD_CSSTUFF_SHIFT 20 /* checksum stuff bit position */ 66 67/* 68 * Programming Notes: 69 * 70 * 1. If a packet occupies more than one descriptor, the software must 71 * turn over the ownership of the descriptors to the hardware 72 * "last-to-first", in order to avoid race conditions. 73 * 74 * 2. If a packet resides in more than one buffer, the Checksum_Enable, 75 * Checksum_Stuff_Offset and Checksum_Start_Offset fields must have the 76 * same values in all the descriptors that were allocated to the packet. 77 * 78 * 3. The hardware implementation relies on the fact that if a buffer 79 * starts at an "odd" boundary, the DMA state machine can "rewind" 80 * to the nearest burst boundary and execute a full DVMA burst Read. 81 * 82 * There is no other alignment restriction for the transmit data buffer. 83 */ 84 85/* Receive Descriptor structure */ 86 87struct hme_rmd { 88 uint_t rmd_flags; /* OWN, OVFLOW, buf/data size, cksum */ 89 uint_t rmd_addr; /* 8-byte aligned buffer address */ 90}; 91 92/* fields in the rmd_flags */ 93 94#define HMERMD_CKSUM (0xffff << 0) /* 0-15 : checksum computed */ 95#define HMERMD_BUFSIZE (0x3fff << 16) /* 16-29 : buffer/data size */ 96#define HMERMD_OVFLOW (1 << 30) /* 30 : Rx buffer overflow */ 97#define HMERMD_OWN (0x80000000) /* 31 : Ownership flag */ 98 /* 0 - owned by software */ 99 /* 1 - owned by hardware */ 100 101#define HMERMD_BUFSIZE_SHIFT 16 /* buffer/data size bit position */ 102 103/* ************************************************************************* */ 104 105/* Global Register set in SEB (Shared Ethernet Block) */ 106 107struct hme_global { 108 uint_t reset; /* Global Software Reset Command */ 109 uint_t config; /* Global Configuration Register */ 110 uint_t reserved[62]; 111 uint_t status; /* Global Status Register */ 112 uint_t intmask; /* Global Interrupt Mask Register */ 113}; 114 115 116/* 117 * Global Software Reset Command Register - RW 118 * These bits become "self cleared" after the corresponding reset command 119 * has been executed. After a reset, the software must poll this register 120 * till both the bits are read as 0's. 121 */ 122 123#define HMEG_RESET_ETX (1 << 0) /* Reset ETX */ 124#define HMEG_RESET_ERX (1 << 1) /* Reset ERX */ 125 126#define HMEG_RESET_GLOBAL HMEG_RESET_ETX | HMEG_RESET_ERX 127 128 129/* Global Configuration Register - RW */ 130 131#define HMEG_CONFIG_BURSTSZ (0x3 << 0) /* sbus max burst size */ 132#define HMEG_CONFIG_64BIT_XFER (1 << 2) /* Extended transfer mode */ 133#define HMEG_CONFIG_PARITY (1 << 3) /* sbus parity enable */ 134#define HMEG_CONFIG_RES1 (1 << 4) /* reserved, should be 0 */ 135 136#define HMEG_CONFIG_BURST16 0x00 /* sbus max burst size 16 */ 137#define HMEG_CONFIG_BURST32 0x01 /* sbus max burst size 32 */ 138#define HMEG_CONFIG_BURST64 0x02 /* sbus max burst size 64 */ 139#define HMEG_CONFIG_BURST_RES 0x03 /* sbus max burst size - reserved */ 140 141#define HMEG_CONFIG_64BIT_SHIFT 2 142/* 143 * Global Status Register - R-AC 144 * 145 * All the bits in the Global Status Register are automatically cleared when 146 * read with the exception of bit 23. The MIF status bit will be cleared after 147 * the MIF Status Register is read. 148 */ 149 150 151#define HMEG_STATUS_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */ 152#define HMEG_STATUS_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */ 153#define HMEG_STATUS_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */ 154#define HMEG_STATUS_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */ 155#define HMEG_STATUS_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */ 156#define HMEG_STATUS_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */ 157#define HMEG_STATUS_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */ 158#define HMEG_STATUS_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */ 159 160#define HMEG_STATUS_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */ 161#define HMEG_STATUS_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */ 162#define HMEG_STATUS_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */ 163#define HMEG_STATUS_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */ 164#define HMEG_STATUS_EXCOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */ 165#define HMEG_STATUS_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */ 166#define HMEG_STATUS_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */ 167#define HMEG_STATUS_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */ 168 169#define HMEG_STATUS_RINT (1 << 16) /* from RxFIFO to host memory */ 170#define HMEG_STATUS_RX_DROP (1 << 17) /* No free Rx descriptors */ 171#define HMEG_STATUS_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */ 172#define HMEG_STATUS_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */ 173#define HMEG_STATUS_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */ 174#define HMEG_STATUS_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */ 175#define HMEG_STATUS_EOP_ERR (1 << 22) /* EOP not set in Tx desc */ 176#define HMEG_STATUS_MIF_INTR (1 << 23) /* MIF interrupt */ 177 178#define HMEG_STATUS_TINT (1 << 24) /* from host mem to TxFIFO */ 179#define HMEG_STATUS_TX_ALL (1 << 25) /* TxFIFO empty */ 180#define HMEG_STATUS_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */ 181#define HMEG_STATUS_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */ 182#define HMEG_STATUS_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */ 183#define HMEG_STATUS_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */ 184#define HMEG_STATUS_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */ 185#define HMEG_STATUS_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */ 186 187#define HMEG_STATUS_FATAL_ERR 0xfc7c0000 /* all fatal errors */ 188#define HMEG_STATUS_NONFATAL_ERR 0x0002fefc /* all non-fatal errors */ 189#define HMEG_STATUS_NORMAL_INT 0x01810000 /* normal interrupts */ 190 191#define HMEG_STATUS_INTR 0xfefffefc /* All interesting interrupts */ 192 193/* 194 * Global Interrupt Mask register 195 * 196 * There is one-to-one correspondence between the bits in this register and 197 * the Global Status register. 198 * 199 * The MIF interrupt [bit 23] is not maskable here. It should be masked at the 200 * source of the interrupt in the MIF. 201 * 202 * Default value of the Global Interrupt Mask register is 0xFF7FFFFF. 203 */ 204 205#define HMEG_MASK_FRAME_RCVD (1 << 0) /* from RX_MAC to RxFIFO */ 206#define HMEG_MASK_RXF_CNT_EXP (1 << 1) /* Rx_frame_counter expired */ 207#define HMEG_MASK_ALN_CNT_EXP (1 << 2) /* Alignment_Error_cntr exp */ 208#define HMEG_MASK_CRC_CNT_EXP (1 << 3) /* CRC_Error_counter expired */ 209#define HMEG_MASK_LEN_CNT_EXP (1 << 4) /* Length_Error_counter exp */ 210#define HMEG_MASK_RXFIFO_OVFL (1 << 5) /* RxFIFO_Overflow in RX_MAC */ 211#define HMEG_MASK_RCV_CNT_EXP (1 << 6) /* Code_Violation_counter exp */ 212#define HMEG_MASK_SQE_TST_ERR (1 << 7) /* SQE Test error in XIF */ 213 214#define HMEG_MASK_FRAME_SENT (1 << 8) /* Frame sent from TX_MAC */ 215#define HMEG_MASK_TXFIFO_UNDR (1 << 9) /* TxFIFO Underrun in TX_MAC */ 216#define HMEG_MASK_MXPKTSZ_ERR (1 << 10) /* Maximum_Packet_Size error */ 217#define HMEG_MASK_NRMCOLC_EXP (1 << 11) /* Normal_collision_cntr exp */ 218#define HMEG_MASK_EXECOLC_EXP (1 << 12) /* Excessive_coll_cntr exp */ 219#define HMEG_MASK_LATCOLC_EXP (1 << 13) /* Late_Collision_cntr exp */ 220#define HMEG_MASK_FSTCOLC_EXP (1 << 14) /* First_Coll_cntr expired */ 221#define HMEG_MASK_DEFTIMR_EXP (1 << 15) /* Defer_Timer expired */ 222 223#define HMEG_MASK_RINT (1 << 16) /* from RxFIFO to host memory */ 224#define HMEG_MASK_RX_DROP (1 << 17) /* No free Rx descriptors */ 225#define HMEG_MASK_RX_ERR_ACK (1 << 18) /* Error Ack in Rx DMA cycle */ 226#define HMEG_MASK_RX_LATE_ERR (1 << 19) /* Late Error in Rx DMA cycle */ 227#define HMEG_MASK_RX_PAR_ERR (1 << 20) /* Parity error in Rx DMA */ 228#define HMEG_MASK_RX_TAG_ERR (1 << 21) /* No two consecutiv tag bits */ 229#define HMEG_MASK_EOP_ERR (1 << 22) /* EOP not set in Tx desc */ 230#define HMEG_MASK_MIF_INTR (1 << 23) /* MIF interrupt */ 231 232#define HMEG_MASK_TINT (1 << 24) /* from host mem to TxFIFO */ 233#define HMEG_MASK_TX_ALL (1 << 25) /* TxFIFO empty */ 234#define HMEG_MASK_TX_ERR_ACK (1 << 26) /* Error Ack in Tx DMA cycle */ 235#define HMEG_MASK_TX_LATE_ERR (1 << 27) /* Late error in Tx DMA cycle */ 236#define HMEG_MASK_TX_PAR_ERR (1 << 28) /* Parity error in Tx DMA */ 237#define HMEG_MASK_TX_TAG_ERR (1 << 29) /* No two consecutiv tag bits */ 238#define HMEG_MASK_SLV_ERR_ACK (1 << 30) /* Error Ack in PIO cycle */ 239#define HMEG_MASK_SLV_PAR_ERR (0x80000000) /* Parity error in PIO write */ 240 241#define HMEG_MASK_INTR (~HMEG_STATUS_INTR) 242 /* uninteresting interrupts */ 243 244/* 245 * Interrupts which are not interesting are: 246 * HMEG_MASK_FRAME_SENT 247 * HMEG_MASK_RXF_CNT_EXP 248 * HMEG_MASK_FRAME_RCVD 249 */ 250 251/* ************************************************************************* */ 252 253/* ETX Register set */ 254 255struct hme_etx { 256 uint_t txpend; /* Transmit Pending Command */ 257 uint_t config; /* ETX Configuration Register */ 258 uint_t txring; /* Transmit Descriptor Ring Pointer */ 259 uint_t txbuf_base; /* Transmit Data Buffer Base Address */ 260 uint_t txbuf_disp; /* Transmit Data Buffer Displacement */ 261 uint_t txfifo_wr_ptr; /* TxFIFO Write Pointer */ 262 uint_t txfifo_sdwr_ptr; /* TxFIFO Shadow Write Pointer */ 263 uint_t txfifo_rd_ptr; /* TxFIFO Read pointer */ 264 uint_t txfifo_sdrd_ptr; /* TxFIFO Shadow Read pointer */ 265 uint_t txfifo_pkt_cnt; /* TxFIFO Packet Counter */ 266 uint_t state_mach; /* ETX State Machine Register */ 267 uint_t txring_size; /* Descriptor Ring Size */ 268 uint_t txbuf_ptr; /* Transmit Data Buffer Pointer */ 269}; 270 271/* 272 * ETX Transmit Pending Command Register - RW 273 * This 1-bit command must be issued by the software for every packet that the 274 * driver posts to the hardware. 275 * This bit becomes "self-cleared" after the command is executed. 276 */ 277 278#define HMET_TXPEND_TDMD (1 << 0) /* wake up Tx DMA engine */ 279 280/* 281 * ETX Configuration Register 282 * If the desire is to buffer an entire standard Ethernet frame before its 283 * transmission is enabled, the Tx-FIFO-Threshold field has to be proframmed 284 * to "0x1ff". 285 * The default value for the register is 0x3fe. 286 * Bit 10 is used to modify the functionality of the Tx_All interrupt. 287 * If it is 0, Tx_All interrupt is generated after processing the last 288 * transmit descriptor with the OWN bit set. This only implies that the 289 * data has been copied to the FIFO. 290 * If it is 1, Tx_All interrupt is generated only after the entire 291 * Transmit FIFO has been drained. 292 */ 293 294#define HMET_CONFIG_TXDMA_EN (1 << 0) /* Enable Tx DMA */ 295#define HMET_CONFIG_TXFIFOTH (0x1ff << 1) /* 1-9 : TX FIFO Threshold */ 296#define HMET_CONFIG_DRAIN_INT (1 << 10) /* TX_all_int modifier */ 297 298/* 299 * Transmit Descriptor Pointer 300 * 301 * This 29-bit register points to the next descriptor in the ring. The 21 most 302 * significant bits are used as the base address for the desriptor ring, 303 * and the 8 least significant bits are used as a displacement for the current 304 * descriptor. 305 * 306 * This register should be initialized to a 2KByte-aligned value after power-on 307 * or Software Reset. 308 * 309 */ 310 311/* 312 * ETX TX ring size register 313 * This is a 4-bit register to determine the no. of descriptor entries in the 314 * TX-ring. The number of entries can vary from 16 through 256 in increments of 315 * 16. 316 */ 317 318#define HMET_RINGSZ_SHIFT 4 319 320/* ************************************************************************* */ 321 322/* ERX Register Set */ 323 324struct hme_erx { 325 uint_t config; /* ERX Configuration Register */ 326 uint_t rxring; /* Receive Descriptor Ring Pointer */ 327 uint_t rxbuf_ptr; /* Receive Data Buffer Pointer */ 328 uint_t rxfifo_wr_ptr; /* RxFIFO Write Pointer */ 329 uint_t rxfifo_sdwr_ptr; /* RxFIFO Shadow Write Pointer */ 330 uint_t rxfifo_rd_ptr; /* RxFIFO Read pointer */ 331 uint_t rxfifo_pkt_cnt; /* RxFIFO Packet Counter */ 332 uint_t state_mach; /* ERX State Machine Register */ 333}; 334 335/* 336 * ERX Configuration Register - RW 337 * This 23-bit register determines the ERX-specific parameters that control the 338 * operation of the receive DMA channel. 339 */ 340 341#define HMER_CONFIG_RXDMA_EN (1 << 0) /* 0 : Enable Rx DMA */ 342#define HMER_CONFIG_RES1 (0x3 << 1) /* 1,2 : reserverd */ 343#define HMER_CONFIG_FBOFFSET (0x7 << 3) /* 3-5 : First Byte Offset */ 344#define HMER_CONFIG_RES2 (0x7 << 6) /* 6-8 : reserverd */ 345#define HMER_CONFIG_RXRINGSZ (0x3 << 9) /* 9,10 : RX desc. ring size */ 346#define HMER_CONFIG_RES3 (0x1f << 11) /* 11-15 : reserverd */ 347#define HMER_CONFIG_RX_CSSTART (0x7f << 16) /* 16-22 : cksum start offset */ 348 349#define HMER_CONFIG_RXRINGSZ32 (0x0 << 9) /* Rx descr. ring size 32 */ 350#define HMER_CONFIG_RXRINGSZ64 (0x1 << 9) /* Rx descr. ring size 64 */ 351#define HMER_CONFIG_RXRINGSZ128 (0x2 << 9) /* Rx descr. ring size 128 */ 352#define HMER_CONFIG_RXRINGSZ256 (0x3 << 9) /* Rx descr. ring size 256 */ 353 354#define HMER_CONFIG_FBO_SHIFT 3 355#define HMER_RXRINGSZ_SHIFT 9 356#define HMER_RX_CSSTART_SHIFT 16 357 358/* 359 * Receive Descriptor Pointer 360 * 361 * This 29-bit register points to the next descriptor in the ring. The 21 most 362 * significant bits are used as the base address for the desriptor ring, 363 * and the 8 least significant bits are used as a displacement for the current 364 * descriptor. 365 * 366 * This register should be initialized to a 2KByte-aligned value after power-on 367 * or Software Reset. 368 * 369 */ 370 371/* ************************************************************************* */ 372 373 374 375/* 376 * Declarations and definitions specific to the BigMAC functional block. 377 * 378 * The BigMAC block will provide the MAC functons for 10 or 100 Mbps CSMA/CD 379 * protocol based interface. 380 * 381 */ 382 383/* 384 * BigMAC Register Set. 385 * BigMAC addresses map on a SBus word boundry. So all registers are 386 * declared for a size of 32 bits. Registers that use fewer than 32 387 * bits will return 0 in the bits not used. 388 */ 389struct hme_bmac { 390 uint_t xifc; /* XIF Configuration register [9-0] (RW) */ 391 uint_t pad1[129]; /* XXX unused */ 392 uint_t txrst; /* tx software reset (RW) */ 393 uint_t txcfg; /* tx configuration register [9-0] (RW) */ 394 uint_t ipg1; /* Inter Packet Gap 1 [7-0] (RW) */ 395 uint_t ipg2; /* Inter Packet Gap 2 [7-0] (RW) */ 396 uint_t alimit; /* attempt limit register [7-0] (RW) */ 397 uint_t slot; /* slot time register [7-0] (RW) */ 398 uint_t palen; /* preamble length register [7-0] (RW) */ 399 uint_t papat; /* preamble pattern register [7-0] (RW) */ 400 uint_t txsfd; /* tx start frame delimiter [7-0] (RW) */ 401 uint_t jam; /* jam size register [7-0] (RW) */ 402 uint_t txmax; /* tx maximum packet size [12-0] (RW) */ 403 uint_t txmin; /* tx minimum frame size [7-0] (RW) */ 404 uint_t parg; /* peak attempt count [7-0] (RW) */ 405 uint_t dcnt; /* defer timer counter [15-0] (RW) */ 406 uint_t nccnt; /* normal collision counter [15-0] (RW) */ 407 uint_t fccnt; /* first succesful coll. counter [15-0] (RW) */ 408 uint_t excnt; /* excess collision counter [7-0] (RW) */ 409 uint_t ltcnt; /* late collision counter [7-0] (RW) */ 410 uint_t rseed; /* random number seed [9-0] (RW) */ 411 uint_t txsm; /* tx state machine register [8-0] (R) */ 412 uint_t pad2[44]; /* XXX Unused */ 413 uint_t rxrst; /* rx software reset register (RW) */ 414 uint_t rxcfg; /* rx configuration register [12-0] (RW) */ 415 uint_t rxmax; /* rx maximum packet size [12-0] (RW) */ 416 uint_t rxmin; /* rx minimum frame size [7-0] (RW) */ 417 uint_t madd2; /* mac address register 2 [47-32] (RW) */ 418 uint_t madd1; /* mac address register 1 [31-16] (RW) */ 419 uint_t madd0; /* mac address register 0 [15-0] (RW) */ 420 uint_t frcnt; /* receive frame count [15-0] (RW) */ 421 uint_t lecnt; /* rx giant length error count [7-0] (RW) */ 422 uint_t aecnt; /* rx alignment error count [7-0] (RW) */ 423 uint_t fecnt; /* receive crc error count [7-0] (RW) */ 424 uint_t rxsm; /* rx state machine register (R) */ 425 uint_t rxcv; /* rx code voilation register (R) */ 426 uchar_t pad3[4]; 427 uint_t hash3; /* hash table 3 [63-48] (RW) */ 428 uint_t hash2; /* hash table 2 [47-32] (RW) */ 429 uint_t hash1; /* hash table 1 [31-16] (RW) */ 430 uint_t hash0; /* hash table 0 [15-0] (RW) */ 431 uint_t afr2; /* addr filter register 0_2 [15-0] (RW) */ 432 uint_t afr1; /* addr filter register 0_1 [15-0] (RW) */ 433 uint_t afr0; /* addr filter register 0_0 [15-0] (RW) */ 434 uint_t afmr; /* addr filter mask reg 0 [15-0] (RW) */ 435}; 436 437/* 438 * BigMAC Register Bit Masks. 439 */ 440 441/* XIF Configuration Register */ 442 443#define BMAC_XIFC_ENAB (1 << 0) /* Enable XIF output drivers */ 444#define BMAC_XIFC_XIFLPBK (1 << 1) /* Enable XIF Loopback mode */ 445#define BMAC_XIFC_MIILPBK (1 << 2) /* Enable MII Loopback mode */ 446#define BMAC_XIFC_MIIBUFDIS (1 << 3) /* Disable MII Recv Buffers */ 447 448/* IN FEPS 2.1 or earlier rev */ 449#define BMAC_XIFC_SQETSTENB (1 << 4) /* Enable SQE Test */ 450#define BMAC_XIFC_SQETSTWIN (0x1f << 5) /* SQE Test time window */ 451 452/* IN FEPS 2.2 or later rev */ 453#define BMAC_XIFC_LANCE_ENAB (1 << 4) /* Enable LANCE mode */ 454#define BMAC_XIFC_LANCE_IPG0 (0x1f << 5) /* IPG0 for LANCE mode */ 455 456#define BMAC_XIFC_IPG0_SHIFT 5 457 458/* 459 * TX_MAC Software Reset Command Register 460 * This bit is set to 1 when a PIO write is done. This bit becomes self-cleared. 461 * after the command has been executed. 462 */ 463 464#define BMAC_TX_RESET (1 << 0) /* TX_MAC Reset Command */ 465 466/* 467 * TX_MAC Configuration Register 468 * To Ensure proper operation of the TX_MAC, the TX_MAC_Enable bit must always 469 * be cleared to 0 and a delay imposed before a PIO write to any of the other 470 * bits in the TX_MAC Configuration register or any of the MAC parameter 471 * registers is done. 472 * 473 * The amount of delay required depends on the time required to transmit a max. 474 * size frame. 475 */ 476 477#define BMACTXRSTDELAY (125) /* 125 us wait period */ 478 479#define BMAC_TXCFG_ENAB (1 << 0) /* tx enable */ 480#define BMAC_TXCFG_RES1 (0xf << 1) /* 1-4 : reserved */ 481#define BMAC_TXCFG_SLOW (1 << 5) /* carrier detect before tx */ 482#define BMAC_TXCFG_IGCOLL (1 << 6) /* tx ignore collision */ 483#define BMAC_TXCFG_NFCS (1 << 7) /* no FCS will be generated */ 484#define BMAC_TXCFG_NBKOFF (1 << 8) /* No Backoff */ 485#define BMAC_TXCFG_FDX (1 << 9) /* Full Duplex */ 486#define BMAC_TXCFG_NGU (1 << 10) /* Never Give Up */ 487 488/* 489 * RX_MAC Configuration Register 490 * A delay of 3.2 us should be allowed after clearing Rx_MAC_Enable or 491 * Hash_Filter_enable or Address_Filter_Enable bits. 492 */ 493 494#define BMACRXRSTDELAY (40) /* 3.2 us wait period */ 495 496#define BMAC_RXCFG_ENAB (1 << 0) /* rx enable */ 497#define BMAC_RXCFG_RES1 (0xf << 1) /* 1-4 : reserved */ 498#define BMAC_RXCFG_STRIP (1 << 5) /* rx strip pad bytes */ 499#define BMAC_RXCFG_PROMIS (1 << 6) /* rx enable promiscous */ 500#define BMAC_RXCFG_ERR (1 << 7) /* rx disable error checking */ 501#define BMAC_RXCFG_CRC (1 << 8) /* rx disable CRC stripping */ 502#define BMAC_RXCFG_MYOWN (1 << 9) /* rx filter own packets */ 503#define BMAC_RXCFG_GRPROM (1 << 10) /* rx promiscuous group mode */ 504#define BMAC_RXCFG_HASH (1 << 11) /* rx enable hash filter */ 505#define BMAC_RXCFG_ADDR (1 << 12) /* rx enable address filter */ 506 507 508 509/* ************************************************************************* */ 510 511/* 512 * MII Transceiver Interface 513 * 514 * The Management Interface (MIF) allows the host to program and collect status 515 * from two transceivers connected to the MII. MIF supports three modes of 516 * operation: 517 * 1. Bit-Bang Mode 518 * This mode is imlemented using three 1-bit registers: data, clock, 519 * and output_enable. 520 * 521 * 2. Frame Mode 522 * This mode is supported using one 32-bit register: Frame register. 523 * The software loads the Frame Register with avalid instaruction 524 * ("frame"), and polls the Valid Bit for completion. 525 * 526 * 3. Polling Mode 527 * The Polling mechanism is used for detecting a status change in the 528 * transceiver. When this mode is enabled, the MIF will continuously 529 * poll a specified transceiver register and generate a maskable 530 * interrupt when a status change is detected. This mode of operation 531 * can only be used when the MIF is in the "Frame mode". 532 * 533 */ 534 535struct hme_mif { 536 uint_t mif_bbclk; /* MIF Bit Bang Clock */ 537 uint_t mif_bbdata; /* MIF Bit Bang Data */ 538 uint_t mif_bbopenb; /* MIF Bit Bang Output Enable */ 539 uint_t mif_frame; /* MIF Frame - ctl and data */ 540 uint_t mif_cfg; /* MIF Configuration */ 541 uint_t mif_imask; /* MIF Interrupt mask */ 542 uint_t mif_bsts; /* MIF Basic/Status register */ 543 uint_t mif_fsm; /* MIF State machine register */ 544}; 545 546/* mif_bbc - Bit Bang Clock register */ 547#define HME_MIF_BBCLK (1 << 0); /* Bit Babg Clock */ 548 549#define HME_BBCLK_LOW 0 550#define HME_BBCLK_HIGH 1 551 552/* mif_bbdata - bit Bang Data register */ 553#define HME_MIF_BBDATA (1 << 0); /* Bit Bang Data */ 554 555/* mif_bbopenb - Bit Bang oOutput Enable register */ 556#define HME_MIF_BBOPENB (1 << 0); /* Bit Bang output Enable */ 557 558/* 559 * Management Frame Structure: 560 * <IDLE> <ST><OP><PHYAD><REGAD><TA> <DATA> <IDLE> 561 * READ: <01><10><AAAAA><RRRRR><Z0><DDDDDDDDDDDDDDDD> 562 * WRITE: <01><01><AAAAA><RRRRR><10><DDDDDDDDDDDDDDDD> 563 */ 564 565/* mif_frame - MIF control and data register */ 566 567#define HME_MIF_FRDATA (0xffff << 0) /* 0-15 : data bits */ 568#define HME_MIF_FRTA0 (0x1 << 16) /* 16 : TA bit, 1 for completion */ 569#define HME_MIF_FRTA1 (0x1 << 17) /* 16-17 : TA bits */ 570#define HME_MIF_FRREGAD (0x1f << 18) /* 18-22 : register address bits */ 571#define HME_MIF_FRPHYAD (0x1f << 23) /* 23-27 : PHY ad, should be 0 */ 572#define HME_MIF_FROP (0x3 << 28) /* 28-29 : Operation - Write/Read */ 573#define HME_MIF_FRST (0xc0000000) /* 30-31 : START bits */ 574 575#define HME_MIF_FRREGAD_SHIFT 18 576#define HME_MIF_FRPHYAD_SHIFT 23 577#define HME_MIF_FRREAD 0x60020000 578#define HME_MIF_FRWRITE 0x50020000 579 580/* maximum delay for MIF Register Read/Write operation */ 581#define HMEMAXMIFDELAY (100) 582 583/* maximum delay for Transceiver Reset */ 584#define HME_PHYRST_MAXDELAY (500) 585 586/* mif_cfg - MIF Configuration Register */ 587 588#define HME_MIF_CFGPS (1 << 0) /* PHY Select */ 589#define HME_MIF_CFGPE (1 << 1) /* Poll Enable */ 590#define HME_MIF_CFGBB (1 << 2) /* Bit Bang Enable */ 591#define HME_MIF_CFGPR (0x1f << 3) /* Poll Register address */ 592#define HME_MIF_CFGM0 (1 << 8) /* MDIO_0 Data / MDIO_0 attached */ 593#define HME_MIF_CFGM1 (1 << 9) /* MDIO_1 Data / MDIO_1 attached */ 594#define HME_MIF_CFGPD (0x1f << 10) /* Poll Device PHY address */ 595 596#define HME_MIF_CFGPR_SHIFT 3 597#define HME_MIF_CFGPD_SHIFT 10 598#define HME_MIF_POLL_DELAY 200 599 600/* 601 * MDIO_0 corresponds to the On Board Transceiver. 602 * MDIO_1 corresponds to the External Transceiver. 603 * The PHYAD for both is 0. 604 */ 605 606#define HME_INTERNAL_PHYAD 1 /* PHY address for int. transceiver */ 607#define HME_EXTERNAL_PHYAD 0 /* PHY address for ext. transceiver */ 608 609 610/* mif_imask - MIF Interrupt Mask Register */ 611/* 612 * This register is bit-to-bit same as Basic/Status Register 613 */ 614#define HME_MIF_INTMASK (0xffff << 0) /* 0-15 : Interrupt mask */ 615 616/* mif_bassts - MIF Basic / Status register */ 617/* 618 * The Basic portion of this register indicates the last value of the register 619 * read indicated in the POLL REG field of the Configuration Register. 620 * The Status portion indicates bit(s) that have changed. 621 * The MIF Mask register is corresponding to this register in terms of the 622 * bit(s) that need to be masked for generating interrupt on the MIF Interrupt 623 * Bit of the Global Status Rgister. 624 */ 625 626#define HME_MIF_STATUS (0xffff << 0) /* 0-15 : Status */ 627#define HME_MIF_BASIC (0xffff << 16) /* 16-31 : Basic register */ 628 629/* mif_fsm - MIF State Machine register */ 630 631#define HME_MIF_FSM (0x3ff << 0) /* 0-9 : MIF state */ 632 633/* ************************************************************************ */ 634 635 636/* 637 * Definition for the time required to wait after a software 638 * reset has been issued. 639 */ 640#define HMEMAXRSTDELAY (200) 641#define HMEPERIOD (20) /* period to wait */ 642#define HMEWAITPERIOD HMEPERIOD 643 644#define HMEDELAY(c, n) \ 645 { \ 646 register int N = n / HMEWAITPERIOD; \ 647 while (--N > 0) { \ 648 if (c) \ 649 break; \ 650 drv_usecwait(HMEWAITPERIOD); \ 651 } \ 652 } 653 654#endif /* HME_MAC_H */ 655