1/* 2 * This file is provided under a CDDLv1 license. When using or 3 * redistributing this file, you may do so under this license. 4 * In redistributing this file this license must be included 5 * and no other modification of this header file is permitted. 6 * 7 * CDDL LICENSE SUMMARY 8 * 9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved. 10 * 11 * The contents of this file are subject to the terms of Version 12 * 1.0 of the Common Development and Distribution License (the "License"). 13 * 14 * You should have received a copy of the License with this software. 15 * You can obtain a copy of the License at 16 * http://www.opensolaris.org/os/licensing. 17 * See the License for the specific language governing permissions 18 * and limitations under the License. 19 */ 20 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms of the CDDLv1. 24 */ 25 26/* 27 * IntelVersion: 1.53 v3-1-10-1_2009-9-18_Release14-6 28 */ 29 30/* 31 * 82542 Gigabit Ethernet Controller 32 */ 33 34#include "e1000_api.h" 35 36static s32 e1000_init_phy_params_82542(struct e1000_hw *hw); 37static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw); 38static s32 e1000_init_mac_params_82542(struct e1000_hw *hw); 39static s32 e1000_get_bus_info_82542(struct e1000_hw *hw); 40static s32 e1000_reset_hw_82542(struct e1000_hw *hw); 41static s32 e1000_init_hw_82542(struct e1000_hw *hw); 42static s32 e1000_setup_link_82542(struct e1000_hw *hw); 43static s32 e1000_led_on_82542(struct e1000_hw *hw); 44static s32 e1000_led_off_82542(struct e1000_hw *hw); 45static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index); 46static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw); 47static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw); 48 49/* 50 * e1000_init_phy_params_82542 - Init PHY func ptrs. 51 * @hw: pointer to the HW structure 52 */ 53static s32 54e1000_init_phy_params_82542(struct e1000_hw *hw) 55{ 56 struct e1000_phy_info *phy = &hw->phy; 57 s32 ret_val = E1000_SUCCESS; 58 59 DEBUGFUNC("e1000_init_phy_params_82542"); 60 61 phy->type = e1000_phy_none; 62 63 return (ret_val); 64} 65 66/* 67 * e1000_init_nvm_params_82542 - Init NVM func ptrs. 68 * @hw: pointer to the HW structure 69 */ 70static s32 71e1000_init_nvm_params_82542(struct e1000_hw *hw) 72{ 73 struct e1000_nvm_info *nvm = &hw->nvm; 74 75 DEBUGFUNC("e1000_init_nvm_params_82542"); 76 77 nvm->address_bits = 6; 78 nvm->delay_usec = 50; 79 nvm->opcode_bits = 3; 80 nvm->type = e1000_nvm_eeprom_microwire; 81 nvm->word_size = 64; 82 83 /* Function Pointers */ 84 nvm->ops.read = e1000_read_nvm_microwire; 85 nvm->ops.release = e1000_stop_nvm; 86 nvm->ops.write = e1000_write_nvm_microwire; 87 nvm->ops.update = e1000_update_nvm_checksum_generic; 88 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 89 90 return (E1000_SUCCESS); 91} 92 93/* 94 * e1000_init_mac_params_82542 - Init MAC func ptrs. 95 * @hw: pointer to the HW structure 96 */ 97static s32 98e1000_init_mac_params_82542(struct e1000_hw *hw) 99{ 100 struct e1000_mac_info *mac = &hw->mac; 101 102 DEBUGFUNC("e1000_init_mac_params_82542"); 103 104 /* Set media type */ 105 hw->phy.media_type = e1000_media_type_fiber; 106 107 /* Set mta register count */ 108 mac->mta_reg_count = 128; 109 /* Set rar entry count */ 110 mac->rar_entry_count = E1000_RAR_ENTRIES; 111 112 /* Function pointers */ 113 114 /* bus type/speed/width */ 115 mac->ops.get_bus_info = e1000_get_bus_info_82542; 116 /* function id */ 117 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci; 118 /* reset */ 119 mac->ops.reset_hw = e1000_reset_hw_82542; 120 /* hw initialization */ 121 mac->ops.init_hw = e1000_init_hw_82542; 122 /* link setup */ 123 mac->ops.setup_link = e1000_setup_link_82542; 124 /* phy/fiber/serdes setup */ 125 mac->ops.setup_physical_interface = 126 e1000_setup_fiber_serdes_link_generic; 127 /* check for link */ 128 mac->ops.check_for_link = e1000_check_for_fiber_link_generic; 129 /* multicast address update */ 130 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 131 /* writing VFTA */ 132 mac->ops.write_vfta = e1000_write_vfta_generic; 133 /* clearing VFTA */ 134 mac->ops.clear_vfta = e1000_clear_vfta_generic; 135 /* setting MTA */ 136 mac->ops.mta_set = e1000_mta_set_generic; 137 /* read mac address */ 138 mac->ops.read_mac_addr = e1000_read_mac_addr_82542; 139 /* set RAR */ 140 mac->ops.rar_set = e1000_rar_set_82542; 141 /* turn on/off LED */ 142 mac->ops.led_on = e1000_led_on_82542; 143 mac->ops.led_off = e1000_led_off_82542; 144 /* clear hardware counters */ 145 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542; 146 /* link info */ 147 mac->ops.get_link_up_info = 148 e1000_get_speed_and_duplex_fiber_serdes_generic; 149 150 return (E1000_SUCCESS); 151} 152 153/* 154 * e1000_init_function_pointers_82542 - Init func ptrs. 155 * @hw: pointer to the HW structure 156 * 157 * Called to initialize all function pointers and parameters. 158 */ 159void 160e1000_init_function_pointers_82542(struct e1000_hw *hw) 161{ 162 DEBUGFUNC("e1000_init_function_pointers_82542"); 163 164 hw->mac.ops.init_params = e1000_init_mac_params_82542; 165 hw->nvm.ops.init_params = e1000_init_nvm_params_82542; 166 hw->phy.ops.init_params = e1000_init_phy_params_82542; 167} 168 169/* 170 * e1000_get_bus_info_82542 - Obtain bus information for adapter 171 * @hw: pointer to the HW structure 172 * 173 * This will obtain information about the HW bus for which the 174 * adapter is attached and stores it in the hw structure. 175 */ 176static s32 177e1000_get_bus_info_82542(struct e1000_hw *hw) 178{ 179 DEBUGFUNC("e1000_get_bus_info_82542"); 180 181 hw->bus.type = e1000_bus_type_pci; 182 hw->bus.speed = e1000_bus_speed_unknown; 183 hw->bus.width = e1000_bus_width_unknown; 184 185 return (E1000_SUCCESS); 186} 187 188/* 189 * e1000_reset_hw_82542 - Reset hardware 190 * @hw: pointer to the HW structure 191 * 192 * This resets the hardware into a known state. 193 */ 194static s32 195e1000_reset_hw_82542(struct e1000_hw *hw) 196{ 197 struct e1000_bus_info *bus = &hw->bus; 198 s32 ret_val = E1000_SUCCESS; 199 u32 ctrl; 200 201 DEBUGFUNC("e1000_reset_hw_82542"); 202 203 if (hw->revision_id == E1000_REVISION_2) { 204 DEBUGOUT("Disabling MWI on 82542 rev 2\n"); 205 e1000_pci_clear_mwi(hw); 206 } 207 208 DEBUGOUT("Masking off all interrupts\n"); 209 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 210 211 E1000_WRITE_REG(hw, E1000_RCTL, 0); 212 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 213 E1000_WRITE_FLUSH(hw); 214 215 /* 216 * Delay to allow any outstanding PCI transactions to complete before 217 * resetting the device 218 */ 219 msec_delay(10); 220 221 ctrl = E1000_READ_REG(hw, E1000_CTRL); 222 223 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n"); 224 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 225 226 hw->nvm.ops.reload(hw); 227 msec_delay(2); 228 229 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff); 230 (void) E1000_READ_REG(hw, E1000_ICR); 231 232 if (hw->revision_id == E1000_REVISION_2) { 233 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 234 e1000_pci_set_mwi(hw); 235 } 236 return (ret_val); 237} 238 239/* 240 * e1000_init_hw_82542 - Initialize hardware 241 * @hw: pointer to the HW structure 242 * 243 * This inits the hardware readying it for operation. 244 */ 245static s32 246e1000_init_hw_82542(struct e1000_hw *hw) 247{ 248 struct e1000_mac_info *mac = &hw->mac; 249 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542; 250 s32 ret_val = E1000_SUCCESS; 251 u32 ctrl; 252 u16 i; 253 254 DEBUGFUNC("e1000_init_hw_82542"); 255 256 /* Disabling VLAN filtering */ 257 E1000_WRITE_REG(hw, E1000_VET, 0); 258 mac->ops.clear_vfta(hw); 259 260 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */ 261 if (hw->revision_id == E1000_REVISION_2) { 262 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n"); 263 e1000_pci_clear_mwi(hw); 264 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST); 265 E1000_WRITE_FLUSH(hw); 266 msec_delay(5); 267 } 268 269 /* Setup the receive address. */ 270 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 271 272 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */ 273 if (hw->revision_id == E1000_REVISION_2) { 274 E1000_WRITE_REG(hw, E1000_RCTL, 0); 275 E1000_WRITE_FLUSH(hw); 276 msec_delay(1); 277 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE) 278 e1000_pci_set_mwi(hw); 279 } 280 281 /* Zero out the Multicast HASH table */ 282 DEBUGOUT("Zeroing the MTA\n"); 283 for (i = 0; i < mac->mta_reg_count; i++) 284 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 285 286 /* 287 * Set the PCI priority bit correctly in the CTRL register. This 288 * determines if the adapter gives priority to receives, or if it 289 * gives equal priority to transmits and receives. 290 */ 291 if (dev_spec->dma_fairness) { 292 ctrl = E1000_READ_REG(hw, E1000_CTRL); 293 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR); 294 } 295 296 /* Setup link and flow control */ 297 ret_val = e1000_setup_link_82542(hw); 298 299 /* 300 * Clear all of the statistics registers (clear on read). It is 301 * important that we do this after we have tried to establish link 302 * because the symbol error count will increment wildly if there 303 * is no link. 304 */ 305 e1000_clear_hw_cntrs_82542(hw); 306 307 return (ret_val); 308} 309 310/* 311 * e1000_setup_link_82542 - Setup flow control and link settings 312 * @hw: pointer to the HW structure 313 * 314 * Determines which flow control settings to use, then configures flow 315 * control. Calls the appropriate media-specific link configuration 316 * function. Assuming the adapter has a valid link partner, a valid link 317 * should be established. Assumes the hardware has previously been reset 318 * and the transmitter and receiver are not enabled. 319 */ 320static s32 321e1000_setup_link_82542(struct e1000_hw *hw) 322{ 323 struct e1000_mac_info *mac = &hw->mac; 324 s32 ret_val = E1000_SUCCESS; 325 326 DEBUGFUNC("e1000_setup_link_82542"); 327 328 ret_val = e1000_set_default_fc_generic(hw); 329 if (ret_val) 330 goto out; 331 332 hw->fc.requested_mode &= ~e1000_fc_tx_pause; 333 334 if (mac->report_tx_early == 1) 335 hw->fc.requested_mode &= ~e1000_fc_rx_pause; 336 337 /* 338 * Save off the requested flow control mode for use later. Depending 339 * on the link partner's capabilities, we may or may not use this mode. 340 */ 341 hw->fc.current_mode = hw->fc.requested_mode; 342 343 DEBUGOUT1("After fix-ups FlowControl is now = %x\n", 344 hw->fc.current_mode); 345 346 /* Call the necessary subroutine to configure the link. */ 347 ret_val = mac->ops.setup_physical_interface(hw); 348 if (ret_val) 349 goto out; 350 351 /* 352 * Initialize the flow control address, type, and PAUSE timer 353 * registers to their default values. This is done even if flow 354 * control is disabled, because it does not hurt anything to 355 * initialize these registers. 356 */ 357 DEBUGOUT("Initializing Flow Control address, type and timer regs\n"); 358 359 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW); 360 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH); 361 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE); 362 363 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time); 364 365 ret_val = e1000_set_fc_watermarks_generic(hw); 366 367out: 368 return (ret_val); 369} 370 371/* 372 * e1000_led_on_82542 - Turn on SW controllable LED 373 * @hw: pointer to the HW structure 374 * 375 * Turns the SW defined LED on. 376 */ 377static s32 378e1000_led_on_82542(struct e1000_hw *hw) 379{ 380 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 381 382 DEBUGFUNC("e1000_led_on_82542"); 383 384 ctrl |= E1000_CTRL_SWDPIN0; 385 ctrl |= E1000_CTRL_SWDPIO0; 386 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 387 388 return (E1000_SUCCESS); 389} 390 391/* 392 * e1000_led_off_82542 - Turn off SW controllable LED 393 * @hw: pointer to the HW structure 394 * 395 * Turns the SW defined LED off. 396 */ 397static s32 398e1000_led_off_82542(struct e1000_hw *hw) 399{ 400 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL); 401 402 DEBUGFUNC("e1000_led_off_82542"); 403 404 ctrl &= ~E1000_CTRL_SWDPIN0; 405 ctrl |= E1000_CTRL_SWDPIO0; 406 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 407 408 return (E1000_SUCCESS); 409} 410 411/* 412 * e1000_rar_set_82542 - Set receive address register 413 * @hw: pointer to the HW structure 414 * @addr: pointer to the receive address 415 * @index: receive address array register 416 * 417 * Sets the receive address array register at index to the address passed 418 * in by addr. 419 */ 420static void 421e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index) 422{ 423 u32 rar_low, rar_high; 424 425 DEBUGFUNC("e1000_rar_set_82542"); 426 427 /* 428 * HW expects these in little endian so we reverse the byte order 429 * from network order (big endian) to little endian 430 */ 431 rar_low = ((u32) addr[0] | 432 ((u32) addr[1] << 8) | 433 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 434 435 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 436 437 /* If MAC address zero, no need to set the AV bit */ 438 if (rar_low || rar_high) 439 rar_high |= E1000_RAH_AV; 440 441 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low); 442 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high); 443} 444 445/* 446 * e1000_translate_register_82542 - Translate the proper register offset 447 * @reg: e1000 register to be read 448 * 449 * Registers in 82542 are located in different offsets than other adapters 450 * even though they function in the same manner. This function takes in 451 * the name of the register to read and returns the correct offset for 452 * 82542 silicon. 453 */ 454u32 455e1000_translate_register_82542(u32 reg) 456{ 457 /* 458 * Some of the 82542 registers are located at different 459 * offsets than they are in newer adapters. 460 * Despite the difference in location, the registers 461 * function in the same manner. 462 */ 463 switch (reg) { 464 case E1000_RA: 465 reg = 0x00040; 466 break; 467 case E1000_RDTR: 468 reg = 0x00108; 469 break; 470 case E1000_RDBAL(0): 471 reg = 0x00110; 472 break; 473 case E1000_RDBAH(0): 474 reg = 0x00114; 475 break; 476 case E1000_RDLEN(0): 477 reg = 0x00118; 478 break; 479 case E1000_RDH(0): 480 reg = 0x00120; 481 break; 482 case E1000_RDT(0): 483 reg = 0x00128; 484 break; 485 case E1000_RDBAL(1): 486 reg = 0x00138; 487 break; 488 case E1000_RDBAH(1): 489 reg = 0x0013C; 490 break; 491 case E1000_RDLEN(1): 492 reg = 0x00140; 493 break; 494 case E1000_RDH(1): 495 reg = 0x00148; 496 break; 497 case E1000_RDT(1): 498 reg = 0x00150; 499 break; 500 case E1000_FCRTH: 501 reg = 0x00160; 502 break; 503 case E1000_FCRTL: 504 reg = 0x00168; 505 break; 506 case E1000_MTA: 507 reg = 0x00200; 508 break; 509 case E1000_TDBAL(0): 510 reg = 0x00420; 511 break; 512 case E1000_TDBAH(0): 513 reg = 0x00424; 514 break; 515 case E1000_TDLEN(0): 516 reg = 0x00428; 517 break; 518 case E1000_TDH(0): 519 reg = 0x00430; 520 break; 521 case E1000_TDT(0): 522 reg = 0x00438; 523 break; 524 case E1000_TIDV: 525 reg = 0x00440; 526 break; 527 case E1000_VFTA: 528 reg = 0x00600; 529 break; 530 case E1000_TDFH: 531 reg = 0x08010; 532 break; 533 case E1000_TDFT: 534 reg = 0x08018; 535 break; 536 default: 537 break; 538 } 539 540 return (reg); 541} 542 543/* 544 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters 545 * @hw: pointer to the HW structure 546 * 547 * Clears the hardware counters by reading the counter registers. 548 */ 549static void 550e1000_clear_hw_cntrs_82542(struct e1000_hw *hw) 551{ 552 DEBUGFUNC("e1000_clear_hw_cntrs_82542"); 553 554 e1000_clear_hw_cntrs_base_generic(hw); 555 556 (void) E1000_READ_REG(hw, E1000_PRC64); 557 (void) E1000_READ_REG(hw, E1000_PRC127); 558 (void) E1000_READ_REG(hw, E1000_PRC255); 559 (void) E1000_READ_REG(hw, E1000_PRC511); 560 (void) E1000_READ_REG(hw, E1000_PRC1023); 561 (void) E1000_READ_REG(hw, E1000_PRC1522); 562 (void) E1000_READ_REG(hw, E1000_PTC64); 563 (void) E1000_READ_REG(hw, E1000_PTC127); 564 (void) E1000_READ_REG(hw, E1000_PTC255); 565 (void) E1000_READ_REG(hw, E1000_PTC511); 566 (void) E1000_READ_REG(hw, E1000_PTC1023); 567 (void) E1000_READ_REG(hw, E1000_PTC1522); 568} 569 570/* 571 * e1000_read_mac_addr_82542 - Read device MAC address 572 * @hw: pointer to the HW structure 573 * 574 * Reads the device MAC address from the EEPROM and stores the value. 575 */ 576s32 577e1000_read_mac_addr_82542(struct e1000_hw *hw) 578{ 579 s32 ret_val = E1000_SUCCESS; 580 u16 offset, nvm_data, i; 581 582 DEBUGFUNC("e1000_read_mac_addr"); 583 584 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 585 offset = i >> 1; 586 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 587 if (ret_val) { 588 DEBUGOUT("NVM Read Error\n"); 589 goto out; 590 } 591 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 592 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 593 } 594 595 for (i = 0; i < ETH_ADDR_LEN; i++) 596 hw->mac.addr[i] = hw->mac.perm_addr[i]; 597 598 out: 599 return (ret_val); 600} 601