1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26#ifndef _SYS_DMFE_H 27#define _SYS_DMFE_H 28 29#pragma ident "%Z%%M% %I% %E% SMI" 30 31#ifdef __cplusplus 32extern "C" { 33#endif 34 35/* Chip ID */ 36#define DAVICOM_VENDOR_ID 0x1282 37#define DEVICE_ID_9100 0x9100 38#define DEVICE_ID_9132 0x9132 39/* The 9102 and 9102A are distinguished by revision ID */ 40#define DEVICE_ID_9102 0x9102 41#define DEVICE_ID_9102A 0x9102 42 43/* Streams */ 44#define DMFEHIWAT 32768 /* driver flow control high water */ 45#define DMFELOWAT 4096 /* driver flow control low water */ 46#define DMFEIDNUM 0 /* DMFE Id; zero works */ 47 48/* Size/count parameters */ 49#define SROM_SIZE 128 50#define SETUPBUF_SIZE 192 /* Setup buffer size in bytes */ 51#define MCASTBUF_SIZE 512 /* multicast hash table size in bits */ 52#define HASH_POLY 0x04C11DB6 53#define HASH_CRC 0xFFFFFFFFU 54#define SETUPBUF_PHYS 39 /* word offset of station physical */ 55 /* address within setup buffer */ 56 57 58/* 59 * Tx/Rx descriptor ring entry formats 60 * 61 * These structures are not actually used; they are just here to show 62 * the layout of the descriptor entries used by the DMFE chip hardware 63 * (we do use "sizeof" these structures). The code uses the #defined 64 * offsets below to access the various members of the descriptors, via 65 * the DDI access functions (remember the DMFE h/w is little-endian). 66 */ 67 68struct rx_desc_type { 69 uint32_t desc0; 70 uint32_t desc1; 71 uint32_t buffer1; 72 uint32_t rd_next; 73}; 74 75struct tx_desc_type { 76 uint32_t desc0; 77 uint32_t desc1; 78 uint32_t buffer1; 79 uint32_t td_next; 80}; 81 82/* 83 * Offsets & sizes for tx/rx descriptors, expressed in (d)words 84 */ 85#define DESC0 0 86#define DESC1 1 87#define BUFFER1 2 88#define RD_NEXT 3 89#define TD_NEXT 3 90#define DESC_SIZE 4 91 92/* 93 * Receive descriptor description 94 */ 95/* desc0 bit definitions */ 96#define RX_OVERFLOW (1UL<<0) 97#define RX_CRC (1UL<<1) 98#define RX_DRIBBLING (1UL<<2) 99#define RX_MII_ERR (1UL<<3) 100#define RX_RCV_WD_TO (1UL<<4) 101#define RX_FRAME_TYPE (1UL<<5) 102#define RX_COLLISION (1UL<<6) 103#define RX_FRAME2LONG (1UL<<7) 104#define RX_LAST_DESC (1UL<<8) 105#define RX_FIRST_DESC (1UL<<9) 106#define RX_MULTI_FRAME (1UL<<10) 107#define RX_RUNT_FRAME (1UL<<11) 108#define RX_LOOP_MODE (3UL<<12) 109#define RX_DESC_ERR (1UL<<14) 110#define RX_ERR_SUMMARY (1UL<<15) 111#define RX_FRAME_LEN (0x3fffUL<<16) 112#define RX_FILTER_FAIL (1UL<<30) 113#define RX_OWN (1UL<<31) 114 115/* desc1 bit definitions */ 116#define RX_BUFFER_SIZE (0x7ff) 117#define RX_CHAINING (1UL<<24) 118#define RX_END_OF_RING (1UL<<25) 119 120/* 121 * Transmit descriptor description 122 */ 123/* desc0 bit definitions */ 124#define TX_DEFERRED (1UL<<0) 125#define TX_UNDERFLOW (1UL<<1) 126#define TX_LINK_FAIL (1UL<<2) 127#define TX_COLL_COUNT (0xfUL<<3) 128#define TX_HEARTBEAT_FAIL (1UL<<7) 129#define TX_EXCESS_COLL (1UL<<8) 130#define TX_LATE_COLL (1UL<<9) 131#define TX_NO_CARRIER (1UL<<10) 132#define TX_CARRIER_LOSS (1UL<<11) 133#define TX_JABBER_TO (1UL<<14) 134#define TX_ERR_SUMMARY (1UL<<15) 135#define TX_SPARE (0x7fffUL<<16) 136#define TX_OWN (1UL<<31) 137 138/* desc1 bit definitions */ 139#define TX_BUFFER_SIZE1 (0x7ffUL<<0) 140#define TX_BUFFER_SIZE2 (0x7ffUL<<11) 141#define TX_FILTER_TYPE0 (1UL<<22) 142#define TX_DISABLE_PAD (1UL<<23) 143#define TX_CHAINING (1UL<<24) 144#define TX_END_OF_RING (1UL<<25) 145#define TX_CRC_DISABLE (1UL<<26) 146#define TX_SETUP_PACKET (1UL<<27) 147#define TX_FILTER_TYPE1 (1UL<<28) 148#define TX_FIRST_DESC (1UL<<29) 149#define TX_LAST_DESC (1UL<<30) 150#define TX_INT_ON_COMP (1UL<<31) 151 152 153/* Device-defined PCI config space registers */ 154#define PCI_DMFE_CONF_CFDD 0x40 155#define CFDD_SNOOZE (1UL<<30) 156#define CFDD_SLEEP (1UL<<31) 157 158 159/* Operating registers in I/O or MEMORY space */ 160#define BUS_MODE_REG 0x00 161#define TX_POLL_REG 0x08 162#define RX_POLL_REG 0x10 163#define RX_BASE_ADDR_REG 0x18 164#define TX_BASE_ADDR_REG 0x20 165#define STATUS_REG 0x28 166#define OPN_MODE_REG 0x30 167#define INT_MASK_REG 0x38 168#define MISSED_FRAME_REG 0x40 169#define ETHER_ROM_REG 0x48 170#define BOOT_ROM_REG 0x50 171#define GP_TIMER_REG 0x58 172#define PHY_STATUS_REG 0x60 173#define FRAME_ACCESS_REG 0x68 174#define FRAME_DATA_REG 0x70 175#define W_J_TIMER_REG 0x78 176 177 178/* Bit descriptions of CSR registers */ 179 180/* BUS_MODE_REG, CSR0 */ 181#define SW_RESET 0x00000001 182#define BURST_SIZE 0 /* unlimited burst length */ 183#define CACHE_ALIGN (3 << 14) /* 32 Dwords */ 184#define TX_POLL_INTVL (1 << 17) /* 200us polling */ 185#define READ_MULTIPLE (1 << 21) /* use Memory Read */ 186 /* Multiple PCI cycles */ 187 188/* STATUS_REG, CSR5 */ 189#define TX_PKTDONE_INT 0x00000001UL 190#define TX_STOPPED_INT 0x00000002UL 191#define TX_ALLDONE_INT 0x00000004UL 192#define TX_JABBER_INT 0x00000008UL 193#define TX_RESERVED_INT 0x00000010UL 194#define TX_UNDERFLOW_INT 0x00000020UL 195 196#define RX_PKTDONE_INT 0x00000040UL 197#define RX_UNAVAIL_INT 0x00000080UL 198#define RX_STOPPED_INT 0x00000100UL 199#define RX_WATCHDOG_INT 0x00000200UL 200 201#define TX_EARLY_INT 0x00000400UL 202#define GP_TIMER_INT 0x00000800UL 203#define LINK_STATUS_INT 0x00001000UL 204#define SYSTEM_ERR_INT 0x00002000UL 205#define RX_EARLY_INT 0x00004000UL 206 207#define ABNORMAL_SUMMARY_INT 0x00008000UL 208#define NORMAL_SUMMARY_INT 0x00010000UL 209#define INT_STATUS_MASK 0x0001ffffUL 210 211#define RX_PROCESS_STOPPED 0x00000000UL 212#define RX_PROCESS_FETCH_DESC 0x00020000UL 213#define RX_PROCESS_WAIT_PKT 0x00040000UL 214#define RX_PROCESS_STORE_DATA 0x00060000UL 215#define RX_PROCESS_CLOSE_OWNER 0x00080000UL 216#define RX_PROCESS_CLOSE_STATUS 0x000a0000UL 217#define RX_PROCESS_SUSPEND 0x000c0000UL 218#define RX_PROCESS_PURGE 0x000e0000UL 219#define RX_PROCESS_STATE_MASK 0x000e0000UL 220#define TX_PROCESS_STOPPED 0x00000000UL 221#define TX_PROCESS_FETCH_DESC 0x00100000UL 222#define TX_PROCESS_FETCH_SETUP 0x00200000UL 223#define TX_PROCESS_FETCH_DATA 0x00300000UL 224#define TX_PROCESS_CLOSE_OWNER 0x00400000UL 225#define TX_PROCESS_WAIT_END 0x00500000UL 226#define TX_PROCESS_CLOSE_STATUS 0x00600000UL 227#define TX_PROCESS_SUSPEND 0x00700000UL 228#define TX_PROCESS_STATE_MASK 0x00700000UL 229#define SYSTEM_ERR_BITS 0x03800000UL 230#define SYSTEM_ERR_PARITY 0x00000000UL 231#define SYSTEM_ERR_M_ABORT 0x00800000UL 232#define SYSTEM_ERR_T_ABORT 0x01000000UL 233 234#define RX_PROCESS_STATE(csr5) (((csr5) & RX_PROCESS_STATE_MASK) >> 17) 235#define RX_PROCESS_MAX_STATE 7 236#define TX_PROCESS_STATE(csr5) (((csr5) & TX_PROCESS_STATE_MASK) >> 20) 237#define TX_PROCESS_MAX_STATE 7 238 239/* OPN_REG , CSR6 */ 240#define HASH_FILTERING (1UL<<0) 241#define START_RECEIVE (1UL<<1) 242#define HASH_ONLY (1UL<<2) 243#define PASSBAD (1UL<<3) 244#define INV_FILTER (1UL<<4) 245#define PROMISC_MODE (1UL<<6) 246#define PASS_MULTICAST (1UL<<7) 247#define FULL_DUPLEX (1UL<<9) 248#define LOOPBACK_OFF (0UL<<10) 249#define LOOPBACK_INTERNAL (1UL<<10) 250#define LOOPBACK_PHY_D (2UL<<10) 251#define LOOPBACK_PHY_A (3UL<<10) 252#define LOOPBACK_MODE_MASK (3UL<<10) 253#define FORCE_COLLISION (1UL<<12) 254#define START_TRANSMIT (1UL<<13) 255#define TX_THRESHOLD_LOW (0UL<<14) 256#define TX_THRESHOLD_MID (1UL<<14) 257#define TX_THRESHOLD_HI (2UL<<14) 258#define TX_THRESHOLD_MASK (3UL<<14) 259#define ONE_PKT_MODE (1UL<<16) 260#define EXT_MII_IF (1UL<<18) 261#define START_TX_IMMED (1UL<<20) 262#define STORE_AND_FORWARD (1UL<<21) 263#define TX_THRESHOLD_MODE (1UL<<22) 264#define OPN_25_MB1 (1UL<<25) 265#define NO_RX_PURGE (1UL<<29) 266#define RECEIVEALL (1UL<<30) 267 268/* INT_MASK_REG , CSR7 */ 269/* 270 * Use the values defined for the INT_STATUS_MASK bits (0..16) 271 * of CSR5. The remaining bits (17..31) are not used. 272 */ 273 274/* MISSED_FRAME_REG, CSR8 */ 275#define MISSED_FRAME_MASK 0x00000ffffUL 276#define MISSED_OVERFLOW 0x000010000UL 277#define PURGED_PACKET_MASK 0x07ffe0000UL 278#define PURGED_OVERFLOW 0x080000000UL 279 280/* Serial ROM/MII Register CSR9 */ 281#define SEL_CHIP 0x00000001UL 282#define SEL_CLK 0x00000002UL 283#define DATA_IN 0x00000004UL 284#define DATA_OUT 0x00000008UL 285#define SER_8_MB1 0x00000300UL 286#define SEL_XRS 0x00000400UL 287#define SEL_EEPROM 0x00000800UL 288#define SEL_BOOTROM 0x00001000UL 289#define WRITE_OP 0x00002000UL 290#define READ_OP 0x00004000UL 291#define SER_15_MB1 0x00008000UL 292#define READ_EEPROM (READ_OP | SEL_EEPROM) 293#define READ_EEPROM_CS (READ_OP | SEL_EEPROM | SEL_CHIP) 294 295#define MII_CLOCK 0x00010000UL 296#define MII_DATA_OUT 0x00020000UL 297#define MII_DATA_OUT_SHIFT 17 298#define MII_READ 0x00040000UL 299#define MII_TRISTATE 0x00040000UL 300#define MII_WRITE 0x00000000UL 301#define MII_DATA_IN 0x00080000UL 302#define MII_DATA_IN_SHIFT 19 303 304#define RELOAD_EEPROM 0x00100000UL 305#define LOADED_EEPROM 0x00200000UL 306 307/* GPR Timer reg, CSR11 */ 308#define GPTIMER_CONT (1UL<<16) 309 310/* PHY Status reg, CSR12 */ 311#define GPS_LINK_10 0x00000001UL 312#define GPS_LINK_100 0x00000002UL 313#define GPS_FULL_DUPLEX 0x00000004UL 314#define GPS_LINK_STATUS 0x00000008UL 315#define GPS_RX_LOCK 0x00000010UL 316#define GPS_SIGNAL_DETECT 0x00000020UL 317#define GPS_UTP_SIG 0x00000040UL 318#define GPS_PHY_RESET 0x00000080UL 319#define GPS_WRITE_ENABLE 0x00000100UL 320 321/* Sample Frame Access reg, CSR13 */ 322#define TX_FIFO_ACCESS (0x32<<3) 323#define RX_FIFO_ACCESS (0x35<<3) 324#define DIAG_RESET (0x38<<3) 325 326/* Sample Frame Data reg, CSR14, when CSR13 is set to DIAG_RESET */ 327#define DIAG_TX_FIFO_WRITE_0 0x00000001UL 328#define DIAG_TX_FIFO_READ_0 0x00000002UL 329#define DIAG_RX_FIFO_WRITE_0 0x00000004UL 330#define DIAG_RX_FIFO_READ_0 0x00000008UL 331#define DIAG_TX_FIFO_WRITE_100 0x00000020UL 332#define DIAG_RX_FIFO_WRITE_100 0x00000040UL 333 334/* CSR15 */ 335#define TX_JABBER_DISABLE 0x00000001UL 336#define UNJABBER_INTERVAL 0x00000002UL 337#define JABBER_CLOCK 0x00000004UL 338#define WD_TIMER_DISABLE 0x00000010UL 339#define WD_TIMER_RELEASE 0x00000020UL 340#define VLAN_ENABLE 0x00000040UL 341#define PAUSE_STATUS_1 0x00000080UL 342#define PAUSE_STATUS_2 0x00000200UL 343#define FLOW_CONTROL 0x00000400UL 344#define PAUSE_ENABLE_1 0x00000800UL 345#define PAUSE_ENABLE_2 0x00001000UL 346#define PAUSE_TX_FFFF 0x00002000UL 347#define PAUSE_TX_0000 0x00004000UL 348#define PAUSE_CONDITION 0x00008000UL 349#define RX_FIFO_THRES_MASK 0x003f0000UL 350#define RX_EARLY_THRES_MASK 0x01c00000UL 351 352 353/* SROM access definitions */ 354#define HIGH_ADDRESS_BIT 0x20 /* 6 bits */ 355#define HIGH_CMD_BIT 0x4 /* 3 bits */ 356#define HIGH_DATA_BIT 0x8000 /* 16 bits */ 357#define SROM_DELAY 5 /* 5 microseconds */ 358#define EEPROM_READ_CMD 6 359#define EEPROM_EN_ADDR 20 360 361/* MII access definitions */ 362#define MII_REG_ADDR_SHIFT 18 363#define MII_PHY_ADDR_SHIFT 23 364#define MII_DELAY 1 /* 1 microsecond */ 365#define MII_PREAMBLE 0xffffffffUL 366#define MII_READ_FRAME 0x60000000UL 367#define MII_WRITE_FRAME 0x50020000UL 368 369 370/* DMFE IOCTLS */ 371#define ND_BASE ('N' << 8) /* base */ 372#define ND_GET (ND_BASE + 0) /* Get a value */ 373#define ND_SET (ND_BASE + 1) /* Set a value */ 374 375#define DMFE_ND_GET ND_GET 376#define DMFE_ND_SET ND_SET 377 378#define DMFEIOC ('G' << 8) 379#define DMFE_SET_LOOP_MODE (DMFEIOC|1) 380#define DMFE_GET_LOOP_MODE (DMFEIOC|2) 381 382/* argument structure for above */ 383typedef struct { 384 int loopback; 385} loopback_t; 386 387#define DMFE_LOOPBACK_OFF 0 388#define DMFE_PHY_A_LOOPBACK_ON 1 389#define DMFE_PHY_D_LOOPBACK_ON 2 390#define DMFE_INT_LOOPBACK_ON 4 391#define DMFE_LOOPBACK_MODES 7 /* Bitwise OR of above */ 392 393#ifdef __cplusplus 394} 395#endif 396 397#endif /* _SYS_DMFE_H */ 398