1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved. 24 */ 25 26#pragma ident "%Z%%M% %I% %E% SMI" 27 28#ifndef _VSC7326_REG_H_ 29#define _VSC7326_REG_H_ 30 31/* Register definitions for Vitesse VSC7326 (Meigs II) MAC 32 * 33 * Straight off the data sheet, VMDS-10038 Rev 2.0 and 34 * PD0011-01-14-Meigs-II 2002-12-12 35 */ 36 37/* Just 'cause it's in here doesn't mean it's used. */ 38 39#define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1)) 40 41/* System and CPU comm's registers */ 42#define REG_CHIP_ID CRA(0x7,0xf,0x00) /* Chip ID */ 43#define REG_BLADE_ID CRA(0x7,0xf,0x01) /* Blade ID */ 44#define REG_SW_RESET CRA(0x7,0xf,0x02) /* Global Soft Reset */ 45#define REG_MEM_BIST CRA(0x7,0xf,0x04) /* mem */ 46#define REG_IFACE_MODE CRA(0x7,0xf,0x07) /* Interface mode */ 47#define REG_MSCH CRA(0x7,0x2,0x06) /* CRC error count */ 48#define REG_CRC_CNT CRA(0x7,0x2,0x0a) /* CRC error count */ 49#define REG_CRC_CFG CRA(0x7,0x2,0x0b) /* CRC config */ 50#define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18) /* SI Transfer Select */ 51#define REG_PLL_CLK_SPEED CRA(0x7,0xf,0x19) /* Clock Speed Selection */ 52#define REG_SYS_CLK_SELECT CRA(0x7,0xf,0x1c) /* System Clock Select */ 53#define REG_GPIO_CTRL CRA(0x7,0xf,0x1d) /* GPIO Control */ 54#define REG_GPIO_OUT CRA(0x7,0xf,0x1e) /* GPIO Out */ 55#define REG_GPIO_IN CRA(0x7,0xf,0x1f) /* GPIO In */ 56#define REG_CPU_TRANSFER_SEL CRA(0x7,0xf,0x20) /* CPU Transfer Select */ 57#define REG_LOCAL_DATA CRA(0x7,0xf,0xfe) /* Local CPU Data Register */ 58#define REG_LOCAL_STATUS CRA(0x7,0xf,0xff) /* Local CPU Status Register */ 59 60/* Aggregator registers */ 61#define REG_AGGR_SETUP CRA(0x7,0x1,0x00) /* Aggregator Setup */ 62#define REG_PMAP_TABLE CRA(0x7,0x1,0x01) /* Port map table */ 63#define REG_MPLS_BIT0 CRA(0x7,0x1,0x08) /* MPLS bit0 position */ 64#define REG_MPLS_BIT1 CRA(0x7,0x1,0x09) /* MPLS bit1 position */ 65#define REG_MPLS_BIT2 CRA(0x7,0x1,0x0a) /* MPLS bit2 position */ 66#define REG_MPLS_BIT3 CRA(0x7,0x1,0x0b) /* MPLS bit3 position */ 67#define REG_MPLS_BITMASK CRA(0x7,0x1,0x0c) /* MPLS bit mask */ 68#define REG_PRE_BIT0POS CRA(0x7,0x1,0x10) /* Preamble bit0 position */ 69#define REG_PRE_BIT1POS CRA(0x7,0x1,0x11) /* Preamble bit1 position */ 70#define REG_PRE_BIT2POS CRA(0x7,0x1,0x12) /* Preamble bit2 position */ 71#define REG_PRE_BIT3POS CRA(0x7,0x1,0x13) /* Preamble bit3 position */ 72#define REG_PRE_ERR_CNT CRA(0x7,0x1,0x14) /* Preamble parity error count */ 73 74/* BIST registers */ 75/*#define REG_RAM_BIST_CMD CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */ 76/*#define REG_RAM_BIST_RESULT CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */ 77#define REG_RAM_BIST_CMD CRA(0x7,0x1,0x00) /* RAM BIST Command Register */ 78#define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01) /* RAM BIST Read Status/Result */ 79#define BIST_PORT_SELECT 0x00 /* BIST port select */ 80#define BIST_COMMAND 0x01 /* BIST enable/disable */ 81#define BIST_STATUS 0x02 /* BIST operation status */ 82#define BIST_ERR_CNT_LSB 0x03 /* BIST error count lo 8b */ 83#define BIST_ERR_CNT_MSB 0x04 /* BIST error count hi 8b */ 84#define BIST_ERR_SEL_LSB 0x05 /* BIST error select lo 8b */ 85#define BIST_ERR_SEL_MSB 0x06 /* BIST error select hi 8b */ 86#define BIST_ERROR_STATE 0x07 /* BIST engine internal state */ 87#define BIST_ERR_ADR0 0x08 /* BIST error address lo 8b */ 88#define BIST_ERR_ADR1 0x09 /* BIST error address lomid 8b */ 89#define BIST_ERR_ADR2 0x0a /* BIST error address himid 8b */ 90#define BIST_ERR_ADR3 0x0b /* BIST error address hi 8b */ 91 92/* FIFO registers 93 * ie = 0 for ingress, 1 for egress 94 * fn = FIFO number, 0-9 95 */ 96#define REG_TEST(ie,fn) CRA(0x2,ie&1,0x00+fn) /* Mode & Test Register */ 97#define REG_TOP_BOTTOM(ie,fn) CRA(0x2,ie&1,0x10+fn) /* FIFO Buffer Top & Bottom */ 98#define REG_TAIL(ie,fn) CRA(0x2,ie&1,0x20+fn) /* FIFO Write Pointer */ 99#define REG_HEAD(ie,fn) CRA(0x2,ie&1,0x30+fn) /* FIFO Read Pointer */ 100#define REG_HIGH_LOW_WM(ie,fn) CRA(0x2,ie&1,0x40+fn) /* Flow Control Water Marks */ 101#define REG_CT_THRHLD(ie,fn) CRA(0x2,ie&1,0x50+fn) /* Cut Through Threshold */ 102#define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn) /* Drop & CRC Error Counter */ 103#define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn) /* Input Side Debug Counter */ 104#define REG_BUCKI(fn) CRA(0x2,2,0x20+fn) /* Input Side Debug Counter */ 105#define REG_BUCKE(fn) CRA(0x2,3,0x20+fn) /* Input Side Debug Counter */ 106 107/* Traffic shaper buckets 108 * ie = 0 for ingress, 1 for egress 109 * bn = bucket number 0-10 (yes, 11 buckets) 110 */ 111/* OK, this one's kinda ugly. Some hardware designers are perverse. */ 112#define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4)) 113#define REG_TRAFFIC_SHAPER_CONTROL(ie) CRA(0x2,ie&1,0x3b) 114 115#define REG_SRAM_ADR(ie) CRA(0x2,ie&1,0x0e) /* FIFO SRAM address */ 116#define REG_SRAM_WR_STRB(ie) CRA(0x2,ie&1,0x1e) /* FIFO SRAM write strobe */ 117#define REG_SRAM_RD_STRB(ie) CRA(0x2,ie&1,0x2e) /* FIFO SRAM read strobe */ 118#define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e) /* FIFO SRAM data lo 8b */ 119#define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e) /* FIFO SRAM data lomid 8b */ 120#define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e) /* FIFO SRAM data himid 8b */ 121#define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e) /* FIFO SRAM data hi 8b */ 122#define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e) /* FIFO SRAM tag */ 123/* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */ 124#define REG_CONTROL(ie) CRA(0x2,ie&1,0x0f) /* FIFO control */ 125#define REG_ING_CONTROL CRA(0x2,0x0,0x0f) /* Ingress control (alias) */ 126#define REG_EGR_CONTROL CRA(0x2,0x1,0x0f) /* Egress control (alias) */ 127#define REG_AGE_TIMER(ie) CRA(0x2,ie&1,0x1f) /* Aging timer */ 128#define REG_AGE_INC(ie) CRA(0x2,ie&1,0x2f) /* Aging increment */ 129#define DEBUG_OUT(ie) CRA(0x2,ie&1,0x3f) /* Output debug counter control */ 130#define DEBUG_CNT(ie) CRA(0x2,ie&1,0x4f) /* Output debug counter */ 131 132/* SPI4 interface */ 133#define REG_SPI4_MISC CRA(0x5,0x0,0x00) /* Misc Register */ 134#define REG_SPI4_STATUS CRA(0x5,0x0,0x01) /* CML Status */ 135#define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02) /* Ingress Status Channel Setup */ 136#define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03) /* Ingress Data Training Setup */ 137#define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04) /* Ingress Data Burst Size Setup */ 138#define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05) /* Egress Status Channel Setup */ 139#define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */ 140#define REG_SPI4_DBG_SETUP CRA(0x5,0x0,0x1A) /* Debug counters setup */ 141#define REG_SPI4_TEST CRA(0x5,0x0,0x20) /* Test Setup Register */ 142#define REG_TPGEN_UP0 CRA(0x5,0x0,0x21) /* Test Pattern generator user pattern 0 */ 143#define REG_TPGEN_UP1 CRA(0x5,0x0,0x22) /* Test Pattern generator user pattern 1 */ 144#define REG_TPCHK_UP0 CRA(0x5,0x0,0x23) /* Test Pattern checker user pattern 0 */ 145#define REG_TPCHK_UP1 CRA(0x5,0x0,0x24) /* Test Pattern checker user pattern 1 */ 146#define REG_TPSAM_P0 CRA(0x5,0x0,0x25) /* Sampled pattern 0 */ 147#define REG_TPSAM_P1 CRA(0x5,0x0,0x26) /* Sampled pattern 1 */ 148#define REG_TPERR_CNT CRA(0x5,0x0,0x27) /* Pattern checker error counter */ 149#define REG_SPI4_STICKY CRA(0x5,0x0,0x30) /* Sticky bits register */ 150#define REG_SPI4_DBG_INH CRA(0x5,0x0,0x31) /* Core egress & ingress inhibit */ 151#define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32) /* Sampled ingress status */ 152#define REG_SPI4_DBG_GRANT CRA(0x5,0x0,0x33) /* Ingress cranted credit value */ 153 154#define REG_SPI4_DESKEW CRA(0x5,0x0,0x43) /* Ingress cranted credit value */ 155 156/* 10GbE MAC Block Registers */ 157/* Note that those registers that are exactly the same for 10GbE as for 158 * tri-speed are only defined with the version that needs a port number. 159 * Pass 0xa in those cases. 160 * 161 * Also note that despite the presence of a MAC address register, this part 162 * does no ingress MAC address filtering. That register is used only for 163 * pause frame detection and generation. 164 */ 165/* 10GbE specific, and different from tri-speed */ 166#define REG_MISC_10G CRA(0x1,0xa,0x00) /* Misc 10GbE setup */ 167#define REG_PAUSE_10G CRA(0x1,0xa,0x01) /* Pause register */ 168#define REG_NORMALIZER_10G CRA(0x1,0xa,0x05) /* 10G normalizer */ 169#define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */ 170#define REG_DENORM_10G CRA(0x1,0xa,0x07) /* Denormalizer */ 171#define REG_STICKY_TX CRA(0x1,0xa,0x08) /* TX sticky bits */ 172#define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */ 173#define REG_MAX_RXLOW CRA(0x1,0xa,0x0b) /* XGMII lane 4-7 debug */ 174#define REG_MAC_TX_STICKY CRA(0x1,0xa,0x0c) /* MAC Tx state sticky debug */ 175#define REG_MAC_TX_RUNNING CRA(0x1,0xa,0x0d) /* MAC Tx state running debug */ 176#define REG_TX_ABORT_AGE CRA(0x1,0xa,0x14) /* Aged Tx frames discarded */ 177#define REG_TX_ABORT_SHORT CRA(0x1,0xa,0x15) /* Short Tx frames discarded */ 178#define REG_TX_ABORT_TAXI CRA(0x1,0xa,0x16) /* Taxi error frames discarded */ 179#define REG_TX_ABORT_UNDERRUN CRA(0x1,0xa,0x17) /* Tx Underrun abort counter */ 180#define REG_TX_DENORM_DISCARD CRA(0x1,0xa,0x18) /* Tx denormalizer discards */ 181#define REG_XAUI_STAT_A CRA(0x1,0xa,0x20) /* XAUI status A */ 182#define REG_XAUI_STAT_B CRA(0x1,0xa,0x21) /* XAUI status B */ 183#define REG_XAUI_STAT_C CRA(0x1,0xa,0x22) /* XAUI status C */ 184#define REG_XAUI_CONF_A CRA(0x1,0xa,0x23) /* XAUI configuration A */ 185#define REG_XAUI_CONF_B CRA(0x1,0xa,0x24) /* XAUI configuration B */ 186#define REG_XAUI_CODE_GRP_CNT CRA(0x1,0xa,0x25) /* XAUI code group error count */ 187#define REG_XAUI_CONF_TEST_A CRA(0x1,0xa,0x26) /* XAUI test register A */ 188#define REG_PDERRCNT CRA(0x1,0xa,0x27) /* XAUI test register B */ 189 190/* pn = port number 0-9 for tri-speed, 10 for 10GbE */ 191/* Both tri-speed and 10GbE */ 192#define REG_MAX_LEN(pn) CRA(0x1,pn,0x02) /* Max length */ 193#define REG_MAC_HIGH_ADDR(pn) CRA(0x1,pn,0x03) /* Upper 24 bits of MAC addr */ 194#define REG_MAC_LOW_ADDR(pn) CRA(0x1,pn,0x04) /* Lower 24 bits of MAC addr */ 195 196/* tri-speed only 197 * pn = port number, 0-9 198 */ 199#define REG_MODE_CFG(pn) CRA(0x1,pn,0x00) /* Mode configuration */ 200#define REG_PAUSE_CFG(pn) CRA(0x1,pn,0x01) /* Pause configuration */ 201#define REG_NORMALIZER(pn) CRA(0x1,pn,0x05) /* Normalizer */ 202#define REG_TBI_STATUS(pn) CRA(0x1,pn,0x06) /* TBI status */ 203#define REG_PCS_STATUS_DBG(pn) CRA(0x1,pn,0x07) /* PCS status debug */ 204#define REG_PCS_CTRL(pn) CRA(0x1,pn,0x08) /* PCS control */ 205#define REG_TBI_CONFIG(pn) CRA(0x1,pn,0x09) /* TBI configuration */ 206#define REG_STICK_BIT(pn) CRA(0x1,pn,0x0a) /* Sticky bits */ 207#define REG_DEV_SETUP(pn) CRA(0x1,pn,0x0b) /* MAC clock/reset setup */ 208#define REG_DROP_CNT(pn) CRA(0x1,pn,0x0c) /* Drop counter */ 209#define REG_PORT_POS(pn) CRA(0x1,pn,0x0d) /* Preamble port position */ 210#define REG_PORT_FAIL(pn) CRA(0x1,pn,0x0e) /* Preamble port position */ 211#define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f) /* SerDes configuration */ 212#define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10) /* SerDes test */ 213#define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11) /* SerDes status */ 214#define REG_SERDES_COM_CNT(pn) CRA(0x1,pn,0x12) /* SerDes comma counter */ 215#define REG_DENORM(pn) CRA(0x1,pn,0x15) /* Frame denormalization */ 216#define REG_DBG(pn) CRA(0x1,pn,0x16) /* Device 1G debug */ 217#define REG_TX_IFG(pn) CRA(0x1,pn,0x18) /* Tx IFG config */ 218#define REG_HDX(pn) CRA(0x1,pn,0x19) /* Half-duplex config */ 219 220/* Statistics */ 221/* pn = port number, 0-a, a = 10GbE */ 222#define REG_RX_IN_BYTES(pn) CRA(0x4,pn,0x00) /* # Rx in octets */ 223#define REG_RX_SYMBOL_CARRIER(pn) CRA(0x4,pn,0x01) /* Frames w/ symbol errors */ 224#define REG_RX_PAUSE(pn) CRA(0x4,pn,0x02) /* # pause frames received */ 225#define REG_RX_UNSUP_OPCODE(pn) CRA(0x4,pn,0x03) /* # control frames with unsupported opcode */ 226#define REG_RX_OK_BYTES(pn) CRA(0x4,pn,0x04) /* # octets in good frames */ 227#define REG_RX_BAD_BYTES(pn) CRA(0x4,pn,0x05) /* # octets in bad frames */ 228#define REG_RX_UNICAST(pn) CRA(0x4,pn,0x06) /* # good unicast frames */ 229#define REG_RX_MULTICAST(pn) CRA(0x4,pn,0x07) /* # good multicast frames */ 230#define REG_RX_BROADCAST(pn) CRA(0x4,pn,0x08) /* # good broadcast frames */ 231#define REG_CRC(pn) CRA(0x4,pn,0x09) /* # frames w/ bad CRC only */ 232#define REG_RX_ALIGNMENT(pn) CRA(0x4,pn,0x0a) /* # frames w/ alignment err */ 233#define REG_RX_UNDERSIZE(pn) CRA(0x4,pn,0x0b) /* # frames undersize */ 234#define REG_RX_FRAGMENTS(pn) CRA(0x4,pn,0x0c) /* # frames undersize w/ crc err */ 235#define REG_RX_IN_RANGE_LENGTH_ERROR(pn) CRA(0x4,pn,0x0d) /* # frames with length error */ 236#define REG_RX_OUT_OF_RANGE_ERROR(pn) CRA(0x4,pn,0x0e) /* # frames with illegal length field */ 237#define REG_RX_OVERSIZE(pn) CRA(0x4,pn,0x0f) /* # frames oversize */ 238#define REG_RX_JABBERS(pn) CRA(0x4,pn,0x10) /* # frames oversize w/ crc err */ 239#define REG_RX_SIZE_64(pn) CRA(0x4,pn,0x11) /* # frames 64 octets long */ 240#define REG_RX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x12) /* # frames 65-127 octets */ 241#define REG_RX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x13) /* # frames 128-255 */ 242#define REG_RX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x14) /* # frames 256-511 */ 243#define REG_RX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x15) /* # frames 512-1023 */ 244#define REG_RX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x16) /* # frames 1024-1518 */ 245#define REG_RX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x17) /* # frames 1519-max */ 246 247#define REG_TX_OUT_BYTES(pn) CRA(0x4,pn,0x18) /* # octets tx */ 248#define REG_TX_PAUSE(pn) CRA(0x4,pn,0x19) /* # pause frames sent */ 249#define REG_TX_OK_BYTES(pn) CRA(0x4,pn,0x1a) /* # octets tx OK */ 250#define REG_TX_UNICAST(pn) CRA(0x4,pn,0x1b) /* # frames unicast */ 251#define REG_TX_MULTICAST(pn) CRA(0x4,pn,0x1c) /* # frames multicast */ 252#define REG_TX_BROADCAST(pn) CRA(0x4,pn,0x1d) /* # frames broadcast */ 253#define REG_TX_MULTIPLE_COLL(pn) CRA(0x4,pn,0x1e) /* # frames tx after multiple collisions */ 254#define REG_TX_LATE_COLL(pn) CRA(0x4,pn,0x1f) /* # late collisions detected */ 255#define REG_TX_XCOLL(pn) CRA(0x4,pn,0x20) /* # frames lost, excessive collisions */ 256#define REG_TX_DEFER(pn) CRA(0x4,pn,0x21) /* # frames deferred on first tx attempt */ 257#define REG_TX_XDEFER(pn) CRA(0x4,pn,0x22) /* # frames excessively deferred */ 258#define REG_TX_CSENSE(pn) CRA(0x4,pn,0x23) /* carrier sense errors at frame end */ 259#define REG_TX_SIZE_64(pn) CRA(0x4,pn,0x24) /* # frames 64 octets long */ 260#define REG_TX_SIZE_65_TO_127(pn) CRA(0x4,pn,0x25) /* # frames 65-127 octets */ 261#define REG_TX_SIZE_128_TO_255(pn) CRA(0x4,pn,0x26) /* # frames 128-255 */ 262#define REG_TX_SIZE_256_TO_511(pn) CRA(0x4,pn,0x27) /* # frames 256-511 */ 263#define REG_TX_SIZE_512_TO_1023(pn) CRA(0x4,pn,0x28) /* # frames 512-1023 */ 264#define REG_TX_SIZE_1024_TO_1518(pn) CRA(0x4,pn,0x29) /* # frames 1024-1518 */ 265#define REG_TX_SIZE_1519_TO_MAX(pn) CRA(0x4,pn,0x2a) /* # frames 1519-max */ 266#define REG_TX_SINGLE_COLL(pn) CRA(0x4,pn,0x2b) /* # frames tx after single collision */ 267#define REG_TX_BACKOFF2(pn) CRA(0x4,pn,0x2c) /* # frames tx ok after 2 backoffs/collisions */ 268#define REG_TX_BACKOFF3(pn) CRA(0x4,pn,0x2d) /* after 3 backoffs/collisions */ 269#define REG_TX_BACKOFF4(pn) CRA(0x4,pn,0x2e) /* after 4 */ 270#define REG_TX_BACKOFF5(pn) CRA(0x4,pn,0x2f) /* after 5 */ 271#define REG_TX_BACKOFF6(pn) CRA(0x4,pn,0x30) /* after 6 */ 272#define REG_TX_BACKOFF7(pn) CRA(0x4,pn,0x31) /* after 7 */ 273#define REG_TX_BACKOFF8(pn) CRA(0x4,pn,0x32) /* after 8 */ 274#define REG_TX_BACKOFF9(pn) CRA(0x4,pn,0x33) /* after 9 */ 275#define REG_TX_BACKOFF10(pn) CRA(0x4,pn,0x34) /* after 10 */ 276#define REG_TX_BACKOFF11(pn) CRA(0x4,pn,0x35) /* after 11 */ 277#define REG_TX_BACKOFF12(pn) CRA(0x4,pn,0x36) /* after 12 */ 278#define REG_TX_BACKOFF13(pn) CRA(0x4,pn,0x37) /* after 13 */ 279#define REG_TX_BACKOFF14(pn) CRA(0x4,pn,0x38) /* after 14 */ 280#define REG_TX_BACKOFF15(pn) CRA(0x4,pn,0x39) /* after 15 */ 281#define REG_TX_UNDERRUN(pn) CRA(0x4,pn,0x3a) /* # frames dropped from underrun */ 282#define REG_RX_XGMII_PROT_ERR CRA(0x4,0xa,0x3b) /* # protocol errors detected on XGMII interface */ 283#define REG_RX_IPG_SHRINK(pn) CRA(0x4,pn,0x3c) /* # of IPG shrinks detected */ 284 285#define REG_STAT_STICKY1G(pn) CRA(0x4,pn,0x3e) /* tri-speed sticky bits */ 286#define REG_STAT_STICKY10G CRA(0x4,0xa,0x3e) /* 10GbE sticky bits */ 287#define REG_STAT_INIT(pn) CRA(0x4,pn,0x3f) /* Clear all statistics */ 288 289/* MII-Management Block registers */ 290/* These are for MII-M interface 0, which is the bidirectional LVTTL one. If 291 * we hooked up to the one with separate directions, the middle 0x0 needs to 292 * change to 0x1. And the current errata states that MII-M 1 doesn't work. 293 */ 294 295#define REG_MIIM_STATUS CRA(0x3,0x0,0x00) /* MII-M Status */ 296#define REG_MIIM_CMD CRA(0x3,0x0,0x01) /* MII-M Command */ 297#define REG_MIIM_DATA CRA(0x3,0x0,0x02) /* MII-M Data */ 298#define REG_MIIM_PRESCALE CRA(0x3,0x0,0x03) /* MII-M MDC Prescale */ 299 300#define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd) 301#define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d) 302#define REG_ING_FFILT_VAL0 CRA(0x2, 0, 0x2d) 303#define REG_ING_FFILT_VAL1 CRA(0x2, 0, 0x3d) 304#define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d) 305#define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d) 306#define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d) 307#define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d) 308 309 310/* Whew. */ 311 312#endif 313