audiots.c revision 9484:fbd5ddc28e96
1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21/* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27/* 28 * audiots Audio Driver 29 * 30 * This Audio Driver controls the T2 audio core in the ALI M1553 31 * southbridge chip. This chip supports multiple play streams, but just 32 * a single record stream. It also supports wave table synthesis and 33 * hardware MIDI and joystick ports. Unfortunately the MIDI ports are 34 * not available because their pins have been re-assigned to expose 35 * interrupts. We also aren't going to do anything with the joystick 36 * ports. The audio core controls an AC-97 V2.1 Codec. 37 * 38 * The DMA engine uses a single buffer which is large enough to hold 39 * two interrupts worth of data. When it gets to the mid point an 40 * interrupt is generated and data is either sent (for record) or 41 * requested and put in that half of the buffer (for play). When the 42 * second half is played we do the same, but the audio core loops the 43 * pointer back to the beginning. 44 * 45 * The audio core has a bug in silicon that doesn't let it read the AC-97 46 * Codec's register. T2 has provided an algorithm that attempts to read the 47 * the Codec several times. This is probably heuristic and thus isn't 48 * absolutely guaranteed to work. However we do have to place a limit on 49 * the looping, otherwise when we read a valid 0x00 we would never exit 50 * the loop. Unfortunately there is also a problem with writing the AC-97 51 * Codec's registers as well. Thus we read it back to verify the write. 52 * 53 * The AC'97 common code provides shadow state for AC'97 registers for us, 54 * so we only need to read those registers during early startup (primarily 55 * to determine codec id and capabilities.) 56 * 57 * We don't save any of the audio controller registers during normal 58 * operation. When we need to save register state we only have to save 59 * the aram and eram. The rest of the controller state is never modified 60 * from the initial programming. Thus restoring the controller state 61 * can be done from audiots_chip_init() as well. 62 * 63 * 64 * WARNING: The SME birdsnest platform uses a PCI bridge chip between the 65 * CPU and the southbridge containing the audio core. There is 66 * a bug in silicon that causes a bogus parity error. With the mixer 67 * reimplementation project, Bug 4374774, the audio driver is always 68 * set to the best precision and number of channels. Thus when turning 69 * the mixer on and off the only thing that changes is the sample rate. 70 * This change in programming doesn't trigger the silicon error. 71 * Thus the supported channels must always be 2 and the precision 72 * must always be 16-bits. This will keep any future change in the 73 * mixer from exposing this bug. 74 * 75 * Due to a hardware bug, system power management is not supported by this 76 * driver. 77 * 78 * CAUTION: If audio controller state is changed outside of aram 79 * and eram then that information must be saved and restored 80 * during power management shutdown and bringup. 81 * 82 * NOTE: The AC-97 Codec's reset pin is set to PCI reset, so we 83 * can't power down the Codec all the way. 84 * 85 * NOTE: This driver depends on the drv/audio and misc/ac97 86 * modules being loaded first. 87 * 88 * NOTE: Don't OR the ap_stop register to stop a play or record. This 89 * will just stop all active channels because a read of ap_stop 90 * returns ap_start. Just set the ap_stop register with the 91 * channels you want to stop. The same goes for ap_start. 92 * 93 * NOTE: There is a hardware problem with P2 rev motherboards. After 94 * prolonged use, reading the AC97 register will always return 95 * busy. The AC97 register is now useless. Consequently, we are no 96 * longer able to program the Codec. This work around disables 97 * audio when this state is detected. It's not great, but its 98 * better than having audio blasting out at 100% all the time. 99 * 100 * NOTE: Power Management testing has also exposed this AC97 timeout 101 * problem. Management has decided this is too risky for customers 102 * and hence they want power management support removed from the 103 * audio subsystem. All PM support is now removed. 104 */ 105 106#include <sys/modctl.h> 107#include <sys/kmem.h> 108#include <sys/pci.h> 109#include <sys/ddi.h> 110#include <sys/sunddi.h> 111#include <sys/debug.h> 112#include <sys/note.h> 113#include <sys/audio/audio_driver.h> 114#include <sys/audio/ac97.h> 115#include "audiots.h" 116 117/* 118 * Module linkage routines for the kernel 119 */ 120static int audiots_attach(dev_info_t *, ddi_attach_cmd_t); 121static int audiots_detach(dev_info_t *, ddi_detach_cmd_t); 122static int audiots_quiesce(dev_info_t *); 123 124/* 125 * Entry point routine prototypes 126 */ 127static int audiots_open(void *, int, unsigned *, unsigned *, caddr_t *); 128static void audiots_close(void *); 129static int audiots_start(void *); 130static void audiots_stop(void *); 131static int audiots_format(void *); 132static int audiots_channels(void *); 133static int audiots_rate(void *); 134static void audiots_chinfo(void *, int, unsigned *, unsigned *); 135static uint64_t audiots_count(void *); 136static void audiots_sync(void *, unsigned); 137static size_t audiots_qlen(void *); 138 139static audio_engine_ops_t audiots_engine_ops = { 140 AUDIO_ENGINE_VERSION, 141 audiots_open, 142 audiots_close, 143 audiots_start, 144 audiots_stop, 145 audiots_count, 146 audiots_format, 147 audiots_channels, 148 audiots_rate, 149 audiots_sync, 150 audiots_qlen, 151 audiots_chinfo 152}; 153 154/* 155 * Local Routine Prototypes 156 */ 157static void audiots_power_up(audiots_state_t *); 158static void audiots_chip_init(audiots_state_t *); 159static uint16_t audiots_get_ac97(void *, uint8_t); 160static void audiots_set_ac97(void *, uint8_t, uint16_t); 161static int audiots_init_state(audiots_state_t *, dev_info_t *); 162static uint_t audiots_intr(caddr_t); 163static int audiots_map_regs(dev_info_t *, audiots_state_t *); 164static void audiots_update_port(audiots_port_t *); 165static void audiots_start_port(audiots_port_t *); 166static void audiots_stop_port(audiots_port_t *); 167static uint16_t audiots_read_ac97(audiots_state_t *, int); 168static void audiots_stop_everything(audiots_state_t *); 169static void audiots_destroy(audiots_state_t *); 170static int audiots_alloc_port(audiots_state_t *, int); 171static void audiots_reset_port(audiots_port_t *); 172 173/* 174 * Global variables, but viewable only by this file. 175 */ 176 177/* anchor for soft state structures */ 178static void *audiots_statep; 179 180/* driver name, so we don't have to call ddi_driver_name() or hard code strs */ 181static char *audiots_name = TS_NAME; 182 183/* 184 * DDI Structures 185 */ 186 187/* Device operations structure */ 188static struct dev_ops audiots_dev_ops = { 189 DEVO_REV, /* devo_rev */ 190 0, /* devo_refcnt */ 191 NULL, /* devo_getinfo */ 192 nulldev, /* devo_identify - obsolete */ 193 nulldev, /* devo_probe */ 194 audiots_attach, /* devo_attach */ 195 audiots_detach, /* devo_detach */ 196 nodev, /* devo_reset */ 197 NULL, /* devo_cb_ops */ 198 NULL, /* devo_bus_ops */ 199 NULL, /* devo_power */ 200 audiots_quiesce, /* devo_quiesce */ 201}; 202 203/* Linkage structure for loadable drivers */ 204static struct modldrv audiots_modldrv = { 205 &mod_driverops, /* drv_modops */ 206 TS_MOD_NAME, /* drv_linkinfo */ 207 &audiots_dev_ops /* drv_dev_ops */ 208}; 209 210/* Module linkage structure */ 211static struct modlinkage audiots_modlinkage = { 212 MODREV_1, /* ml_rev */ 213 (void *)&audiots_modldrv, /* ml_linkage */ 214 NULL /* NULL terminates the list */ 215}; 216 217 218/* 219 * NOTE: Grover OBP v4.0.166 and rev G of the ALI Southbridge chip force the 220 * audiots driver to use the upper 2 GB DMA address range. However to maintain 221 * backwards compatibility with older systems/OBP, we're going to try the full 222 * 4 GB DMA range. 223 * 224 * Eventually, this will be set back to using the proper high 2 GB DMA range. 225 */ 226 227/* Device attribute structure - full 4 gig address range */ 228static ddi_dma_attr_t audiots_attr = { 229 DMA_ATTR_VERSION, /* version */ 230 0x0000000000000000LL, /* dlim_addr_lo */ 231 0x00000000ffffffffLL, /* dlim_addr_hi */ 232 0x0000000000003fffLL, /* DMA counter register - 16 bits */ 233 0x0000000000000008LL, /* DMA address alignment, 64-bit */ 234 0x0000007f, /* 1 through 64 byte burst sizes */ 235 0x00000001, /* min effective DMA size */ 236 0x0000000000003fffLL, /* maximum transfer size, 16k */ 237 0x000000000000ffffLL, /* segment boundary, 64k */ 238 0x00000001, /* s/g list length, no s/g */ 239 0x00000001, /* granularity of device, don't care */ 240 0 /* DMA flags */ 241}; 242 243static ddi_device_acc_attr_t ts_acc_attr = { 244 DDI_DEVICE_ATTR_V0, 245 DDI_NEVERSWAP_ACC, 246 DDI_STRICTORDER_ACC 247}; 248 249static ddi_device_acc_attr_t ts_regs_attr = { 250 DDI_DEVICE_ATTR_V0, 251 DDI_STRUCTURE_LE_ACC, 252 DDI_STRICTORDER_ACC 253}; 254 255/* 256 * _init() 257 * 258 * Description: 259 * Driver initialization, called when driver is first loaded. 260 * This is how access is initially given to all the static structures. 261 * 262 * Arguments: 263 * None 264 * 265 * Returns: 266 * ddi_soft_state_init() status, see ddi_soft_state_init(9f), or 267 * mod_install() status, see mod_install(9f) 268 */ 269int 270_init(void) 271{ 272 int error; 273 274 audio_init_ops(&audiots_dev_ops, TS_NAME); 275 276 /* initialize the soft state */ 277 if ((error = ddi_soft_state_init(&audiots_statep, 278 sizeof (audiots_state_t), 1)) != 0) { 279 audio_fini_ops(&audiots_dev_ops); 280 return (error); 281 } 282 283 if ((error = mod_install(&audiots_modlinkage)) != 0) { 284 audio_fini_ops(&audiots_dev_ops); 285 ddi_soft_state_fini(&audiots_statep); 286 } 287 288 return (error); 289} 290 291/* 292 * _fini() 293 * 294 * Description: 295 * Module de-initialization, called when the driver is to be unloaded. 296 * 297 * Arguments: 298 * None 299 * 300 * Returns: 301 * mod_remove() status, see mod_remove(9f) 302 */ 303int 304_fini(void) 305{ 306 int error; 307 308 if ((error = mod_remove(&audiots_modlinkage)) != 0) { 309 return (error); 310 } 311 312 /* free the soft state internal structures */ 313 ddi_soft_state_fini(&audiots_statep); 314 315 /* clean up ops */ 316 audio_fini_ops(&audiots_dev_ops); 317 318 return (0); 319} 320 321/* 322 * _info() 323 * 324 * Description: 325 * Module information, returns infomation about the driver. 326 * 327 * Arguments: 328 * modinfo *modinfop Pointer to the opaque modinfo structure 329 * 330 * Returns: 331 * mod_info() status, see mod_info(9f) 332 */ 333int 334_info(struct modinfo *modinfop) 335{ 336 int error; 337 338 error = mod_info(&audiots_modlinkage, modinfop); 339 340 return (error); 341} 342 343 344/* 345 * audiots_attach() 346 * 347 * Description: 348 * Attach an instance of the audiots driver. This routine does the 349 * device dependent attach tasks. 350 * 351 * Arguments: 352 * dev_info_t *dip Pointer to the device's dev_info struct 353 * ddi_attach_cmd_t cmd Attach command 354 * 355 * Returns: 356 * DDI_SUCCESS The driver was initialized properly 357 * DDI_FAILURE The driver couldn't be initialized properly 358 */ 359static int 360audiots_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 361{ 362 audiots_state_t *state; 363 int instance; 364 365 instance = ddi_get_instance(dip); 366 367 switch (cmd) { 368 case DDI_ATTACH: 369 break; 370 case DDI_RESUME: 371 372 /* we've already allocated the state structure so get ptr */ 373 if ((state = ddi_get_soft_state(audiots_statep, instance)) == 374 NULL) { 375 /* this will probably panic */ 376 cmn_err(CE_WARN, 377 "!%s%d: RESUME get soft state failed", 378 audiots_name, instance); 379 return (DDI_FAILURE); 380 } 381 382 ASSERT(dip == state->ts_dip); 383 384 /* suspend/resume resets the chip, so we have no more faults */ 385 if (state->ts_flags & TS_AUDIO_READ_FAILED) { 386 ddi_dev_report_fault(state->ts_dip, 387 DDI_SERVICE_RESTORED, 388 DDI_DEVICE_FAULT, 389 "check port, gain, balance, and mute settings"); 390 /* and clear the fault state flags */ 391 state->ts_flags &= 392 ~(TS_AUDIO_READ_FAILED|TS_READ_FAILURE_PRINTED); 393 } 394 395 audiots_power_up(state); 396 audiots_chip_init(state); 397 ac97_resume(state->ts_ac97); 398 399 mutex_enter(&state->ts_lock); 400 /* 401 * Initialize/reset ports. Done under the lock, to 402 * avoid race with interrupt service routine. 403 */ 404 state->ts_suspended = B_FALSE; 405 for (int i = 0; i < TS_NUM_PORTS; i++) { 406 audiots_port_t *port = state->ts_ports[i]; 407 if (port != NULL) { 408 /* relocate any streams properly */ 409 if (port->tp_engine) 410 audio_engine_reset(port->tp_engine); 411 412 /* do a hardware reset on the port */ 413 audiots_reset_port(port); 414 if (port->tp_started) { 415 audiots_start_port(port); 416 } else { 417 audiots_stop_port(port); 418 } 419 } 420 } 421 mutex_exit(&state->ts_lock); 422 423 return (DDI_SUCCESS); 424 425 default: 426 cmn_err(CE_WARN, "!%s%d: attach() unknown command: 0x%x", 427 audiots_name, instance, cmd); 428 return (DDI_FAILURE); 429 } 430 431 /* before we do anything make sure that we haven't had a h/w failure */ 432 if (ddi_get_devstate(dip) == DDI_DEVSTATE_DOWN) { 433 cmn_err(CE_WARN, "%s%d: The audio hardware has " 434 "been disabled.", audiots_name, instance); 435 cmn_err(CE_CONT, "Please reboot to restore audio."); 436 return (DDI_FAILURE); 437 } 438 439 /* we don't support high level interrupts in this driver */ 440 if (ddi_intr_hilevel(dip, 0) != 0) { 441 cmn_err(CE_WARN, "!%s%d: unsupported high level interrupt", 442 audiots_name, instance); 443 return (DDI_FAILURE); 444 } 445 446 /* allocate the state structure */ 447 if (ddi_soft_state_zalloc(audiots_statep, instance) == DDI_FAILURE) { 448 cmn_err(CE_WARN, "!%s%d: soft state allocate failed", 449 audiots_name, instance); 450 return (DDI_FAILURE); 451 } 452 453 /* 454 * WARNING: From here on all errors require that we free memory, 455 * including the state structure. 456 */ 457 458 /* get the state structure - cannot fail */ 459 state = ddi_get_soft_state(audiots_statep, instance); 460 ASSERT(state != NULL); 461 462 if ((state->ts_adev = audio_dev_alloc(dip, 0)) == NULL) { 463 cmn_err(CE_WARN, "unable to allocate audio dev"); 464 goto error; 465 } 466 467 /* map in the registers, allocate DMA buffers, etc. */ 468 if (audiots_map_regs(dip, state) == DDI_FAILURE) { 469 audio_dev_warn(state->ts_adev, "unable to map registers"); 470 goto error; 471 } 472 473 /* initialize the audio state structures */ 474 if (audiots_init_state(state, dip) == DDI_FAILURE) { 475 audio_dev_warn(state->ts_adev, "init state structure failed"); 476 goto error; 477 } 478 479 /* power up */ 480 audiots_power_up(state); 481 482 /* initialize the audio controller */ 483 audiots_chip_init(state); 484 485 /* initialize the AC-97 Codec */ 486 ac97_init(state->ts_ac97, state->ts_adev); 487 488 /* put the engine interrupts into a known state -- all off */ 489 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten, 490 TS_ALL_DMA_OFF); 491 492 /* call the framework attach routine */ 493 if (audio_dev_register(state->ts_adev) != DDI_SUCCESS) { 494 audio_dev_warn(state->ts_adev, "unable to register audio"); 495 goto error; 496 } 497 498 /* set up kernel statistics */ 499 state->ts_ksp = kstat_create(TS_NAME, instance, TS_NAME, 500 "controller", KSTAT_TYPE_INTR, 1, KSTAT_FLAG_PERSISTENT); 501 if (state->ts_ksp != NULL) { 502 kstat_install(state->ts_ksp); 503 } 504 505 /* set up the interrupt handler */ 506 if (ddi_add_intr(dip, 0, NULL, NULL, audiots_intr, 507 (caddr_t)state) != DDI_SUCCESS) { 508 audio_dev_warn(state->ts_adev, 509 "failed to register interrupt handler"); 510 goto error; 511 } 512 state->ts_flags |= TS_INTR_INSTALLED; 513 514 /* everything worked out, so report the device */ 515 ddi_report_dev(dip); 516 517 return (DDI_SUCCESS); 518 519error: 520 audiots_destroy(state); 521 return (DDI_FAILURE); 522} 523 524/* 525 * audiots_detach() 526 * 527 * Description: 528 * Detach an instance of the audiots driver. 529 * 530 * Arguments: 531 * dev_info_t *dip Pointer to the device's dev_info struct 532 * ddi_detach_cmd_t cmd Detach command 533 * 534 * Returns: 535 * DDI_SUCCESS The driver was detached 536 * DDI_FAILURE The driver couldn't be detached 537 */ 538static int 539audiots_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 540{ 541 audiots_state_t *state; 542 int instance; 543 544 instance = ddi_get_instance(dip); 545 546 /* get the state structure */ 547 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) { 548 cmn_err(CE_WARN, "!%s%d: detach get soft state failed", 549 audiots_name, instance); 550 return (DDI_FAILURE); 551 } 552 553 switch (cmd) { 554 case DDI_DETACH: 555 break; 556 case DDI_SUSPEND: 557 558 ac97_suspend(state->ts_ac97); 559 560 mutex_enter(&state->ts_lock); 561 562 state->ts_suspended = B_TRUE; /* stop new ops */ 563 564 /* we may already be powered down, so only save state if up */ 565 566 /* stop playing and recording */ 567 (void) audiots_stop_everything(state); 568 569 mutex_exit(&state->ts_lock); 570 571 return (DDI_SUCCESS); 572 573 default: 574 return (DDI_FAILURE); 575 } 576 577 /* attempt to unregister from the framework first */ 578 if (audio_dev_unregister(state->ts_adev) != DDI_SUCCESS) { 579 return (DDI_FAILURE); 580 } 581 582 audiots_destroy(state); 583 584 return (DDI_SUCCESS); 585 586} 587 588/* 589 * audiots_quiesce() 590 * 591 * Description: 592 * Quiesce an instance of the audiots driver. Stops all DMA and 593 * interrupts. 594 * 595 * Arguments: 596 * dev_info_t *dip Pointer to the device's dev_info struct 597 * 598 * Returns: 599 * DDI_SUCCESS The driver was quiesced 600 * DDI_SUCCESS The driver was NOT quiesced 601 */ 602static int 603audiots_quiesce(dev_info_t *dip) 604{ 605 audiots_state_t *state; 606 int instance; 607 608 instance = ddi_get_instance(dip); 609 610 /* get the state structure */ 611 if ((state = ddi_get_soft_state(audiots_statep, instance)) == NULL) { 612 return (DDI_FAILURE); 613 } 614 615 audiots_stop_everything(state); 616 617 return (DDI_SUCCESS); 618} 619 620/* 621 * audiots_power_up() 622 * 623 * Description 624 * Ensure that the device is running in PCI power state D0. 625 */ 626static void 627audiots_power_up(audiots_state_t *state) 628{ 629 ddi_acc_handle_t pcih = state->ts_pcih; 630 uint8_t ptr; 631 uint16_t pmcsr; 632 633 if ((pci_config_get16(pcih, PCI_CONF_STAT) & PCI_STAT_CAP) == 0) { 634 /* does not implement PCI capabilities -- no PM */ 635 return; 636 } 637 638 ptr = pci_config_get8(pcih, PCI_CONF_CAP_PTR); 639 for (;;) { 640 if (ptr == PCI_CAP_NEXT_PTR_NULL) { 641 /* PM capability not found */ 642 return; 643 } 644 if (pci_config_get8(pcih, ptr + PCI_CAP_ID) == PCI_CAP_ID_PM) { 645 /* found it */ 646 break; 647 } 648 ptr = pci_config_get8(pcih, ptr + PCI_CAP_NEXT_PTR); 649 } 650 651 /* if we got here, then got valid PMCSR pointer */ 652 ptr += PCI_PMCSR; 653 654 /* check to see if we are already in state D0 */ 655 pmcsr = pci_config_get16(pcih, ptr); 656 if ((pmcsr & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 657 658 /* D3hot (or any other state) -> D0 */ 659 pmcsr &= ~PCI_PMCSR_STATE_MASK; 660 pmcsr |= PCI_PMCSR_D0; 661 pci_config_put16(pcih, ptr, pmcsr); 662 } 663 664 /* 665 * Wait for it to power up - PCI spec says 10 ms is enough. 666 * We double it. Note that no locks are held when this routine 667 * is called, so we can sleep (we are in attach context only). 668 * 669 * We do this delay even if already powerd up, just to make 670 * sure we aren't seeing something that *just* transitioned 671 * into D0 state. 672 */ 673 delay(drv_usectohz(TS_20MS)); 674 675 /* clear PME# flag */ 676 pmcsr = pci_config_get16(pcih, ptr); 677 pci_config_put16(pcih, ptr, pmcsr | PCI_PMCSR_PME_STAT); 678} 679 680/* 681 * audiots_chip_init() 682 * 683 * Description: 684 * Initialize the audio core. 685 * 686 * Arguments: 687 * audiots_state_t *state The device's state structure 688 * 689 * Returns: 690 * void 691 */ 692static void 693audiots_chip_init(audiots_state_t *state) 694{ 695 ddi_acc_handle_t handle = state->ts_acch; 696 audiots_regs_t *regs = state->ts_regs; 697 int str; 698 699 /* start with all interrupts & dma channels disabled */ 700 ddi_put32(handle, ®s->aud_regs.ap_stop, TS_ALL_DMA_ENGINES); 701 ddi_put32(handle, ®s->aud_regs.ap_ainten, TS_ALL_DMA_OFF); 702 703 /* set global music and wave volume to 0dB */ 704 ddi_put32(handle, ®s->aud_regs.ap_volume, 0x0); 705 706 /* enable end interrupts for all channels. */ 707 ddi_put32(handle, ®s->aud_regs.ap_cir_gc, AP_CIR_GC_ENDLP_IE); 708 709 /* for each stream, set gain and vol settings */ 710 for (str = 0; str < TS_MAX_HW_CHANNELS; str++) { 711 /* 712 * Set volume to all off, 1st left and then right. 713 * These are never changed, so we don't have to save them. 714 */ 715 ddi_put16(handle, 716 ®s->aud_ram[str].eram.eram_gvsel_pan_vol, 717 (ERAM_WAVE_VOL|ERAM_PAN_LEFT|ERAM_PAN_0dB| 718 ERAM_VOL_MAX_ATTEN)); 719 ddi_put16(handle, 720 ®s->aud_ram[str].eram.eram_gvsel_pan_vol, 721 (ERAM_WAVE_VOL|ERAM_PAN_RIGHT|ERAM_PAN_0dB| 722 ERAM_VOL_MAX_ATTEN)); 723 724 /* 725 * The envelope engine *MUST* remain in still mode (off). 726 * Otherwise bad things like gain randomly disappearing might 727 * happen. See bug #4332773. 728 */ 729 730 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf1, 731 ERAM_EBUF_STILL); 732 ddi_put32(handle, ®s->aud_ram[str].eram.eram_ebuf2, 733 ERAM_EBUF_STILL); 734 735 /* program the initial eram and aram rate */ 736 ddi_put16(handle, ®s->aud_ram[str].aram.aram_delta, 737 1 << TS_SRC_SHIFT); 738 ddi_put16(handle, ®s->aud_ram[str].eram.eram_ctrl_ec, 739 ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | 740 ERAM_SIGNED_PCM); 741 } 742 743 /* program channel 31 for record */ 744 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_global_control, 745 (AP_CLOGAL_CTRL_E_PCMIN_CH31|AP_CLOGAL_CTRL_PCM_OUT_AC97| 746 AP_CLOGAL_CTRL_MMC_FROM_MIXER|AP_CLOGAL_CTRL_PCM_OUT_TO_AC97)); 747 748 /* do a warm reset, which powers up the Codec */ 749 OR_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl, 750 AP_SCTRL_WRST_CODEC); 751 drv_usecwait(2); 752 AND_SET_WORD(handle, &state->ts_regs->aud_regs.ap_sctrl, 753 ~AP_SCTRL_WRST_CODEC); 754 755 /* do a warm reset via the Codec, yes, I'm being paranoid! */ 756 audiots_set_ac97(state, AC97_RESET_REGISTER, 0); 757 758 /* Make sure the Codec is powered up. */ 759 int i = TS_WAIT_CNT; 760 while ((audiots_get_ac97(state, AC97_POWERDOWN_CTRL_STAT_REGISTER) & 761 PCSR_POWERD_UP) != PCSR_POWERD_UP && i--) { 762 drv_usecwait(1); 763 } 764 765} 766 767/* 768 * audiots_get_ac97() 769 * 770 * Description: 771 * Get the value in the specified AC-97 Codec register. There is a 772 * bug in silicon which forces us to do multiple reads of the Codec's 773 * register. This algorithm was provided by T2 and is heuristic in 774 * nature. Unfortunately we have no guarantees that the real answer 775 * isn't 0x0000, which is what we get when a read fails. So we loop 776 * TS_LOOP_CNT times before we give up. We just have to hope this is 777 * sufficient to give us the correct value. 778 * 779 * Arguments: 780 * audiots_state_t *state The device's state structure 781 * int reg AC-97 register number 782 * 783 * Returns: 784 * unsigned short The value in the specified register 785 */ 786static uint16_t 787audiots_get_ac97(void *arg, uint8_t reg) 788{ 789 audiots_state_t *state = arg; 790 ddi_acc_handle_t handle = state->ts_acch; 791 uint16_t *data; 792 int count; 793 int delay; 794 uint16_t first; 795 uint16_t next; 796 797 if (state->ts_revid == AC_REV_ID1) { 798 data = &state->ts_regs->aud_regs.ap_acrd_35D_data; 799 } else { 800 data = &state->ts_regs->aud_regs.ap_acrdwr_data; 801 } 802 803 /* make sure the register is good */ 804 reg &= AP_ACRD_INDEX_MASK; 805 for (count = TS_LOOP_CNT; count--; ) { 806 if ((first = audiots_read_ac97(state, reg)) != 0) { 807 next = first; 808 break; 809 } 810 811 delay = TS_DELAY_CNT; 812 while (delay--) { 813 (void) ddi_get16(handle, data); 814 } 815 816 if ((next = audiots_read_ac97(state, reg)) != 0) { 817 break; 818 } 819 } 820 821 /* 822 * Arggg, if you let the next read happen too soon then it fails. 823 * 12 usec fails, 13 usec succeeds. So set it to 20 for safety. 824 */ 825 drv_usecwait(TS_20US); 826 827 return (next); 828 829} 830 831/* 832 * audiots_init_state() 833 * 834 * Description: 835 * This routine initializes the audio driver's state structure. 836 * This includes reading the properties. 837 * 838 * CAUTION: This routine cannot allocate resources, unless it frees 839 * them before returning for an error. Also, error_destroy: 840 * in audiots_attach() would need to be fixed as well. 841 * 842 * NOTE: birdsnest supports CD ROM input. We check for the cdrom 843 * property. If there we turn it on. 844 * 845 * Arguments: 846 * audiots_state_t *state The device's state structure 847 * dev_info_t *dip Pointer to the device's dev_info struct 848 * 849 * Returns: 850 * DDI_SUCCESS State structure initialized 851 * DDI_FAILURE State structure not initialized 852 */ 853static int 854audiots_init_state(audiots_state_t *state, dev_info_t *dip) 855{ 856 state->ts_ac97 = ac97_alloc(dip, audiots_get_ac97, 857 audiots_set_ac97, state); 858 859 if (state->ts_ac97 == NULL) { 860 return (DDI_FAILURE); 861 } 862 863 /* save the device info pointer */ 864 state->ts_dip = dip; 865 866 /* get the iblock cookie needed for interrupt context */ 867 if (ddi_get_iblock_cookie(dip, 0, &state->ts_iblock) != DDI_SUCCESS) { 868 audio_dev_warn(state->ts_adev, 869 "cannot get iblock cookie"); 870 return (DDI_FAILURE); 871 } 872 873 /* initialize the state mutexes and condition variables */ 874 mutex_init(&state->ts_lock, NULL, MUTEX_DRIVER, state->ts_iblock); 875 state->ts_flags |= TS_MUTEX_INIT; 876 877 for (int i = 0; i < TS_NUM_PORTS; i++) { 878 if (audiots_alloc_port(state, i) != DDI_SUCCESS) { 879 return (DDI_FAILURE); 880 } 881 } 882 /* init power management state */ 883 state->ts_suspended = B_FALSE; 884 885 return (DDI_SUCCESS); 886 887} 888 889/* 890 * audiots_intr() 891 * 892 * Description: 893 * Interrupt service routine for both play and record. For play we 894 * get the next buffers worth of audio. For record we send it on to 895 * the mixer. 896 * 897 * NOTE: This device needs to make sure any PIO access required to clear 898 * its interrupt has made it out on the PCI bus before returning from its 899 * interrupt handler so that the interrupt has been deasserted. This is 900 * done by rereading the address engine interrupt register. 901 * 902 * Arguments: 903 * caddr_t T Pointer to the interrupting device's state 904 * structure 905 * 906 * Returns: 907 * DDI_INTR_CLAIMED Interrupt claimed and processed 908 * DDI_INTR_UNCLAIMED Interrupt not claimed, and thus ignored 909 */ 910static uint_t 911audiots_intr(caddr_t T) 912{ 913 audiots_state_t *state = (void *)T; 914 audiots_regs_t *regs = state->ts_regs; 915 ddi_acc_handle_t handle = state->ts_acch; 916 uint32_t interrupts; 917 918 mutex_enter(&state->ts_lock); 919 920 if (state->ts_suspended) { 921 mutex_exit(&state->ts_lock); 922 return (DDI_INTR_UNCLAIMED); 923 } 924 925 interrupts = ddi_get32(handle, ®s->aud_regs.ap_aint); 926 if (interrupts == 0) { 927 mutex_exit(&state->ts_lock); 928 /* no interrupts to process, so it's not us */ 929 return (DDI_INTR_UNCLAIMED); 930 } 931 932 /* 933 * Clear the interrupts to acknowledge. Also, reread the 934 * interrupt reg to ensure that PIO write has completed. 935 */ 936 ddi_put32(handle, ®s->aud_regs.ap_aint, interrupts); 937 (void) ddi_get32(handle, ®s->aud_regs.ap_aint); 938 939 /* update the kernel interrupt statistics */ 940 if (state->ts_ksp) { 941 TS_KIOP(state)->intrs[KSTAT_INTR_HARD]++; 942 } 943 944 mutex_exit(&state->ts_lock); 945 946 for (int i = 0; i < TS_NUM_PORTS; i++) { 947 audiots_port_t *port = state->ts_ports[i]; 948 949 if (((interrupts & port->tp_int_mask) == 0) || 950 (!port->tp_started)) 951 continue; 952 953 if (i == TS_INPUT_PORT) { 954 audio_engine_produce(port->tp_engine); 955 } else { 956 audio_engine_consume(port->tp_engine); 957 } 958 } 959 960 return (DDI_INTR_CLAIMED); 961 962} 963 964/* 965 * audiots_map_regs() 966 * 967 * Description: 968 * This routine maps the registers in. 969 * 970 * Once the config space registers are mapped in we determine if the 971 * audio core may be power managed. It should, but if it doesn't, 972 * then trying to may cause the core to hang. 973 * 974 * CAUTION: Make sure all errors call audio_dev_warn(). 975 * 976 * Arguments: 977 * dev_info_t *dip Pointer to the device's devinfo 978 * audiots_state_t *state The device's state structure 979 * Returns: 980 * DDI_SUCCESS Registers successfully mapped 981 * DDI_FAILURE Registers not successfully mapped 982 */ 983static int 984audiots_map_regs(dev_info_t *dip, audiots_state_t *state) 985{ 986 char rev[16]; 987 char *name; 988 989 /* map in the registers, the config and memory mapped registers */ 990 if (pci_config_setup(dip, &state->ts_pcih) != DDI_SUCCESS) { 991 audio_dev_warn(state->ts_adev, 992 "unable to map PCI configuration space"); 993 return (DDI_FAILURE); 994 } 995 996 /* Read the Audio Controller's vendor, device, and revision IDs */ 997 state->ts_devid = 998 (pci_config_get16(state->ts_pcih, PCI_CONF_VENID) << 16) | 999 pci_config_get16(state->ts_pcih, PCI_CONF_DEVID); 1000 state->ts_revid = pci_config_get8(state->ts_pcih, PCI_CONF_REVID); 1001 1002 if (ddi_regs_map_setup(dip, TS_MEM_MAPPED_REGS, 1003 (caddr_t *)&state->ts_regs, 0, 0, &ts_regs_attr, &state->ts_acch) != 1004 DDI_SUCCESS) { 1005 audio_dev_warn(state->ts_adev, 1006 "unable to map PCI device registers"); 1007 return (DDI_FAILURE); 1008 } 1009 1010 switch (state->ts_devid) { 1011 case 0x10b95451: 1012 name = "ALI M5451"; 1013 break; 1014 default: 1015 name = "audiots"; 1016 break; 1017 } 1018 (void) snprintf(rev, sizeof (rev), "Rev %x", state->ts_revid); 1019 audio_dev_set_description(state->ts_adev, name); 1020 audio_dev_set_version(state->ts_adev, rev); 1021 1022 return (DDI_SUCCESS); 1023} 1024 1025/* 1026 * audiots_alloc_port() 1027 * 1028 * Description: 1029 * This routine allocates the DMA handles and the memory for the 1030 * DMA engines to use. It then binds each of the buffers to its 1031 * respective handle, getting a DMA cookie. 1032 * 1033 * NOTE: All of the ddi_dma_... routines sleep if they cannot get 1034 * memory. This means these calls should always succeed. 1035 * 1036 * NOTE: ddi_dma_alloc_handle() attempts to use the full 4 GB DMA address 1037 * range. This is to work around Southbridge rev E/G OBP issues. 1038 * (See Grover OBP note above) 1039 * 1040 * CAUTION: Make sure all errors call audio_dev_warn(). 1041 * 1042 * Arguments: 1043 * audiots_port_t *state The port structure for a device stream 1044 * int num The port number 1045 * 1046 * Returns: 1047 * DDI_SUCCESS DMA resources mapped 1048 * DDI_FAILURE DMA resources not successfully mapped 1049 */ 1050int 1051audiots_alloc_port(audiots_state_t *state, int num) 1052{ 1053 audiots_port_t *port; 1054 dev_info_t *dip = state->ts_dip; 1055 audio_dev_t *adev = state->ts_adev; 1056 char *prop; 1057 int dir; 1058 unsigned caps; 1059 ddi_dma_cookie_t cookie; 1060 unsigned count; 1061 int rc; 1062 ddi_acc_handle_t regsh = state->ts_acch; 1063 uint32_t *gcptr = &state->ts_regs->aud_regs.ap_cir_gc; 1064 char *namestr; 1065 1066 port = kmem_zalloc(sizeof (*port), KM_SLEEP); 1067 state->ts_ports[num] = port; 1068 port->tp_num = num; 1069 port->tp_state = state; 1070 port->tp_started = B_FALSE; 1071 port->tp_rate = 48000; 1072 1073 if (num == TS_INPUT_PORT) { 1074 prop = "record-interrupts"; 1075 dir = DDI_DMA_READ; 1076 caps = ENGINE_INPUT_CAP; 1077 port->tp_dma_stream = 31; 1078 port->tp_int_stream = 2; 1079 port->tp_sync_dir = DDI_DMA_SYNC_FORKERNEL; 1080 } else { 1081 prop = "play-interrupts"; 1082 dir = DDI_DMA_WRITE; 1083 caps = ENGINE_OUTPUT_CAP; 1084 port->tp_dma_stream = 0; 1085 port->tp_int_stream = 1; 1086 port->tp_sync_dir = DDI_DMA_SYNC_FORDEV; 1087 } 1088 port->tp_int_mask = (1U << port->tp_int_stream); 1089 port->tp_dma_mask = (1U << port->tp_dma_stream); 1090 1091 /* get the number of interrupts per second */ 1092 port->tp_intrs = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1093 DDI_PROP_DONTPASS, prop, TS_INTS); 1094 1095 /* make sure the values are good */ 1096 if (port->tp_intrs < TS_MIN_INTS) { 1097 audio_dev_warn(adev, "%s too low, %d, resetting to %d", 1098 prop, port->tp_intrs, TS_INTS); 1099 port->tp_intrs = TS_INTS; 1100 } else if (port->tp_intrs > TS_MAX_INTS) { 1101 audio_dev_warn(adev, "%s too high, %d, resetting to %d", 1102 prop, port->tp_intrs, TS_INTS); 1103 port->tp_intrs = TS_INTS; 1104 } 1105 1106 /* 1107 * Now allocate space. We configure for the worst case. The 1108 * worst (biggest) case is 48000 kHz, at 4 bytes per frame 1109 * (16-bit stereo), with the lowest interrupt frequency. We 1110 * need two fragments though, and each half has to be rounded 1111 * up to allow for alignment considerations. 1112 */ 1113 1114 /* allocate dma handle */ 1115 rc = ddi_dma_alloc_handle(dip, &audiots_attr, DDI_DMA_SLEEP, 1116 NULL, &port->tp_dmah); 1117 if (rc != DDI_SUCCESS) { 1118 audio_dev_warn(adev, "ddi_dma_alloc_handle failed: %d", rc); 1119 return (DDI_FAILURE); 1120 } 1121 /* allocate DMA buffer */ 1122 rc = ddi_dma_mem_alloc(port->tp_dmah, TS_BUFSZ, &ts_acc_attr, 1123 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, &port->tp_kaddr, 1124 &port->tp_size, &port->tp_acch); 1125 if (rc == DDI_FAILURE) { 1126 audio_dev_warn(adev, "dma_mem_alloc failed"); 1127 return (DDI_FAILURE); 1128 } 1129 1130 /* bind DMA buffer */ 1131 rc = ddi_dma_addr_bind_handle(port->tp_dmah, NULL, 1132 port->tp_kaddr, port->tp_size, dir|DDI_DMA_CONSISTENT, 1133 DDI_DMA_SLEEP, NULL, &cookie, &count); 1134 if (rc != DDI_DMA_MAPPED) { 1135 audio_dev_warn(adev, 1136 "ddi_dma_addr_bind_handle failed: %d", rc); 1137 return (DDI_FAILURE); 1138 } 1139 ASSERT(count == 1); 1140 1141 port->tp_paddr = cookie.dmac_address; 1142 if ((unsigned)port->tp_paddr & 0x80000000U) { 1143 ddi_put32(regsh, gcptr, 1144 ddi_get32(regsh, gcptr) | AP_CIR_GC_SYS_MEM_4G_ENABLE); 1145 } else { 1146 ddi_put32(regsh, gcptr, 1147 ddi_get32(regsh, gcptr) & ~(AP_CIR_GC_SYS_MEM_4G_ENABLE)); 1148 } 1149 port->tp_engine = audio_engine_alloc(&audiots_engine_ops, caps); 1150 if (port->tp_engine == NULL) { 1151 audio_dev_warn(adev, "audio_engine_alloc failed"); 1152 return (DDI_FAILURE); 1153 } 1154 1155 audio_engine_set_private(port->tp_engine, port); 1156 audio_dev_add_engine(adev, port->tp_engine); 1157 1158 state->ts_swapped = B_FALSE; 1159 1160 /* 1161 * SPARCLE platform specific hack. For reasons that I can't 1162 * seem to fathom, the SPARCLE platform only gets the 1163 * endianness correct when transferring whole 32-bit words and 1164 * using little endian mapping. That isn't compatible with 1165 * the audio framework's access mode, so we have to set up 1166 * explicit swapping of the left and right channels. 1167 * 1168 * The real mystery here is why this is required for Tadpole 1169 * SPARCLE, but not for any other standard Sun platforms that 1170 * I've tested. 1171 * 1172 * "swap_channels" property can be used in driver.conf to 1173 * force the left/right as well. 1174 */ 1175 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_root_node(), 0, 1176 "name", &namestr); 1177 if (rc == DDI_PROP_SUCCESS) { 1178 if (strcmp(namestr, "TAD,SPARCLE") == 0) { 1179 state->ts_swapped = B_TRUE; 1180 } 1181 ddi_prop_free(namestr); 1182 } 1183 1184 state->ts_swapped = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1185 DDI_PROP_NOTPROM | DDI_PROP_DONTPASS, "swap_channels", 1186 state->ts_swapped); 1187 1188 return (DDI_SUCCESS); 1189} 1190 1191/* 1192 * audiots_read_ac97() 1193 * 1194 * Description: 1195 * This routine actually reads the AC-97 Codec's register. It may 1196 * be called several times to succeed. 1197 * 1198 * NOTE: 1199 * Revision M1535D B1-C of the ALI SouthBridge includes a workaround for 1200 * the broken busy flag. Resetting the busy flag requires a software tweak 1201 * to go with the worked around hardware. When we detect failure, we make 1202 * 10 attempts to reset the chip before we fail. This should reset the new 1203 * SB systems. On all SB systems, this will increse the read delay 1204 * slightly, but shouldn't bother it otherwise. 1205 * 1206 * Arguments: 1207 * audiots_state_t *state The device's state structure 1208 * int reg AC-97 register number 1209 * 1210 * Returns: 1211 * unsigned short The value in the specified register 1212 */ 1213static uint16_t 1214audiots_read_ac97(audiots_state_t *state, int reg) 1215{ 1216 ddi_acc_handle_t acch = state->ts_acch; 1217 uint16_t *addr; 1218 uint16_t *data; 1219 uint32_t *stimer = &state->ts_regs->aud_regs.ap_stimer; 1220 uint32_t chk1; 1221 uint32_t chk2; 1222 int resets = 0; 1223 int i; 1224 1225 if (state->ts_revid == AC_REV_ID1) { 1226 addr = &state->ts_regs->aud_regs.ap_acrd_35D_reg; 1227 data = &state->ts_regs->aud_regs.ap_acrd_35D_data; 1228 } else { 1229 addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; 1230 data = &state->ts_regs->aud_regs.ap_acrdwr_data; 1231 } 1232 1233first_read: 1234 /* wait for ready to send read request */ 1235 for (i = 0; i < TS_READ_TRIES; i++) { 1236 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) { 1237 break; 1238 } 1239 /* don't beat on the bus */ 1240 drv_usecwait(1); 1241 } 1242 if (i >= TS_READ_TRIES) { 1243 if (resets < TS_RESET_TRIES) { 1244 /* Attempt to reset */ 1245 drv_usecwait(TS_20US); 1246 ddi_put16(acch, addr, TS_SB_RESET); 1247 resets++; 1248 goto first_read; 1249 } else { 1250 state->ts_flags |= TS_AUDIO_READ_FAILED; 1251 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) { 1252 ddi_dev_report_fault(state->ts_dip, 1253 DDI_SERVICE_LOST, DDI_DEVICE_FAULT, 1254 "Unable to communicate with AC97 CODEC"); 1255 audio_dev_warn(state->ts_adev, 1256 "The audio AC97 register has timed out."); 1257 audio_dev_warn(state->ts_adev, 1258 "Audio is now disabled."); 1259 audio_dev_warn(state->ts_adev, 1260 "Please reboot to restore audio."); 1261 1262 /* Don't flood the console */ 1263 state->ts_flags |= TS_READ_FAILURE_PRINTED; 1264 } 1265 } 1266 return (0); 1267 } 1268 1269 /* program the register to read */ 1270 ddi_put16(acch, addr, (reg|AP_ACRD_W_PRIMARY_CODEC| 1271 AP_ACRD_W_READ_MIXER_REG|AP_ACRD_W_AUDIO_READ_REQ& 1272 (~AP_ACWR_W_SELECT_WRITE))); 1273 1274 /* hardware bug work around */ 1275 chk1 = ddi_get32(acch, stimer); 1276 chk2 = ddi_get32(acch, stimer); 1277 i = TS_WAIT_CNT; 1278 while (chk1 == chk2 && i) { 1279 chk2 = ddi_get32(acch, stimer); 1280 i--; 1281 } 1282 OR_SET_SHORT(acch, addr, AP_ACRD_W_READ_MIXER_REG); 1283 resets = 0; 1284 1285second_read: 1286 /* wait again for read to send read request */ 1287 for (i = 0; i < TS_READ_TRIES; i++) { 1288 if (!(ddi_get16(acch, addr) & AP_ACRD_R_READ_BUSY)) { 1289 break; 1290 } 1291 /* don't beat on the bus */ 1292 drv_usecwait(1); 1293 } 1294 if (i >= TS_READ_TRIES) { 1295 if (resets < TS_RESET_TRIES) { 1296 /* Attempt to reset */ 1297 drv_usecwait(TS_20US); 1298 ddi_put16(acch, addr, TS_SB_RESET); 1299 resets++; 1300 goto second_read; 1301 } else { 1302 state->ts_flags |= TS_AUDIO_READ_FAILED; 1303 if (!(state->ts_flags & TS_READ_FAILURE_PRINTED)) { 1304 ddi_dev_report_fault(state->ts_dip, 1305 DDI_SERVICE_LOST, DDI_DEVICE_FAULT, 1306 "Unable to communicate with AC97 CODEC"); 1307 audio_dev_warn(state->ts_adev, 1308 "The audio AC97 register has timed out."); 1309 audio_dev_warn(state->ts_adev, 1310 "Audio is now disabled."); 1311 audio_dev_warn(state->ts_adev, 1312 "Please reboot to restore audio."); 1313 1314 /* Don't flood the console */ 1315 state->ts_flags |= TS_READ_FAILURE_PRINTED; 1316 } 1317 } 1318 return (0); 1319 } 1320 1321 return (ddi_get16(acch, data)); 1322 1323} /* audiots_read_ac97() */ 1324 1325/* 1326 * audiots_set_ac97() 1327 * 1328 * Description: 1329 * Set the value in the specified AC-97 Codec register. Just like 1330 * reading the AC-97 Codec, it is possible there is a problem writing 1331 * it as well. So we loop. 1332 * 1333 * Arguments: 1334 * audiots_state_t *state The device's state structure 1335 * int reg AC-97 register number 1336 * uint16_t value The value to write 1337 * 1338 * Returns: 1339 * void 1340 */ 1341static void 1342audiots_set_ac97(void *arg, uint8_t reg8, uint16_t data) 1343{ 1344 audiots_state_t *state = arg; 1345 ddi_acc_handle_t handle = state->ts_acch; 1346 uint16_t *data_addr = &state->ts_regs->aud_regs.ap_acrdwr_data; 1347 uint16_t *reg_addr = &state->ts_regs->aud_regs.ap_acrdwr_reg; 1348 int count; 1349 int i; 1350 uint16_t tmp_short; 1351 uint16_t reg = reg8; 1352 1353 reg &= AP_ACWR_INDEX_MASK; 1354 1355 /* Don't touch the reserved bits on the pre 35D+ SouthBridge */ 1356 if (state->ts_revid == AC_REV_ID1) { 1357 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG; 1358 } else { 1359 reg |= AP_ACWR_W_PRIMARY_CODEC|AP_ACWR_W_WRITE_MIXER_REG| 1360 AP_ACWR_W_SELECT_WRITE; 1361 } 1362 1363 for (count = TS_LOOP_CNT; count--; ) { 1364 /* wait for ready to write */ 1365 for (i = 0; i < TS_WAIT_CNT; i++) { 1366 if (!(ddi_get16(handle, reg_addr) & 1367 AP_ACWR_R_WRITE_BUSY)) { 1368 /* ready to write */ 1369 ddi_put16(handle, reg_addr, reg); 1370 1371 /* Write the data */ 1372 ddi_put16(handle, data_addr, data); 1373 break; 1374 } 1375 } 1376 if (i >= TS_WAIT_CNT) { 1377 /* try again */ 1378 continue; 1379 } 1380 1381 /* wait for write to complete */ 1382 for (i = 0; i < TS_WAIT_CNT; i++) { 1383 if (!(ddi_get16(handle, reg_addr) & 1384 AP_ACWR_R_WRITE_BUSY)) { 1385 /* done writing */ 1386 break; 1387 } 1388 } 1389 1390 /* verify the value written */ 1391 tmp_short = audiots_get_ac97(state, reg8); 1392 if (data == tmp_short) { 1393 /* successfully loaded, so we can return */ 1394 return; 1395 } 1396 } 1397 1398} /* audiots_set_ac97() */ 1399 1400/* 1401 * audiots_reset_port() 1402 * 1403 * Description: 1404 * Initializes the hardware for a DMA engine. 1405 * We only support stereo 16-bit linear PCM (signed native endian). 1406 * 1407 * The audio core uses a single DMA buffer which is divided into two 1408 * halves. An interrupt is generated when the middle of the buffer has 1409 * been reached and at the end. The audio core resets the pointer back 1410 * to the beginning automatically. After the interrupt the driver clears 1411 * the buffer and asks the mixer for more audio samples. If there aren't 1412 * enough then silence is played out. 1413 * 1414 * Arguments: 1415 * audiots_port_t *port The DMA engine to reset 1416 * 1417 * Returns: 1418 * void 1419 */ 1420static void 1421audiots_reset_port(audiots_port_t *port) 1422{ 1423 audiots_state_t *state = port->tp_state; 1424 ddi_acc_handle_t handle = state->ts_acch; 1425 audiots_regs_t *regs = state->ts_regs; 1426 audiots_aram_t *aram; 1427 audiots_eram_t *eram; 1428 unsigned delta; 1429 uint16_t ctrl; 1430 uint16_t gvsel; 1431 uint16_t eso; 1432 1433 if (state->ts_suspended) 1434 return; 1435 1436 port->tp_cso = 0; 1437 1438 gvsel = ERAM_WAVE_VOL | ERAM_PAN_0dB | ERAM_VOL_DEFAULT; 1439 ctrl = ERAM_16_BITS | ERAM_STEREO | ERAM_LOOP_MODE | ERAM_SIGNED_PCM; 1440 for (int i = 0; i < 2; i++) { 1441 1442 delta = (port->tp_rate << TS_SRC_SHIFT) / TS_RATE; 1443 1444 if (i == 0) { 1445 /* first do the DMA stream */ 1446 aram = ®s->aud_ram[port->tp_dma_stream].aram; 1447 eram = ®s->aud_ram[port->tp_dma_stream].eram; 1448 if (port->tp_num == TS_INPUT_PORT) { 1449 delta = (TS_RATE << TS_SRC_SHIFT) / 1450 port->tp_rate; 1451 } 1452 eso = port->tp_nframes - 1; 1453 } else { 1454 /* else do the interrupt stream */ 1455 aram = ®s->aud_ram[port->tp_int_stream].aram; 1456 eram = ®s->aud_ram[port->tp_int_stream].eram; 1457 /* interrupt stream is silent */ 1458 gvsel |= ERAM_VOL_MAX_ATTEN; 1459 eso = port->tp_fragfr - 1; 1460 } 1461 1462 /* program the sample rate */ 1463 ddi_put16(handle, &aram->aram_delta, (uint16_t)delta); 1464 1465 /* program the precision, number of channels and loop mode */ 1466 ddi_put16(handle, &eram->eram_ctrl_ec, ctrl); 1467 1468 /* program the volume settings */ 1469 ddi_put16(handle, &eram->eram_gvsel_pan_vol, gvsel); 1470 1471 /* set ALPHA and FMS to 0 */ 1472 ddi_put16(handle, &aram->aram_alpha_fms, 0x0); 1473 1474 /* set CSO to 0 */ 1475 ddi_put16(handle, &aram->aram_cso, 0x0); 1476 1477 /* set LBA */ 1478 ddi_put32(handle, &aram->aram_cptr_lba, 1479 port->tp_paddr & ARAM_LBA_MASK); 1480 1481 /* set ESO */ 1482 ddi_put16(handle, &aram->aram_eso, eso); 1483 } 1484 1485 /* stop the DMA & interrupt engines */ 1486 ddi_put32(handle, ®s->aud_regs.ap_stop, 1487 port->tp_int_mask | port->tp_dma_mask); 1488 1489 /* enable interrupts */ 1490 OR_SET_WORD(handle, ®s->aud_regs.ap_ainten, port->tp_int_mask); 1491} 1492 1493/* 1494 * audiots_open() 1495 * 1496 * Description: 1497 * Opens a DMA engine for use. Will also ensure the device is powered 1498 * up if not already done so. 1499 * 1500 * Arguments: 1501 * void *arg The DMA engine to set up 1502 * int flag Open flags 1503 * unsigned *fragfrp Receives number of frames per fragment 1504 * unsigned *nfragsp Receives number of fragments 1505 * caddr_t *bufp Receives kernel data buffer 1506 * 1507 * Returns: 1508 * 0 on success 1509 * errno on failure 1510 */ 1511static int 1512audiots_open(void *arg, int flag, 1513 unsigned *fragfrp, unsigned *nfragsp, caddr_t *bufp) 1514{ 1515 audiots_port_t *port = arg; 1516 unsigned nfrag; 1517 1518 _NOTE(ARGUNUSED(flag)); 1519 1520 /* 1521 * Round up - we have to have a sample that is a whole number 1522 * of 64-bit words. Since our frames are 4 bytes wide, we 1523 * just need an even number of frames. 1524 */ 1525 port->tp_fragfr = port->tp_rate / port->tp_intrs; 1526 port->tp_fragfr = (port->tp_fragfr + 1) & ~1; 1527 nfrag = port->tp_size / (port->tp_fragfr * TS_FRAMESZ); 1528 port->tp_nframes = nfrag * port->tp_fragfr; 1529 port->tp_started = B_FALSE; 1530 port->tp_count = 0; 1531 port->tp_cso = 0; 1532 *fragfrp = port->tp_fragfr; 1533 *nfragsp = nfrag; 1534 *bufp = port->tp_kaddr; 1535 1536 /* 1537 * This should always be true because we used a worst case 1538 * assumption when calculating the port->tp_size. 1539 */ 1540 ASSERT((port->tp_fragfr * nfrag) <= port->tp_size); 1541 1542 mutex_enter(&port->tp_state->ts_lock); 1543 audiots_reset_port(port); 1544 mutex_exit(&port->tp_state->ts_lock); 1545 1546 return (0); 1547} 1548 1549/* 1550 * audiots_close() 1551 * 1552 * Description: 1553 * Closes an audio DMA engine that was previously opened. Since 1554 * nobody is using it, we take this opportunity to possibly power 1555 * down the entire device. 1556 * 1557 * Arguments: 1558 * void *arg The DMA engine to shut down 1559 * 1560 * Returns: 1561 * void 1562 */ 1563static void 1564audiots_close(void *arg) 1565{ 1566 audiots_port_t *port = arg; 1567 audiots_state_t *state = port->tp_state; 1568 1569 mutex_enter(&state->ts_lock); 1570 audiots_stop_port(port); 1571 port->tp_started = B_FALSE; 1572 mutex_exit(&state->ts_lock); 1573} 1574 1575/* 1576 * audiots_stop() 1577 * 1578 * Description: 1579 * This is called by the framework to stop a port that is 1580 * transferring data. 1581 * 1582 * Arguments: 1583 * void *arg The DMA engine to stop 1584 * 1585 * Returns: 1586 * void 1587 */ 1588static void 1589audiots_stop(void *arg) 1590{ 1591 audiots_port_t *port = arg; 1592 audiots_state_t *state = port->tp_state; 1593 1594 mutex_enter(&state->ts_lock); 1595 if (port->tp_started) { 1596 audiots_stop_port(port); 1597 } 1598 port->tp_started = B_FALSE; 1599 mutex_exit(&state->ts_lock); 1600} 1601 1602/* 1603 * audiots_start() 1604 * 1605 * Description: 1606 * This is called by the framework to start a port transferring data. 1607 * 1608 * Arguments: 1609 * void *arg The DMA engine to start 1610 * 1611 * Returns: 1612 * 0 on success (never fails, errno if it did) 1613 */ 1614static int 1615audiots_start(void *arg) 1616{ 1617 audiots_port_t *port = arg; 1618 audiots_state_t *state = port->tp_state; 1619 1620 mutex_enter(&state->ts_lock); 1621 if (!port->tp_started) { 1622 audiots_start_port(port); 1623 port->tp_started = B_TRUE; 1624 } 1625 mutex_exit(&state->ts_lock); 1626 return (0); 1627} 1628 1629/* 1630 * audiots_chinfo() 1631 * 1632 * Description: 1633 * This is called by the framework to query the channel offsets 1634 * and ordering. 1635 * 1636 * Arguments: 1637 * void *arg The DMA engine to query 1638 * int chan Channel number. 1639 * unsigned *offset Starting offset of channel. 1640 * unsigned *incr Increment (in samples) between frames. 1641 * 1642 * Returns: 1643 * 0 indicating rate array is range instead of enumeration 1644 */ 1645 1646static void 1647audiots_chinfo(void *arg, int chan, unsigned *offset, unsigned *incr) 1648{ 1649 audiots_port_t *port = arg; 1650 1651 /* if channels are swapped (SPARCLE), then deal with it */ 1652 if (port->tp_state->ts_swapped) { 1653 *offset = (chan ? 0 : 1); 1654 } else { 1655 *offset = chan; 1656 } 1657 *incr = 2; 1658} 1659 1660/* 1661 * audiots_format() 1662 * 1663 * Description: 1664 * Called by the framework to query the format for the device. 1665 * 1666 * Arguments: 1667 * void *arg The DMA engine to query 1668 * 1669 * Returns: 1670 * AUDIO_FORMAT_S16_LE. 1671 */ 1672static int 1673audiots_format(void *arg) 1674{ 1675 _NOTE(ARGUNUSED(arg)); 1676 1677 return (AUDIO_FORMAT_S16_LE); 1678} 1679 1680 1681/* 1682 * audiots_channels() 1683 * 1684 * Description: 1685 * Called by the framework to query the channnels for the device. 1686 * 1687 * Arguments: 1688 * void *arg The DMA engine to query 1689 * 1690 * Returns: 1691 * 2 (Stereo). 1692 */ 1693static int 1694audiots_channels(void *arg) 1695{ 1696 _NOTE(ARGUNUSED(arg)); 1697 1698 return (2); 1699} 1700 1701/* 1702 * audiots_rate() 1703 * 1704 * Description: 1705 * Called by the framework to query the sample rates for the device. 1706 * 1707 * Arguments: 1708 * void *arg The DMA engine to query 1709 * 1710 * Returns: 1711 * Sample rate in HZ (always 48000). 1712 */ 1713static int 1714audiots_rate(void *arg) 1715{ 1716 audiots_port_t *port = arg; 1717 1718 return (port->tp_rate); 1719} 1720 1721/* 1722 * audiots_count() 1723 * 1724 * Description: 1725 * This is called by the framework to get the engine's frame counter 1726 * 1727 * Arguments: 1728 * void *arg The DMA engine to query 1729 * 1730 * Returns: 1731 * frame count for current engine 1732 */ 1733static uint64_t 1734audiots_count(void *arg) 1735{ 1736 audiots_port_t *port = arg; 1737 audiots_state_t *state = port->tp_state; 1738 uint64_t val; 1739 1740 mutex_enter(&state->ts_lock); 1741 audiots_update_port(port); 1742 1743 val = port->tp_count; 1744 mutex_exit(&state->ts_lock); 1745 return (val); 1746} 1747 1748/* 1749 * audiots_sync() 1750 * 1751 * Description: 1752 * This is called by the framework to synchronize DMA caches. 1753 * We also leverage this do some endian swapping, because on SPARC 1754 * the chip accesses the DMA region using 32-bit little-endian 1755 * accesses. Its not enough to just use the framework's sample 1756 * conversion logic, because the channels will also be backwards. 1757 * 1758 * Arguments: 1759 * void *arg The DMA engine to sync 1760 * 1761 * Returns: 1762 * void 1763 */ 1764static void 1765audiots_sync(void *arg, unsigned nframes) 1766{ 1767 audiots_port_t *port = arg; 1768 _NOTE(ARGUNUSED(nframes)); 1769 1770 (void) ddi_dma_sync(port->tp_dmah, 0, 0, port->tp_sync_dir); 1771} 1772 1773/* 1774 * audiots_qlen() 1775 * 1776 * Description: 1777 * This is called by the framework to determine on-device queue length. 1778 * 1779 * Arguments: 1780 * void *arg The DMA engine to query 1781 * 1782 * Returns: 1783 * hardware queue length not reported by count (0 for this device) 1784 */ 1785static size_t 1786audiots_qlen(void *arg) 1787{ 1788 _NOTE(ARGUNUSED(arg)); 1789 return (0); 1790} 1791 1792/* 1793 * audiots_start_port() 1794 * 1795 * Description: 1796 * The audio core uses a single DMA buffer which is divided into two 1797 * halves. An interrupt is generated when the middle of the buffer has 1798 * been reached and at the end. The audio core resets the pointer back 1799 * to the beginning automatically. After the interrupt the driver clears 1800 * the buffer and asks the mixer for more audio samples. If there aren't 1801 * enough then silence is played out. 1802 * 1803 * Arguments: 1804 * audiots_port_t *port The DMA engine to start up 1805 * 1806 * Returns: 1807 * void 1808 */ 1809static void 1810audiots_start_port(audiots_port_t *port) 1811{ 1812 audiots_state_t *state = port->tp_state; 1813 audiots_regs_t *regs = state->ts_regs; 1814 ddi_acc_handle_t handle = state->ts_acch; 1815 1816 ASSERT(mutex_owned(&state->ts_lock)); 1817 1818 /* if suspended then do nothing else */ 1819 if (state->ts_suspended) { 1820 return; 1821 } 1822 1823 /* make sure it starts playing */ 1824 ddi_put32(handle, ®s->aud_regs.ap_start, 1825 port->tp_dma_mask | port->tp_int_mask); 1826 1827 ASSERT(mutex_owned(&state->ts_lock)); 1828} 1829 1830/* 1831 * audiots_stop_port() 1832 * 1833 * Description: 1834 * This routine stops a DMA engine. 1835 * 1836 * Arguments: 1837 * audiots_port_t *port The port to stop 1838 * 1839 * Returns: 1840 * void 1841 */ 1842static void 1843audiots_stop_port(audiots_port_t *port) 1844{ 1845 audiots_state_t *state = port->tp_state; 1846 1847 ASSERT(mutex_owned(&state->ts_lock)); 1848 1849 if (state->ts_suspended) 1850 return; 1851 1852 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop, 1853 port->tp_int_mask | port->tp_dma_mask); 1854 1855 ASSERT(mutex_owned(&state->ts_lock)); 1856} 1857 1858/* 1859 * audiots_update_port() 1860 * 1861 * Description: 1862 * This routine updates the ports frame counter from hardware, and 1863 * gracefully handles wraps. 1864 * 1865 * Arguments: 1866 * audiots_port_t *port The port to stop 1867 * 1868 * Returns: 1869 * void 1870 */ 1871static void 1872audiots_update_port(audiots_port_t *port) 1873{ 1874 audiots_state_t *state = port->tp_state; 1875 1876 uint16_t cso; 1877 unsigned n; 1878 1879 ASSERT(mutex_owned(&state->ts_lock)); 1880 1881 if (state->ts_suspended) 1882 return; 1883 1884 cso = ddi_get16(state->ts_acch, 1885 &state->ts_regs->aud_ram[port->tp_dma_stream].aram.aram_cso); 1886 1887 n = (cso >= port->tp_cso) ? 1888 cso - port->tp_cso : 1889 cso + port->tp_nframes - port->tp_cso; 1890 1891 port->tp_cso = cso; 1892 port->tp_count += n; 1893} 1894 1895/* 1896 * audiots_stop_everything() 1897 * 1898 * Description: 1899 * This routine disables the address engine interrupt for all 32 DMA 1900 * engines. Just to be sure, it then explicitly issues a stop command to 1901 * the address engine and envelope engines for all 32 channels. 1902 * 1903 * NOTE: 1904 * 1905 * There is a hardware bug that generates a spurious interrupt 1906 * when the DMA engines are stopped. It's not consistent - it 1907 * happens every 1 out of 6 stops or so. It will show up as a 1908 * record interrupt. The problem is that once the driver is 1909 * detached or if the system goes into low power mode, nobody 1910 * will service that interrupt. The system will eventually become 1911 * unusable. 1912 * 1913 * Arguments: 1914 * audiots_state_t *state The device's state structure 1915 * 1916 * Returns: 1917 * void 1918 */ 1919static void 1920audiots_stop_everything(audiots_state_t *state) 1921{ 1922 if (state->ts_acch == NULL) 1923 return; 1924 1925 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_ainten, 1926 TS_ALL_DMA_OFF); 1927 1928 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_stop, 1929 TS_ALL_DMA_ENGINES); 1930 1931 ddi_put32(state->ts_acch, &state->ts_regs->aud_regs.ap_aint, 1932 TS_ALL_DMA_ENGINES); 1933} 1934 1935/* 1936 * audiots_free_port() 1937 * 1938 * Description: 1939 * This routine unbinds the DMA cookies, frees the DMA buffers, 1940 * deallocates the DMA handles. 1941 * 1942 * Arguments: 1943 * audiots_port_t *port The port structure for a device stream. 1944 * 1945 * Returns: 1946 * None 1947 */ 1948void 1949audiots_free_port(audiots_port_t *port) 1950{ 1951 if (port == NULL) 1952 return; 1953 1954 if (port->tp_engine) { 1955 audio_dev_remove_engine(port->tp_state->ts_adev, 1956 port->tp_engine); 1957 audio_engine_free(port->tp_engine); 1958 } 1959 if (port->tp_paddr) { 1960 (void) ddi_dma_unbind_handle(port->tp_dmah); 1961 } 1962 if (port->tp_acch) { 1963 ddi_dma_mem_free(&port->tp_acch); 1964 } 1965 if (port->tp_dmah) { 1966 ddi_dma_free_handle(&port->tp_dmah); 1967 } 1968 kmem_free(port, sizeof (*port)); 1969} 1970 1971/* 1972 * audiots_destroy() 1973 * 1974 * Description: 1975 * This routine releases all resources held by the device instance, 1976 * as part of either detach or a failure in attach. 1977 * 1978 * Arguments: 1979 * audiots_state_t *state The device soft state. 1980 * 1981 * Returns: 1982 * None 1983 */ 1984void 1985audiots_destroy(audiots_state_t *state) 1986{ 1987 audiots_stop_everything(state); 1988 1989 if (state->ts_flags & TS_INTR_INSTALLED) 1990 ddi_remove_intr(state->ts_dip, 0, NULL); 1991 1992 if (state->ts_ksp) 1993 kstat_delete(state->ts_ksp); 1994 1995 for (int i = 0; i < TS_NUM_PORTS; i++) 1996 audiots_free_port(state->ts_ports[i]); 1997 1998 if (state->ts_acch) 1999 ddi_regs_map_free(&state->ts_acch); 2000 2001 if (state->ts_pcih) 2002 pci_config_teardown(&state->ts_pcih); 2003 2004 if (state->ts_ac97) 2005 ac97_free(state->ts_ac97); 2006 2007 if (state->ts_adev) 2008 audio_dev_free(state->ts_adev); 2009 2010 if (state->ts_flags & TS_MUTEX_INIT) { 2011 mutex_destroy(&state->ts_lock); 2012 } 2013 2014 ddi_soft_state_free(audiots_statep, ddi_get_instance(state->ts_dip)); 2015} 2016