1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#ifndef _CHEETAH_SDC_H 28#define _CHEETAH_SDC_H 29 30#pragma ident "%Z%%M% %I% %E% SMI" 31 32/* 33 * TARGET_REG: The register that is being tested 34 * TEMP_REG: The register that is used for the random 35 * instructions. This must be a odd register. 36 * The fault does not occur if even registers 37 * are used. 38 * CHECK_REG1: The register to which the contents of the 39 * TARGET_REG will be moved. 40 * CHECK_REG2: Same as CHECK_REG1. 41 */ 42 43#ifdef __cplusplus 44extern "C" { 45#endif 46 47/* Global Registers */ 48 49#ifdef GLOBALS 50#define TEMP_REG l1 51#define CHECK_REG1 o0 52#define CHECK_REG2 o1 53#endif 54 55#ifdef G1 56#define TARGET_REG g1 57#endif 58 59#ifdef G2 60#define TARGET_REG g2 61.register %g2, #scratch 62#endif 63 64#ifdef G3 65#define TARGET_REG g3 66.register %g3, #scratch 67#endif 68 69#ifdef G4 70#define TARGET_REG g4 71#endif 72 73 74/* Local Registers */ 75 76#ifdef LOCALS 77#define TEMP_REG o3 78#define CHECK_REG1 o0 79#define CHECK_REG2 o1 80#endif 81 82#ifdef L0 83#define TARGET_REG l0 84#endif 85 86#ifdef L1 87#define TARGET_REG l1 88#endif 89 90#ifdef L2 91#define TARGET_REG l2 92#endif 93 94#ifdef L3 95#define TARGET_REG l3 96#endif 97 98#ifdef L4 99#define TARGET_REG l4 100#endif 101 102#ifdef L5 103#define TARGET_REG l5 104#endif 105 106#ifdef L6 107#define TARGET_REG l6 108#endif 109 110#ifdef L7 111#define TARGET_REG l7 112#endif 113 114 115/* Out Registers */ 116 117#ifdef OUTS 118#define TEMP_REG l3 119#define CHECK_REG1 l0 120#define CHECK_REG2 l1 121#endif 122 123#ifdef O0 124#define TARGET_REG o0 125#endif 126 127#ifdef O1 128#define TARGET_REG o1 129#endif 130 131#ifdef O2 132#define TARGET_REG o2 133#endif 134 135#ifdef O3 136#define TARGET_REG o3 137#endif 138 139#ifdef O4 140#define TARGET_REG o4 141#endif 142 143#ifdef O5 144#define TARGET_REG o5 145#endif 146 147/* %o6 not tested as it is the %sp */ 148 149#ifdef O7 150#define TARGET_REG o7 151#endif 152 153#ifdef __cplusplus 154} 155#endif 156 157#endif /* _CHEETAH_SDC_H */ 158