1/* 2 * Copyright (c) 1999, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "asm/assembler.hpp" 27#include "c1/c1_Defs.hpp" 28#include "c1/c1_MacroAssembler.hpp" 29#include "c1/c1_Runtime1.hpp" 30#include "interpreter/interpreter.hpp" 31#include "nativeInst_x86.hpp" 32#include "oops/compiledICHolder.hpp" 33#include "oops/oop.inline.hpp" 34#include "prims/jvmtiExport.hpp" 35#include "register_x86.hpp" 36#include "runtime/sharedRuntime.hpp" 37#include "runtime/signature.hpp" 38#include "runtime/vframeArray.hpp" 39#include "utilities/macros.hpp" 40#include "vmreg_x86.inline.hpp" 41#if INCLUDE_ALL_GCS 42#include "gc/g1/g1SATBCardTableModRefBS.hpp" 43#endif 44 45 46// Implementation of StubAssembler 47 48int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) { 49 // setup registers 50 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); // is callee-saved register (Visual C++ calling conventions) 51 assert(!(oop_result1->is_valid() || metadata_result->is_valid()) || oop_result1 != metadata_result, "registers must be different"); 52 assert(oop_result1 != thread && metadata_result != thread, "registers must be different"); 53 assert(args_size >= 0, "illegal args_size"); 54 bool align_stack = false; 55#ifdef _LP64 56 // At a method handle call, the stack may not be properly aligned 57 // when returning with an exception. 58 align_stack = (stub_id() == Runtime1::handle_exception_from_callee_id); 59#endif 60 61#ifdef _LP64 62 mov(c_rarg0, thread); 63 set_num_rt_args(0); // Nothing on stack 64#else 65 set_num_rt_args(1 + args_size); 66 67 // push java thread (becomes first argument of C function) 68 get_thread(thread); 69 push(thread); 70#endif // _LP64 71 72 int call_offset; 73 if (!align_stack) { 74 set_last_Java_frame(thread, noreg, rbp, NULL); 75 } else { 76 address the_pc = pc(); 77 call_offset = offset(); 78 set_last_Java_frame(thread, noreg, rbp, the_pc); 79 andptr(rsp, -(StackAlignmentInBytes)); // Align stack 80 } 81 82 // do the call 83 call(RuntimeAddress(entry)); 84 if (!align_stack) { 85 call_offset = offset(); 86 } 87 // verify callee-saved register 88#ifdef ASSERT 89 guarantee(thread != rax, "change this code"); 90 push(rax); 91 { Label L; 92 get_thread(rax); 93 cmpptr(thread, rax); 94 jcc(Assembler::equal, L); 95 int3(); 96 stop("StubAssembler::call_RT: rdi not callee saved?"); 97 bind(L); 98 } 99 pop(rax); 100#endif 101 reset_last_Java_frame(thread, true); 102 103 // discard thread and arguments 104 NOT_LP64(addptr(rsp, num_rt_args()*BytesPerWord)); 105 106 // check for pending exceptions 107 { Label L; 108 cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 109 jcc(Assembler::equal, L); 110 // exception pending => remove activation and forward to exception handler 111 movptr(rax, Address(thread, Thread::pending_exception_offset())); 112 // make sure that the vm_results are cleared 113 if (oop_result1->is_valid()) { 114 movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); 115 } 116 if (metadata_result->is_valid()) { 117 movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); 118 } 119 if (frame_size() == no_frame_size) { 120 leave(); 121 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 122 } else if (_stub_id == Runtime1::forward_exception_id) { 123 should_not_reach_here(); 124 } else { 125 jump(RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); 126 } 127 bind(L); 128 } 129 // get oop results if there are any and reset the values in the thread 130 if (oop_result1->is_valid()) { 131 get_vm_result(oop_result1, thread); 132 } 133 if (metadata_result->is_valid()) { 134 get_vm_result_2(metadata_result, thread); 135 } 136 return call_offset; 137} 138 139 140int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) { 141#ifdef _LP64 142 mov(c_rarg1, arg1); 143#else 144 push(arg1); 145#endif // _LP64 146 return call_RT(oop_result1, metadata_result, entry, 1); 147} 148 149 150int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) { 151#ifdef _LP64 152 if (c_rarg1 == arg2) { 153 if (c_rarg2 == arg1) { 154 xchgq(arg1, arg2); 155 } else { 156 mov(c_rarg2, arg2); 157 mov(c_rarg1, arg1); 158 } 159 } else { 160 mov(c_rarg1, arg1); 161 mov(c_rarg2, arg2); 162 } 163#else 164 push(arg2); 165 push(arg1); 166#endif // _LP64 167 return call_RT(oop_result1, metadata_result, entry, 2); 168} 169 170 171int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) { 172#ifdef _LP64 173 // if there is any conflict use the stack 174 if (arg1 == c_rarg2 || arg1 == c_rarg3 || 175 arg2 == c_rarg1 || arg1 == c_rarg3 || 176 arg3 == c_rarg1 || arg1 == c_rarg2) { 177 push(arg3); 178 push(arg2); 179 push(arg1); 180 pop(c_rarg1); 181 pop(c_rarg2); 182 pop(c_rarg3); 183 } else { 184 mov(c_rarg1, arg1); 185 mov(c_rarg2, arg2); 186 mov(c_rarg3, arg3); 187 } 188#else 189 push(arg3); 190 push(arg2); 191 push(arg1); 192#endif // _LP64 193 return call_RT(oop_result1, metadata_result, entry, 3); 194} 195 196 197// Implementation of StubFrame 198 199class StubFrame: public StackObj { 200 private: 201 StubAssembler* _sasm; 202 203 public: 204 StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments); 205 void load_argument(int offset_in_words, Register reg); 206 207 ~StubFrame(); 208}; 209 210 211#define __ _sasm-> 212 213StubFrame::StubFrame(StubAssembler* sasm, const char* name, bool must_gc_arguments) { 214 _sasm = sasm; 215 __ set_info(name, must_gc_arguments); 216 __ enter(); 217} 218 219// load parameters that were stored with LIR_Assembler::store_parameter 220// Note: offsets for store_parameter and load_argument must match 221void StubFrame::load_argument(int offset_in_words, Register reg) { 222 // rbp, + 0: link 223 // + 1: return address 224 // + 2: argument with offset 0 225 // + 3: argument with offset 1 226 // + 4: ... 227 228 __ movptr(reg, Address(rbp, (offset_in_words + 2) * BytesPerWord)); 229} 230 231 232StubFrame::~StubFrame() { 233 __ leave(); 234 __ ret(0); 235} 236 237#undef __ 238 239 240// Implementation of Runtime1 241 242#define __ sasm-> 243 244const int float_regs_as_doubles_size_in_slots = pd_nof_fpu_regs_frame_map * 2; 245const int xmm_regs_as_doubles_size_in_slots = FrameMap::nof_xmm_regs * 2; 246 247// Stack layout for saving/restoring all the registers needed during a runtime 248// call (this includes deoptimization) 249// Note: note that users of this frame may well have arguments to some runtime 250// while these values are on the stack. These positions neglect those arguments 251// but the code in save_live_registers will take the argument count into 252// account. 253// 254#ifdef _LP64 255 #define SLOT2(x) x, 256 #define SLOT_PER_WORD 2 257#else 258 #define SLOT2(x) 259 #define SLOT_PER_WORD 1 260#endif // _LP64 261 262enum reg_save_layout { 263 // 64bit needs to keep stack 16 byte aligned. So we add some alignment dummies to make that 264 // happen and will assert if the stack size we create is misaligned 265#ifdef _LP64 266 align_dummy_0, align_dummy_1, 267#endif // _LP64 268#ifdef _WIN64 269 // Windows always allocates space for it's argument registers (see 270 // frame::arg_reg_save_area_bytes). 271 arg_reg_save_1, arg_reg_save_1H, // 0, 4 272 arg_reg_save_2, arg_reg_save_2H, // 8, 12 273 arg_reg_save_3, arg_reg_save_3H, // 16, 20 274 arg_reg_save_4, arg_reg_save_4H, // 24, 28 275#endif // _WIN64 276 xmm_regs_as_doubles_off, // 32 277 float_regs_as_doubles_off = xmm_regs_as_doubles_off + xmm_regs_as_doubles_size_in_slots, // 160 278 fpu_state_off = float_regs_as_doubles_off + float_regs_as_doubles_size_in_slots, // 224 279 // fpu_state_end_off is exclusive 280 fpu_state_end_off = fpu_state_off + (FPUStateSizeInWords / SLOT_PER_WORD), // 352 281 marker = fpu_state_end_off, SLOT2(markerH) // 352, 356 282 extra_space_offset, // 360 283#ifdef _LP64 284 r15_off = extra_space_offset, r15H_off, // 360, 364 285 r14_off, r14H_off, // 368, 372 286 r13_off, r13H_off, // 376, 380 287 r12_off, r12H_off, // 384, 388 288 r11_off, r11H_off, // 392, 396 289 r10_off, r10H_off, // 400, 404 290 r9_off, r9H_off, // 408, 412 291 r8_off, r8H_off, // 416, 420 292 rdi_off, rdiH_off, // 424, 428 293#else 294 rdi_off = extra_space_offset, 295#endif // _LP64 296 rsi_off, SLOT2(rsiH_off) // 432, 436 297 rbp_off, SLOT2(rbpH_off) // 440, 444 298 rsp_off, SLOT2(rspH_off) // 448, 452 299 rbx_off, SLOT2(rbxH_off) // 456, 460 300 rdx_off, SLOT2(rdxH_off) // 464, 468 301 rcx_off, SLOT2(rcxH_off) // 472, 476 302 rax_off, SLOT2(raxH_off) // 480, 484 303 saved_rbp_off, SLOT2(saved_rbpH_off) // 488, 492 304 return_off, SLOT2(returnH_off) // 496, 500 305 reg_save_frame_size // As noted: neglects any parameters to runtime // 504 306}; 307 308 309 310// Save off registers which might be killed by calls into the runtime. 311// Tries to smart of about FP registers. In particular we separate 312// saving and describing the FPU registers for deoptimization since we 313// have to save the FPU registers twice if we describe them and on P4 314// saving FPU registers which don't contain anything appears 315// expensive. The deopt blob is the only thing which needs to 316// describe FPU registers. In all other cases it should be sufficient 317// to simply save their current value. 318 319static OopMap* generate_oop_map(StubAssembler* sasm, int num_rt_args, 320 bool save_fpu_registers = true) { 321 322 // In 64bit all the args are in regs so there are no additional stack slots 323 LP64_ONLY(num_rt_args = 0); 324 LP64_ONLY(assert((reg_save_frame_size * VMRegImpl::stack_slot_size) % 16 == 0, "must be 16 byte aligned");) 325 int frame_size_in_slots = reg_save_frame_size + num_rt_args; // args + thread 326 sasm->set_frame_size(frame_size_in_slots / VMRegImpl::slots_per_word); 327 328 // record saved value locations in an OopMap 329 // locations are offsets from sp after runtime call; num_rt_args is number of arguments in call, including thread 330 OopMap* map = new OopMap(frame_size_in_slots, 0); 331 map->set_callee_saved(VMRegImpl::stack2reg(rax_off + num_rt_args), rax->as_VMReg()); 332 map->set_callee_saved(VMRegImpl::stack2reg(rcx_off + num_rt_args), rcx->as_VMReg()); 333 map->set_callee_saved(VMRegImpl::stack2reg(rdx_off + num_rt_args), rdx->as_VMReg()); 334 map->set_callee_saved(VMRegImpl::stack2reg(rbx_off + num_rt_args), rbx->as_VMReg()); 335 map->set_callee_saved(VMRegImpl::stack2reg(rsi_off + num_rt_args), rsi->as_VMReg()); 336 map->set_callee_saved(VMRegImpl::stack2reg(rdi_off + num_rt_args), rdi->as_VMReg()); 337#ifdef _LP64 338 map->set_callee_saved(VMRegImpl::stack2reg(r8_off + num_rt_args), r8->as_VMReg()); 339 map->set_callee_saved(VMRegImpl::stack2reg(r9_off + num_rt_args), r9->as_VMReg()); 340 map->set_callee_saved(VMRegImpl::stack2reg(r10_off + num_rt_args), r10->as_VMReg()); 341 map->set_callee_saved(VMRegImpl::stack2reg(r11_off + num_rt_args), r11->as_VMReg()); 342 map->set_callee_saved(VMRegImpl::stack2reg(r12_off + num_rt_args), r12->as_VMReg()); 343 map->set_callee_saved(VMRegImpl::stack2reg(r13_off + num_rt_args), r13->as_VMReg()); 344 map->set_callee_saved(VMRegImpl::stack2reg(r14_off + num_rt_args), r14->as_VMReg()); 345 map->set_callee_saved(VMRegImpl::stack2reg(r15_off + num_rt_args), r15->as_VMReg()); 346 347 // This is stupid but needed. 348 map->set_callee_saved(VMRegImpl::stack2reg(raxH_off + num_rt_args), rax->as_VMReg()->next()); 349 map->set_callee_saved(VMRegImpl::stack2reg(rcxH_off + num_rt_args), rcx->as_VMReg()->next()); 350 map->set_callee_saved(VMRegImpl::stack2reg(rdxH_off + num_rt_args), rdx->as_VMReg()->next()); 351 map->set_callee_saved(VMRegImpl::stack2reg(rbxH_off + num_rt_args), rbx->as_VMReg()->next()); 352 map->set_callee_saved(VMRegImpl::stack2reg(rsiH_off + num_rt_args), rsi->as_VMReg()->next()); 353 map->set_callee_saved(VMRegImpl::stack2reg(rdiH_off + num_rt_args), rdi->as_VMReg()->next()); 354 355 map->set_callee_saved(VMRegImpl::stack2reg(r8H_off + num_rt_args), r8->as_VMReg()->next()); 356 map->set_callee_saved(VMRegImpl::stack2reg(r9H_off + num_rt_args), r9->as_VMReg()->next()); 357 map->set_callee_saved(VMRegImpl::stack2reg(r10H_off + num_rt_args), r10->as_VMReg()->next()); 358 map->set_callee_saved(VMRegImpl::stack2reg(r11H_off + num_rt_args), r11->as_VMReg()->next()); 359 map->set_callee_saved(VMRegImpl::stack2reg(r12H_off + num_rt_args), r12->as_VMReg()->next()); 360 map->set_callee_saved(VMRegImpl::stack2reg(r13H_off + num_rt_args), r13->as_VMReg()->next()); 361 map->set_callee_saved(VMRegImpl::stack2reg(r14H_off + num_rt_args), r14->as_VMReg()->next()); 362 map->set_callee_saved(VMRegImpl::stack2reg(r15H_off + num_rt_args), r15->as_VMReg()->next()); 363#endif // _LP64 364 365 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 366#ifdef _LP64 367 if (UseAVX < 3) { 368 xmm_bypass_limit = xmm_bypass_limit / 2; 369 } 370#endif 371 372 if (save_fpu_registers) { 373 if (UseSSE < 2) { 374 int fpu_off = float_regs_as_doubles_off; 375 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 376 VMReg fpu_name_0 = FrameMap::fpu_regname(n); 377 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + num_rt_args), fpu_name_0); 378 // %%% This is really a waste but we'll keep things as they were for now 379 if (true) { 380 map->set_callee_saved(VMRegImpl::stack2reg(fpu_off + 1 + num_rt_args), fpu_name_0->next()); 381 } 382 fpu_off += 2; 383 } 384 assert(fpu_off == fpu_state_off, "incorrect number of fpu stack slots"); 385 } 386 387 if (UseSSE >= 2) { 388 int xmm_off = xmm_regs_as_doubles_off; 389 for (int n = 0; n < FrameMap::nof_xmm_regs; n++) { 390 if (n < xmm_bypass_limit) { 391 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); 392 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); 393 // %%% This is really a waste but we'll keep things as they were for now 394 if (true) { 395 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + 1 + num_rt_args), xmm_name_0->next()); 396 } 397 } 398 xmm_off += 2; 399 } 400 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); 401 402 } else if (UseSSE == 1) { 403 int xmm_off = xmm_regs_as_doubles_off; 404 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 405 VMReg xmm_name_0 = as_XMMRegister(n)->as_VMReg(); 406 map->set_callee_saved(VMRegImpl::stack2reg(xmm_off + num_rt_args), xmm_name_0); 407 xmm_off += 2; 408 } 409 assert(xmm_off == float_regs_as_doubles_off, "incorrect number of xmm registers"); 410 } 411 } 412 413 return map; 414} 415 416static OopMap* save_live_registers(StubAssembler* sasm, int num_rt_args, 417 bool save_fpu_registers = true) { 418 __ block_comment("save_live_registers"); 419 420 __ pusha(); // integer registers 421 422 // assert(float_regs_as_doubles_off % 2 == 0, "misaligned offset"); 423 // assert(xmm_regs_as_doubles_off % 2 == 0, "misaligned offset"); 424 425 __ subptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); 426 427#ifdef ASSERT 428 __ movptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); 429#endif 430 431 if (save_fpu_registers) { 432 if (UseSSE < 2) { 433 // save FPU stack 434 __ fnsave(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 435 __ fwait(); 436 437#ifdef ASSERT 438 Label ok; 439 __ cmpw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); 440 __ jccb(Assembler::equal, ok); 441 __ stop("corrupted control word detected"); 442 __ bind(ok); 443#endif 444 445 // Reset the control word to guard against exceptions being unmasked 446 // since fstp_d can cause FPU stack underflow exceptions. Write it 447 // into the on stack copy and then reload that to make sure that the 448 // current and future values are correct. 449 __ movw(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size), StubRoutines::fpu_cntrl_wrd_std()); 450 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 451 452 // Save the FPU registers in de-opt-able form 453 int offset = 0; 454 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 455 __ fstp_d(Address(rsp, float_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 456 offset += 8; 457 } 458 } 459 460 if (UseSSE >= 2) { 461 // save XMM registers 462 // XMM registers can contain float or double values, but this is not known here, 463 // so always save them as doubles. 464 // note that float values are _not_ converted automatically, so for float values 465 // the second word contains only garbage data. 466 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 467 int offset = 0; 468#ifdef _LP64 469 if (UseAVX < 3) { 470 xmm_bypass_limit = xmm_bypass_limit / 2; 471 } 472#endif 473 for (int n = 0; n < xmm_bypass_limit; n++) { 474 XMMRegister xmm_name = as_XMMRegister(n); 475 __ movdbl(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name); 476 offset += 8; 477 } 478 } else if (UseSSE == 1) { 479 // save XMM registers as float because double not supported without SSE2(num MMX == num fpu) 480 int offset = 0; 481 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 482 XMMRegister xmm_name = as_XMMRegister(n); 483 __ movflt(Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset), xmm_name); 484 offset += 8; 485 } 486 } 487 } 488 489 // FPU stack must be empty now 490 __ verify_FPU(0, "save_live_registers"); 491 492 return generate_oop_map(sasm, num_rt_args, save_fpu_registers); 493} 494 495 496static void restore_fpu(StubAssembler* sasm, bool restore_fpu_registers = true) { 497 if (restore_fpu_registers) { 498 if (UseSSE >= 2) { 499 // restore XMM registers 500 int xmm_bypass_limit = FrameMap::nof_xmm_regs; 501#ifdef _LP64 502 if (UseAVX < 3) { 503 xmm_bypass_limit = xmm_bypass_limit / 2; 504 } 505#endif 506 int offset = 0; 507 for (int n = 0; n < xmm_bypass_limit; n++) { 508 XMMRegister xmm_name = as_XMMRegister(n); 509 __ movdbl(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 510 offset += 8; 511 } 512 } else if (UseSSE == 1) { 513 // restore XMM registers(num MMX == num fpu) 514 int offset = 0; 515 for (int n = 0; n < FrameMap::nof_fpu_regs; n++) { 516 XMMRegister xmm_name = as_XMMRegister(n); 517 __ movflt(xmm_name, Address(rsp, xmm_regs_as_doubles_off * VMRegImpl::stack_slot_size + offset)); 518 offset += 8; 519 } 520 } 521 522 if (UseSSE < 2) { 523 __ frstor(Address(rsp, fpu_state_off * VMRegImpl::stack_slot_size)); 524 } else { 525 // check that FPU stack is really empty 526 __ verify_FPU(0, "restore_live_registers"); 527 } 528 529 } else { 530 // check that FPU stack is really empty 531 __ verify_FPU(0, "restore_live_registers"); 532 } 533 534#ifdef ASSERT 535 { 536 Label ok; 537 __ cmpptr(Address(rsp, marker * VMRegImpl::stack_slot_size), (int32_t)0xfeedbeef); 538 __ jcc(Assembler::equal, ok); 539 __ stop("bad offsets in frame"); 540 __ bind(ok); 541 } 542#endif // ASSERT 543 544 __ addptr(rsp, extra_space_offset * VMRegImpl::stack_slot_size); 545} 546 547 548static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = true) { 549 __ block_comment("restore_live_registers"); 550 551 restore_fpu(sasm, restore_fpu_registers); 552 __ popa(); 553} 554 555 556static void restore_live_registers_except_rax(StubAssembler* sasm, bool restore_fpu_registers = true) { 557 __ block_comment("restore_live_registers_except_rax"); 558 559 restore_fpu(sasm, restore_fpu_registers); 560 561#ifdef _LP64 562 __ movptr(r15, Address(rsp, 0)); 563 __ movptr(r14, Address(rsp, wordSize)); 564 __ movptr(r13, Address(rsp, 2 * wordSize)); 565 __ movptr(r12, Address(rsp, 3 * wordSize)); 566 __ movptr(r11, Address(rsp, 4 * wordSize)); 567 __ movptr(r10, Address(rsp, 5 * wordSize)); 568 __ movptr(r9, Address(rsp, 6 * wordSize)); 569 __ movptr(r8, Address(rsp, 7 * wordSize)); 570 __ movptr(rdi, Address(rsp, 8 * wordSize)); 571 __ movptr(rsi, Address(rsp, 9 * wordSize)); 572 __ movptr(rbp, Address(rsp, 10 * wordSize)); 573 // skip rsp 574 __ movptr(rbx, Address(rsp, 12 * wordSize)); 575 __ movptr(rdx, Address(rsp, 13 * wordSize)); 576 __ movptr(rcx, Address(rsp, 14 * wordSize)); 577 578 __ addptr(rsp, 16 * wordSize); 579#else 580 581 __ pop(rdi); 582 __ pop(rsi); 583 __ pop(rbp); 584 __ pop(rbx); // skip this value 585 __ pop(rbx); 586 __ pop(rdx); 587 __ pop(rcx); 588 __ addptr(rsp, BytesPerWord); 589#endif // _LP64 590} 591 592 593void Runtime1::initialize_pd() { 594 // nothing to do 595} 596 597 598// target: the entry point of the method that creates and posts the exception oop 599// has_argument: true if the exception needs an argument (passed on stack because registers must be preserved) 600 601OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) { 602 // preserve all registers 603 int num_rt_args = has_argument ? 2 : 1; 604 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 605 606 // now all registers are saved and can be used freely 607 // verify that no old value is used accidentally 608 __ invalidate_registers(true, true, true, true, true, true); 609 610 // registers used by this stub 611 const Register temp_reg = rbx; 612 613 // load argument for exception that is passed as an argument into the stub 614 if (has_argument) { 615#ifdef _LP64 616 __ movptr(c_rarg1, Address(rbp, 2*BytesPerWord)); 617#else 618 __ movptr(temp_reg, Address(rbp, 2*BytesPerWord)); 619 __ push(temp_reg); 620#endif // _LP64 621 } 622 int call_offset = __ call_RT(noreg, noreg, target, num_rt_args - 1); 623 624 OopMapSet* oop_maps = new OopMapSet(); 625 oop_maps->add_gc_map(call_offset, oop_map); 626 627 __ stop("should not reach here"); 628 629 return oop_maps; 630} 631 632 633OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler *sasm) { 634 __ block_comment("generate_handle_exception"); 635 636 // incoming parameters 637 const Register exception_oop = rax; 638 const Register exception_pc = rdx; 639 // other registers used in this stub 640 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 641 642 // Save registers, if required. 643 OopMapSet* oop_maps = new OopMapSet(); 644 OopMap* oop_map = NULL; 645 switch (id) { 646 case forward_exception_id: 647 // We're handling an exception in the context of a compiled frame. 648 // The registers have been saved in the standard places. Perform 649 // an exception lookup in the caller and dispatch to the handler 650 // if found. Otherwise unwind and dispatch to the callers 651 // exception handler. 652 oop_map = generate_oop_map(sasm, 1 /*thread*/); 653 654 // load and clear pending exception oop into RAX 655 __ movptr(exception_oop, Address(thread, Thread::pending_exception_offset())); 656 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); 657 658 // load issuing PC (the return address for this stub) into rdx 659 __ movptr(exception_pc, Address(rbp, 1*BytesPerWord)); 660 661 // make sure that the vm_results are cleared (may be unnecessary) 662 __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD); 663 __ movptr(Address(thread, JavaThread::vm_result_2_offset()), NULL_WORD); 664 break; 665 case handle_exception_nofpu_id: 666 case handle_exception_id: 667 // At this point all registers MAY be live. 668 oop_map = save_live_registers(sasm, 1 /*thread*/, id != handle_exception_nofpu_id); 669 break; 670 case handle_exception_from_callee_id: { 671 // At this point all registers except exception oop (RAX) and 672 // exception pc (RDX) are dead. 673 const int frame_size = 2 /*BP, return address*/ NOT_LP64(+ 1 /*thread*/) WIN64_ONLY(+ frame::arg_reg_save_area_bytes / BytesPerWord); 674 oop_map = new OopMap(frame_size * VMRegImpl::slots_per_word, 0); 675 sasm->set_frame_size(frame_size); 676 WIN64_ONLY(__ subq(rsp, frame::arg_reg_save_area_bytes)); 677 break; 678 } 679 default: ShouldNotReachHere(); 680 } 681 682#ifdef TIERED 683 // C2 can leave the fpu stack dirty 684 if (UseSSE < 2) { 685 __ empty_FPU_stack(); 686 } 687#endif // TIERED 688 689 // verify that only rax, and rdx is valid at this time 690 __ invalidate_registers(false, true, true, false, true, true); 691 // verify that rax, contains a valid exception 692 __ verify_not_null_oop(exception_oop); 693 694 // load address of JavaThread object for thread-local data 695 NOT_LP64(__ get_thread(thread);) 696 697#ifdef ASSERT 698 // check that fields in JavaThread for exception oop and issuing pc are 699 // empty before writing to them 700 Label oop_empty; 701 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t) NULL_WORD); 702 __ jcc(Assembler::equal, oop_empty); 703 __ stop("exception oop already set"); 704 __ bind(oop_empty); 705 706 Label pc_empty; 707 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); 708 __ jcc(Assembler::equal, pc_empty); 709 __ stop("exception pc already set"); 710 __ bind(pc_empty); 711#endif 712 713 // save exception oop and issuing pc into JavaThread 714 // (exception handler will load it from here) 715 __ movptr(Address(thread, JavaThread::exception_oop_offset()), exception_oop); 716 __ movptr(Address(thread, JavaThread::exception_pc_offset()), exception_pc); 717 718 // patch throwing pc into return address (has bci & oop map) 719 __ movptr(Address(rbp, 1*BytesPerWord), exception_pc); 720 721 // compute the exception handler. 722 // the exception oop and the throwing pc are read from the fields in JavaThread 723 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc)); 724 oop_maps->add_gc_map(call_offset, oop_map); 725 726 // rax: handler address 727 // will be the deopt blob if nmethod was deoptimized while we looked up 728 // handler regardless of whether handler existed in the nmethod. 729 730 // only rax, is valid at this time, all other registers have been destroyed by the runtime call 731 __ invalidate_registers(false, true, true, true, true, true); 732 733 // patch the return address, this stub will directly return to the exception handler 734 __ movptr(Address(rbp, 1*BytesPerWord), rax); 735 736 switch (id) { 737 case forward_exception_id: 738 case handle_exception_nofpu_id: 739 case handle_exception_id: 740 // Restore the registers that were saved at the beginning. 741 restore_live_registers(sasm, id != handle_exception_nofpu_id); 742 break; 743 case handle_exception_from_callee_id: 744 // WIN64_ONLY: No need to add frame::arg_reg_save_area_bytes to SP 745 // since we do a leave anyway. 746 747 // Pop the return address. 748 __ leave(); 749 __ pop(rcx); 750 __ jmp(rcx); // jump to exception handler 751 break; 752 default: ShouldNotReachHere(); 753 } 754 755 return oop_maps; 756} 757 758 759void Runtime1::generate_unwind_exception(StubAssembler *sasm) { 760 // incoming parameters 761 const Register exception_oop = rax; 762 // callee-saved copy of exception_oop during runtime call 763 const Register exception_oop_callee_saved = NOT_LP64(rsi) LP64_ONLY(r14); 764 // other registers used in this stub 765 const Register exception_pc = rdx; 766 const Register handler_addr = rbx; 767 const Register thread = NOT_LP64(rdi) LP64_ONLY(r15_thread); 768 769 // verify that only rax, is valid at this time 770 __ invalidate_registers(false, true, true, true, true, true); 771 772#ifdef ASSERT 773 // check that fields in JavaThread for exception oop and issuing pc are empty 774 NOT_LP64(__ get_thread(thread);) 775 Label oop_empty; 776 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), 0); 777 __ jcc(Assembler::equal, oop_empty); 778 __ stop("exception oop must be empty"); 779 __ bind(oop_empty); 780 781 Label pc_empty; 782 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), 0); 783 __ jcc(Assembler::equal, pc_empty); 784 __ stop("exception pc must be empty"); 785 __ bind(pc_empty); 786#endif 787 788 // clear the FPU stack in case any FPU results are left behind 789 __ empty_FPU_stack(); 790 791 // save exception_oop in callee-saved register to preserve it during runtime calls 792 __ verify_not_null_oop(exception_oop); 793 __ movptr(exception_oop_callee_saved, exception_oop); 794 795 NOT_LP64(__ get_thread(thread);) 796 // Get return address (is on top of stack after leave). 797 __ movptr(exception_pc, Address(rsp, 0)); 798 799 // search the exception handler address of the caller (using the return address) 800 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), thread, exception_pc); 801 // rax: exception handler address of the caller 802 803 // Only RAX and RSI are valid at this time, all other registers have been destroyed by the call. 804 __ invalidate_registers(false, true, true, true, false, true); 805 806 // move result of call into correct register 807 __ movptr(handler_addr, rax); 808 809 // Restore exception oop to RAX (required convention of exception handler). 810 __ movptr(exception_oop, exception_oop_callee_saved); 811 812 // verify that there is really a valid exception in rax 813 __ verify_not_null_oop(exception_oop); 814 815 // get throwing pc (= return address). 816 // rdx has been destroyed by the call, so it must be set again 817 // the pop is also necessary to simulate the effect of a ret(0) 818 __ pop(exception_pc); 819 820 // continue at exception handler (return address removed) 821 // note: do *not* remove arguments when unwinding the 822 // activation since the caller assumes having 823 // all arguments on the stack when entering the 824 // runtime to determine the exception handler 825 // (GC happens at call site with arguments!) 826 // rax: exception oop 827 // rdx: throwing pc 828 // rbx: exception handler 829 __ jmp(handler_addr); 830} 831 832 833OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) { 834 // use the maximum number of runtime-arguments here because it is difficult to 835 // distinguish each RT-Call. 836 // Note: This number affects also the RT-Call in generate_handle_exception because 837 // the oop-map is shared for all calls. 838 const int num_rt_args = 2; // thread + dummy 839 840 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 841 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 842 843 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 844 845#ifdef _LP64 846 const Register thread = r15_thread; 847 // No need to worry about dummy 848 __ mov(c_rarg0, thread); 849#else 850 __ push(rax); // push dummy 851 852 const Register thread = rdi; // is callee-saved register (Visual C++ calling conventions) 853 // push java thread (becomes first argument of C function) 854 __ get_thread(thread); 855 __ push(thread); 856#endif // _LP64 857 __ set_last_Java_frame(thread, noreg, rbp, NULL); 858 // do the call 859 __ call(RuntimeAddress(target)); 860 OopMapSet* oop_maps = new OopMapSet(); 861 oop_maps->add_gc_map(__ offset(), oop_map); 862 // verify callee-saved register 863#ifdef ASSERT 864 guarantee(thread != rax, "change this code"); 865 __ push(rax); 866 { Label L; 867 __ get_thread(rax); 868 __ cmpptr(thread, rax); 869 __ jcc(Assembler::equal, L); 870 __ stop("StubAssembler::call_RT: rdi/r15 not callee saved?"); 871 __ bind(L); 872 } 873 __ pop(rax); 874#endif 875 __ reset_last_Java_frame(thread, true); 876#ifndef _LP64 877 __ pop(rcx); // discard thread arg 878 __ pop(rcx); // discard dummy 879#endif // _LP64 880 881 // check for pending exceptions 882 { Label L; 883 __ cmpptr(Address(thread, Thread::pending_exception_offset()), (int32_t)NULL_WORD); 884 __ jcc(Assembler::equal, L); 885 // exception pending => remove activation and forward to exception handler 886 887 __ testptr(rax, rax); // have we deoptimized? 888 __ jump_cc(Assembler::equal, 889 RuntimeAddress(Runtime1::entry_for(Runtime1::forward_exception_id))); 890 891 // the deopt blob expects exceptions in the special fields of 892 // JavaThread, so copy and clear pending exception. 893 894 // load and clear pending exception 895 __ movptr(rax, Address(thread, Thread::pending_exception_offset())); 896 __ movptr(Address(thread, Thread::pending_exception_offset()), NULL_WORD); 897 898 // check that there is really a valid exception 899 __ verify_not_null_oop(rax); 900 901 // load throwing pc: this is the return address of the stub 902 __ movptr(rdx, Address(rsp, return_off * VMRegImpl::stack_slot_size)); 903 904#ifdef ASSERT 905 // check that fields in JavaThread for exception oop and issuing pc are empty 906 Label oop_empty; 907 __ cmpptr(Address(thread, JavaThread::exception_oop_offset()), (int32_t)NULL_WORD); 908 __ jcc(Assembler::equal, oop_empty); 909 __ stop("exception oop must be empty"); 910 __ bind(oop_empty); 911 912 Label pc_empty; 913 __ cmpptr(Address(thread, JavaThread::exception_pc_offset()), (int32_t)NULL_WORD); 914 __ jcc(Assembler::equal, pc_empty); 915 __ stop("exception pc must be empty"); 916 __ bind(pc_empty); 917#endif 918 919 // store exception oop and throwing pc to JavaThread 920 __ movptr(Address(thread, JavaThread::exception_oop_offset()), rax); 921 __ movptr(Address(thread, JavaThread::exception_pc_offset()), rdx); 922 923 restore_live_registers(sasm); 924 925 __ leave(); 926 __ addptr(rsp, BytesPerWord); // remove return address from stack 927 928 // Forward the exception directly to deopt blob. We can blow no 929 // registers and must leave throwing pc on the stack. A patch may 930 // have values live in registers so the entry point with the 931 // exception in tls. 932 __ jump(RuntimeAddress(deopt_blob->unpack_with_exception_in_tls())); 933 934 __ bind(L); 935 } 936 937 938 // Runtime will return true if the nmethod has been deoptimized during 939 // the patching process. In that case we must do a deopt reexecute instead. 940 941 Label reexecuteEntry, cont; 942 943 __ testptr(rax, rax); // have we deoptimized? 944 __ jcc(Assembler::equal, cont); // no 945 946 // Will reexecute. Proper return address is already on the stack we just restore 947 // registers, pop all of our frame but the return address and jump to the deopt blob 948 restore_live_registers(sasm); 949 __ leave(); 950 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 951 952 __ bind(cont); 953 restore_live_registers(sasm); 954 __ leave(); 955 __ ret(0); 956 957 return oop_maps; 958} 959 960 961OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) { 962 963 // for better readability 964 const bool must_gc_arguments = true; 965 const bool dont_gc_arguments = false; 966 967 // default value; overwritten for some optimized stubs that are called from methods that do not use the fpu 968 bool save_fpu_registers = true; 969 970 // stub code & info for the different stubs 971 OopMapSet* oop_maps = NULL; 972 switch (id) { 973 case forward_exception_id: 974 { 975 oop_maps = generate_handle_exception(id, sasm); 976 __ leave(); 977 __ ret(0); 978 } 979 break; 980 981 case new_instance_id: 982 case fast_new_instance_id: 983 case fast_new_instance_init_check_id: 984 { 985 Register klass = rdx; // Incoming 986 Register obj = rax; // Result 987 988 if (id == new_instance_id) { 989 __ set_info("new_instance", dont_gc_arguments); 990 } else if (id == fast_new_instance_id) { 991 __ set_info("fast new_instance", dont_gc_arguments); 992 } else { 993 assert(id == fast_new_instance_init_check_id, "bad StubID"); 994 __ set_info("fast new_instance init check", dont_gc_arguments); 995 } 996 997 if ((id == fast_new_instance_id || id == fast_new_instance_init_check_id) && 998 UseTLAB && FastTLABRefill) { 999 Label slow_path; 1000 Register obj_size = rcx; 1001 Register t1 = rbx; 1002 Register t2 = rsi; 1003 assert_different_registers(klass, obj, obj_size, t1, t2); 1004 1005 __ push(rdi); 1006 __ push(rbx); 1007 1008 if (id == fast_new_instance_init_check_id) { 1009 // make sure the klass is initialized 1010 __ cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); 1011 __ jcc(Assembler::notEqual, slow_path); 1012 } 1013 1014#ifdef ASSERT 1015 // assert object can be fast path allocated 1016 { 1017 Label ok, not_ok; 1018 __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); 1019 __ cmpl(obj_size, 0); // make sure it's an instance (LH > 0) 1020 __ jcc(Assembler::lessEqual, not_ok); 1021 __ testl(obj_size, Klass::_lh_instance_slow_path_bit); 1022 __ jcc(Assembler::zero, ok); 1023 __ bind(not_ok); 1024 __ stop("assert(can be fast path allocated)"); 1025 __ should_not_reach_here(); 1026 __ bind(ok); 1027 } 1028#endif // ASSERT 1029 1030 // if we got here then the TLAB allocation failed, so try 1031 // refilling the TLAB or allocating directly from eden. 1032 Label retry_tlab, try_eden; 1033 const Register thread = 1034 __ tlab_refill(retry_tlab, try_eden, slow_path); // does not destroy rdx (klass), returns rdi 1035 1036 __ bind(retry_tlab); 1037 1038 // get the instance size (size is postive so movl is fine for 64bit) 1039 __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); 1040 1041 __ tlab_allocate(obj, obj_size, 0, t1, t2, slow_path); 1042 1043 __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ true); 1044 __ verify_oop(obj); 1045 __ pop(rbx); 1046 __ pop(rdi); 1047 __ ret(0); 1048 1049 __ bind(try_eden); 1050 // get the instance size (size is postive so movl is fine for 64bit) 1051 __ movl(obj_size, Address(klass, Klass::layout_helper_offset())); 1052 1053 __ eden_allocate(obj, obj_size, 0, t1, slow_path); 1054 __ incr_allocated_bytes(thread, obj_size, 0); 1055 1056 __ initialize_object(obj, klass, obj_size, 0, t1, t2, /* is_tlab_allocated */ false); 1057 __ verify_oop(obj); 1058 __ pop(rbx); 1059 __ pop(rdi); 1060 __ ret(0); 1061 1062 __ bind(slow_path); 1063 __ pop(rbx); 1064 __ pop(rdi); 1065 } 1066 1067 __ enter(); 1068 OopMap* map = save_live_registers(sasm, 2); 1069 int call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_instance), klass); 1070 oop_maps = new OopMapSet(); 1071 oop_maps->add_gc_map(call_offset, map); 1072 restore_live_registers_except_rax(sasm); 1073 __ verify_oop(obj); 1074 __ leave(); 1075 __ ret(0); 1076 1077 // rax,: new instance 1078 } 1079 1080 break; 1081 1082 case counter_overflow_id: 1083 { 1084 Register bci = rax, method = rbx; 1085 __ enter(); 1086 OopMap* map = save_live_registers(sasm, 3); 1087 // Retrieve bci 1088 __ movl(bci, Address(rbp, 2*BytesPerWord)); 1089 // And a pointer to the Method* 1090 __ movptr(method, Address(rbp, 3*BytesPerWord)); 1091 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), bci, method); 1092 oop_maps = new OopMapSet(); 1093 oop_maps->add_gc_map(call_offset, map); 1094 restore_live_registers(sasm); 1095 __ leave(); 1096 __ ret(0); 1097 } 1098 break; 1099 1100 case new_type_array_id: 1101 case new_object_array_id: 1102 { 1103 Register length = rbx; // Incoming 1104 Register klass = rdx; // Incoming 1105 Register obj = rax; // Result 1106 1107 if (id == new_type_array_id) { 1108 __ set_info("new_type_array", dont_gc_arguments); 1109 } else { 1110 __ set_info("new_object_array", dont_gc_arguments); 1111 } 1112 1113#ifdef ASSERT 1114 // assert object type is really an array of the proper kind 1115 { 1116 Label ok; 1117 Register t0 = obj; 1118 __ movl(t0, Address(klass, Klass::layout_helper_offset())); 1119 __ sarl(t0, Klass::_lh_array_tag_shift); 1120 int tag = ((id == new_type_array_id) 1121 ? Klass::_lh_array_tag_type_value 1122 : Klass::_lh_array_tag_obj_value); 1123 __ cmpl(t0, tag); 1124 __ jcc(Assembler::equal, ok); 1125 __ stop("assert(is an array klass)"); 1126 __ should_not_reach_here(); 1127 __ bind(ok); 1128 } 1129#endif // ASSERT 1130 1131 if (UseTLAB && FastTLABRefill) { 1132 Register arr_size = rsi; 1133 Register t1 = rcx; // must be rcx for use as shift count 1134 Register t2 = rdi; 1135 Label slow_path; 1136 assert_different_registers(length, klass, obj, arr_size, t1, t2); 1137 1138 // check that array length is small enough for fast path. 1139 __ cmpl(length, C1_MacroAssembler::max_array_allocation_length); 1140 __ jcc(Assembler::above, slow_path); 1141 1142 // if we got here then the TLAB allocation failed, so try 1143 // refilling the TLAB or allocating directly from eden. 1144 Label retry_tlab, try_eden; 1145 const Register thread = 1146 __ tlab_refill(retry_tlab, try_eden, slow_path); // preserves rbx & rdx, returns rdi 1147 1148 __ bind(retry_tlab); 1149 1150 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F)) 1151 // since size is positive movl does right thing on 64bit 1152 __ movl(t1, Address(klass, Klass::layout_helper_offset())); 1153 // since size is postive movl does right thing on 64bit 1154 __ movl(arr_size, length); 1155 assert(t1 == rcx, "fixed register usage"); 1156 __ shlptr(arr_size /* by t1=rcx, mod 32 */); 1157 __ shrptr(t1, Klass::_lh_header_size_shift); 1158 __ andptr(t1, Klass::_lh_header_size_mask); 1159 __ addptr(arr_size, t1); 1160 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up 1161 __ andptr(arr_size, ~MinObjAlignmentInBytesMask); 1162 1163 __ tlab_allocate(obj, arr_size, 0, t1, t2, slow_path); // preserves arr_size 1164 1165 __ initialize_header(obj, klass, length, t1, t2); 1166 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte))); 1167 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise"); 1168 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise"); 1169 __ andptr(t1, Klass::_lh_header_size_mask); 1170 __ subptr(arr_size, t1); // body length 1171 __ addptr(t1, obj); // body start 1172 if (!ZeroTLAB) { 1173 __ initialize_body(t1, arr_size, 0, t2); 1174 } 1175 __ verify_oop(obj); 1176 __ ret(0); 1177 1178 __ bind(try_eden); 1179 // get the allocation size: round_up(hdr + length << (layout_helper & 0x1F)) 1180 // since size is positive movl does right thing on 64bit 1181 __ movl(t1, Address(klass, Klass::layout_helper_offset())); 1182 // since size is postive movl does right thing on 64bit 1183 __ movl(arr_size, length); 1184 assert(t1 == rcx, "fixed register usage"); 1185 __ shlptr(arr_size /* by t1=rcx, mod 32 */); 1186 __ shrptr(t1, Klass::_lh_header_size_shift); 1187 __ andptr(t1, Klass::_lh_header_size_mask); 1188 __ addptr(arr_size, t1); 1189 __ addptr(arr_size, MinObjAlignmentInBytesMask); // align up 1190 __ andptr(arr_size, ~MinObjAlignmentInBytesMask); 1191 1192 __ eden_allocate(obj, arr_size, 0, t1, slow_path); // preserves arr_size 1193 __ incr_allocated_bytes(thread, arr_size, 0); 1194 1195 __ initialize_header(obj, klass, length, t1, t2); 1196 __ movb(t1, Address(klass, in_bytes(Klass::layout_helper_offset()) + (Klass::_lh_header_size_shift / BitsPerByte))); 1197 assert(Klass::_lh_header_size_shift % BitsPerByte == 0, "bytewise"); 1198 assert(Klass::_lh_header_size_mask <= 0xFF, "bytewise"); 1199 __ andptr(t1, Klass::_lh_header_size_mask); 1200 __ subptr(arr_size, t1); // body length 1201 __ addptr(t1, obj); // body start 1202 __ initialize_body(t1, arr_size, 0, t2); 1203 __ verify_oop(obj); 1204 __ ret(0); 1205 1206 __ bind(slow_path); 1207 } 1208 1209 __ enter(); 1210 OopMap* map = save_live_registers(sasm, 3); 1211 int call_offset; 1212 if (id == new_type_array_id) { 1213 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length); 1214 } else { 1215 call_offset = __ call_RT(obj, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length); 1216 } 1217 1218 oop_maps = new OopMapSet(); 1219 oop_maps->add_gc_map(call_offset, map); 1220 restore_live_registers_except_rax(sasm); 1221 1222 __ verify_oop(obj); 1223 __ leave(); 1224 __ ret(0); 1225 1226 // rax,: new array 1227 } 1228 break; 1229 1230 case new_multi_array_id: 1231 { StubFrame f(sasm, "new_multi_array", dont_gc_arguments); 1232 // rax,: klass 1233 // rbx,: rank 1234 // rcx: address of 1st dimension 1235 OopMap* map = save_live_registers(sasm, 4); 1236 int call_offset = __ call_RT(rax, noreg, CAST_FROM_FN_PTR(address, new_multi_array), rax, rbx, rcx); 1237 1238 oop_maps = new OopMapSet(); 1239 oop_maps->add_gc_map(call_offset, map); 1240 restore_live_registers_except_rax(sasm); 1241 1242 // rax,: new multi array 1243 __ verify_oop(rax); 1244 } 1245 break; 1246 1247 case register_finalizer_id: 1248 { 1249 __ set_info("register_finalizer", dont_gc_arguments); 1250 1251 // This is called via call_runtime so the arguments 1252 // will be place in C abi locations 1253 1254#ifdef _LP64 1255 __ verify_oop(c_rarg0); 1256 __ mov(rax, c_rarg0); 1257#else 1258 // The object is passed on the stack and we haven't pushed a 1259 // frame yet so it's one work away from top of stack. 1260 __ movptr(rax, Address(rsp, 1 * BytesPerWord)); 1261 __ verify_oop(rax); 1262#endif // _LP64 1263 1264 // load the klass and check the has finalizer flag 1265 Label register_finalizer; 1266 Register t = rsi; 1267 __ load_klass(t, rax); 1268 __ movl(t, Address(t, Klass::access_flags_offset())); 1269 __ testl(t, JVM_ACC_HAS_FINALIZER); 1270 __ jcc(Assembler::notZero, register_finalizer); 1271 __ ret(0); 1272 1273 __ bind(register_finalizer); 1274 __ enter(); 1275 OopMap* oop_map = save_live_registers(sasm, 2 /*num_rt_args */); 1276 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), rax); 1277 oop_maps = new OopMapSet(); 1278 oop_maps->add_gc_map(call_offset, oop_map); 1279 1280 // Now restore all the live registers 1281 restore_live_registers(sasm); 1282 1283 __ leave(); 1284 __ ret(0); 1285 } 1286 break; 1287 1288 case throw_range_check_failed_id: 1289 { StubFrame f(sasm, "range_check_failed", dont_gc_arguments); 1290 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true); 1291 } 1292 break; 1293 1294 case throw_index_exception_id: 1295 { StubFrame f(sasm, "index_range_check_failed", dont_gc_arguments); 1296 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true); 1297 } 1298 break; 1299 1300 case throw_div0_exception_id: 1301 { StubFrame f(sasm, "throw_div0_exception", dont_gc_arguments); 1302 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false); 1303 } 1304 break; 1305 1306 case throw_null_pointer_exception_id: 1307 { StubFrame f(sasm, "throw_null_pointer_exception", dont_gc_arguments); 1308 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false); 1309 } 1310 break; 1311 1312 case handle_exception_nofpu_id: 1313 case handle_exception_id: 1314 { StubFrame f(sasm, "handle_exception", dont_gc_arguments); 1315 oop_maps = generate_handle_exception(id, sasm); 1316 } 1317 break; 1318 1319 case handle_exception_from_callee_id: 1320 { StubFrame f(sasm, "handle_exception_from_callee", dont_gc_arguments); 1321 oop_maps = generate_handle_exception(id, sasm); 1322 } 1323 break; 1324 1325 case unwind_exception_id: 1326 { __ set_info("unwind_exception", dont_gc_arguments); 1327 // note: no stubframe since we are about to leave the current 1328 // activation and we are calling a leaf VM function only. 1329 generate_unwind_exception(sasm); 1330 } 1331 break; 1332 1333 case throw_array_store_exception_id: 1334 { StubFrame f(sasm, "throw_array_store_exception", dont_gc_arguments); 1335 // tos + 0: link 1336 // + 1: return address 1337 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true); 1338 } 1339 break; 1340 1341 case throw_class_cast_exception_id: 1342 { StubFrame f(sasm, "throw_class_cast_exception", dont_gc_arguments); 1343 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true); 1344 } 1345 break; 1346 1347 case throw_incompatible_class_change_error_id: 1348 { StubFrame f(sasm, "throw_incompatible_class_cast_exception", dont_gc_arguments); 1349 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false); 1350 } 1351 break; 1352 1353 case slow_subtype_check_id: 1354 { 1355 // Typical calling sequence: 1356 // __ push(klass_RInfo); // object klass or other subclass 1357 // __ push(sup_k_RInfo); // array element klass or other superclass 1358 // __ call(slow_subtype_check); 1359 // Note that the subclass is pushed first, and is therefore deepest. 1360 // Previous versions of this code reversed the names 'sub' and 'super'. 1361 // This was operationally harmless but made the code unreadable. 1362 enum layout { 1363 rax_off, SLOT2(raxH_off) 1364 rcx_off, SLOT2(rcxH_off) 1365 rsi_off, SLOT2(rsiH_off) 1366 rdi_off, SLOT2(rdiH_off) 1367 // saved_rbp_off, SLOT2(saved_rbpH_off) 1368 return_off, SLOT2(returnH_off) 1369 sup_k_off, SLOT2(sup_kH_off) 1370 klass_off, SLOT2(superH_off) 1371 framesize, 1372 result_off = klass_off // deepest argument is also the return value 1373 }; 1374 1375 __ set_info("slow_subtype_check", dont_gc_arguments); 1376 __ push(rdi); 1377 __ push(rsi); 1378 __ push(rcx); 1379 __ push(rax); 1380 1381 // This is called by pushing args and not with C abi 1382 __ movptr(rsi, Address(rsp, (klass_off) * VMRegImpl::stack_slot_size)); // subclass 1383 __ movptr(rax, Address(rsp, (sup_k_off) * VMRegImpl::stack_slot_size)); // superclass 1384 1385 Label miss; 1386 __ check_klass_subtype_slow_path(rsi, rax, rcx, rdi, NULL, &miss); 1387 1388 // fallthrough on success: 1389 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), 1); // result 1390 __ pop(rax); 1391 __ pop(rcx); 1392 __ pop(rsi); 1393 __ pop(rdi); 1394 __ ret(0); 1395 1396 __ bind(miss); 1397 __ movptr(Address(rsp, (result_off) * VMRegImpl::stack_slot_size), NULL_WORD); // result 1398 __ pop(rax); 1399 __ pop(rcx); 1400 __ pop(rsi); 1401 __ pop(rdi); 1402 __ ret(0); 1403 } 1404 break; 1405 1406 case monitorenter_nofpu_id: 1407 save_fpu_registers = false; 1408 // fall through 1409 case monitorenter_id: 1410 { 1411 StubFrame f(sasm, "monitorenter", dont_gc_arguments); 1412 OopMap* map = save_live_registers(sasm, 3, save_fpu_registers); 1413 1414 // Called with store_parameter and not C abi 1415 1416 f.load_argument(1, rax); // rax,: object 1417 f.load_argument(0, rbx); // rbx,: lock address 1418 1419 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), rax, rbx); 1420 1421 oop_maps = new OopMapSet(); 1422 oop_maps->add_gc_map(call_offset, map); 1423 restore_live_registers(sasm, save_fpu_registers); 1424 } 1425 break; 1426 1427 case monitorexit_nofpu_id: 1428 save_fpu_registers = false; 1429 // fall through 1430 case monitorexit_id: 1431 { 1432 StubFrame f(sasm, "monitorexit", dont_gc_arguments); 1433 OopMap* map = save_live_registers(sasm, 2, save_fpu_registers); 1434 1435 // Called with store_parameter and not C abi 1436 1437 f.load_argument(0, rax); // rax,: lock address 1438 1439 // note: really a leaf routine but must setup last java sp 1440 // => use call_RT for now (speed can be improved by 1441 // doing last java sp setup manually) 1442 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), rax); 1443 1444 oop_maps = new OopMapSet(); 1445 oop_maps->add_gc_map(call_offset, map); 1446 restore_live_registers(sasm, save_fpu_registers); 1447 } 1448 break; 1449 1450 case deoptimize_id: 1451 { 1452 StubFrame f(sasm, "deoptimize", dont_gc_arguments); 1453 const int num_rt_args = 2; // thread, trap_request 1454 OopMap* oop_map = save_live_registers(sasm, num_rt_args); 1455 f.load_argument(0, rax); 1456 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), rax); 1457 oop_maps = new OopMapSet(); 1458 oop_maps->add_gc_map(call_offset, oop_map); 1459 restore_live_registers(sasm); 1460 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 1461 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 1462 __ leave(); 1463 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 1464 } 1465 break; 1466 1467 case access_field_patching_id: 1468 { StubFrame f(sasm, "access_field_patching", dont_gc_arguments); 1469 // we should set up register map 1470 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching)); 1471 } 1472 break; 1473 1474 case load_klass_patching_id: 1475 { StubFrame f(sasm, "load_klass_patching", dont_gc_arguments); 1476 // we should set up register map 1477 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching)); 1478 } 1479 break; 1480 1481 case load_mirror_patching_id: 1482 { StubFrame f(sasm, "load_mirror_patching", dont_gc_arguments); 1483 // we should set up register map 1484 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching)); 1485 } 1486 break; 1487 1488 case load_appendix_patching_id: 1489 { StubFrame f(sasm, "load_appendix_patching", dont_gc_arguments); 1490 // we should set up register map 1491 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching)); 1492 } 1493 break; 1494 1495 case dtrace_object_alloc_id: 1496 { // rax,: object 1497 StubFrame f(sasm, "dtrace_object_alloc", dont_gc_arguments); 1498 // we can't gc here so skip the oopmap but make sure that all 1499 // the live registers get saved. 1500 save_live_registers(sasm, 1); 1501 1502 __ NOT_LP64(push(rax)) LP64_ONLY(mov(c_rarg0, rax)); 1503 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_object_alloc))); 1504 NOT_LP64(__ pop(rax)); 1505 1506 restore_live_registers(sasm); 1507 } 1508 break; 1509 1510 case fpu2long_stub_id: 1511 { 1512 // rax, and rdx are destroyed, but should be free since the result is returned there 1513 // preserve rsi,ecx 1514 __ push(rsi); 1515 __ push(rcx); 1516 LP64_ONLY(__ push(rdx);) 1517 1518 // check for NaN 1519 Label return0, do_return, return_min_jlong, do_convert; 1520 1521 Address value_high_word(rsp, wordSize + 4); 1522 Address value_low_word(rsp, wordSize); 1523 Address result_high_word(rsp, 3*wordSize + 4); 1524 Address result_low_word(rsp, 3*wordSize); 1525 1526 __ subptr(rsp, 32); // more than enough on 32bit 1527 __ fst_d(value_low_word); 1528 __ movl(rax, value_high_word); 1529 __ andl(rax, 0x7ff00000); 1530 __ cmpl(rax, 0x7ff00000); 1531 __ jcc(Assembler::notEqual, do_convert); 1532 __ movl(rax, value_high_word); 1533 __ andl(rax, 0xfffff); 1534 __ orl(rax, value_low_word); 1535 __ jcc(Assembler::notZero, return0); 1536 1537 __ bind(do_convert); 1538 __ fnstcw(Address(rsp, 0)); 1539 __ movzwl(rax, Address(rsp, 0)); 1540 __ orl(rax, 0xc00); 1541 __ movw(Address(rsp, 2), rax); 1542 __ fldcw(Address(rsp, 2)); 1543 __ fwait(); 1544 __ fistp_d(result_low_word); 1545 __ fldcw(Address(rsp, 0)); 1546 __ fwait(); 1547 // This gets the entire long in rax on 64bit 1548 __ movptr(rax, result_low_word); 1549 // testing of high bits 1550 __ movl(rdx, result_high_word); 1551 __ mov(rcx, rax); 1552 // What the heck is the point of the next instruction??? 1553 __ xorl(rcx, 0x0); 1554 __ movl(rsi, 0x80000000); 1555 __ xorl(rsi, rdx); 1556 __ orl(rcx, rsi); 1557 __ jcc(Assembler::notEqual, do_return); 1558 __ fldz(); 1559 __ fcomp_d(value_low_word); 1560 __ fnstsw_ax(); 1561#ifdef _LP64 1562 __ testl(rax, 0x4100); // ZF & CF == 0 1563 __ jcc(Assembler::equal, return_min_jlong); 1564#else 1565 __ sahf(); 1566 __ jcc(Assembler::above, return_min_jlong); 1567#endif // _LP64 1568 // return max_jlong 1569#ifndef _LP64 1570 __ movl(rdx, 0x7fffffff); 1571 __ movl(rax, 0xffffffff); 1572#else 1573 __ mov64(rax, CONST64(0x7fffffffffffffff)); 1574#endif // _LP64 1575 __ jmp(do_return); 1576 1577 __ bind(return_min_jlong); 1578#ifndef _LP64 1579 __ movl(rdx, 0x80000000); 1580 __ xorl(rax, rax); 1581#else 1582 __ mov64(rax, UCONST64(0x8000000000000000)); 1583#endif // _LP64 1584 __ jmp(do_return); 1585 1586 __ bind(return0); 1587 __ fpop(); 1588#ifndef _LP64 1589 __ xorptr(rdx,rdx); 1590 __ xorptr(rax,rax); 1591#else 1592 __ xorptr(rax, rax); 1593#endif // _LP64 1594 1595 __ bind(do_return); 1596 __ addptr(rsp, 32); 1597 LP64_ONLY(__ pop(rdx);) 1598 __ pop(rcx); 1599 __ pop(rsi); 1600 __ ret(0); 1601 } 1602 break; 1603 1604#if INCLUDE_ALL_GCS 1605 case g1_pre_barrier_slow_id: 1606 { 1607 StubFrame f(sasm, "g1_pre_barrier", dont_gc_arguments); 1608 // arg0 : previous value of memory 1609 1610 BarrierSet* bs = Universe::heap()->barrier_set(); 1611 if (bs->kind() != BarrierSet::G1SATBCTLogging) { 1612 __ movptr(rax, (int)id); 1613 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); 1614 __ should_not_reach_here(); 1615 break; 1616 } 1617 __ push(rax); 1618 __ push(rdx); 1619 1620 const Register pre_val = rax; 1621 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); 1622 const Register tmp = rdx; 1623 1624 NOT_LP64(__ get_thread(thread);) 1625 1626 Address queue_active(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 1627 SATBMarkQueue::byte_offset_of_active())); 1628 Address queue_index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 1629 SATBMarkQueue::byte_offset_of_index())); 1630 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 1631 SATBMarkQueue::byte_offset_of_buf())); 1632 1633 Label done; 1634 Label runtime; 1635 1636 // Is marking still active? 1637 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 1638 __ cmpl(queue_active, 0); 1639 } else { 1640 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 1641 __ cmpb(queue_active, 0); 1642 } 1643 __ jcc(Assembler::equal, done); 1644 1645 // Can we store original value in the thread's buffer? 1646 1647 __ movptr(tmp, queue_index); 1648 __ testptr(tmp, tmp); 1649 __ jcc(Assembler::zero, runtime); 1650 __ subptr(tmp, wordSize); 1651 __ movptr(queue_index, tmp); 1652 __ addptr(tmp, buffer); 1653 1654 // prev_val (rax) 1655 f.load_argument(0, pre_val); 1656 __ movptr(Address(tmp, 0), pre_val); 1657 __ jmp(done); 1658 1659 __ bind(runtime); 1660 1661 save_live_registers(sasm, 3); 1662 1663 // load the pre-value 1664 f.load_argument(0, rcx); 1665 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), rcx, thread); 1666 1667 restore_live_registers(sasm); 1668 1669 __ bind(done); 1670 1671 __ pop(rdx); 1672 __ pop(rax); 1673 } 1674 break; 1675 1676 case g1_post_barrier_slow_id: 1677 { 1678 StubFrame f(sasm, "g1_post_barrier", dont_gc_arguments); 1679 1680 1681 // arg0: store_address 1682 Address store_addr(rbp, 2*BytesPerWord); 1683 1684 CardTableModRefBS* ct = 1685 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 1686 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 1687 1688 Label done; 1689 Label enqueued; 1690 Label runtime; 1691 1692 // At this point we know new_value is non-NULL and the new_value crosses regions. 1693 // Must check to see if card is already dirty 1694 1695 const Register thread = NOT_LP64(rax) LP64_ONLY(r15_thread); 1696 1697 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 1698 DirtyCardQueue::byte_offset_of_index())); 1699 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 1700 DirtyCardQueue::byte_offset_of_buf())); 1701 1702 __ push(rax); 1703 __ push(rcx); 1704 1705 const Register cardtable = rax; 1706 const Register card_addr = rcx; 1707 1708 f.load_argument(0, card_addr); 1709 __ shrptr(card_addr, CardTableModRefBS::card_shift); 1710 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 1711 // a valid address and therefore is not properly handled by the relocation code. 1712 __ movptr(cardtable, (intptr_t)ct->byte_map_base); 1713 __ addptr(card_addr, cardtable); 1714 1715 NOT_LP64(__ get_thread(thread);) 1716 1717 __ cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 1718 __ jcc(Assembler::equal, done); 1719 1720 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 1721 __ cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 1722 __ jcc(Assembler::equal, done); 1723 1724 // storing region crossing non-NULL, card is clean. 1725 // dirty card and log. 1726 1727 __ movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 1728 1729 const Register tmp = rdx; 1730 __ push(rdx); 1731 1732 __ movptr(tmp, queue_index); 1733 __ testptr(tmp, tmp); 1734 __ jcc(Assembler::zero, runtime); 1735 __ subptr(tmp, wordSize); 1736 __ movptr(queue_index, tmp); 1737 __ addptr(tmp, buffer); 1738 __ movptr(Address(tmp, 0), card_addr); 1739 __ jmp(enqueued); 1740 1741 __ bind(runtime); 1742 1743 save_live_registers(sasm, 3); 1744 1745 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 1746 1747 restore_live_registers(sasm); 1748 1749 __ bind(enqueued); 1750 __ pop(rdx); 1751 1752 __ bind(done); 1753 __ pop(rcx); 1754 __ pop(rax); 1755 } 1756 break; 1757#endif // INCLUDE_ALL_GCS 1758 1759 case predicate_failed_trap_id: 1760 { 1761 StubFrame f(sasm, "predicate_failed_trap", dont_gc_arguments); 1762 1763 OopMap* map = save_live_registers(sasm, 1); 1764 1765 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap)); 1766 oop_maps = new OopMapSet(); 1767 oop_maps->add_gc_map(call_offset, map); 1768 restore_live_registers(sasm); 1769 __ leave(); 1770 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob(); 1771 assert(deopt_blob != NULL, "deoptimization blob must have been created"); 1772 1773 __ jump(RuntimeAddress(deopt_blob->unpack_with_reexecution())); 1774 } 1775 break; 1776 1777 default: 1778 { StubFrame f(sasm, "unimplemented entry", dont_gc_arguments); 1779 __ movptr(rax, (int)id); 1780 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), rax); 1781 __ should_not_reach_here(); 1782 } 1783 break; 1784 } 1785 return oop_maps; 1786} 1787 1788#undef __ 1789 1790const char *Runtime1::pd_name_for_address(address entry) { 1791 return "<unknown function>"; 1792} 1793