c1_LIRAssembler_x86.cpp revision 3413:e2fe93124108
164562Sgshapiro/* 264562Sgshapiro * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 364562Sgshapiro * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 464562Sgshapiro * 564562Sgshapiro * This code is free software; you can redistribute it and/or modify it 6111823Sgshapiro * under the terms of the GNU General Public License version 2 only, as 764562Sgshapiro * published by the Free Software Foundation. 864562Sgshapiro * 964562Sgshapiro * This code is distributed in the hope that it will be useful, but WITHOUT 1064562Sgshapiro * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1164562Sgshapiro * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1264562Sgshapiro * version 2 for more details (a copy is included in the LICENSE file that 1364562Sgshapiro * accompanied this code). 1464562Sgshapiro * 1564562Sgshapiro * You should have received a copy of the GNU General Public License version 1664562Sgshapiro * 2 along with this work; if not, write to the Free Software Foundation, 17159609Sgshapiro * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 1864562Sgshapiro * 1964562Sgshapiro * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 2064562Sgshapiro * or visit www.oracle.com if you need additional information or have any 2164562Sgshapiro * questions. 2264562Sgshapiro * 2364562Sgshapiro */ 2464562Sgshapiro 2564562Sgshapiro#include "precompiled.hpp" 26159609Sgshapiro#include "asm/assembler.hpp" 27159609Sgshapiro#include "c1/c1_Compilation.hpp" 28159609Sgshapiro#include "c1/c1_LIRAssembler.hpp" 29159609Sgshapiro#include "c1/c1_MacroAssembler.hpp" 30159609Sgshapiro#include "c1/c1_Runtime1.hpp" 31159609Sgshapiro#include "c1/c1_ValueStack.hpp" 32159609Sgshapiro#include "ci/ciArrayKlass.hpp" 33159609Sgshapiro#include "ci/ciInstance.hpp" 34159609Sgshapiro#include "gc_interface/collectedHeap.hpp" 35159609Sgshapiro#include "memory/barrierSet.hpp" 36159609Sgshapiro#include "memory/cardTableModRefBS.hpp" 37159609Sgshapiro#include "nativeInst_x86.hpp" 38159609Sgshapiro#include "oops/objArrayKlass.hpp" 39159609Sgshapiro#include "runtime/sharedRuntime.hpp" 40159609Sgshapiro 41159609Sgshapiro 42159609Sgshapiro// These masks are used to provide 128-bit aligned bitmasks to the XMM 43159609Sgshapiro// instructions, to allow sign-masking or sign-bit flipping. They allow 44159609Sgshapiro// fast versions of NegF/NegD and AbsF/AbsD. 45159609Sgshapiro 46159609Sgshapiro// Note: 'double' and 'long long' have 32-bits alignment on x86. 4780785Sgshapirostatic jlong* double_quadword(jlong *adr, jlong lo, jlong hi) { 48159609Sgshapiro // Use the expression (adr)&(~0xF) to provide 128-bits aligned address 49159609Sgshapiro // of 128-bits operands for SSE instructions. 50159609Sgshapiro jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF))); 51159609Sgshapiro // Store the value to a 128-bits operand. 52159609Sgshapiro operand[0] = lo; 53159609Sgshapiro operand[1] = hi; 54159609Sgshapiro return operand; 55159609Sgshapiro} 56159609Sgshapiro 57159609Sgshapiro// Buffer for 128-bits masks used by SSE instructions. 58159609Sgshapirostatic jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment) 59159609Sgshapiro 60159609Sgshapiro// Static initialization during VM startup. 61159609Sgshapirostatic jlong *float_signmask_pool = double_quadword(&fp_signmask_pool[1*2], CONST64(0x7FFFFFFF7FFFFFFF), CONST64(0x7FFFFFFF7FFFFFFF)); 62159609Sgshapirostatic jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2], CONST64(0x7FFFFFFFFFFFFFFF), CONST64(0x7FFFFFFFFFFFFFFF)); 63159609Sgshapirostatic jlong *float_signflip_pool = double_quadword(&fp_signmask_pool[3*2], CONST64(0x8000000080000000), CONST64(0x8000000080000000)); 64159609Sgshapirostatic jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], CONST64(0x8000000000000000), CONST64(0x8000000000000000)); 65159609Sgshapiro 6680785Sgshapiro 67159609Sgshapiro 68159609SgshapiroNEEDS_CLEANUP // remove this definitions ? 69159609Sgshapiroconst Register IC_Klass = rax; // where the IC klass is cached 70159609Sgshapiroconst Register SYNC_header = rax; // synchronization header 71159609Sgshapiroconst Register SHIFT_count = rcx; // where count for shift operations must be 72159609Sgshapiro 73159609Sgshapiro#define __ _masm-> 74159609Sgshapiro 75159609Sgshapiro 76159609Sgshapirostatic void select_different_registers(Register preserve, 77159609Sgshapiro Register extra, 78159609Sgshapiro Register &tmp1, 79159609Sgshapiro Register &tmp2) { 80159609Sgshapiro if (tmp1 == preserve) { 81159609Sgshapiro assert_different_registers(tmp1, tmp2, extra); 82159609Sgshapiro tmp1 = extra; 83159609Sgshapiro } else if (tmp2 == preserve) { 84159609Sgshapiro assert_different_registers(tmp1, tmp2, extra); 85159609Sgshapiro tmp2 = extra; 86159609Sgshapiro } 87159609Sgshapiro assert_different_registers(preserve, tmp1, tmp2); 88159609Sgshapiro} 89159609Sgshapiro 90159609Sgshapiro 91159609Sgshapiro 92159609Sgshapirostatic void select_different_registers(Register preserve, 93159609Sgshapiro Register extra, 94159609Sgshapiro Register &tmp1, 95159609Sgshapiro Register &tmp2, 96159609Sgshapiro Register &tmp3) { 97159609Sgshapiro if (tmp1 == preserve) { 98159609Sgshapiro assert_different_registers(tmp1, tmp2, tmp3, extra); 99159609Sgshapiro tmp1 = extra; 100159609Sgshapiro } else if (tmp2 == preserve) { 101159609Sgshapiro assert_different_registers(tmp1, tmp2, tmp3, extra); 102159609Sgshapiro tmp2 = extra; 103159609Sgshapiro } else if (tmp3 == preserve) { 104159609Sgshapiro assert_different_registers(tmp1, tmp2, tmp3, extra); 105159609Sgshapiro tmp3 = extra; 106159609Sgshapiro } 107159609Sgshapiro assert_different_registers(preserve, tmp1, tmp2, tmp3); 108159609Sgshapiro} 109159609Sgshapiro 110159609Sgshapiro 111159609Sgshapiro 112159609Sgshapirobool LIR_Assembler::is_small_constant(LIR_Opr opr) { 113159609Sgshapiro if (opr->is_constant()) { 114159609Sgshapiro LIR_Const* constant = opr->as_constant_ptr(); 115159609Sgshapiro switch (constant->type()) { 116159609Sgshapiro case T_INT: { 117159609Sgshapiro return true; 118159609Sgshapiro } 119159609Sgshapiro 120159609Sgshapiro default: 121159609Sgshapiro return false; 122159609Sgshapiro } 123159609Sgshapiro } 124159609Sgshapiro return false; 125159609Sgshapiro} 126159609Sgshapiro 127159609Sgshapiro 128159609SgshapiroLIR_Opr LIR_Assembler::receiverOpr() { 129159609Sgshapiro return FrameMap::receiver_opr; 130159609Sgshapiro} 131159609Sgshapiro 132159609SgshapiroLIR_Opr LIR_Assembler::osrBufferPointer() { 133159609Sgshapiro return FrameMap::as_pointer_opr(receiverOpr()->as_register()); 134159609Sgshapiro} 135159609Sgshapiro 136159609Sgshapiro//--------------fpu register translations----------------------- 137159609Sgshapiro 138159609Sgshapiro 139159609Sgshapiroaddress LIR_Assembler::float_constant(float f) { 140159609Sgshapiro address const_addr = __ float_constant(f); 141159609Sgshapiro if (const_addr == NULL) { 14264562Sgshapiro bailout("const section overflow"); 14364562Sgshapiro return __ code()->consts()->start(); 14464562Sgshapiro } else { 145244833Sgshapiro return const_addr; 146244833Sgshapiro } 147244833Sgshapiro} 148244833Sgshapiro 149244833Sgshapiro 150244833Sgshapiroaddress LIR_Assembler::double_constant(double d) { 151244833Sgshapiro address const_addr = __ double_constant(d); 152244833Sgshapiro if (const_addr == NULL) { 153244833Sgshapiro bailout("const section overflow"); 154244833Sgshapiro return __ code()->consts()->start(); 155244833Sgshapiro } else { 156244833Sgshapiro return const_addr; 157244833Sgshapiro } 158244833Sgshapiro} 159244833Sgshapiro 160244833Sgshapiro 161244833Sgshapirovoid LIR_Assembler::set_24bit_FPU() { 162244833Sgshapiro __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 163244833Sgshapiro} 164244833Sgshapiro 165244833Sgshapirovoid LIR_Assembler::reset_FPU() { 166244833Sgshapiro __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 167244833Sgshapiro} 168244833Sgshapiro 169244833Sgshapirovoid LIR_Assembler::fpop() { 170244833Sgshapiro __ fpop(); 171244833Sgshapiro} 172244833Sgshapiro 173244833Sgshapirovoid LIR_Assembler::fxch(int i) { 174244833Sgshapiro __ fxch(i); 175244833Sgshapiro} 176244833Sgshapiro 177244833Sgshapirovoid LIR_Assembler::fld(int i) { 178244833Sgshapiro __ fld_s(i); 179244833Sgshapiro} 180244833Sgshapiro 181244833Sgshapirovoid LIR_Assembler::ffree(int i) { 182244833Sgshapiro __ ffree(i); 183244833Sgshapiro} 184244833Sgshapiro 185244833Sgshapirovoid LIR_Assembler::breakpoint() { 186244833Sgshapiro __ int3(); 187244833Sgshapiro} 188244833Sgshapiro 189244833Sgshapirovoid LIR_Assembler::push(LIR_Opr opr) { 190244833Sgshapiro if (opr->is_single_cpu()) { 191244833Sgshapiro __ push_reg(opr->as_register()); 192244833Sgshapiro } else if (opr->is_double_cpu()) { 193244833Sgshapiro NOT_LP64(__ push_reg(opr->as_register_hi())); 194244833Sgshapiro __ push_reg(opr->as_register_lo()); 195244833Sgshapiro } else if (opr->is_stack()) { 196244833Sgshapiro __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix())); 197244833Sgshapiro } else if (opr->is_constant()) { 198244833Sgshapiro LIR_Const* const_opr = opr->as_constant_ptr(); 199244833Sgshapiro if (const_opr->type() == T_OBJECT) { 200244833Sgshapiro __ push_oop(const_opr->as_jobject()); 201244833Sgshapiro } else if (const_opr->type() == T_INT) { 202244833Sgshapiro __ push_jint(const_opr->as_jint()); 203244833Sgshapiro } else { 204244833Sgshapiro ShouldNotReachHere(); 205244833Sgshapiro } 206244833Sgshapiro 207244833Sgshapiro } else { 208244833Sgshapiro ShouldNotReachHere(); 209244833Sgshapiro } 210244833Sgshapiro} 211244833Sgshapiro 212244833Sgshapirovoid LIR_Assembler::pop(LIR_Opr opr) { 213244833Sgshapiro if (opr->is_single_cpu()) { 214244833Sgshapiro __ pop_reg(opr->as_register()); 215244833Sgshapiro } else { 216244833Sgshapiro ShouldNotReachHere(); 217244833Sgshapiro } 218244833Sgshapiro} 219244833Sgshapiro 220244833Sgshapirobool LIR_Assembler::is_literal_address(LIR_Address* addr) { 221244833Sgshapiro return addr->base()->is_illegal() && addr->index()->is_illegal(); 222244833Sgshapiro} 223244833Sgshapiro 224244833Sgshapiro//------------------------------------------- 225244833Sgshapiro 226244833SgshapiroAddress LIR_Assembler::as_Address(LIR_Address* addr) { 227244833Sgshapiro return as_Address(addr, rscratch1); 228244833Sgshapiro} 229244833Sgshapiro 230244833SgshapiroAddress LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) { 231244833Sgshapiro if (addr->base()->is_illegal()) { 232244833Sgshapiro assert(addr->index()->is_illegal(), "must be illegal too"); 233244833Sgshapiro AddressLiteral laddr((address)addr->disp(), relocInfo::none); 234244833Sgshapiro if (! __ reachable(laddr)) { 235244833Sgshapiro __ movptr(tmp, laddr.addr()); 236244833Sgshapiro Address res(tmp, 0); 237244833Sgshapiro return res; 238244833Sgshapiro } else { 239244833Sgshapiro return __ as_Address(laddr); 240244833Sgshapiro } 241244833Sgshapiro } 242244833Sgshapiro 243244833Sgshapiro Register base = addr->base()->as_pointer_register(); 244244833Sgshapiro 245244833Sgshapiro if (addr->index()->is_illegal()) { 246244833Sgshapiro return Address( base, addr->disp()); 247244833Sgshapiro } else if (addr->index()->is_cpu_register()) { 248244833Sgshapiro Register index = addr->index()->as_pointer_register(); 249244833Sgshapiro return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp()); 250244833Sgshapiro } else if (addr->index()->is_constant()) { 251244833Sgshapiro intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp(); 252244833Sgshapiro assert(Assembler::is_simm32(addr_offset), "must be"); 253244833Sgshapiro 254244833Sgshapiro return Address(base, addr_offset); 255244833Sgshapiro } else { 256244833Sgshapiro Unimplemented(); 257244833Sgshapiro return Address(); 258244833Sgshapiro } 259244833Sgshapiro} 260244833Sgshapiro 261244833Sgshapiro 262244833SgshapiroAddress LIR_Assembler::as_Address_hi(LIR_Address* addr) { 263244833Sgshapiro Address base = as_Address(addr); 264244833Sgshapiro return Address(base._base, base._index, base._scale, base._disp + BytesPerWord); 265244833Sgshapiro} 266244833Sgshapiro 267244833Sgshapiro 268244833SgshapiroAddress LIR_Assembler::as_Address_lo(LIR_Address* addr) { 269244833Sgshapiro return as_Address(addr); 270244833Sgshapiro} 271244833Sgshapiro 272244833Sgshapiro 273244833Sgshapirovoid LIR_Assembler::osr_entry() { 274244833Sgshapiro offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 275244833Sgshapiro BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 276244833Sgshapiro ValueStack* entry_state = osr_entry->state(); 277244833Sgshapiro int number_of_locks = entry_state->locks_size(); 278244833Sgshapiro 279244833Sgshapiro // we jump here if osr happens with the interpreter 280244833Sgshapiro // state set up to continue at the beginning of the 281244833Sgshapiro // loop that triggered osr - in particular, we have 282244833Sgshapiro // the following registers setup: 283244833Sgshapiro // 284244833Sgshapiro // rcx: osr buffer 285244833Sgshapiro // 286244833Sgshapiro 287244833Sgshapiro // build frame 288223067Sgshapiro ciMethod* m = compilation()->method(); 289223067Sgshapiro __ build_frame(initial_frame_size_in_bytes()); 290223067Sgshapiro 291223067Sgshapiro // OSR buffer is 292223067Sgshapiro // 293223067Sgshapiro // locals[nlocals-1..0] 294223067Sgshapiro // monitors[0..number_of_locks] 295223067Sgshapiro // 296223067Sgshapiro // locals is a direct copy of the interpreter frame so in the osr buffer 297223067Sgshapiro // so first slot in the local array is the last local from the interpreter 298223067Sgshapiro // and last slot is local[0] (receiver) from the interpreter 299223067Sgshapiro // 300223067Sgshapiro // Similarly with locks. The first lock slot in the osr buffer is the nth lock 301223067Sgshapiro // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 302223067Sgshapiro // in the interpreter frame (the method lock if a sync method) 303223067Sgshapiro 304223067Sgshapiro // Initialize monitors in the compiled activation. 305223067Sgshapiro // rcx: pointer to osr buffer 306223067Sgshapiro // 307223067Sgshapiro // All other registers are dead at this point and the locals will be 308223067Sgshapiro // copied into place by code emitted in the IR. 309223067Sgshapiro 310223067Sgshapiro Register OSR_buf = osrBufferPointer()->as_pointer_register(); 311223067Sgshapiro { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 312223067Sgshapiro int monitor_offset = BytesPerWord * method()->max_locals() + 313223067Sgshapiro (2 * BytesPerWord) * (number_of_locks - 1); 314223067Sgshapiro // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 315223067Sgshapiro // the OSR buffer using 2 word entries: first the lock and then 316223067Sgshapiro // the oop. 317223067Sgshapiro for (int i = 0; i < number_of_locks; i++) { 318223067Sgshapiro int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 319223067Sgshapiro#ifdef ASSERT 320223067Sgshapiro // verify the interpreter's monitor has a non-null object 321223067Sgshapiro { 322223067Sgshapiro Label L; 323223067Sgshapiro __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD); 324223067Sgshapiro __ jcc(Assembler::notZero, L); 325223067Sgshapiro __ stop("locked object is NULL"); 326223067Sgshapiro __ bind(L); 327223067Sgshapiro } 328223067Sgshapiro#endif 329223067Sgshapiro __ movptr(rbx, Address(OSR_buf, slot_offset + 0)); 330223067Sgshapiro __ movptr(frame_map()->address_for_monitor_lock(i), rbx); 331223067Sgshapiro __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord)); 332223067Sgshapiro __ movptr(frame_map()->address_for_monitor_object(i), rbx); 333223067Sgshapiro } 334223067Sgshapiro } 335223067Sgshapiro} 336223067Sgshapiro 337223067Sgshapiro 338223067Sgshapiro// inline cache check; done before the frame is built. 339223067Sgshapiroint LIR_Assembler::check_icache() { 340223067Sgshapiro Register receiver = FrameMap::receiver_opr->as_register(); 341223067Sgshapiro Register ic_klass = IC_Klass; 342223067Sgshapiro const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9); 343223067Sgshapiro const bool do_post_padding = VerifyOops || UseCompressedOops; 344223067Sgshapiro if (!do_post_padding) { 345223067Sgshapiro // insert some nops so that the verified entry point is aligned on CodeEntryAlignment 346223067Sgshapiro while ((__ offset() + ic_cmp_size) % CodeEntryAlignment != 0) { 347223067Sgshapiro __ nop(); 348223067Sgshapiro } 349223067Sgshapiro } 350223067Sgshapiro int offset = __ offset(); 351223067Sgshapiro __ inline_cache_check(receiver, IC_Klass); 352223067Sgshapiro assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct"); 353223067Sgshapiro if (do_post_padding) { 354223067Sgshapiro // force alignment after the cache check. 355223067Sgshapiro // It's been verified to be aligned if !VerifyOops 356223067Sgshapiro __ align(CodeEntryAlignment); 357223067Sgshapiro } 358223067Sgshapiro return offset; 359223067Sgshapiro} 360223067Sgshapiro 361223067Sgshapiro 362223067Sgshapirovoid LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) { 363223067Sgshapiro jobject o = NULL; 364223067Sgshapiro PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id); 365223067Sgshapiro __ movoop(reg, o); 366223067Sgshapiro patching_epilog(patch, lir_patch_normal, reg, info); 367223067Sgshapiro} 368223067Sgshapiro 369223067Sgshapiro 370223067Sgshapiro// This specifies the rsp decrement needed to build the frame 371223067Sgshapiroint LIR_Assembler::initial_frame_size_in_bytes() { 372223067Sgshapiro // if rounding, must let FrameMap know! 373223067Sgshapiro 374223067Sgshapiro // The frame_map records size in slots (32bit word) 375223067Sgshapiro 376223067Sgshapiro // subtract two words to account for return address and link 377223067Sgshapiro return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word)) * VMRegImpl::stack_slot_size; 378223067Sgshapiro} 379223067Sgshapiro 380223067Sgshapiro 381223067Sgshapiroint LIR_Assembler::emit_exception_handler() { 382223067Sgshapiro // if the last instruction is a call (typically to do a throw which 383223067Sgshapiro // is coming at the end after block reordering) the return address 384223067Sgshapiro // must still point into the code area in order to avoid assertion 385223067Sgshapiro // failures when searching for the corresponding bci => add a nop 386223067Sgshapiro // (was bug 5/14/1999 - gri) 387223067Sgshapiro __ nop(); 388223067Sgshapiro 389223067Sgshapiro // generate code for exception handler 390223067Sgshapiro address handler_base = __ start_a_stub(exception_handler_size); 391223067Sgshapiro if (handler_base == NULL) { 392223067Sgshapiro // not enough space left for the handler 393223067Sgshapiro bailout("exception handler overflow"); 394223067Sgshapiro return -1; 395223067Sgshapiro } 396244833Sgshapiro 397223067Sgshapiro int offset = code_offset(); 398223067Sgshapiro 399223067Sgshapiro // the exception oop and pc are in rax, and rdx 400223067Sgshapiro // no other registers need to be preserved, so invalidate them 401223067Sgshapiro __ invalidate_registers(false, true, true, false, true, true); 402223067Sgshapiro 403223067Sgshapiro // check that there is really an exception 404223067Sgshapiro __ verify_not_null_oop(rax); 405223067Sgshapiro 406223067Sgshapiro // search an exception handler (rax: exception oop, rdx: throwing pc) 407223067Sgshapiro __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id))); 408223067Sgshapiro __ should_not_reach_here(); 409223067Sgshapiro guarantee(code_offset() - offset <= exception_handler_size, "overflow"); 410223067Sgshapiro __ end_a_stub(); 411223067Sgshapiro 412223067Sgshapiro return offset; 413223067Sgshapiro} 414223067Sgshapiro 415223067Sgshapiro 416223067Sgshapiro// Emit the code to remove the frame from the stack in the exception 417223067Sgshapiro// unwind path. 418223067Sgshapiroint LIR_Assembler::emit_unwind_handler() { 419223067Sgshapiro#ifndef PRODUCT 420223067Sgshapiro if (CommentedAssembly) { 421223067Sgshapiro _masm->block_comment("Unwind handler"); 422223067Sgshapiro } 423223067Sgshapiro#endif 424223067Sgshapiro 425223067Sgshapiro int offset = code_offset(); 426223067Sgshapiro 427223067Sgshapiro // Fetch the exception from TLS and clear out exception related thread state 428223067Sgshapiro __ get_thread(rsi); 429223067Sgshapiro __ movptr(rax, Address(rsi, JavaThread::exception_oop_offset())); 430223067Sgshapiro __ movptr(Address(rsi, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD); 431223067Sgshapiro __ movptr(Address(rsi, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD); 432223067Sgshapiro 433223067Sgshapiro __ bind(_unwind_handler_entry); 434223067Sgshapiro __ verify_not_null_oop(rax); 435223067Sgshapiro if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 436223067Sgshapiro __ mov(rsi, rax); // Preserve the exception 437223067Sgshapiro } 438223067Sgshapiro 439223067Sgshapiro // Preform needed unlocking 440223067Sgshapiro MonitorExitStub* stub = NULL; 441223067Sgshapiro if (method()->is_synchronized()) { 442223067Sgshapiro monitor_address(0, FrameMap::rax_opr); 443223067Sgshapiro stub = new MonitorExitStub(FrameMap::rax_opr, true, 0); 444223067Sgshapiro __ unlock_object(rdi, rbx, rax, *stub->entry()); 445223067Sgshapiro __ bind(*stub->continuation()); 446223067Sgshapiro } 447223067Sgshapiro 448223067Sgshapiro if (compilation()->env()->dtrace_method_probes()) { 449223067Sgshapiro __ get_thread(rax); 450223067Sgshapiro __ movptr(Address(rsp, 0), rax); 451223067Sgshapiro __ movoop(Address(rsp, sizeof(void*)), method()->constant_encoding()); 452223067Sgshapiro __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit))); 453223067Sgshapiro } 454223067Sgshapiro 455223067Sgshapiro if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 456223067Sgshapiro __ mov(rax, rsi); // Restore the exception 457223067Sgshapiro } 458223067Sgshapiro 459223067Sgshapiro // remove the activation and dispatch to the unwind handler 460223067Sgshapiro __ remove_frame(initial_frame_size_in_bytes()); 461223067Sgshapiro __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id))); 462223067Sgshapiro 463223067Sgshapiro // Emit the slow path assembly 464223067Sgshapiro if (stub != NULL) { 465223067Sgshapiro stub->emit_code(this); 466223067Sgshapiro } 467223067Sgshapiro 468223067Sgshapiro return offset; 469223067Sgshapiro} 470223067Sgshapiro 471223067Sgshapiro 472223067Sgshapiroint LIR_Assembler::emit_deopt_handler() { 473223067Sgshapiro // if the last instruction is a call (typically to do a throw which 474223067Sgshapiro // is coming at the end after block reordering) the return address 475223067Sgshapiro // must still point into the code area in order to avoid assertion 476223067Sgshapiro // failures when searching for the corresponding bci => add a nop 477223067Sgshapiro // (was bug 5/14/1999 - gri) 478223067Sgshapiro __ nop(); 479223067Sgshapiro 480223067Sgshapiro // generate code for exception handler 481223067Sgshapiro address handler_base = __ start_a_stub(deopt_handler_size); 482223067Sgshapiro if (handler_base == NULL) { 483223067Sgshapiro // not enough space left for the handler 484223067Sgshapiro bailout("deopt handler overflow"); 485223067Sgshapiro return -1; 486223067Sgshapiro } 487223067Sgshapiro 488223067Sgshapiro int offset = code_offset(); 489223067Sgshapiro InternalAddress here(__ pc()); 490223067Sgshapiro 491223067Sgshapiro __ pushptr(here.addr()); 492223067Sgshapiro __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack())); 493223067Sgshapiro guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); 494223067Sgshapiro __ end_a_stub(); 495223067Sgshapiro 496223067Sgshapiro return offset; 497223067Sgshapiro} 498223067Sgshapiro 499223067Sgshapiro 500223067Sgshapiro// This is the fast version of java.lang.String.compare; it has not 501223067Sgshapiro// OSR-entry and therefore, we generate a slow version for OSR's 502223067Sgshapirovoid LIR_Assembler::emit_string_compare(LIR_Opr arg0, LIR_Opr arg1, LIR_Opr dst, CodeEmitInfo* info) { 503223067Sgshapiro __ movptr (rbx, rcx); // receiver is in rcx 504203004Sgshapiro __ movptr (rax, arg1->as_register()); 505203004Sgshapiro 506203004Sgshapiro // Get addresses of first characters from both Strings 507203004Sgshapiro __ load_heap_oop(rsi, Address(rax, java_lang_String::value_offset_in_bytes())); 508203004Sgshapiro if (java_lang_String::has_offset_field()) { 509203004Sgshapiro __ movptr (rcx, Address(rax, java_lang_String::offset_offset_in_bytes())); 510203004Sgshapiro __ movl (rax, Address(rax, java_lang_String::count_offset_in_bytes())); 511203004Sgshapiro __ lea (rsi, Address(rsi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 512203004Sgshapiro } else { 513203004Sgshapiro __ movl (rax, Address(rsi, arrayOopDesc::length_offset_in_bytes())); 514203004Sgshapiro __ lea (rsi, Address(rsi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 515203004Sgshapiro } 516203004Sgshapiro 517203004Sgshapiro // rbx, may be NULL 518203004Sgshapiro add_debug_info_for_null_check_here(info); 519203004Sgshapiro __ load_heap_oop(rdi, Address(rbx, java_lang_String::value_offset_in_bytes())); 520203004Sgshapiro if (java_lang_String::has_offset_field()) { 521203004Sgshapiro __ movptr (rcx, Address(rbx, java_lang_String::offset_offset_in_bytes())); 522203004Sgshapiro __ movl (rbx, Address(rbx, java_lang_String::count_offset_in_bytes())); 523203004Sgshapiro __ lea (rdi, Address(rdi, rcx, Address::times_2, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 524203004Sgshapiro } else { 525203004Sgshapiro __ movl (rbx, Address(rdi, arrayOopDesc::length_offset_in_bytes())); 526203004Sgshapiro __ lea (rdi, Address(rdi, arrayOopDesc::base_offset_in_bytes(T_CHAR))); 527203004Sgshapiro } 528203004Sgshapiro 529203004Sgshapiro // compute minimum length (in rax) and difference of lengths (on top of stack) 530203004Sgshapiro __ mov (rcx, rbx); 531203004Sgshapiro __ subptr(rbx, rax); // subtract lengths 532203004Sgshapiro __ push (rbx); // result 533203004Sgshapiro __ cmov (Assembler::lessEqual, rax, rcx); 534203004Sgshapiro 535203004Sgshapiro // is minimum length 0? 536203004Sgshapiro Label noLoop, haveResult; 537203004Sgshapiro __ testptr (rax, rax); 538203004Sgshapiro __ jcc (Assembler::zero, noLoop); 539203004Sgshapiro 540203004Sgshapiro // compare first characters 541203004Sgshapiro __ load_unsigned_short(rcx, Address(rdi, 0)); 542203004Sgshapiro __ load_unsigned_short(rbx, Address(rsi, 0)); 543203004Sgshapiro __ subl(rcx, rbx); 544203004Sgshapiro __ jcc(Assembler::notZero, haveResult); 545203004Sgshapiro // starting loop 546203004Sgshapiro __ decrement(rax); // we already tested index: skip one 547203004Sgshapiro __ jcc(Assembler::zero, noLoop); 548203004Sgshapiro 549203004Sgshapiro // set rsi.edi to the end of the arrays (arrays have same length) 550203004Sgshapiro // negate the index 551203004Sgshapiro 552203004Sgshapiro __ lea(rsi, Address(rsi, rax, Address::times_2, type2aelembytes(T_CHAR))); 553203004Sgshapiro __ lea(rdi, Address(rdi, rax, Address::times_2, type2aelembytes(T_CHAR))); 554203004Sgshapiro __ negptr(rax); 555203004Sgshapiro 556203004Sgshapiro // compare the strings in a loop 557203004Sgshapiro 558203004Sgshapiro Label loop; 559203004Sgshapiro __ align(wordSize); 560203004Sgshapiro __ bind(loop); 561203004Sgshapiro __ load_unsigned_short(rcx, Address(rdi, rax, Address::times_2, 0)); 562203004Sgshapiro __ load_unsigned_short(rbx, Address(rsi, rax, Address::times_2, 0)); 563203004Sgshapiro __ subl(rcx, rbx); 564203004Sgshapiro __ jcc(Assembler::notZero, haveResult); 565203004Sgshapiro __ increment(rax); 566203004Sgshapiro __ jcc(Assembler::notZero, loop); 567203004Sgshapiro 568203004Sgshapiro // strings are equal up to min length 569203004Sgshapiro 570203004Sgshapiro __ bind(noLoop); 571203004Sgshapiro __ pop(rax); 572203004Sgshapiro return_op(LIR_OprFact::illegalOpr); 573203004Sgshapiro 574203004Sgshapiro __ bind(haveResult); 575203004Sgshapiro // leave instruction is going to discard the TOS value 576203004Sgshapiro __ mov (rax, rcx); // result of call is in rax, 577182352Sgshapiro} 578182352Sgshapiro 579182352Sgshapiro 580182352Sgshapirovoid LIR_Assembler::return_op(LIR_Opr result) { 581182352Sgshapiro assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,"); 582182352Sgshapiro if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) { 583182352Sgshapiro assert(result->fpu() == 0, "result must already be on TOS"); 584182352Sgshapiro } 585182352Sgshapiro 586182352Sgshapiro // Pop the stack before the safepoint code 587182352Sgshapiro __ remove_frame(initial_frame_size_in_bytes()); 588182352Sgshapiro 589182352Sgshapiro bool result_is_oop = result->is_valid() ? result->is_oop() : false; 590182352Sgshapiro 591182352Sgshapiro // Note: we do not need to round double result; float result has the right precision 592182352Sgshapiro // the poll sets the condition code, but no data registers 593182352Sgshapiro AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 594182352Sgshapiro relocInfo::poll_return_type); 595182352Sgshapiro 596182352Sgshapiro if (Assembler::is_polling_page_far()) { 597182352Sgshapiro __ lea(rscratch1, polling_page); 598182352Sgshapiro __ relocate(relocInfo::poll_return_type); 599182352Sgshapiro __ testl(rax, Address(rscratch1, 0)); 600182352Sgshapiro } else { 601182352Sgshapiro __ testl(rax, polling_page); 602182352Sgshapiro } 603182352Sgshapiro __ ret(0); 604182352Sgshapiro} 605182352Sgshapiro 606182352Sgshapiro 607182352Sgshapiroint LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 608182352Sgshapiro AddressLiteral polling_page(os::get_polling_page() + (SafepointPollOffset % os::vm_page_size()), 609182352Sgshapiro relocInfo::poll_type); 610182352Sgshapiro guarantee(info != NULL, "Shouldn't be NULL"); 611182352Sgshapiro int offset = __ offset(); 612182352Sgshapiro if (Assembler::is_polling_page_far()) { 613182352Sgshapiro __ lea(rscratch1, polling_page); 614182352Sgshapiro offset = __ offset(); 615182352Sgshapiro add_debug_info_for_branch(info); 616182352Sgshapiro __ testl(rax, Address(rscratch1, 0)); 617182352Sgshapiro } else { 618182352Sgshapiro add_debug_info_for_branch(info); 619182352Sgshapiro __ testl(rax, polling_page); 620182352Sgshapiro } 621182352Sgshapiro return offset; 622182352Sgshapiro} 623182352Sgshapiro 624182352Sgshapiro 625182352Sgshapirovoid LIR_Assembler::move_regs(Register from_reg, Register to_reg) { 626182352Sgshapiro if (from_reg != to_reg) __ mov(to_reg, from_reg); 627182352Sgshapiro} 628182352Sgshapiro 629182352Sgshapirovoid LIR_Assembler::swap_reg(Register a, Register b) { 630182352Sgshapiro __ xchgptr(a, b); 631182352Sgshapiro} 632182352Sgshapiro 633182352Sgshapiro 634182352Sgshapirovoid LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 635182352Sgshapiro assert(src->is_constant(), "should not call otherwise"); 636182352Sgshapiro assert(dest->is_register(), "should not call otherwise"); 637182352Sgshapiro LIR_Const* c = src->as_constant_ptr(); 638182352Sgshapiro 639182352Sgshapiro switch (c->type()) { 640168515Sgshapiro case T_INT: { 641168515Sgshapiro assert(patch_code == lir_patch_none, "no patching handled here"); 642168515Sgshapiro __ movl(dest->as_register(), c->as_jint()); 643168515Sgshapiro break; 644168515Sgshapiro } 645168515Sgshapiro 646168515Sgshapiro case T_ADDRESS: { 647168515Sgshapiro assert(patch_code == lir_patch_none, "no patching handled here"); 648168515Sgshapiro __ movptr(dest->as_register(), c->as_jint()); 649168515Sgshapiro break; 650168515Sgshapiro } 651168515Sgshapiro 652168515Sgshapiro case T_LONG: { 653168515Sgshapiro assert(patch_code == lir_patch_none, "no patching handled here"); 654168515Sgshapiro#ifdef _LP64 655168515Sgshapiro __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong()); 656168515Sgshapiro#else 657168515Sgshapiro __ movptr(dest->as_register_lo(), c->as_jint_lo()); 658168515Sgshapiro __ movptr(dest->as_register_hi(), c->as_jint_hi()); 659168515Sgshapiro#endif // _LP64 660168515Sgshapiro break; 661168515Sgshapiro } 662168515Sgshapiro 663168515Sgshapiro case T_OBJECT: { 664168515Sgshapiro if (patch_code != lir_patch_none) { 665168515Sgshapiro jobject2reg_with_patching(dest->as_register(), info); 666168515Sgshapiro } else { 667168515Sgshapiro __ movoop(dest->as_register(), c->as_jobject()); 668168515Sgshapiro } 669168515Sgshapiro break; 670168515Sgshapiro } 671168515Sgshapiro 672168515Sgshapiro case T_FLOAT: { 673168515Sgshapiro if (dest->is_single_xmm()) { 674168515Sgshapiro if (c->is_zero_float()) { 675168515Sgshapiro __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg()); 676168515Sgshapiro } else { 677168515Sgshapiro __ movflt(dest->as_xmm_float_reg(), 678168515Sgshapiro InternalAddress(float_constant(c->as_jfloat()))); 679168515Sgshapiro } 680168515Sgshapiro } else { 681168515Sgshapiro assert(dest->is_single_fpu(), "must be"); 682168515Sgshapiro assert(dest->fpu_regnr() == 0, "dest must be TOS"); 683168515Sgshapiro if (c->is_zero_float()) { 684168515Sgshapiro __ fldz(); 685168515Sgshapiro } else if (c->is_one_float()) { 686168515Sgshapiro __ fld1(); 687168515Sgshapiro } else { 688168515Sgshapiro __ fld_s (InternalAddress(float_constant(c->as_jfloat()))); 689168515Sgshapiro } 690168515Sgshapiro } 691168515Sgshapiro break; 692168515Sgshapiro } 693168515Sgshapiro 694168515Sgshapiro case T_DOUBLE: { 695168515Sgshapiro if (dest->is_double_xmm()) { 696168515Sgshapiro if (c->is_zero_double()) { 697168515Sgshapiro __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg()); 698168515Sgshapiro } else { 699168515Sgshapiro __ movdbl(dest->as_xmm_double_reg(), 700168515Sgshapiro InternalAddress(double_constant(c->as_jdouble()))); 701168515Sgshapiro } 702168515Sgshapiro } else { 703168515Sgshapiro assert(dest->is_double_fpu(), "must be"); 704168515Sgshapiro assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 705168515Sgshapiro if (c->is_zero_double()) { 706168515Sgshapiro __ fldz(); 707168515Sgshapiro } else if (c->is_one_double()) { 708168515Sgshapiro __ fld1(); 709168515Sgshapiro } else { 710168515Sgshapiro __ fld_d (InternalAddress(double_constant(c->as_jdouble()))); 711168515Sgshapiro } 712168515Sgshapiro } 713168515Sgshapiro break; 714168515Sgshapiro } 715168515Sgshapiro 716157001Sgshapiro default: 717157001Sgshapiro ShouldNotReachHere(); 718157001Sgshapiro } 719157001Sgshapiro} 720157001Sgshapiro 721159609Sgshapirovoid LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 722157001Sgshapiro assert(src->is_constant(), "should not call otherwise"); 723157001Sgshapiro assert(dest->is_stack(), "should not call otherwise"); 724157001Sgshapiro LIR_Const* c = src->as_constant_ptr(); 725157001Sgshapiro 726157001Sgshapiro switch (c->type()) { 727157001Sgshapiro case T_INT: // fall through 728157001Sgshapiro case T_FLOAT: 729157001Sgshapiro __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 730157001Sgshapiro break; 731157001Sgshapiro 732157001Sgshapiro case T_ADDRESS: 733157001Sgshapiro __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits()); 734157001Sgshapiro break; 735157001Sgshapiro 736157001Sgshapiro case T_OBJECT: 737157001Sgshapiro __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject()); 738157001Sgshapiro break; 739157001Sgshapiro 740157001Sgshapiro case T_LONG: // fall through 741157001Sgshapiro case T_DOUBLE: 742157001Sgshapiro#ifdef _LP64 743157001Sgshapiro __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 744157001Sgshapiro lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits()); 745157001Sgshapiro#else 746157001Sgshapiro __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 747157001Sgshapiro lo_word_offset_in_bytes), c->as_jint_lo_bits()); 748157001Sgshapiro __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(), 749157001Sgshapiro hi_word_offset_in_bytes), c->as_jint_hi_bits()); 750157001Sgshapiro#endif // _LP64 751157001Sgshapiro break; 752157001Sgshapiro 753157001Sgshapiro default: 754157001Sgshapiro ShouldNotReachHere(); 755157001Sgshapiro } 756157001Sgshapiro} 757157001Sgshapiro 758157001Sgshapirovoid LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 759157001Sgshapiro assert(src->is_constant(), "should not call otherwise"); 760157001Sgshapiro assert(dest->is_address(), "should not call otherwise"); 761157001Sgshapiro LIR_Const* c = src->as_constant_ptr(); 762157001Sgshapiro LIR_Address* addr = dest->as_address_ptr(); 763157001Sgshapiro 764157001Sgshapiro int null_check_here = code_offset(); 765157001Sgshapiro switch (type) { 766157001Sgshapiro case T_INT: // fall through 767157001Sgshapiro case T_FLOAT: 768157001Sgshapiro __ movl(as_Address(addr), c->as_jint_bits()); 769157001Sgshapiro break; 770157001Sgshapiro 771157001Sgshapiro case T_ADDRESS: 772157001Sgshapiro __ movptr(as_Address(addr), c->as_jint_bits()); 773157001Sgshapiro break; 774157001Sgshapiro 775157001Sgshapiro case T_OBJECT: // fall through 776157001Sgshapiro case T_ARRAY: 777157001Sgshapiro if (c->as_jobject() == NULL) { 778157001Sgshapiro if (UseCompressedOops && !wide) { 779157001Sgshapiro __ movl(as_Address(addr), (int32_t)NULL_WORD); 780157001Sgshapiro } else { 781157001Sgshapiro __ movptr(as_Address(addr), NULL_WORD); 782157001Sgshapiro } 783157001Sgshapiro } else { 784157001Sgshapiro if (is_literal_address(addr)) { 785157001Sgshapiro ShouldNotReachHere(); 786157001Sgshapiro __ movoop(as_Address(addr, noreg), c->as_jobject()); 787157001Sgshapiro } else { 788157001Sgshapiro#ifdef _LP64 789157001Sgshapiro __ movoop(rscratch1, c->as_jobject()); 790157001Sgshapiro if (UseCompressedOops && !wide) { 791157001Sgshapiro __ encode_heap_oop(rscratch1); 792157001Sgshapiro null_check_here = code_offset(); 793141858Sgshapiro __ movl(as_Address_lo(addr), rscratch1); 794141858Sgshapiro } else { 795141858Sgshapiro null_check_here = code_offset(); 796141858Sgshapiro __ movptr(as_Address_lo(addr), rscratch1); 797141858Sgshapiro } 798159609Sgshapiro#else 799141858Sgshapiro __ movoop(as_Address(addr), c->as_jobject()); 800141858Sgshapiro#endif 801141858Sgshapiro } 802141858Sgshapiro } 803141858Sgshapiro break; 804141858Sgshapiro 805141858Sgshapiro case T_LONG: // fall through 806141858Sgshapiro case T_DOUBLE: 807141858Sgshapiro#ifdef _LP64 808141858Sgshapiro if (is_literal_address(addr)) { 809141858Sgshapiro ShouldNotReachHere(); 810141858Sgshapiro __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits()); 811141858Sgshapiro } else { 812141858Sgshapiro __ movptr(r10, (intptr_t)c->as_jlong_bits()); 813141858Sgshapiro null_check_here = code_offset(); 814141858Sgshapiro __ movptr(as_Address_lo(addr), r10); 815141858Sgshapiro } 816141858Sgshapiro#else 817141858Sgshapiro // Always reachable in 32bit so this doesn't produce useless move literal 818141858Sgshapiro __ movptr(as_Address_hi(addr), c->as_jint_hi_bits()); 819141858Sgshapiro __ movptr(as_Address_lo(addr), c->as_jint_lo_bits()); 820141858Sgshapiro#endif // _LP64 821141858Sgshapiro break; 822141858Sgshapiro 823141858Sgshapiro case T_BOOLEAN: // fall through 824141858Sgshapiro case T_BYTE: 825141858Sgshapiro __ movb(as_Address(addr), c->as_jint() & 0xFF); 826141858Sgshapiro break; 827141858Sgshapiro 828141858Sgshapiro case T_CHAR: // fall through 829141858Sgshapiro case T_SHORT: 830141858Sgshapiro __ movw(as_Address(addr), c->as_jint() & 0xFFFF); 831141858Sgshapiro break; 832141858Sgshapiro 833141858Sgshapiro default: 834141858Sgshapiro ShouldNotReachHere(); 835141858Sgshapiro }; 836141858Sgshapiro 837141858Sgshapiro if (info != NULL) { 838141858Sgshapiro add_debug_info_for_null_check(null_check_here, info); 839141858Sgshapiro } 840141858Sgshapiro} 841141858Sgshapiro 842141858Sgshapiro 843141858Sgshapirovoid LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) { 844141858Sgshapiro assert(src->is_register(), "should not call otherwise"); 845159609Sgshapiro assert(dest->is_register(), "should not call otherwise"); 846159609Sgshapiro 847159609Sgshapiro // move between cpu-registers 848159609Sgshapiro if (dest->is_single_cpu()) { 849159609Sgshapiro#ifdef _LP64 850159609Sgshapiro if (src->type() == T_LONG) { 851159609Sgshapiro // Can do LONG -> OBJECT 852159609Sgshapiro move_regs(src->as_register_lo(), dest->as_register()); 853159609Sgshapiro return; 854159609Sgshapiro } 855159609Sgshapiro#endif 856159609Sgshapiro assert(src->is_single_cpu(), "must match"); 857159609Sgshapiro if (src->type() == T_OBJECT) { 858159609Sgshapiro __ verify_oop(src->as_register()); 859159609Sgshapiro } 860159609Sgshapiro move_regs(src->as_register(), dest->as_register()); 861159609Sgshapiro 862159609Sgshapiro } else if (dest->is_double_cpu()) { 863159609Sgshapiro#ifdef _LP64 864159609Sgshapiro if (src->type() == T_OBJECT || src->type() == T_ARRAY) { 865159609Sgshapiro // Surprising to me but we can see move of a long to t_object 866159609Sgshapiro __ verify_oop(src->as_register()); 867159609Sgshapiro move_regs(src->as_register(), dest->as_register_lo()); 868159609Sgshapiro return; 869159609Sgshapiro } 870159609Sgshapiro#endif 871159609Sgshapiro assert(src->is_double_cpu(), "must match"); 872159609Sgshapiro Register f_lo = src->as_register_lo(); 873159609Sgshapiro Register f_hi = src->as_register_hi(); 874159609Sgshapiro Register t_lo = dest->as_register_lo(); 875159609Sgshapiro Register t_hi = dest->as_register_hi(); 876159609Sgshapiro#ifdef _LP64 877159609Sgshapiro assert(f_hi == f_lo, "must be same"); 878159609Sgshapiro assert(t_hi == t_lo, "must be same"); 879159609Sgshapiro move_regs(f_lo, t_lo); 880159609Sgshapiro#else 881159609Sgshapiro assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation"); 882159609Sgshapiro 883159609Sgshapiro 884159609Sgshapiro if (f_lo == t_hi && f_hi == t_lo) { 885159609Sgshapiro swap_reg(f_lo, f_hi); 886141858Sgshapiro } else if (f_hi == t_lo) { 887141858Sgshapiro assert(f_lo != t_hi, "overwriting register"); 888141858Sgshapiro move_regs(f_hi, t_hi); 889125820Sgshapiro move_regs(f_lo, t_lo); 890125820Sgshapiro } else { 891125820Sgshapiro assert(f_hi != t_lo, "overwriting register"); 892125820Sgshapiro move_regs(f_lo, t_lo); 893125820Sgshapiro move_regs(f_hi, t_hi); 894159609Sgshapiro } 895125820Sgshapiro#endif // LP64 896125820Sgshapiro 897125820Sgshapiro // special moves from fpu-register to xmm-register 898125820Sgshapiro // necessary for method results 899125820Sgshapiro } else if (src->is_single_xmm() && !dest->is_single_xmm()) { 900125820Sgshapiro __ movflt(Address(rsp, 0), src->as_xmm_float_reg()); 901125820Sgshapiro __ fld_s(Address(rsp, 0)); 902125820Sgshapiro } else if (src->is_double_xmm() && !dest->is_double_xmm()) { 903125820Sgshapiro __ movdbl(Address(rsp, 0), src->as_xmm_double_reg()); 904125820Sgshapiro __ fld_d(Address(rsp, 0)); 905125820Sgshapiro } else if (dest->is_single_xmm() && !src->is_single_xmm()) { 906125820Sgshapiro __ fstp_s(Address(rsp, 0)); 907125820Sgshapiro __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0)); 908125820Sgshapiro } else if (dest->is_double_xmm() && !src->is_double_xmm()) { 909125820Sgshapiro __ fstp_d(Address(rsp, 0)); 910125820Sgshapiro __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0)); 911125820Sgshapiro 912125820Sgshapiro // move between xmm-registers 913125820Sgshapiro } else if (dest->is_single_xmm()) { 914125820Sgshapiro assert(src->is_single_xmm(), "must match"); 915125820Sgshapiro __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg()); 916125820Sgshapiro } else if (dest->is_double_xmm()) { 917125820Sgshapiro assert(src->is_double_xmm(), "must match"); 918125820Sgshapiro __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg()); 919125820Sgshapiro 920125820Sgshapiro // move between fpu-registers (no instruction necessary because of fpu-stack) 921125820Sgshapiro } else if (dest->is_single_fpu() || dest->is_double_fpu()) { 922125820Sgshapiro assert(src->is_single_fpu() || src->is_double_fpu(), "must match"); 923125820Sgshapiro assert(src->fpu() == dest->fpu(), "currently should be nothing to do"); 924125820Sgshapiro } else { 925125820Sgshapiro ShouldNotReachHere(); 926125820Sgshapiro } 927125820Sgshapiro} 928125820Sgshapiro 929125820Sgshapirovoid LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 930125820Sgshapiro assert(src->is_register(), "should not call otherwise"); 931125820Sgshapiro assert(dest->is_stack(), "should not call otherwise"); 932125820Sgshapiro 933125820Sgshapiro if (src->is_single_cpu()) { 934125820Sgshapiro Address dst = frame_map()->address_for_slot(dest->single_stack_ix()); 935125820Sgshapiro if (type == T_OBJECT || type == T_ARRAY) { 936125820Sgshapiro __ verify_oop(src->as_register()); 937125820Sgshapiro __ movptr (dst, src->as_register()); 938159609Sgshapiro } else { 939159609Sgshapiro __ movl (dst, src->as_register()); 940159609Sgshapiro } 941159609Sgshapiro 942159609Sgshapiro } else if (src->is_double_cpu()) { 943159609Sgshapiro Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes); 944159609Sgshapiro Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes); 945159609Sgshapiro __ movptr (dstLO, src->as_register_lo()); 946159609Sgshapiro NOT_LP64(__ movptr (dstHI, src->as_register_hi())); 947159609Sgshapiro 948159609Sgshapiro } else if (src->is_single_xmm()) { 949159609Sgshapiro Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 950159609Sgshapiro __ movflt(dst_addr, src->as_xmm_float_reg()); 951159609Sgshapiro 952125820Sgshapiro } else if (src->is_double_xmm()) { 953159609Sgshapiro Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 954159609Sgshapiro __ movdbl(dst_addr, src->as_xmm_double_reg()); 955159609Sgshapiro 956159609Sgshapiro } else if (src->is_single_fpu()) { 957159609Sgshapiro assert(src->fpu_regnr() == 0, "argument must be on TOS"); 958159609Sgshapiro Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix()); 959159609Sgshapiro if (pop_fpu_stack) __ fstp_s (dst_addr); 960159609Sgshapiro else __ fst_s (dst_addr); 961159609Sgshapiro 962159609Sgshapiro } else if (src->is_double_fpu()) { 963159609Sgshapiro assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 964159609Sgshapiro Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix()); 965159609Sgshapiro if (pop_fpu_stack) __ fstp_d (dst_addr); 966159609Sgshapiro else __ fst_d (dst_addr); 967159609Sgshapiro 968159609Sgshapiro } else { 969159609Sgshapiro ShouldNotReachHere(); 970159609Sgshapiro } 971159609Sgshapiro} 972159609Sgshapiro 973159609Sgshapiro 974159609Sgshapirovoid LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) { 975159609Sgshapiro LIR_Address* to_addr = dest->as_address_ptr(); 976159609Sgshapiro PatchingStub* patch = NULL; 977125820Sgshapiro Register compressed_src = rscratch1; 978125820Sgshapiro 979125820Sgshapiro if (type == T_ARRAY || type == T_OBJECT) { 980111823Sgshapiro __ verify_oop(src->as_register()); 981111823Sgshapiro#ifdef _LP64 982111823Sgshapiro if (UseCompressedOops && !wide) { 983111823Sgshapiro __ movptr(compressed_src, src->as_register()); 984111823Sgshapiro __ encode_heap_oop(compressed_src); 985159609Sgshapiro } 986111823Sgshapiro#endif 987111823Sgshapiro } 988111823Sgshapiro 989111823Sgshapiro if (patch_code != lir_patch_none) { 990111823Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 991111823Sgshapiro Address toa = as_Address(to_addr); 992111823Sgshapiro assert(toa.disp() != 0, "must have"); 993111823Sgshapiro } 994111823Sgshapiro 995111823Sgshapiro int null_check_here = code_offset(); 996111823Sgshapiro switch (type) { 997111823Sgshapiro case T_FLOAT: { 998111823Sgshapiro if (src->is_single_xmm()) { 999111823Sgshapiro __ movflt(as_Address(to_addr), src->as_xmm_float_reg()); 1000111823Sgshapiro } else { 1001111823Sgshapiro assert(src->is_single_fpu(), "must be"); 1002111823Sgshapiro assert(src->fpu_regnr() == 0, "argument must be on TOS"); 1003111823Sgshapiro if (pop_fpu_stack) __ fstp_s(as_Address(to_addr)); 1004111823Sgshapiro else __ fst_s (as_Address(to_addr)); 1005111823Sgshapiro } 1006111823Sgshapiro break; 1007111823Sgshapiro } 1008111823Sgshapiro 1009111823Sgshapiro case T_DOUBLE: { 1010111823Sgshapiro if (src->is_double_xmm()) { 1011111823Sgshapiro __ movdbl(as_Address(to_addr), src->as_xmm_double_reg()); 1012111823Sgshapiro } else { 1013111823Sgshapiro assert(src->is_double_fpu(), "must be"); 1014111823Sgshapiro assert(src->fpu_regnrLo() == 0, "argument must be on TOS"); 1015111823Sgshapiro if (pop_fpu_stack) __ fstp_d(as_Address(to_addr)); 1016111823Sgshapiro else __ fst_d (as_Address(to_addr)); 1017111823Sgshapiro } 1018111823Sgshapiro break; 1019111823Sgshapiro } 1020111823Sgshapiro 1021111823Sgshapiro case T_ARRAY: // fall through 1022159609Sgshapiro case T_OBJECT: // fall through 1023159609Sgshapiro if (UseCompressedOops && !wide) { 1024159609Sgshapiro __ movl(as_Address(to_addr), compressed_src); 1025159609Sgshapiro } else { 1026159609Sgshapiro __ movptr(as_Address(to_addr), src->as_register()); 1027159609Sgshapiro } 1028159609Sgshapiro break; 1029159609Sgshapiro case T_ADDRESS: 1030159609Sgshapiro __ movptr(as_Address(to_addr), src->as_register()); 1031159609Sgshapiro break; 1032159609Sgshapiro case T_INT: 1033159609Sgshapiro __ movl(as_Address(to_addr), src->as_register()); 1034159609Sgshapiro break; 1035159609Sgshapiro 1036159609Sgshapiro case T_LONG: { 1037159609Sgshapiro Register from_lo = src->as_register_lo(); 1038159609Sgshapiro Register from_hi = src->as_register_hi(); 1039159609Sgshapiro#ifdef _LP64 1040159609Sgshapiro __ movptr(as_Address_lo(to_addr), from_lo); 1041159609Sgshapiro#else 1042159609Sgshapiro Register base = to_addr->base()->as_register(); 1043159609Sgshapiro Register index = noreg; 1044159609Sgshapiro if (to_addr->index()->is_register()) { 1045159609Sgshapiro index = to_addr->index()->as_register(); 1046159609Sgshapiro } 1047159609Sgshapiro if (base == from_lo || index == from_lo) { 1048159609Sgshapiro assert(base != from_hi, "can't be"); 1049159609Sgshapiro assert(index == noreg || (index != base && index != from_hi), "can't handle this"); 1050159609Sgshapiro __ movl(as_Address_hi(to_addr), from_hi); 1051159609Sgshapiro if (patch != NULL) { 1052159609Sgshapiro patching_epilog(patch, lir_patch_high, base, info); 1053159609Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1054159609Sgshapiro patch_code = lir_patch_low; 1055159609Sgshapiro } 1056159609Sgshapiro __ movl(as_Address_lo(to_addr), from_lo); 1057159609Sgshapiro } else { 1058159609Sgshapiro assert(index == noreg || (index != base && index != from_lo), "can't handle this"); 1059159609Sgshapiro __ movl(as_Address_lo(to_addr), from_lo); 1060159609Sgshapiro if (patch != NULL) { 1061159609Sgshapiro patching_epilog(patch, lir_patch_low, base, info); 1062159609Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1063159609Sgshapiro patch_code = lir_patch_high; 1064159609Sgshapiro } 1065159609Sgshapiro __ movl(as_Address_hi(to_addr), from_hi); 1066159609Sgshapiro } 1067159609Sgshapiro#endif // _LP64 1068159609Sgshapiro break; 1069159609Sgshapiro } 1070159609Sgshapiro 1071159609Sgshapiro case T_BYTE: // fall through 1072159609Sgshapiro case T_BOOLEAN: { 1073159609Sgshapiro Register src_reg = src->as_register(); 1074159609Sgshapiro Address dst_addr = as_Address(to_addr); 1075159609Sgshapiro assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6"); 1076159609Sgshapiro __ movb(dst_addr, src_reg); 1077159609Sgshapiro break; 1078159609Sgshapiro } 1079159609Sgshapiro 1080159609Sgshapiro case T_CHAR: // fall through 1081159609Sgshapiro case T_SHORT: 1082159609Sgshapiro __ movw(as_Address(to_addr), src->as_register()); 1083159609Sgshapiro break; 1084159609Sgshapiro 1085159609Sgshapiro default: 1086159609Sgshapiro ShouldNotReachHere(); 1087111823Sgshapiro } 1088111823Sgshapiro if (info != NULL) { 1089111823Sgshapiro add_debug_info_for_null_check(null_check_here, info); 109090792Sgshapiro } 109190792Sgshapiro 109290792Sgshapiro if (patch_code != lir_patch_none) { 109390792Sgshapiro patching_epilog(patch, patch_code, to_addr->base()->as_register(), info); 109490792Sgshapiro } 1095159609Sgshapiro} 109690792Sgshapiro 109790792Sgshapiro 109890792Sgshapirovoid LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 109990792Sgshapiro assert(src->is_stack(), "should not call otherwise"); 110090792Sgshapiro assert(dest->is_register(), "should not call otherwise"); 110190792Sgshapiro 110290792Sgshapiro if (dest->is_single_cpu()) { 110390792Sgshapiro if (type == T_ARRAY || type == T_OBJECT) { 110490792Sgshapiro __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 110590792Sgshapiro __ verify_oop(dest->as_register()); 110690792Sgshapiro } else { 110790792Sgshapiro __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix())); 110890792Sgshapiro } 110990792Sgshapiro 111090792Sgshapiro } else if (dest->is_double_cpu()) { 111190792Sgshapiro Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes); 111290792Sgshapiro Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes); 111390792Sgshapiro __ movptr(dest->as_register_lo(), src_addr_LO); 111490792Sgshapiro NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI)); 111590792Sgshapiro 111690792Sgshapiro } else if (dest->is_single_xmm()) { 111790792Sgshapiro Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 111890792Sgshapiro __ movflt(dest->as_xmm_float_reg(), src_addr); 111990792Sgshapiro 112090792Sgshapiro } else if (dest->is_double_xmm()) { 112190792Sgshapiro Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 112290792Sgshapiro __ movdbl(dest->as_xmm_double_reg(), src_addr); 112390792Sgshapiro 112490792Sgshapiro } else if (dest->is_single_fpu()) { 112590792Sgshapiro assert(dest->fpu_regnr() == 0, "dest must be TOS"); 112690792Sgshapiro Address src_addr = frame_map()->address_for_slot(src->single_stack_ix()); 112790792Sgshapiro __ fld_s(src_addr); 112890792Sgshapiro 112990792Sgshapiro } else if (dest->is_double_fpu()) { 113090792Sgshapiro assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 113190792Sgshapiro Address src_addr = frame_map()->address_for_slot(src->double_stack_ix()); 113290792Sgshapiro __ fld_d(src_addr); 113390792Sgshapiro 113490792Sgshapiro } else { 113590792Sgshapiro ShouldNotReachHere(); 113690792Sgshapiro } 113790792Sgshapiro} 113890792Sgshapiro 1139159609Sgshapiro 1140159609Sgshapirovoid LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1141159609Sgshapiro if (src->is_single_stack()) { 1142159609Sgshapiro if (type == T_OBJECT || type == T_ARRAY) { 1143159609Sgshapiro __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix())); 1144159609Sgshapiro __ popptr (frame_map()->address_for_slot(dest->single_stack_ix())); 1145159609Sgshapiro } else { 1146159609Sgshapiro#ifndef _LP64 1147159609Sgshapiro __ pushl(frame_map()->address_for_slot(src ->single_stack_ix())); 1148159609Sgshapiro __ popl (frame_map()->address_for_slot(dest->single_stack_ix())); 1149159609Sgshapiro#else 1150159609Sgshapiro //no pushl on 64bits 1151159609Sgshapiro __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix())); 1152159609Sgshapiro __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1); 1153159609Sgshapiro#endif 1154159609Sgshapiro } 1155159609Sgshapiro 1156159609Sgshapiro } else if (src->is_double_stack()) { 1157159609Sgshapiro#ifdef _LP64 1158159609Sgshapiro __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix())); 1159159609Sgshapiro __ popptr (frame_map()->address_for_slot(dest->double_stack_ix())); 1160159609Sgshapiro#else 1161159609Sgshapiro __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0)); 1162159609Sgshapiro // push and pop the part at src + wordSize, adding wordSize for the previous push 1163159609Sgshapiro __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize)); 1164159609Sgshapiro __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize)); 1165159609Sgshapiro __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0)); 1166159609Sgshapiro#endif // _LP64 1167159609Sgshapiro 1168159609Sgshapiro } else { 1169159609Sgshapiro ShouldNotReachHere(); 1170159609Sgshapiro } 1171159609Sgshapiro} 1172159609Sgshapiro 1173159609Sgshapiro 1174159609Sgshapirovoid LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) { 1175159609Sgshapiro assert(src->is_address(), "should not call otherwise"); 1176159609Sgshapiro assert(dest->is_register(), "should not call otherwise"); 1177159609Sgshapiro 1178159609Sgshapiro LIR_Address* addr = src->as_address_ptr(); 1179159609Sgshapiro Address from_addr = as_Address(addr); 1180159609Sgshapiro 1181159609Sgshapiro switch (type) { 118290792Sgshapiro case T_BOOLEAN: // fall through 118390792Sgshapiro case T_BYTE: // fall through 118490792Sgshapiro case T_CHAR: // fall through 118571345Sgshapiro case T_SHORT: 118671345Sgshapiro if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) { 118771345Sgshapiro // on pre P6 processors we may get partial register stalls 118871345Sgshapiro // so blow away the value of to_rinfo before loading a 118971345Sgshapiro // partial word into it. Do it here so that it precedes 1190159609Sgshapiro // the potential patch point below. 119171345Sgshapiro __ xorptr(dest->as_register(), dest->as_register()); 119271345Sgshapiro } 119371345Sgshapiro break; 119471345Sgshapiro } 119571345Sgshapiro 119671345Sgshapiro PatchingStub* patch = NULL; 119771345Sgshapiro if (patch_code != lir_patch_none) { 119871345Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1199159609Sgshapiro assert(from_addr.disp() != 0, "must have"); 1200159609Sgshapiro } 1201159609Sgshapiro if (info != NULL) { 1202159609Sgshapiro add_debug_info_for_null_check_here(info); 1203159609Sgshapiro } 1204159609Sgshapiro 1205159609Sgshapiro switch (type) { 1206159609Sgshapiro case T_FLOAT: { 1207159609Sgshapiro if (dest->is_single_xmm()) { 1208159609Sgshapiro __ movflt(dest->as_xmm_float_reg(), from_addr); 1209159609Sgshapiro } else { 1210159609Sgshapiro assert(dest->is_single_fpu(), "must be"); 1211159609Sgshapiro assert(dest->fpu_regnr() == 0, "dest must be TOS"); 1212159609Sgshapiro __ fld_s(from_addr); 1213159609Sgshapiro } 1214159609Sgshapiro break; 1215159609Sgshapiro } 1216159609Sgshapiro 1217159609Sgshapiro case T_DOUBLE: { 1218159609Sgshapiro if (dest->is_double_xmm()) { 1219159609Sgshapiro __ movdbl(dest->as_xmm_double_reg(), from_addr); 1220159609Sgshapiro } else { 1221159609Sgshapiro assert(dest->is_double_fpu(), "must be"); 1222159609Sgshapiro assert(dest->fpu_regnrLo() == 0, "dest must be TOS"); 1223159609Sgshapiro __ fld_d(from_addr); 1224159609Sgshapiro } 1225159609Sgshapiro break; 1226159609Sgshapiro } 1227159609Sgshapiro 1228159609Sgshapiro case T_OBJECT: // fall through 1229159609Sgshapiro case T_ARRAY: // fall through 1230159609Sgshapiro if (UseCompressedOops && !wide) { 1231159609Sgshapiro __ movl(dest->as_register(), from_addr); 1232159609Sgshapiro } else { 1233159609Sgshapiro __ movptr(dest->as_register(), from_addr); 1234159609Sgshapiro } 1235159609Sgshapiro break; 1236159609Sgshapiro 123780785Sgshapiro case T_ADDRESS: 123880785Sgshapiro __ movptr(dest->as_register(), from_addr); 1239159609Sgshapiro break; 1240159609Sgshapiro case T_INT: 1241159609Sgshapiro __ movl(dest->as_register(), from_addr); 1242159609Sgshapiro break; 1243159609Sgshapiro 1244159609Sgshapiro case T_LONG: { 1245159609Sgshapiro Register to_lo = dest->as_register_lo(); 1246159609Sgshapiro Register to_hi = dest->as_register_hi(); 1247159609Sgshapiro#ifdef _LP64 1248159609Sgshapiro __ movptr(to_lo, as_Address_lo(addr)); 1249159609Sgshapiro#else 1250159609Sgshapiro Register base = addr->base()->as_register(); 1251159609Sgshapiro Register index = noreg; 1252159609Sgshapiro if (addr->index()->is_register()) { 1253159609Sgshapiro index = addr->index()->as_register(); 1254159609Sgshapiro } 1255159609Sgshapiro if ((base == to_lo && index == to_hi) || 1256159609Sgshapiro (base == to_hi && index == to_lo)) { 1257159609Sgshapiro // addresses with 2 registers are only formed as a result of 1258159609Sgshapiro // array access so this code will never have to deal with 1259159609Sgshapiro // patches or null checks. 1260159609Sgshapiro assert(info == NULL && patch == NULL, "must be"); 1261159609Sgshapiro __ lea(to_hi, as_Address(addr)); 1262159609Sgshapiro __ movl(to_lo, Address(to_hi, 0)); 1263159609Sgshapiro __ movl(to_hi, Address(to_hi, BytesPerWord)); 1264159609Sgshapiro } else if (base == to_lo || index == to_lo) { 1265159609Sgshapiro assert(base != to_hi, "can't be"); 1266159609Sgshapiro assert(index == noreg || (index != base && index != to_hi), "can't handle this"); 1267159609Sgshapiro __ movl(to_hi, as_Address_hi(addr)); 1268159609Sgshapiro if (patch != NULL) { 1269159609Sgshapiro patching_epilog(patch, lir_patch_high, base, info); 1270159609Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1271159609Sgshapiro patch_code = lir_patch_low; 1272159609Sgshapiro } 1273159609Sgshapiro __ movl(to_lo, as_Address_lo(addr)); 1274159609Sgshapiro } else { 1275159609Sgshapiro assert(index == noreg || (index != base && index != to_lo), "can't handle this"); 1276159609Sgshapiro __ movl(to_lo, as_Address_lo(addr)); 1277159609Sgshapiro if (patch != NULL) { 1278159609Sgshapiro patching_epilog(patch, lir_patch_low, base, info); 1279159609Sgshapiro patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1280159609Sgshapiro patch_code = lir_patch_high; 1281159609Sgshapiro } 1282159609Sgshapiro __ movl(to_hi, as_Address_hi(addr)); 1283159609Sgshapiro } 128471345Sgshapiro#endif // _LP64 128571345Sgshapiro break; 128671345Sgshapiro } 128771345Sgshapiro 128871345Sgshapiro case T_BOOLEAN: // fall through 128971345Sgshapiro case T_BYTE: { 129071345Sgshapiro Register dest_reg = dest->as_register(); 129171345Sgshapiro assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 1292159609Sgshapiro if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 129371345Sgshapiro __ movsbl(dest_reg, from_addr); 129471345Sgshapiro } else { 129571345Sgshapiro __ movb(dest_reg, from_addr); 129671345Sgshapiro __ shll(dest_reg, 24); 129771345Sgshapiro __ sarl(dest_reg, 24); 129871345Sgshapiro } 129971345Sgshapiro break; 130071345Sgshapiro } 130171345Sgshapiro 130271345Sgshapiro case T_CHAR: { 130371345Sgshapiro Register dest_reg = dest->as_register(); 130471345Sgshapiro assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6"); 130571345Sgshapiro if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 130671345Sgshapiro __ movzwl(dest_reg, from_addr); 130771345Sgshapiro } else { 130871345Sgshapiro __ movw(dest_reg, from_addr); 130971345Sgshapiro } 131071345Sgshapiro break; 131171345Sgshapiro } 131271345Sgshapiro 131371345Sgshapiro case T_SHORT: { 131471345Sgshapiro Register dest_reg = dest->as_register(); 131571345Sgshapiro if (VM_Version::is_P6() || from_addr.uses(dest_reg)) { 131671345Sgshapiro __ movswl(dest_reg, from_addr); 131771345Sgshapiro } else { 131871345Sgshapiro __ movw(dest_reg, from_addr); 131971345Sgshapiro __ shll(dest_reg, 16); 132071345Sgshapiro __ sarl(dest_reg, 16); 132171345Sgshapiro } 132271345Sgshapiro break; 1323159609Sgshapiro } 1324159609Sgshapiro 1325159609Sgshapiro default: 1326159609Sgshapiro ShouldNotReachHere(); 1327159609Sgshapiro } 1328159609Sgshapiro 1329159609Sgshapiro if (patch != NULL) { 1330159609Sgshapiro patching_epilog(patch, patch_code, addr->base()->as_register(), info); 1331159609Sgshapiro } 1332159609Sgshapiro 1333159609Sgshapiro if (type == T_ARRAY || type == T_OBJECT) { 1334159609Sgshapiro#ifdef _LP64 1335159609Sgshapiro if (UseCompressedOops && !wide) { 1336159609Sgshapiro __ decode_heap_oop(dest->as_register()); 1337159609Sgshapiro } 1338159609Sgshapiro#endif 1339159609Sgshapiro __ verify_oop(dest->as_register()); 1340159609Sgshapiro } 1341159609Sgshapiro} 1342159609Sgshapiro 1343159609Sgshapiro 1344159609Sgshapirovoid LIR_Assembler::prefetchr(LIR_Opr src) { 1345159609Sgshapiro LIR_Address* addr = src->as_address_ptr(); 1346159609Sgshapiro Address from_addr = as_Address(addr); 1347159609Sgshapiro 1348159609Sgshapiro if (VM_Version::supports_sse()) { 1349159609Sgshapiro switch (ReadPrefetchInstr) { 1350159609Sgshapiro case 0: 1351159609Sgshapiro __ prefetchnta(from_addr); break; 1352159609Sgshapiro case 1: 1353159609Sgshapiro __ prefetcht0(from_addr); break; 1354159609Sgshapiro case 2: 1355159609Sgshapiro __ prefetcht2(from_addr); break; 1356159609Sgshapiro default: 1357159609Sgshapiro ShouldNotReachHere(); break; 1358159609Sgshapiro } 1359159609Sgshapiro } else if (VM_Version::supports_3dnow_prefetch()) { 1360159609Sgshapiro __ prefetchr(from_addr); 1361159609Sgshapiro } 1362159609Sgshapiro} 1363159609Sgshapiro 1364159609Sgshapiro 1365159609Sgshapirovoid LIR_Assembler::prefetchw(LIR_Opr src) { 1366159609Sgshapiro LIR_Address* addr = src->as_address_ptr(); 1367159609Sgshapiro Address from_addr = as_Address(addr); 1368159609Sgshapiro 1369159609Sgshapiro if (VM_Version::supports_sse()) { 1370159609Sgshapiro switch (AllocatePrefetchInstr) { 1371159609Sgshapiro case 0: 1372159609Sgshapiro __ prefetchnta(from_addr); break; 1373159609Sgshapiro case 1: 1374159609Sgshapiro __ prefetcht0(from_addr); break; 137571345Sgshapiro case 2: 137671345Sgshapiro __ prefetcht2(from_addr); break; 137771345Sgshapiro case 3: 137864562Sgshapiro __ prefetchw(from_addr); break; 137964562Sgshapiro default: 138064562Sgshapiro ShouldNotReachHere(); break; 138164562Sgshapiro } 138264562Sgshapiro } else if (VM_Version::supports_3dnow_prefetch()) { 1383159609Sgshapiro __ prefetchw(from_addr); 138464562Sgshapiro } 138564562Sgshapiro} 138664562Sgshapiro 138764562Sgshapiro 138864562SgshapiroNEEDS_CLEANUP; // This could be static? 138964562SgshapiroAddress::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const { 139064562Sgshapiro int elem_size = type2aelembytes(type); 139164562Sgshapiro switch (elem_size) { 139264562Sgshapiro case 1: return Address::times_1; 139364562Sgshapiro case 2: return Address::times_2; 139464562Sgshapiro case 4: return Address::times_4; 139564562Sgshapiro case 8: return Address::times_8; 139664562Sgshapiro } 139764562Sgshapiro ShouldNotReachHere(); 139864562Sgshapiro return Address::no_scale; 139964562Sgshapiro} 140064562Sgshapiro 140164562Sgshapiro 140264562Sgshapirovoid LIR_Assembler::emit_op3(LIR_Op3* op) { 140364562Sgshapiro switch (op->code()) { 140464562Sgshapiro case lir_idiv: 140564562Sgshapiro case lir_irem: 140664562Sgshapiro arithmetic_idiv(op->code(), 140764562Sgshapiro op->in_opr1(), 140864562Sgshapiro op->in_opr2(), 140964562Sgshapiro op->in_opr3(), 141064562Sgshapiro op->result_opr(), 141164562Sgshapiro op->info()); 141264562Sgshapiro break; 1413159609Sgshapiro default: ShouldNotReachHere(); break; 1414159609Sgshapiro } 1415159609Sgshapiro} 1416159609Sgshapiro 1417159609Sgshapirovoid LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 1418159609Sgshapiro#ifdef ASSERT 1419159609Sgshapiro assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 1420159609Sgshapiro if (op->block() != NULL) _branch_target_blocks.append(op->block()); 1421159609Sgshapiro if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 1422159609Sgshapiro#endif 1423159609Sgshapiro 1424159609Sgshapiro if (op->cond() == lir_cond_always) { 1425159609Sgshapiro if (op->info() != NULL) add_debug_info_for_branch(op->info()); 1426159609Sgshapiro __ jmp (*(op->label())); 1427159609Sgshapiro } else { 1428159609Sgshapiro Assembler::Condition acond = Assembler::zero; 1429159609Sgshapiro if (op->code() == lir_cond_float_branch) { 1430159609Sgshapiro assert(op->ublock() != NULL, "must have unordered successor"); 1431159609Sgshapiro __ jcc(Assembler::parity, *(op->ublock()->label())); 1432159609Sgshapiro switch(op->cond()) { 143364562Sgshapiro case lir_cond_equal: acond = Assembler::equal; break; 143464562Sgshapiro case lir_cond_notEqual: acond = Assembler::notEqual; break; 143564562Sgshapiro case lir_cond_less: acond = Assembler::below; break; 143664562Sgshapiro case lir_cond_lessEqual: acond = Assembler::belowEqual; break; 143764562Sgshapiro case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break; 143864562Sgshapiro case lir_cond_greater: acond = Assembler::above; break; 143964562Sgshapiro default: ShouldNotReachHere(); 144064562Sgshapiro } 1441159609Sgshapiro } else { 144264562Sgshapiro switch (op->cond()) { 144364562Sgshapiro case lir_cond_equal: acond = Assembler::equal; break; 144464562Sgshapiro case lir_cond_notEqual: acond = Assembler::notEqual; break; 144564562Sgshapiro case lir_cond_less: acond = Assembler::less; break; 144664562Sgshapiro case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 144764562Sgshapiro case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break; 144864562Sgshapiro case lir_cond_greater: acond = Assembler::greater; break; 144964562Sgshapiro case lir_cond_belowEqual: acond = Assembler::belowEqual; break; 145064562Sgshapiro case lir_cond_aboveEqual: acond = Assembler::aboveEqual; break; 145164562Sgshapiro default: ShouldNotReachHere(); 145264562Sgshapiro } 145364562Sgshapiro } 145464562Sgshapiro __ jcc(acond,*(op->label())); 145564562Sgshapiro } 145664562Sgshapiro} 145764562Sgshapiro 145864562Sgshapirovoid LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 145964562Sgshapiro LIR_Opr src = op->in_opr(); 146064562Sgshapiro LIR_Opr dest = op->result_opr(); 146164562Sgshapiro 146264562Sgshapiro switch (op->bytecode()) { 146364562Sgshapiro case Bytecodes::_i2l: 146464562Sgshapiro#ifdef _LP64 146564562Sgshapiro __ movl2ptr(dest->as_register_lo(), src->as_register()); 146664562Sgshapiro#else 146764562Sgshapiro move_regs(src->as_register(), dest->as_register_lo()); 146864562Sgshapiro move_regs(src->as_register(), dest->as_register_hi()); 146964562Sgshapiro __ sarl(dest->as_register_hi(), 31); 147064562Sgshapiro#endif // LP64 147164562Sgshapiro break; 147264562Sgshapiro 147364562Sgshapiro case Bytecodes::_l2i: 147464562Sgshapiro#ifdef _LP64 147564562Sgshapiro __ movl(dest->as_register(), src->as_register_lo()); 147664562Sgshapiro#else 147764562Sgshapiro move_regs(src->as_register_lo(), dest->as_register()); 147864562Sgshapiro#endif 147964562Sgshapiro break; 148064562Sgshapiro 148164562Sgshapiro case Bytecodes::_i2b: 148264562Sgshapiro move_regs(src->as_register(), dest->as_register()); 148364562Sgshapiro __ sign_extend_byte(dest->as_register()); 148464562Sgshapiro break; 148564562Sgshapiro 148664562Sgshapiro case Bytecodes::_i2c: 148764562Sgshapiro move_regs(src->as_register(), dest->as_register()); 148864562Sgshapiro __ andl(dest->as_register(), 0xFFFF); 148964562Sgshapiro break; 149064562Sgshapiro 149164562Sgshapiro case Bytecodes::_i2s: 149264562Sgshapiro move_regs(src->as_register(), dest->as_register()); 149364562Sgshapiro __ sign_extend_short(dest->as_register()); 149464562Sgshapiro break; 149564562Sgshapiro 149664562Sgshapiro 149764562Sgshapiro case Bytecodes::_f2d: 149864562Sgshapiro case Bytecodes::_d2f: 149964562Sgshapiro if (dest->is_single_xmm()) { 150064562Sgshapiro __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg()); 150164562Sgshapiro } else if (dest->is_double_xmm()) { 1502159609Sgshapiro __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg()); 1503159609Sgshapiro } else { 1504159609Sgshapiro assert(src->fpu() == dest->fpu(), "register must be equal"); 1505159609Sgshapiro // do nothing (float result is rounded later through spilling) 1506159609Sgshapiro } 1507159609Sgshapiro break; 1508159609Sgshapiro 1509159609Sgshapiro case Bytecodes::_i2f: 1510159609Sgshapiro case Bytecodes::_i2d: 1511159609Sgshapiro if (dest->is_single_xmm()) { 151264562Sgshapiro __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register()); 151364562Sgshapiro } else if (dest->is_double_xmm()) { 151464562Sgshapiro __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register()); 151564562Sgshapiro } else { 151664562Sgshapiro assert(dest->fpu() == 0, "result must be on TOS"); 151764562Sgshapiro __ movl(Address(rsp, 0), src->as_register()); 151864562Sgshapiro __ fild_s(Address(rsp, 0)); 151964562Sgshapiro } 1520159609Sgshapiro break; 152164562Sgshapiro 152264562Sgshapiro case Bytecodes::_f2i: 152364562Sgshapiro case Bytecodes::_d2i: 152464562Sgshapiro if (src->is_single_xmm()) { 152564562Sgshapiro __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg()); 152664562Sgshapiro } else if (src->is_double_xmm()) { 152764562Sgshapiro __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg()); 152864562Sgshapiro } else { 152964562Sgshapiro assert(src->fpu() == 0, "input must be on TOS"); 153064562Sgshapiro __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc())); 153164562Sgshapiro __ fist_s(Address(rsp, 0)); 153264562Sgshapiro __ movl(dest->as_register(), Address(rsp, 0)); 153364562Sgshapiro __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std())); 153464562Sgshapiro } 153564562Sgshapiro 153664562Sgshapiro // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 153764562Sgshapiro assert(op->stub() != NULL, "stub required"); 153864562Sgshapiro __ cmpl(dest->as_register(), 0x80000000); 153964562Sgshapiro __ jcc(Assembler::equal, *op->stub()->entry()); 154064562Sgshapiro __ bind(*op->stub()->continuation()); 154164562Sgshapiro break; 154264562Sgshapiro 154364562Sgshapiro case Bytecodes::_l2f: 154464562Sgshapiro case Bytecodes::_l2d: 154564562Sgshapiro assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)"); 154664562Sgshapiro assert(dest->fpu() == 0, "result must be on TOS"); 154764562Sgshapiro 154864562Sgshapiro __ movptr(Address(rsp, 0), src->as_register_lo()); 154964562Sgshapiro NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi())); 155064562Sgshapiro __ fild_d(Address(rsp, 0)); 155164562Sgshapiro // float result is rounded later through spilling 155264562Sgshapiro break; 155364562Sgshapiro 155464562Sgshapiro case Bytecodes::_f2l: 155564562Sgshapiro case Bytecodes::_d2l: 155664562Sgshapiro assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)"); 155764562Sgshapiro assert(src->fpu() == 0, "input must be on TOS"); 155864562Sgshapiro assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers"); 155964562Sgshapiro 156064562Sgshapiro // instruction sequence too long to inline it here 156164562Sgshapiro { 156264562Sgshapiro __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id))); 156364562Sgshapiro } 156464562Sgshapiro break; 156564562Sgshapiro 156664562Sgshapiro default: ShouldNotReachHere(); 156764562Sgshapiro } 156864562Sgshapiro} 156964562Sgshapiro 157064562Sgshapirovoid LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 157164562Sgshapiro if (op->init_check()) { 157264562Sgshapiro __ cmpb(Address(op->klass()->as_register(), 157364562Sgshapiro instanceKlass::init_state_offset()), 157464562Sgshapiro instanceKlass::fully_initialized); 157564562Sgshapiro add_debug_info_for_null_check_here(op->stub()->info()); 157664562Sgshapiro __ jcc(Assembler::notEqual, *op->stub()->entry()); 157764562Sgshapiro } 1578159609Sgshapiro __ allocate_object(op->obj()->as_register(), 1579159609Sgshapiro op->tmp1()->as_register(), 1580159609Sgshapiro op->tmp2()->as_register(), 1581159609Sgshapiro op->header_size(), 1582159609Sgshapiro op->object_size(), 1583159609Sgshapiro op->klass()->as_register(), 1584159609Sgshapiro *op->stub()->entry()); 1585159609Sgshapiro __ bind(*op->stub()->continuation()); 1586159609Sgshapiro} 1587159609Sgshapiro 1588159609Sgshapirovoid LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 1589159609Sgshapiro Register len = op->len()->as_register(); 1590159609Sgshapiro LP64_ONLY( __ movslq(len, len); ) 1591159609Sgshapiro 1592159609Sgshapiro if (UseSlowPath || 1593159609Sgshapiro (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 1594159609Sgshapiro (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 159564562Sgshapiro __ jmp(*op->stub()->entry()); 159664562Sgshapiro } else { 159764562Sgshapiro Register tmp1 = op->tmp1()->as_register(); 1598244833Sgshapiro Register tmp2 = op->tmp2()->as_register(); 1599244833Sgshapiro Register tmp3 = op->tmp3()->as_register(); 1600244833Sgshapiro if (len == tmp1) { 1601244833Sgshapiro tmp1 = tmp3; 1602244833Sgshapiro } else if (len == tmp2) { 1603244833Sgshapiro tmp2 = tmp3; 1604244833Sgshapiro } else if (len == tmp3) { 1605244833Sgshapiro // everything is ok 1606244833Sgshapiro } else { 1607244833Sgshapiro __ mov(tmp3, len); 1608244833Sgshapiro } 1609244833Sgshapiro __ allocate_array(op->obj()->as_register(), 1610244833Sgshapiro len, 1611244833Sgshapiro tmp1, 1612244833Sgshapiro tmp2, 1613244833Sgshapiro arrayOopDesc::header_size(op->type()), 1614244833Sgshapiro array_element_size(op->type()), 1615244833Sgshapiro op->klass()->as_register(), 1616244833Sgshapiro *op->stub()->entry()); 1617244833Sgshapiro } 1618244833Sgshapiro __ bind(*op->stub()->continuation()); 1619244833Sgshapiro} 1620244833Sgshapiro 1621244833Sgshapirovoid LIR_Assembler::type_profile_helper(Register mdo, 1622244833Sgshapiro ciMethodData *md, ciProfileData *data, 1623244833Sgshapiro Register recv, Label* update_done) { 1624244833Sgshapiro for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1625244833Sgshapiro Label next_test; 1626244833Sgshapiro // See if the receiver is receiver[n]. 1627244833Sgshapiro __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)))); 1628244833Sgshapiro __ jccb(Assembler::notEqual, next_test); 1629244833Sgshapiro Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))); 1630244833Sgshapiro __ addptr(data_addr, DataLayout::counter_increment); 1631244833Sgshapiro __ jmp(*update_done); 1632244833Sgshapiro __ bind(next_test); 1633244833Sgshapiro } 1634244833Sgshapiro 1635244833Sgshapiro // Didn't find receiver; find next empty slot and fill it in 1636244833Sgshapiro for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) { 1637244833Sgshapiro Label next_test; 1638244833Sgshapiro Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))); 1639244833Sgshapiro __ cmpptr(recv_addr, (intptr_t)NULL_WORD); 1640244833Sgshapiro __ jccb(Assembler::notEqual, next_test); 1641244833Sgshapiro __ movptr(recv_addr, recv); 1642244833Sgshapiro __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment); 1643244833Sgshapiro __ jmp(*update_done); 1644244833Sgshapiro __ bind(next_test); 1645244833Sgshapiro } 1646244833Sgshapiro} 1647244833Sgshapiro 1648244833Sgshapirovoid LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 1649244833Sgshapiro // we always need a stub for the failure case. 1650244833Sgshapiro CodeStub* stub = op->stub(); 1651244833Sgshapiro Register obj = op->object()->as_register(); 1652244833Sgshapiro Register k_RInfo = op->tmp1()->as_register(); 1653244833Sgshapiro Register klass_RInfo = op->tmp2()->as_register(); 1654244833Sgshapiro Register dst = op->result_opr()->as_register(); 1655244833Sgshapiro ciKlass* k = op->klass(); 1656244833Sgshapiro Register Rtmp1 = noreg; 1657244833Sgshapiro 1658244833Sgshapiro // check if it needs to be profiled 1659244833Sgshapiro ciMethodData* md; 1660244833Sgshapiro ciProfileData* data; 1661244833Sgshapiro 1662244833Sgshapiro if (op->should_profile()) { 1663244833Sgshapiro ciMethod* method = op->profiled_method(); 1664159609Sgshapiro assert(method != NULL, "Should have method"); 1665159609Sgshapiro int bci = op->profiled_bci(); 1666159609Sgshapiro md = method->method_data_or_null(); 1667244833Sgshapiro assert(md != NULL, "Sanity"); 1668159609Sgshapiro data = md->bci_to_data(bci); 1669159609Sgshapiro assert(data != NULL, "need data for type check"); 1670244833Sgshapiro assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1671159609Sgshapiro } 1672159609Sgshapiro Label profile_cast_success, profile_cast_failure; 1673159609Sgshapiro Label *success_target = op->should_profile() ? &profile_cast_success : success; 1674159609Sgshapiro Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 1675159609Sgshapiro 1676159609Sgshapiro if (obj == k_RInfo) { 1677159609Sgshapiro k_RInfo = dst; 1678159609Sgshapiro } else if (obj == klass_RInfo) { 1679159609Sgshapiro klass_RInfo = dst; 1680244833Sgshapiro } 1681244833Sgshapiro if (k->is_loaded() && !UseCompressedOops) { 1682244833Sgshapiro select_different_registers(obj, dst, k_RInfo, klass_RInfo); 1683244833Sgshapiro } else { 1684244833Sgshapiro Rtmp1 = op->tmp3()->as_register(); 1685244833Sgshapiro select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1); 1686244833Sgshapiro } 1687244833Sgshapiro 1688244833Sgshapiro assert_different_registers(obj, k_RInfo, klass_RInfo); 1689244833Sgshapiro if (!k->is_loaded()) { 1690244833Sgshapiro jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 1691244833Sgshapiro } else { 1692244833Sgshapiro#ifdef _LP64 1693244833Sgshapiro __ movoop(k_RInfo, k->constant_encoding()); 1694244833Sgshapiro#endif // _LP64 1695244833Sgshapiro } 1696244833Sgshapiro assert(obj != k_RInfo, "must be different"); 1697244833Sgshapiro 1698244833Sgshapiro __ cmpptr(obj, (int32_t)NULL_WORD); 1699244833Sgshapiro if (op->should_profile()) { 1700244833Sgshapiro Label not_null; 1701244833Sgshapiro __ jccb(Assembler::notEqual, not_null); 1702244833Sgshapiro // Object is null; update MDO and exit 1703244833Sgshapiro Register mdo = klass_RInfo; 1704244833Sgshapiro __ movoop(mdo, md->constant_encoding()); 1705244833Sgshapiro Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1706244833Sgshapiro int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1707244833Sgshapiro __ orl(data_addr, header_bits); 1708244833Sgshapiro __ jmp(*obj_is_null); 1709244833Sgshapiro __ bind(not_null); 1710244833Sgshapiro } else { 1711244833Sgshapiro __ jcc(Assembler::equal, *obj_is_null); 1712244833Sgshapiro } 1713244833Sgshapiro __ verify_oop(obj); 1714244833Sgshapiro 1715244833Sgshapiro if (op->fast_check()) { 1716244833Sgshapiro // get object class 1717244833Sgshapiro // not a safepoint as obj null check happens earlier 1718244833Sgshapiro#ifdef _LP64 1719244833Sgshapiro if (UseCompressedOops) { 1720244833Sgshapiro __ load_klass(Rtmp1, obj); 1721244833Sgshapiro __ cmpptr(k_RInfo, Rtmp1); 1722244833Sgshapiro } else { 1723244833Sgshapiro __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 1724159609Sgshapiro } 1725159609Sgshapiro#else 1726159609Sgshapiro if (k->is_loaded()) { 172764562Sgshapiro __ cmpoop(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding()); 172864562Sgshapiro } else { 172964562Sgshapiro __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes())); 173064562Sgshapiro } 173164562Sgshapiro#endif 1732159609Sgshapiro __ jcc(Assembler::notEqual, *failure_target); 173364562Sgshapiro // successful cast, fall through to profile or jump 173464562Sgshapiro } else { 173564562Sgshapiro // get object class 173664562Sgshapiro // not a safepoint as obj null check happens earlier 173780785Sgshapiro __ load_klass(klass_RInfo, obj); 173880785Sgshapiro if (k->is_loaded()) { 173980785Sgshapiro // See if we get an immediate positive hit 174080785Sgshapiro#ifdef _LP64 174180785Sgshapiro __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset())); 174280785Sgshapiro#else 174380785Sgshapiro __ cmpoop(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding()); 174480785Sgshapiro#endif // _LP64 174580785Sgshapiro if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) { 174680785Sgshapiro __ jcc(Assembler::notEqual, *failure_target); 174780785Sgshapiro // successful cast, fall through to profile or jump 174880785Sgshapiro } else { 174980785Sgshapiro // See if we get an immediate positive hit 175080785Sgshapiro __ jcc(Assembler::equal, *success_target); 175180785Sgshapiro // check for self 175280785Sgshapiro#ifdef _LP64 175380785Sgshapiro __ cmpptr(klass_RInfo, k_RInfo); 175480785Sgshapiro#else 175580785Sgshapiro __ cmpoop(klass_RInfo, k->constant_encoding()); 1756159609Sgshapiro#endif // _LP64 1757159609Sgshapiro __ jcc(Assembler::equal, *success_target); 1758159609Sgshapiro 1759159609Sgshapiro __ push(klass_RInfo); 1760159609Sgshapiro#ifdef _LP64 1761159609Sgshapiro __ push(k_RInfo); 1762159609Sgshapiro#else 1763159609Sgshapiro __ pushoop(k->constant_encoding()); 1764159609Sgshapiro#endif // _LP64 1765159609Sgshapiro __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1766159609Sgshapiro __ pop(klass_RInfo); 1767159609Sgshapiro __ pop(klass_RInfo); 1768159609Sgshapiro // result is a boolean 1769159609Sgshapiro __ cmpl(klass_RInfo, 0); 1770159609Sgshapiro __ jcc(Assembler::equal, *failure_target); 1771159609Sgshapiro // successful cast, fall through to profile or jump 1772159609Sgshapiro } 1773159609Sgshapiro } else { 1774159609Sgshapiro // perform the fast part of the checking logic 1775159609Sgshapiro __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1776159609Sgshapiro // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1777159609Sgshapiro __ push(klass_RInfo); 1778159609Sgshapiro __ push(k_RInfo); 1779159609Sgshapiro __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1780159609Sgshapiro __ pop(klass_RInfo); 1781159609Sgshapiro __ pop(k_RInfo); 1782159609Sgshapiro // result is a boolean 1783159609Sgshapiro __ cmpl(k_RInfo, 0); 1784159609Sgshapiro __ jcc(Assembler::equal, *failure_target); 1785159609Sgshapiro // successful cast, fall through to profile or jump 1786159609Sgshapiro } 1787159609Sgshapiro } 1788159609Sgshapiro if (op->should_profile()) { 1789159609Sgshapiro Register mdo = klass_RInfo, recv = k_RInfo; 1790159609Sgshapiro __ bind(profile_cast_success); 1791159609Sgshapiro __ movoop(mdo, md->constant_encoding()); 1792159609Sgshapiro __ load_klass(recv, obj); 1793159609Sgshapiro Label update_done; 1794159609Sgshapiro type_profile_helper(mdo, md, data, recv, success); 1795159609Sgshapiro __ jmp(*success); 1796159609Sgshapiro 1797159609Sgshapiro __ bind(profile_cast_failure); 1798159609Sgshapiro __ movoop(mdo, md->constant_encoding()); 1799159609Sgshapiro Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 1800159609Sgshapiro __ subptr(counter_addr, DataLayout::counter_increment); 1801159609Sgshapiro __ jmp(*failure); 1802159609Sgshapiro } 1803159609Sgshapiro __ jmp(*success); 1804159609Sgshapiro} 1805159609Sgshapiro 1806159609Sgshapiro 1807159609Sgshapirovoid LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 1808159609Sgshapiro LIR_Code code = op->code(); 1809159609Sgshapiro if (code == lir_store_check) { 1810159609Sgshapiro Register value = op->object()->as_register(); 1811159609Sgshapiro Register array = op->array()->as_register(); 1812159609Sgshapiro Register k_RInfo = op->tmp1()->as_register(); 1813159609Sgshapiro Register klass_RInfo = op->tmp2()->as_register(); 1814159609Sgshapiro Register Rtmp1 = op->tmp3()->as_register(); 1815159609Sgshapiro 1816159609Sgshapiro CodeStub* stub = op->stub(); 1817159609Sgshapiro 1818159609Sgshapiro // check if it needs to be profiled 1819159609Sgshapiro ciMethodData* md; 1820159609Sgshapiro ciProfileData* data; 1821159609Sgshapiro 1822159609Sgshapiro if (op->should_profile()) { 1823159609Sgshapiro ciMethod* method = op->profiled_method(); 1824159609Sgshapiro assert(method != NULL, "Should have method"); 1825159609Sgshapiro int bci = op->profiled_bci(); 1826159609Sgshapiro md = method->method_data_or_null(); 1827159609Sgshapiro assert(md != NULL, "Sanity"); 1828159609Sgshapiro data = md->bci_to_data(bci); 1829159609Sgshapiro assert(data != NULL, "need data for type check"); 1830159609Sgshapiro assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 1831159609Sgshapiro } 1832159609Sgshapiro Label profile_cast_success, profile_cast_failure, done; 1833159609Sgshapiro Label *success_target = op->should_profile() ? &profile_cast_success : &done; 1834159609Sgshapiro Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 1835159609Sgshapiro 1836159609Sgshapiro __ cmpptr(value, (int32_t)NULL_WORD); 1837159609Sgshapiro if (op->should_profile()) { 1838159609Sgshapiro Label not_null; 1839159609Sgshapiro __ jccb(Assembler::notEqual, not_null); 1840159609Sgshapiro // Object is null; update MDO and exit 1841159609Sgshapiro Register mdo = klass_RInfo; 1842159609Sgshapiro __ movoop(mdo, md->constant_encoding()); 1843159609Sgshapiro Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::header_offset())); 1844159609Sgshapiro int header_bits = DataLayout::flag_mask_to_header_mask(BitData::null_seen_byte_constant()); 1845159609Sgshapiro __ orl(data_addr, header_bits); 1846159609Sgshapiro __ jmp(done); 1847159609Sgshapiro __ bind(not_null); 1848159609Sgshapiro } else { 1849159609Sgshapiro __ jcc(Assembler::equal, done); 1850159609Sgshapiro } 1851159609Sgshapiro 1852159609Sgshapiro add_debug_info_for_null_check_here(op->info_for_exception()); 1853159609Sgshapiro __ load_klass(k_RInfo, array); 1854159609Sgshapiro __ load_klass(klass_RInfo, value); 1855159609Sgshapiro 1856159609Sgshapiro // get instance klass (it's already uncompressed) 1857159609Sgshapiro __ movptr(k_RInfo, Address(k_RInfo, objArrayKlass::element_klass_offset())); 1858159609Sgshapiro // perform the fast part of the checking logic 1859159609Sgshapiro __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL); 1860159609Sgshapiro // call out-of-line instance of __ check_klass_subtype_slow_path(...): 1861159609Sgshapiro __ push(klass_RInfo); 1862159609Sgshapiro __ push(k_RInfo); 1863159609Sgshapiro __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 1864159609Sgshapiro __ pop(klass_RInfo); 1865159609Sgshapiro __ pop(k_RInfo); 1866159609Sgshapiro // result is a boolean 1867159609Sgshapiro __ cmpl(k_RInfo, 0); 1868159609Sgshapiro __ jcc(Assembler::equal, *failure_target); 1869159609Sgshapiro // fall through to the success case 1870159609Sgshapiro 1871159609Sgshapiro if (op->should_profile()) { 1872159609Sgshapiro Register mdo = klass_RInfo, recv = k_RInfo; 1873159609Sgshapiro __ bind(profile_cast_success); 1874159609Sgshapiro __ movoop(mdo, md->constant_encoding()); 1875159609Sgshapiro __ load_klass(recv, value); 1876159609Sgshapiro Label update_done; 1877159609Sgshapiro type_profile_helper(mdo, md, data, recv, &done); 1878159609Sgshapiro __ jmpb(done); 187964562Sgshapiro 188064562Sgshapiro __ bind(profile_cast_failure); 188164562Sgshapiro __ movoop(mdo, md->constant_encoding()); 188264562Sgshapiro Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 188364562Sgshapiro __ subptr(counter_addr, DataLayout::counter_increment); 188464562Sgshapiro __ jmp(*stub->entry()); 188564562Sgshapiro } 188664562Sgshapiro 188764562Sgshapiro __ bind(done); 1888159609Sgshapiro } else 188964562Sgshapiro if (code == lir_checkcast) { 189064562Sgshapiro Register obj = op->object()->as_register(); 189164562Sgshapiro Register dst = op->result_opr()->as_register(); 189264562Sgshapiro Label success; 189364562Sgshapiro emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 189464562Sgshapiro __ bind(success); 189564562Sgshapiro if (dst != obj) { 189664562Sgshapiro __ mov(dst, obj); 1897159609Sgshapiro } 1898159609Sgshapiro } else 1899159609Sgshapiro if (code == lir_instanceof) { 1900159609Sgshapiro Register obj = op->object()->as_register(); 1901159609Sgshapiro Register dst = op->result_opr()->as_register(); 1902159609Sgshapiro Label success, failure, done; 1903159609Sgshapiro emit_typecheck_helper(op, &success, &failure, &failure); 1904159609Sgshapiro __ bind(failure); 1905159609Sgshapiro __ xorptr(dst, dst); 1906159609Sgshapiro __ jmpb(done); 1907159609Sgshapiro __ bind(success); 1908159609Sgshapiro __ movptr(dst, 1); 1909159609Sgshapiro __ bind(done); 1910159609Sgshapiro } else { 1911159609Sgshapiro ShouldNotReachHere(); 1912159609Sgshapiro } 1913159609Sgshapiro 1914159609Sgshapiro} 1915159609Sgshapiro 1916159609Sgshapiro 1917159609Sgshapirovoid LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 1918159609Sgshapiro if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) { 1919159609Sgshapiro assert(op->cmp_value()->as_register_lo() == rax, "wrong register"); 1920159609Sgshapiro assert(op->cmp_value()->as_register_hi() == rdx, "wrong register"); 1921159609Sgshapiro assert(op->new_value()->as_register_lo() == rbx, "wrong register"); 1922159609Sgshapiro assert(op->new_value()->as_register_hi() == rcx, "wrong register"); 1923159609Sgshapiro Register addr = op->addr()->as_register(); 1924159609Sgshapiro if (os::is_MP()) { 1925159609Sgshapiro __ lock(); 1926159609Sgshapiro } 1927159609Sgshapiro NOT_LP64(__ cmpxchg8(Address(addr, 0))); 1928159609Sgshapiro 1929159609Sgshapiro } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) { 1930159609Sgshapiro NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");) 1931159609Sgshapiro Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1932159609Sgshapiro Register newval = op->new_value()->as_register(); 1933159609Sgshapiro Register cmpval = op->cmp_value()->as_register(); 1934159609Sgshapiro assert(cmpval == rax, "wrong register"); 1935159609Sgshapiro assert(newval != NULL, "new val must be register"); 1936159609Sgshapiro assert(cmpval != newval, "cmp and new values must be in different registers"); 1937159609Sgshapiro assert(cmpval != addr, "cmp and addr must be in different registers"); 1938159609Sgshapiro assert(newval != addr, "new value and addr must be in different registers"); 1939159609Sgshapiro 1940159609Sgshapiro if ( op->code() == lir_cas_obj) { 1941159609Sgshapiro#ifdef _LP64 1942159609Sgshapiro if (UseCompressedOops) { 1943159609Sgshapiro __ encode_heap_oop(cmpval); 1944159609Sgshapiro __ mov(rscratch1, newval); 1945159609Sgshapiro __ encode_heap_oop(rscratch1); 1946159609Sgshapiro if (os::is_MP()) { 1947159609Sgshapiro __ lock(); 1948159609Sgshapiro } 1949159609Sgshapiro // cmpval (rax) is implicitly used by this instruction 1950159609Sgshapiro __ cmpxchgl(rscratch1, Address(addr, 0)); 1951159609Sgshapiro } else 1952159609Sgshapiro#endif 1953159609Sgshapiro { 1954159609Sgshapiro if (os::is_MP()) { 1955159609Sgshapiro __ lock(); 1956159609Sgshapiro } 1957159609Sgshapiro __ cmpxchgptr(newval, Address(addr, 0)); 1958159609Sgshapiro } 1959159609Sgshapiro } else { 1960159609Sgshapiro assert(op->code() == lir_cas_int, "lir_cas_int expected"); 1961159609Sgshapiro if (os::is_MP()) { 1962159609Sgshapiro __ lock(); 1963159609Sgshapiro } 1964159609Sgshapiro __ cmpxchgl(newval, Address(addr, 0)); 1965159609Sgshapiro } 1966159609Sgshapiro#ifdef _LP64 1967159609Sgshapiro } else if (op->code() == lir_cas_long) { 1968159609Sgshapiro Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo()); 1969159609Sgshapiro Register newval = op->new_value()->as_register_lo(); 1970159609Sgshapiro Register cmpval = op->cmp_value()->as_register_lo(); 1971159609Sgshapiro assert(cmpval == rax, "wrong register"); 1972159609Sgshapiro assert(newval != NULL, "new val must be register"); 1973159609Sgshapiro assert(cmpval != newval, "cmp and new values must be in different registers"); 1974159609Sgshapiro assert(cmpval != addr, "cmp and addr must be in different registers"); 1975159609Sgshapiro assert(newval != addr, "new value and addr must be in different registers"); 1976159609Sgshapiro if (os::is_MP()) { 1977159609Sgshapiro __ lock(); 1978159609Sgshapiro } 1979159609Sgshapiro __ cmpxchgq(newval, Address(addr, 0)); 1980159609Sgshapiro#endif // _LP64 1981159609Sgshapiro } else { 1982159609Sgshapiro Unimplemented(); 1983159609Sgshapiro } 1984159609Sgshapiro} 1985159609Sgshapiro 1986159609Sgshapirovoid LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1987159609Sgshapiro Assembler::Condition acond, ncond; 1988159609Sgshapiro switch (condition) { 1989159609Sgshapiro case lir_cond_equal: acond = Assembler::equal; ncond = Assembler::notEqual; break; 1990159609Sgshapiro case lir_cond_notEqual: acond = Assembler::notEqual; ncond = Assembler::equal; break; 1991159609Sgshapiro case lir_cond_less: acond = Assembler::less; ncond = Assembler::greaterEqual; break; 1992159609Sgshapiro case lir_cond_lessEqual: acond = Assembler::lessEqual; ncond = Assembler::greater; break; 1993159609Sgshapiro case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less; break; 1994159609Sgshapiro case lir_cond_greater: acond = Assembler::greater; ncond = Assembler::lessEqual; break; 1995159609Sgshapiro case lir_cond_belowEqual: acond = Assembler::belowEqual; ncond = Assembler::above; break; 1996159609Sgshapiro case lir_cond_aboveEqual: acond = Assembler::aboveEqual; ncond = Assembler::below; break; 1997159609Sgshapiro default: ShouldNotReachHere(); 1998159609Sgshapiro } 1999159609Sgshapiro 2000159609Sgshapiro if (opr1->is_cpu_register()) { 2001159609Sgshapiro reg2reg(opr1, result); 2002159609Sgshapiro } else if (opr1->is_stack()) { 2003159609Sgshapiro stack2reg(opr1, result, result->type()); 2004159609Sgshapiro } else if (opr1->is_constant()) { 2005159609Sgshapiro const2reg(opr1, result, lir_patch_none, NULL); 2006159609Sgshapiro } else { 2007159609Sgshapiro ShouldNotReachHere(); 2008159609Sgshapiro } 2009159609Sgshapiro 2010159609Sgshapiro if (VM_Version::supports_cmov() && !opr2->is_constant()) { 2011159609Sgshapiro // optimized version that does not require a branch 2012159609Sgshapiro if (opr2->is_single_cpu()) { 2013159609Sgshapiro assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move"); 2014159609Sgshapiro __ cmov(ncond, result->as_register(), opr2->as_register()); 2015159609Sgshapiro } else if (opr2->is_double_cpu()) { 2016159609Sgshapiro assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2017159609Sgshapiro assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move"); 2018159609Sgshapiro __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo()); 2019159609Sgshapiro NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());) 2020159609Sgshapiro } else if (opr2->is_single_stack()) { 2021159609Sgshapiro __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix())); 2022159609Sgshapiro } else if (opr2->is_double_stack()) { 2023159609Sgshapiro __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes)); 2024159609Sgshapiro NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));) 2025159609Sgshapiro } else { 2026159609Sgshapiro ShouldNotReachHere(); 2027159609Sgshapiro } 2028159609Sgshapiro 2029159609Sgshapiro } else { 2030159609Sgshapiro Label skip; 2031159609Sgshapiro __ jcc (acond, skip); 2032159609Sgshapiro if (opr2->is_cpu_register()) { 2033159609Sgshapiro reg2reg(opr2, result); 2034159609Sgshapiro } else if (opr2->is_stack()) { 2035159609Sgshapiro stack2reg(opr2, result, result->type()); 2036159609Sgshapiro } else if (opr2->is_constant()) { 2037159609Sgshapiro const2reg(opr2, result, lir_patch_none, NULL); 2038159609Sgshapiro } else { 2039159609Sgshapiro ShouldNotReachHere(); 2040159609Sgshapiro } 2041159609Sgshapiro __ bind(skip); 2042159609Sgshapiro } 2043159609Sgshapiro} 2044159609Sgshapiro 2045159609Sgshapiro 2046159609Sgshapirovoid LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 2047159609Sgshapiro assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method"); 2048159609Sgshapiro 2049159609Sgshapiro if (left->is_single_cpu()) { 2050159609Sgshapiro assert(left == dest, "left and dest must be equal"); 2051159609Sgshapiro Register lreg = left->as_register(); 2052159609Sgshapiro 2053159609Sgshapiro if (right->is_single_cpu()) { 2054159609Sgshapiro // cpu register - cpu register 2055159609Sgshapiro Register rreg = right->as_register(); 2056159609Sgshapiro switch (code) { 2057159609Sgshapiro case lir_add: __ addl (lreg, rreg); break; 2058159609Sgshapiro case lir_sub: __ subl (lreg, rreg); break; 2059159609Sgshapiro case lir_mul: __ imull(lreg, rreg); break; 2060159609Sgshapiro default: ShouldNotReachHere(); 2061159609Sgshapiro } 2062159609Sgshapiro 2063159609Sgshapiro } else if (right->is_stack()) { 2064159609Sgshapiro // cpu register - stack 2065159609Sgshapiro Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2066159609Sgshapiro switch (code) { 2067159609Sgshapiro case lir_add: __ addl(lreg, raddr); break; 2068159609Sgshapiro case lir_sub: __ subl(lreg, raddr); break; 2069159609Sgshapiro default: ShouldNotReachHere(); 2070159609Sgshapiro } 2071159609Sgshapiro 2072159609Sgshapiro } else if (right->is_constant()) { 2073159609Sgshapiro // cpu register - constant 2074159609Sgshapiro jint c = right->as_constant_ptr()->as_jint(); 2075159609Sgshapiro switch (code) { 2076159609Sgshapiro case lir_add: { 2077159609Sgshapiro __ incrementl(lreg, c); 2078159609Sgshapiro break; 2079159609Sgshapiro } 2080159609Sgshapiro case lir_sub: { 2081159609Sgshapiro __ decrementl(lreg, c); 2082159609Sgshapiro break; 2083159609Sgshapiro } 2084159609Sgshapiro default: ShouldNotReachHere(); 2085159609Sgshapiro } 2086159609Sgshapiro 2087159609Sgshapiro } else { 2088159609Sgshapiro ShouldNotReachHere(); 2089159609Sgshapiro } 2090159609Sgshapiro 2091159609Sgshapiro } else if (left->is_double_cpu()) { 2092159609Sgshapiro assert(left == dest, "left and dest must be equal"); 2093159609Sgshapiro Register lreg_lo = left->as_register_lo(); 2094159609Sgshapiro Register lreg_hi = left->as_register_hi(); 2095159609Sgshapiro 2096159609Sgshapiro if (right->is_double_cpu()) { 2097159609Sgshapiro // cpu register - cpu register 2098159609Sgshapiro Register rreg_lo = right->as_register_lo(); 2099159609Sgshapiro Register rreg_hi = right->as_register_hi(); 2100159609Sgshapiro NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi)); 2101159609Sgshapiro LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo)); 2102159609Sgshapiro switch (code) { 2103159609Sgshapiro case lir_add: 2104159609Sgshapiro __ addptr(lreg_lo, rreg_lo); 2105159609Sgshapiro NOT_LP64(__ adcl(lreg_hi, rreg_hi)); 2106159609Sgshapiro break; 2107159609Sgshapiro case lir_sub: 2108159609Sgshapiro __ subptr(lreg_lo, rreg_lo); 2109159609Sgshapiro NOT_LP64(__ sbbl(lreg_hi, rreg_hi)); 2110159609Sgshapiro break; 2111159609Sgshapiro case lir_mul: 2112159609Sgshapiro#ifdef _LP64 2113159609Sgshapiro __ imulq(lreg_lo, rreg_lo); 2114159609Sgshapiro#else 2115159609Sgshapiro assert(lreg_lo == rax && lreg_hi == rdx, "must be"); 2116159609Sgshapiro __ imull(lreg_hi, rreg_lo); 2117159609Sgshapiro __ imull(rreg_hi, lreg_lo); 2118159609Sgshapiro __ addl (rreg_hi, lreg_hi); 2119159609Sgshapiro __ mull (rreg_lo); 2120159609Sgshapiro __ addl (lreg_hi, rreg_hi); 2121159609Sgshapiro#endif // _LP64 2122159609Sgshapiro break; 2123159609Sgshapiro default: 2124159609Sgshapiro ShouldNotReachHere(); 2125159609Sgshapiro } 2126159609Sgshapiro 2127159609Sgshapiro } else if (right->is_constant()) { 2128159609Sgshapiro // cpu register - constant 2129159609Sgshapiro#ifdef _LP64 2130159609Sgshapiro jlong c = right->as_constant_ptr()->as_jlong_bits(); 2131159609Sgshapiro __ movptr(r10, (intptr_t) c); 2132159609Sgshapiro switch (code) { 2133159609Sgshapiro case lir_add: 2134159609Sgshapiro __ addptr(lreg_lo, r10); 2135159609Sgshapiro break; 2136159609Sgshapiro case lir_sub: 2137159609Sgshapiro __ subptr(lreg_lo, r10); 2138159609Sgshapiro break; 2139159609Sgshapiro default: 2140159609Sgshapiro ShouldNotReachHere(); 2141159609Sgshapiro } 2142159609Sgshapiro#else 2143159609Sgshapiro jint c_lo = right->as_constant_ptr()->as_jint_lo(); 2144159609Sgshapiro jint c_hi = right->as_constant_ptr()->as_jint_hi(); 2145159609Sgshapiro switch (code) { 2146159609Sgshapiro case lir_add: 2147159609Sgshapiro __ addptr(lreg_lo, c_lo); 2148159609Sgshapiro __ adcl(lreg_hi, c_hi); 2149159609Sgshapiro break; 2150159609Sgshapiro case lir_sub: 2151159609Sgshapiro __ subptr(lreg_lo, c_lo); 2152159609Sgshapiro __ sbbl(lreg_hi, c_hi); 2153159609Sgshapiro break; 2154159609Sgshapiro default: 2155159609Sgshapiro ShouldNotReachHere(); 2156159609Sgshapiro } 2157159609Sgshapiro#endif // _LP64 2158159609Sgshapiro 2159159609Sgshapiro } else { 2160159609Sgshapiro ShouldNotReachHere(); 2161159609Sgshapiro } 2162159609Sgshapiro 2163159609Sgshapiro } else if (left->is_single_xmm()) { 2164159609Sgshapiro assert(left == dest, "left and dest must be equal"); 2165159609Sgshapiro XMMRegister lreg = left->as_xmm_float_reg(); 2166159609Sgshapiro 2167159609Sgshapiro if (right->is_single_xmm()) { 2168159609Sgshapiro XMMRegister rreg = right->as_xmm_float_reg(); 2169159609Sgshapiro switch (code) { 2170159609Sgshapiro case lir_add: __ addss(lreg, rreg); break; 2171159609Sgshapiro case lir_sub: __ subss(lreg, rreg); break; 2172159609Sgshapiro case lir_mul_strictfp: // fall through 2173159609Sgshapiro case lir_mul: __ mulss(lreg, rreg); break; 2174159609Sgshapiro case lir_div_strictfp: // fall through 2175159609Sgshapiro case lir_div: __ divss(lreg, rreg); break; 2176159609Sgshapiro default: ShouldNotReachHere(); 2177159609Sgshapiro } 2178159609Sgshapiro } else { 2179159609Sgshapiro Address raddr; 2180159609Sgshapiro if (right->is_single_stack()) { 2181159609Sgshapiro raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2182159609Sgshapiro } else if (right->is_constant()) { 2183159609Sgshapiro // hack for now 2184159609Sgshapiro raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat()))); 2185159609Sgshapiro } else { 2186159609Sgshapiro ShouldNotReachHere(); 2187159609Sgshapiro } 2188159609Sgshapiro switch (code) { 2189159609Sgshapiro case lir_add: __ addss(lreg, raddr); break; 2190159609Sgshapiro case lir_sub: __ subss(lreg, raddr); break; 2191159609Sgshapiro case lir_mul_strictfp: // fall through 2192159609Sgshapiro case lir_mul: __ mulss(lreg, raddr); break; 2193159609Sgshapiro case lir_div_strictfp: // fall through 2194159609Sgshapiro case lir_div: __ divss(lreg, raddr); break; 2195159609Sgshapiro default: ShouldNotReachHere(); 2196159609Sgshapiro } 2197159609Sgshapiro } 2198159609Sgshapiro 2199159609Sgshapiro } else if (left->is_double_xmm()) { 2200159609Sgshapiro assert(left == dest, "left and dest must be equal"); 2201159609Sgshapiro 2202159609Sgshapiro XMMRegister lreg = left->as_xmm_double_reg(); 2203159609Sgshapiro if (right->is_double_xmm()) { 2204159609Sgshapiro XMMRegister rreg = right->as_xmm_double_reg(); 2205159609Sgshapiro switch (code) { 2206159609Sgshapiro case lir_add: __ addsd(lreg, rreg); break; 2207159609Sgshapiro case lir_sub: __ subsd(lreg, rreg); break; 2208159609Sgshapiro case lir_mul_strictfp: // fall through 2209159609Sgshapiro case lir_mul: __ mulsd(lreg, rreg); break; 2210159609Sgshapiro case lir_div_strictfp: // fall through 2211159609Sgshapiro case lir_div: __ divsd(lreg, rreg); break; 2212159609Sgshapiro default: ShouldNotReachHere(); 2213159609Sgshapiro } 2214159609Sgshapiro } else { 2215159609Sgshapiro Address raddr; 2216159609Sgshapiro if (right->is_double_stack()) { 2217159609Sgshapiro raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2218159609Sgshapiro } else if (right->is_constant()) { 221964562Sgshapiro // hack for now 222064562Sgshapiro raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 222180785Sgshapiro } else { 222280785Sgshapiro ShouldNotReachHere(); 222380785Sgshapiro } 222480785Sgshapiro switch (code) { 222580785Sgshapiro case lir_add: __ addsd(lreg, raddr); break; 222680785Sgshapiro case lir_sub: __ subsd(lreg, raddr); break; 2227159609Sgshapiro case lir_mul_strictfp: // fall through 222880785Sgshapiro case lir_mul: __ mulsd(lreg, raddr); break; 222980785Sgshapiro case lir_div_strictfp: // fall through 223080785Sgshapiro case lir_div: __ divsd(lreg, raddr); break; 223180785Sgshapiro default: ShouldNotReachHere(); 223280785Sgshapiro } 2233159609Sgshapiro } 2234159609Sgshapiro 2235159609Sgshapiro } else if (left->is_single_fpu()) { 2236159609Sgshapiro assert(dest->is_single_fpu(), "fpu stack allocation required"); 2237159609Sgshapiro 2238159609Sgshapiro if (right->is_single_fpu()) { 2239159609Sgshapiro arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack); 2240159609Sgshapiro 2241159609Sgshapiro } else { 2242159609Sgshapiro assert(left->fpu_regnr() == 0, "left must be on TOS"); 2243159609Sgshapiro assert(dest->fpu_regnr() == 0, "dest must be on TOS"); 2244159609Sgshapiro 2245159609Sgshapiro Address raddr; 2246159609Sgshapiro if (right->is_single_stack()) { 2247159609Sgshapiro raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2248159609Sgshapiro } else if (right->is_constant()) { 2249159609Sgshapiro address const_addr = float_constant(right->as_jfloat()); 2250159609Sgshapiro assert(const_addr != NULL, "incorrect float/double constant maintainance"); 2251159609Sgshapiro // hack for now 225280785Sgshapiro raddr = __ as_Address(InternalAddress(const_addr)); 225380785Sgshapiro } else { 225480785Sgshapiro ShouldNotReachHere(); 2255159609Sgshapiro } 2256159609Sgshapiro 2257159609Sgshapiro switch (code) { 2258159609Sgshapiro case lir_add: __ fadd_s(raddr); break; 2259159609Sgshapiro case lir_sub: __ fsub_s(raddr); break; 226080785Sgshapiro case lir_mul_strictfp: // fall through 226180785Sgshapiro case lir_mul: __ fmul_s(raddr); break; 2262159609Sgshapiro case lir_div_strictfp: // fall through 2263159609Sgshapiro case lir_div: __ fdiv_s(raddr); break; 2264159609Sgshapiro default: ShouldNotReachHere(); 2265159609Sgshapiro } 2266159609Sgshapiro } 2267159609Sgshapiro 2268159609Sgshapiro } else if (left->is_double_fpu()) { 2269159609Sgshapiro assert(dest->is_double_fpu(), "fpu stack allocation required"); 2270159609Sgshapiro 2271159609Sgshapiro if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2272159609Sgshapiro // Double values require special handling for strictfp mul/div on x86 2273159609Sgshapiro __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1())); 2274159609Sgshapiro __ fmulp(left->fpu_regnrLo() + 1); 2275159609Sgshapiro } 2276159609Sgshapiro 2277159609Sgshapiro if (right->is_double_fpu()) { 2278159609Sgshapiro arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack); 2279159609Sgshapiro 2280159609Sgshapiro } else { 2281159609Sgshapiro assert(left->fpu_regnrLo() == 0, "left must be on TOS"); 2282159609Sgshapiro assert(dest->fpu_regnrLo() == 0, "dest must be on TOS"); 2283159609Sgshapiro 2284159609Sgshapiro Address raddr; 2285159609Sgshapiro if (right->is_double_stack()) { 2286159609Sgshapiro raddr = frame_map()->address_for_slot(right->double_stack_ix()); 2287159609Sgshapiro } else if (right->is_constant()) { 2288159609Sgshapiro // hack for now 2289159609Sgshapiro raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble()))); 2290159609Sgshapiro } else { 2291159609Sgshapiro ShouldNotReachHere(); 2292159609Sgshapiro } 2293159609Sgshapiro 2294159609Sgshapiro switch (code) { 2295159609Sgshapiro case lir_add: __ fadd_d(raddr); break; 2296159609Sgshapiro case lir_sub: __ fsub_d(raddr); break; 2297159609Sgshapiro case lir_mul_strictfp: // fall through 2298159609Sgshapiro case lir_mul: __ fmul_d(raddr); break; 229980785Sgshapiro case lir_div_strictfp: // fall through 230080785Sgshapiro case lir_div: __ fdiv_d(raddr); break; 2301244833Sgshapiro default: ShouldNotReachHere(); 2302 } 2303 } 2304 2305 if (code == lir_mul_strictfp || code == lir_div_strictfp) { 2306 // Double values require special handling for strictfp mul/div on x86 2307 __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2())); 2308 __ fmulp(dest->fpu_regnrLo() + 1); 2309 } 2310 2311 } else if (left->is_single_stack() || left->is_address()) { 2312 assert(left == dest, "left and dest must be equal"); 2313 2314 Address laddr; 2315 if (left->is_single_stack()) { 2316 laddr = frame_map()->address_for_slot(left->single_stack_ix()); 2317 } else if (left->is_address()) { 2318 laddr = as_Address(left->as_address_ptr()); 2319 } else { 2320 ShouldNotReachHere(); 2321 } 2322 2323 if (right->is_single_cpu()) { 2324 Register rreg = right->as_register(); 2325 switch (code) { 2326 case lir_add: __ addl(laddr, rreg); break; 2327 case lir_sub: __ subl(laddr, rreg); break; 2328 default: ShouldNotReachHere(); 2329 } 2330 } else if (right->is_constant()) { 2331 jint c = right->as_constant_ptr()->as_jint(); 2332 switch (code) { 2333 case lir_add: { 2334 __ incrementl(laddr, c); 2335 break; 2336 } 2337 case lir_sub: { 2338 __ decrementl(laddr, c); 2339 break; 2340 } 2341 default: ShouldNotReachHere(); 2342 } 2343 } else { 2344 ShouldNotReachHere(); 2345 } 2346 2347 } else { 2348 ShouldNotReachHere(); 2349 } 2350} 2351 2352void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { 2353 assert(pop_fpu_stack || (left_index == dest_index || right_index == dest_index), "invalid LIR"); 2354 assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR"); 2355 assert(left_index == 0 || right_index == 0, "either must be on top of stack"); 2356 2357 bool left_is_tos = (left_index == 0); 2358 bool dest_is_tos = (dest_index == 0); 2359 int non_tos_index = (left_is_tos ? right_index : left_index); 2360 2361 switch (code) { 2362 case lir_add: 2363 if (pop_fpu_stack) __ faddp(non_tos_index); 2364 else if (dest_is_tos) __ fadd (non_tos_index); 2365 else __ fadda(non_tos_index); 2366 break; 2367 2368 case lir_sub: 2369 if (left_is_tos) { 2370 if (pop_fpu_stack) __ fsubrp(non_tos_index); 2371 else if (dest_is_tos) __ fsub (non_tos_index); 2372 else __ fsubra(non_tos_index); 2373 } else { 2374 if (pop_fpu_stack) __ fsubp (non_tos_index); 2375 else if (dest_is_tos) __ fsubr (non_tos_index); 2376 else __ fsuba (non_tos_index); 2377 } 2378 break; 2379 2380 case lir_mul_strictfp: // fall through 2381 case lir_mul: 2382 if (pop_fpu_stack) __ fmulp(non_tos_index); 2383 else if (dest_is_tos) __ fmul (non_tos_index); 2384 else __ fmula(non_tos_index); 2385 break; 2386 2387 case lir_div_strictfp: // fall through 2388 case lir_div: 2389 if (left_is_tos) { 2390 if (pop_fpu_stack) __ fdivrp(non_tos_index); 2391 else if (dest_is_tos) __ fdiv (non_tos_index); 2392 else __ fdivra(non_tos_index); 2393 } else { 2394 if (pop_fpu_stack) __ fdivp (non_tos_index); 2395 else if (dest_is_tos) __ fdivr (non_tos_index); 2396 else __ fdiva (non_tos_index); 2397 } 2398 break; 2399 2400 case lir_rem: 2401 assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation"); 2402 __ fremr(noreg); 2403 break; 2404 2405 default: 2406 ShouldNotReachHere(); 2407 } 2408} 2409 2410 2411void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) { 2412 if (value->is_double_xmm()) { 2413 switch(code) { 2414 case lir_abs : 2415 { 2416 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) { 2417 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); 2418 } 2419 __ andpd(dest->as_xmm_double_reg(), 2420 ExternalAddress((address)double_signmask_pool)); 2421 } 2422 break; 2423 2424 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break; 2425 // all other intrinsics are not available in the SSE instruction set, so FPU is used 2426 default : ShouldNotReachHere(); 2427 } 2428 2429 } else if (value->is_double_fpu()) { 2430 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS"); 2431 switch(code) { 2432 case lir_log : __ flog() ; break; 2433 case lir_log10 : __ flog10() ; break; 2434 case lir_abs : __ fabs() ; break; 2435 case lir_sqrt : __ fsqrt(); break; 2436 case lir_sin : 2437 // Should consider not saving rbx, if not necessary 2438 __ trigfunc('s', op->as_Op2()->fpu_stack_size()); 2439 break; 2440 case lir_cos : 2441 // Should consider not saving rbx, if not necessary 2442 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots"); 2443 __ trigfunc('c', op->as_Op2()->fpu_stack_size()); 2444 break; 2445 case lir_tan : 2446 // Should consider not saving rbx, if not necessary 2447 __ trigfunc('t', op->as_Op2()->fpu_stack_size()); 2448 break; 2449 case lir_exp : 2450 __ exp_with_fallback(op->as_Op2()->fpu_stack_size()); 2451 break; 2452 case lir_pow : 2453 __ pow_with_fallback(op->as_Op2()->fpu_stack_size()); 2454 break; 2455 default : ShouldNotReachHere(); 2456 } 2457 } else { 2458 Unimplemented(); 2459 } 2460} 2461 2462void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) { 2463 // assert(left->destroys_register(), "check"); 2464 if (left->is_single_cpu()) { 2465 Register reg = left->as_register(); 2466 if (right->is_constant()) { 2467 int val = right->as_constant_ptr()->as_jint(); 2468 switch (code) { 2469 case lir_logic_and: __ andl (reg, val); break; 2470 case lir_logic_or: __ orl (reg, val); break; 2471 case lir_logic_xor: __ xorl (reg, val); break; 2472 default: ShouldNotReachHere(); 2473 } 2474 } else if (right->is_stack()) { 2475 // added support for stack operands 2476 Address raddr = frame_map()->address_for_slot(right->single_stack_ix()); 2477 switch (code) { 2478 case lir_logic_and: __ andl (reg, raddr); break; 2479 case lir_logic_or: __ orl (reg, raddr); break; 2480 case lir_logic_xor: __ xorl (reg, raddr); break; 2481 default: ShouldNotReachHere(); 2482 } 2483 } else { 2484 Register rright = right->as_register(); 2485 switch (code) { 2486 case lir_logic_and: __ andptr (reg, rright); break; 2487 case lir_logic_or : __ orptr (reg, rright); break; 2488 case lir_logic_xor: __ xorptr (reg, rright); break; 2489 default: ShouldNotReachHere(); 2490 } 2491 } 2492 move_regs(reg, dst->as_register()); 2493 } else { 2494 Register l_lo = left->as_register_lo(); 2495 Register l_hi = left->as_register_hi(); 2496 if (right->is_constant()) { 2497#ifdef _LP64 2498 __ mov64(rscratch1, right->as_constant_ptr()->as_jlong()); 2499 switch (code) { 2500 case lir_logic_and: 2501 __ andq(l_lo, rscratch1); 2502 break; 2503 case lir_logic_or: 2504 __ orq(l_lo, rscratch1); 2505 break; 2506 case lir_logic_xor: 2507 __ xorq(l_lo, rscratch1); 2508 break; 2509 default: ShouldNotReachHere(); 2510 } 2511#else 2512 int r_lo = right->as_constant_ptr()->as_jint_lo(); 2513 int r_hi = right->as_constant_ptr()->as_jint_hi(); 2514 switch (code) { 2515 case lir_logic_and: 2516 __ andl(l_lo, r_lo); 2517 __ andl(l_hi, r_hi); 2518 break; 2519 case lir_logic_or: 2520 __ orl(l_lo, r_lo); 2521 __ orl(l_hi, r_hi); 2522 break; 2523 case lir_logic_xor: 2524 __ xorl(l_lo, r_lo); 2525 __ xorl(l_hi, r_hi); 2526 break; 2527 default: ShouldNotReachHere(); 2528 } 2529#endif // _LP64 2530 } else { 2531#ifdef _LP64 2532 Register r_lo; 2533 if (right->type() == T_OBJECT || right->type() == T_ARRAY) { 2534 r_lo = right->as_register(); 2535 } else { 2536 r_lo = right->as_register_lo(); 2537 } 2538#else 2539 Register r_lo = right->as_register_lo(); 2540 Register r_hi = right->as_register_hi(); 2541 assert(l_lo != r_hi, "overwriting registers"); 2542#endif 2543 switch (code) { 2544 case lir_logic_and: 2545 __ andptr(l_lo, r_lo); 2546 NOT_LP64(__ andptr(l_hi, r_hi);) 2547 break; 2548 case lir_logic_or: 2549 __ orptr(l_lo, r_lo); 2550 NOT_LP64(__ orptr(l_hi, r_hi);) 2551 break; 2552 case lir_logic_xor: 2553 __ xorptr(l_lo, r_lo); 2554 NOT_LP64(__ xorptr(l_hi, r_hi);) 2555 break; 2556 default: ShouldNotReachHere(); 2557 } 2558 } 2559 2560 Register dst_lo = dst->as_register_lo(); 2561 Register dst_hi = dst->as_register_hi(); 2562 2563#ifdef _LP64 2564 move_regs(l_lo, dst_lo); 2565#else 2566 if (dst_lo == l_hi) { 2567 assert(dst_hi != l_lo, "overwriting registers"); 2568 move_regs(l_hi, dst_hi); 2569 move_regs(l_lo, dst_lo); 2570 } else { 2571 assert(dst_lo != l_hi, "overwriting registers"); 2572 move_regs(l_lo, dst_lo); 2573 move_regs(l_hi, dst_hi); 2574 } 2575#endif // _LP64 2576 } 2577} 2578 2579 2580// we assume that rax, and rdx can be overwritten 2581void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) { 2582 2583 assert(left->is_single_cpu(), "left must be register"); 2584 assert(right->is_single_cpu() || right->is_constant(), "right must be register or constant"); 2585 assert(result->is_single_cpu(), "result must be register"); 2586 2587 // assert(left->destroys_register(), "check"); 2588 // assert(right->destroys_register(), "check"); 2589 2590 Register lreg = left->as_register(); 2591 Register dreg = result->as_register(); 2592 2593 if (right->is_constant()) { 2594 int divisor = right->as_constant_ptr()->as_jint(); 2595 assert(divisor > 0 && is_power_of_2(divisor), "must be"); 2596 if (code == lir_idiv) { 2597 assert(lreg == rax, "must be rax,"); 2598 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2599 __ cdql(); // sign extend into rdx:rax 2600 if (divisor == 2) { 2601 __ subl(lreg, rdx); 2602 } else { 2603 __ andl(rdx, divisor - 1); 2604 __ addl(lreg, rdx); 2605 } 2606 __ sarl(lreg, log2_intptr(divisor)); 2607 move_regs(lreg, dreg); 2608 } else if (code == lir_irem) { 2609 Label done; 2610 __ mov(dreg, lreg); 2611 __ andl(dreg, 0x80000000 | (divisor - 1)); 2612 __ jcc(Assembler::positive, done); 2613 __ decrement(dreg); 2614 __ orl(dreg, ~(divisor - 1)); 2615 __ increment(dreg); 2616 __ bind(done); 2617 } else { 2618 ShouldNotReachHere(); 2619 } 2620 } else { 2621 Register rreg = right->as_register(); 2622 assert(lreg == rax, "left register must be rax,"); 2623 assert(rreg != rdx, "right register must not be rdx"); 2624 assert(temp->as_register() == rdx, "tmp register must be rdx"); 2625 2626 move_regs(lreg, rax); 2627 2628 int idivl_offset = __ corrected_idivl(rreg); 2629 add_debug_info_for_div0(idivl_offset, info); 2630 if (code == lir_irem) { 2631 move_regs(rdx, dreg); // result is in rdx 2632 } else { 2633 move_regs(rax, dreg); 2634 } 2635 } 2636} 2637 2638 2639void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 2640 if (opr1->is_single_cpu()) { 2641 Register reg1 = opr1->as_register(); 2642 if (opr2->is_single_cpu()) { 2643 // cpu register - cpu register 2644 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2645 __ cmpptr(reg1, opr2->as_register()); 2646 } else { 2647 assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?"); 2648 __ cmpl(reg1, opr2->as_register()); 2649 } 2650 } else if (opr2->is_stack()) { 2651 // cpu register - stack 2652 if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) { 2653 __ cmpptr(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2654 } else { 2655 __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2656 } 2657 } else if (opr2->is_constant()) { 2658 // cpu register - constant 2659 LIR_Const* c = opr2->as_constant_ptr(); 2660 if (c->type() == T_INT) { 2661 __ cmpl(reg1, c->as_jint()); 2662 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2663 // In 64bit oops are single register 2664 jobject o = c->as_jobject(); 2665 if (o == NULL) { 2666 __ cmpptr(reg1, (int32_t)NULL_WORD); 2667 } else { 2668#ifdef _LP64 2669 __ movoop(rscratch1, o); 2670 __ cmpptr(reg1, rscratch1); 2671#else 2672 __ cmpoop(reg1, c->as_jobject()); 2673#endif // _LP64 2674 } 2675 } else { 2676 fatal(err_msg("unexpected type: %s", basictype_to_str(c->type()))); 2677 } 2678 // cpu register - address 2679 } else if (opr2->is_address()) { 2680 if (op->info() != NULL) { 2681 add_debug_info_for_null_check_here(op->info()); 2682 } 2683 __ cmpl(reg1, as_Address(opr2->as_address_ptr())); 2684 } else { 2685 ShouldNotReachHere(); 2686 } 2687 2688 } else if(opr1->is_double_cpu()) { 2689 Register xlo = opr1->as_register_lo(); 2690 Register xhi = opr1->as_register_hi(); 2691 if (opr2->is_double_cpu()) { 2692#ifdef _LP64 2693 __ cmpptr(xlo, opr2->as_register_lo()); 2694#else 2695 // cpu register - cpu register 2696 Register ylo = opr2->as_register_lo(); 2697 Register yhi = opr2->as_register_hi(); 2698 __ subl(xlo, ylo); 2699 __ sbbl(xhi, yhi); 2700 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 2701 __ orl(xhi, xlo); 2702 } 2703#endif // _LP64 2704 } else if (opr2->is_constant()) { 2705 // cpu register - constant 0 2706 assert(opr2->as_jlong() == (jlong)0, "only handles zero"); 2707#ifdef _LP64 2708 __ cmpptr(xlo, (int32_t)opr2->as_jlong()); 2709#else 2710 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case"); 2711 __ orl(xhi, xlo); 2712#endif // _LP64 2713 } else { 2714 ShouldNotReachHere(); 2715 } 2716 2717 } else if (opr1->is_single_xmm()) { 2718 XMMRegister reg1 = opr1->as_xmm_float_reg(); 2719 if (opr2->is_single_xmm()) { 2720 // xmm register - xmm register 2721 __ ucomiss(reg1, opr2->as_xmm_float_reg()); 2722 } else if (opr2->is_stack()) { 2723 // xmm register - stack 2724 __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix())); 2725 } else if (opr2->is_constant()) { 2726 // xmm register - constant 2727 __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat()))); 2728 } else if (opr2->is_address()) { 2729 // xmm register - address 2730 if (op->info() != NULL) { 2731 add_debug_info_for_null_check_here(op->info()); 2732 } 2733 __ ucomiss(reg1, as_Address(opr2->as_address_ptr())); 2734 } else { 2735 ShouldNotReachHere(); 2736 } 2737 2738 } else if (opr1->is_double_xmm()) { 2739 XMMRegister reg1 = opr1->as_xmm_double_reg(); 2740 if (opr2->is_double_xmm()) { 2741 // xmm register - xmm register 2742 __ ucomisd(reg1, opr2->as_xmm_double_reg()); 2743 } else if (opr2->is_stack()) { 2744 // xmm register - stack 2745 __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix())); 2746 } else if (opr2->is_constant()) { 2747 // xmm register - constant 2748 __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble()))); 2749 } else if (opr2->is_address()) { 2750 // xmm register - address 2751 if (op->info() != NULL) { 2752 add_debug_info_for_null_check_here(op->info()); 2753 } 2754 __ ucomisd(reg1, as_Address(opr2->pointer()->as_address())); 2755 } else { 2756 ShouldNotReachHere(); 2757 } 2758 2759 } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) { 2760 assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)"); 2761 assert(opr2->is_fpu_register(), "both must be registers"); 2762 __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2763 2764 } else if (opr1->is_address() && opr2->is_constant()) { 2765 LIR_Const* c = opr2->as_constant_ptr(); 2766#ifdef _LP64 2767 if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2768 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse"); 2769 __ movoop(rscratch1, c->as_jobject()); 2770 } 2771#endif // LP64 2772 if (op->info() != NULL) { 2773 add_debug_info_for_null_check_here(op->info()); 2774 } 2775 // special case: address - constant 2776 LIR_Address* addr = opr1->as_address_ptr(); 2777 if (c->type() == T_INT) { 2778 __ cmpl(as_Address(addr), c->as_jint()); 2779 } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) { 2780#ifdef _LP64 2781 // %%% Make this explode if addr isn't reachable until we figure out a 2782 // better strategy by giving noreg as the temp for as_Address 2783 __ cmpptr(rscratch1, as_Address(addr, noreg)); 2784#else 2785 __ cmpoop(as_Address(addr), c->as_jobject()); 2786#endif // _LP64 2787 } else { 2788 ShouldNotReachHere(); 2789 } 2790 2791 } else { 2792 ShouldNotReachHere(); 2793 } 2794} 2795 2796void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) { 2797 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 2798 if (left->is_single_xmm()) { 2799 assert(right->is_single_xmm(), "must match"); 2800 __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2801 } else if (left->is_double_xmm()) { 2802 assert(right->is_double_xmm(), "must match"); 2803 __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i); 2804 2805 } else { 2806 assert(left->is_single_fpu() || left->is_double_fpu(), "must be"); 2807 assert(right->is_single_fpu() || right->is_double_fpu(), "must match"); 2808 2809 assert(left->fpu() == 0, "left must be on TOS"); 2810 __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(), 2811 op->fpu_pop_count() > 0, op->fpu_pop_count() > 1); 2812 } 2813 } else { 2814 assert(code == lir_cmp_l2i, "check"); 2815#ifdef _LP64 2816 Label done; 2817 Register dest = dst->as_register(); 2818 __ cmpptr(left->as_register_lo(), right->as_register_lo()); 2819 __ movl(dest, -1); 2820 __ jccb(Assembler::less, done); 2821 __ set_byte_if_not_zero(dest); 2822 __ movzbl(dest, dest); 2823 __ bind(done); 2824#else 2825 __ lcmp2int(left->as_register_hi(), 2826 left->as_register_lo(), 2827 right->as_register_hi(), 2828 right->as_register_lo()); 2829 move_regs(left->as_register_hi(), dst->as_register()); 2830#endif // _LP64 2831 } 2832} 2833 2834 2835void LIR_Assembler::align_call(LIR_Code code) { 2836 if (os::is_MP()) { 2837 // make sure that the displacement word of the call ends up word aligned 2838 int offset = __ offset(); 2839 switch (code) { 2840 case lir_static_call: 2841 case lir_optvirtual_call: 2842 case lir_dynamic_call: 2843 offset += NativeCall::displacement_offset; 2844 break; 2845 case lir_icvirtual_call: 2846 offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size; 2847 break; 2848 case lir_virtual_call: // currently, sparc-specific for niagara 2849 default: ShouldNotReachHere(); 2850 } 2851 while (offset++ % BytesPerWord != 0) { 2852 __ nop(); 2853 } 2854 } 2855} 2856 2857 2858void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 2859 assert(!os::is_MP() || (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2860 "must be aligned"); 2861 __ call(AddressLiteral(op->addr(), rtype)); 2862 add_call_info(code_offset(), op->info()); 2863} 2864 2865 2866void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 2867 RelocationHolder rh = virtual_call_Relocation::spec(pc()); 2868 __ movoop(IC_Klass, (jobject)Universe::non_oop_word()); 2869 assert(!os::is_MP() || 2870 (__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0, 2871 "must be aligned"); 2872 __ call(AddressLiteral(op->addr(), rh)); 2873 add_call_info(code_offset(), op->info()); 2874} 2875 2876 2877/* Currently, vtable-dispatch is only enabled for sparc platforms */ 2878void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 2879 ShouldNotReachHere(); 2880} 2881 2882 2883void LIR_Assembler::emit_static_call_stub() { 2884 address call_pc = __ pc(); 2885 address stub = __ start_a_stub(call_stub_size); 2886 if (stub == NULL) { 2887 bailout("static call stub overflow"); 2888 return; 2889 } 2890 2891 int start = __ offset(); 2892 if (os::is_MP()) { 2893 // make sure that the displacement word of the call ends up word aligned 2894 int offset = __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset; 2895 while (offset++ % BytesPerWord != 0) { 2896 __ nop(); 2897 } 2898 } 2899 __ relocate(static_stub_Relocation::spec(call_pc)); 2900 __ movoop(rbx, (jobject)NULL); 2901 // must be set to -1 at code generation time 2902 assert(!os::is_MP() || ((__ offset() + 1) % BytesPerWord) == 0, "must be aligned on MP"); 2903 // On 64bit this will die since it will take a movq & jmp, must be only a jmp 2904 __ jump(RuntimeAddress(__ pc())); 2905 2906 assert(__ offset() - start <= call_stub_size, "stub too big"); 2907 __ end_a_stub(); 2908} 2909 2910 2911void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2912 assert(exceptionOop->as_register() == rax, "must match"); 2913 assert(exceptionPC->as_register() == rdx, "must match"); 2914 2915 // exception object is not added to oop map by LinearScan 2916 // (LinearScan assumes that no oops are in fixed registers) 2917 info->add_register_oop(exceptionOop); 2918 Runtime1::StubID unwind_id; 2919 2920 // get current pc information 2921 // pc is only needed if the method has an exception handler, the unwind code does not need it. 2922 int pc_for_athrow_offset = __ offset(); 2923 InternalAddress pc_for_athrow(__ pc()); 2924 __ lea(exceptionPC->as_register(), pc_for_athrow); 2925 add_call_info(pc_for_athrow_offset, info); // for exception handler 2926 2927 __ verify_not_null_oop(rax); 2928 // search an exception handler (rax: exception oop, rdx: throwing pc) 2929 if (compilation()->has_fpu_code()) { 2930 unwind_id = Runtime1::handle_exception_id; 2931 } else { 2932 unwind_id = Runtime1::handle_exception_nofpu_id; 2933 } 2934 __ call(RuntimeAddress(Runtime1::entry_for(unwind_id))); 2935 2936 // enough room for two byte trap 2937 __ nop(); 2938} 2939 2940 2941void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2942 assert(exceptionOop->as_register() == rax, "must match"); 2943 2944 __ jmp(_unwind_handler_entry); 2945} 2946 2947 2948void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2949 2950 // optimized version for linear scan: 2951 // * count must be already in ECX (guaranteed by LinearScan) 2952 // * left and dest must be equal 2953 // * tmp must be unused 2954 assert(count->as_register() == SHIFT_count, "count must be in ECX"); 2955 assert(left == dest, "left and dest must be equal"); 2956 assert(tmp->is_illegal(), "wasting a register if tmp is allocated"); 2957 2958 if (left->is_single_cpu()) { 2959 Register value = left->as_register(); 2960 assert(value != SHIFT_count, "left cannot be ECX"); 2961 2962 switch (code) { 2963 case lir_shl: __ shll(value); break; 2964 case lir_shr: __ sarl(value); break; 2965 case lir_ushr: __ shrl(value); break; 2966 default: ShouldNotReachHere(); 2967 } 2968 } else if (left->is_double_cpu()) { 2969 Register lo = left->as_register_lo(); 2970 Register hi = left->as_register_hi(); 2971 assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX"); 2972#ifdef _LP64 2973 switch (code) { 2974 case lir_shl: __ shlptr(lo); break; 2975 case lir_shr: __ sarptr(lo); break; 2976 case lir_ushr: __ shrptr(lo); break; 2977 default: ShouldNotReachHere(); 2978 } 2979#else 2980 2981 switch (code) { 2982 case lir_shl: __ lshl(hi, lo); break; 2983 case lir_shr: __ lshr(hi, lo, true); break; 2984 case lir_ushr: __ lshr(hi, lo, false); break; 2985 default: ShouldNotReachHere(); 2986 } 2987#endif // LP64 2988 } else { 2989 ShouldNotReachHere(); 2990 } 2991} 2992 2993 2994void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2995 if (dest->is_single_cpu()) { 2996 // first move left into dest so that left is not destroyed by the shift 2997 Register value = dest->as_register(); 2998 count = count & 0x1F; // Java spec 2999 3000 move_regs(left->as_register(), value); 3001 switch (code) { 3002 case lir_shl: __ shll(value, count); break; 3003 case lir_shr: __ sarl(value, count); break; 3004 case lir_ushr: __ shrl(value, count); break; 3005 default: ShouldNotReachHere(); 3006 } 3007 } else if (dest->is_double_cpu()) { 3008#ifndef _LP64 3009 Unimplemented(); 3010#else 3011 // first move left into dest so that left is not destroyed by the shift 3012 Register value = dest->as_register_lo(); 3013 count = count & 0x1F; // Java spec 3014 3015 move_regs(left->as_register_lo(), value); 3016 switch (code) { 3017 case lir_shl: __ shlptr(value, count); break; 3018 case lir_shr: __ sarptr(value, count); break; 3019 case lir_ushr: __ shrptr(value, count); break; 3020 default: ShouldNotReachHere(); 3021 } 3022#endif // _LP64 3023 } else { 3024 ShouldNotReachHere(); 3025 } 3026} 3027 3028 3029void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) { 3030 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3031 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3032 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3033 __ movptr (Address(rsp, offset_from_rsp_in_bytes), r); 3034} 3035 3036 3037void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) { 3038 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3039 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3040 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3041 __ movptr (Address(rsp, offset_from_rsp_in_bytes), c); 3042} 3043 3044 3045void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) { 3046 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp"); 3047 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord; 3048 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset"); 3049 __ movoop (Address(rsp, offset_from_rsp_in_bytes), o); 3050} 3051 3052 3053// This code replaces a call to arraycopy; no exception may 3054// be thrown in this code, they must be thrown in the System.arraycopy 3055// activation frame; we could save some checks if this would not be the case 3056void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 3057 ciArrayKlass* default_type = op->expected_type(); 3058 Register src = op->src()->as_register(); 3059 Register dst = op->dst()->as_register(); 3060 Register src_pos = op->src_pos()->as_register(); 3061 Register dst_pos = op->dst_pos()->as_register(); 3062 Register length = op->length()->as_register(); 3063 Register tmp = op->tmp()->as_register(); 3064 3065 CodeStub* stub = op->stub(); 3066 int flags = op->flags(); 3067 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 3068 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 3069 3070 // if we don't know anything, just go through the generic arraycopy 3071 if (default_type == NULL) { 3072 Label done; 3073 // save outgoing arguments on stack in case call to System.arraycopy is needed 3074 // HACK ALERT. This code used to push the parameters in a hardwired fashion 3075 // for interpreter calling conventions. Now we have to do it in new style conventions. 3076 // For the moment until C1 gets the new register allocator I just force all the 3077 // args to the right place (except the register args) and then on the back side 3078 // reload the register args properly if we go slow path. Yuck 3079 3080 // These are proper for the calling convention 3081 store_parameter(length, 2); 3082 store_parameter(dst_pos, 1); 3083 store_parameter(dst, 0); 3084 3085 // these are just temporary placements until we need to reload 3086 store_parameter(src_pos, 3); 3087 store_parameter(src, 4); 3088 NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");) 3089 3090 address C_entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy); 3091 3092 address copyfunc_addr = StubRoutines::generic_arraycopy(); 3093 3094 // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint 3095#ifdef _LP64 3096 // The arguments are in java calling convention so we can trivially shift them to C 3097 // convention 3098 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4); 3099 __ mov(c_rarg0, j_rarg0); 3100 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4); 3101 __ mov(c_rarg1, j_rarg1); 3102 assert_different_registers(c_rarg2, j_rarg3, j_rarg4); 3103 __ mov(c_rarg2, j_rarg2); 3104 assert_different_registers(c_rarg3, j_rarg4); 3105 __ mov(c_rarg3, j_rarg3); 3106#ifdef _WIN64 3107 // Allocate abi space for args but be sure to keep stack aligned 3108 __ subptr(rsp, 6*wordSize); 3109 store_parameter(j_rarg4, 4); 3110 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3111 __ call(RuntimeAddress(C_entry)); 3112 } else { 3113#ifndef PRODUCT 3114 if (PrintC1Statistics) { 3115 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3116 } 3117#endif 3118 __ call(RuntimeAddress(copyfunc_addr)); 3119 } 3120 __ addptr(rsp, 6*wordSize); 3121#else 3122 __ mov(c_rarg4, j_rarg4); 3123 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3124 __ call(RuntimeAddress(C_entry)); 3125 } else { 3126#ifndef PRODUCT 3127 if (PrintC1Statistics) { 3128 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3129 } 3130#endif 3131 __ call(RuntimeAddress(copyfunc_addr)); 3132 } 3133#endif // _WIN64 3134#else 3135 __ push(length); 3136 __ push(dst_pos); 3137 __ push(dst); 3138 __ push(src_pos); 3139 __ push(src); 3140 3141 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 3142 __ call_VM_leaf(C_entry, 5); // removes pushed parameter from the stack 3143 } else { 3144#ifndef PRODUCT 3145 if (PrintC1Statistics) { 3146 __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt)); 3147 } 3148#endif 3149 __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack 3150 } 3151 3152#endif // _LP64 3153 3154 __ cmpl(rax, 0); 3155 __ jcc(Assembler::equal, *stub->continuation()); 3156 3157 if (copyfunc_addr != NULL) { 3158 __ mov(tmp, rax); 3159 __ xorl(tmp, -1); 3160 } 3161 3162 // Reload values from the stack so they are where the stub 3163 // expects them. 3164 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3165 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3166 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3167 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3168 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3169 3170 if (copyfunc_addr != NULL) { 3171 __ subl(length, tmp); 3172 __ addl(src_pos, tmp); 3173 __ addl(dst_pos, tmp); 3174 } 3175 __ jmp(*stub->entry()); 3176 3177 __ bind(*stub->continuation()); 3178 return; 3179 } 3180 3181 assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point"); 3182 3183 int elem_size = type2aelembytes(basic_type); 3184 int shift_amount; 3185 Address::ScaleFactor scale; 3186 3187 switch (elem_size) { 3188 case 1 : 3189 shift_amount = 0; 3190 scale = Address::times_1; 3191 break; 3192 case 2 : 3193 shift_amount = 1; 3194 scale = Address::times_2; 3195 break; 3196 case 4 : 3197 shift_amount = 2; 3198 scale = Address::times_4; 3199 break; 3200 case 8 : 3201 shift_amount = 3; 3202 scale = Address::times_8; 3203 break; 3204 default: 3205 ShouldNotReachHere(); 3206 } 3207 3208 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes()); 3209 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes()); 3210 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes()); 3211 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes()); 3212 3213 // length and pos's are all sign extended at this point on 64bit 3214 3215 // test for NULL 3216 if (flags & LIR_OpArrayCopy::src_null_check) { 3217 __ testptr(src, src); 3218 __ jcc(Assembler::zero, *stub->entry()); 3219 } 3220 if (flags & LIR_OpArrayCopy::dst_null_check) { 3221 __ testptr(dst, dst); 3222 __ jcc(Assembler::zero, *stub->entry()); 3223 } 3224 3225 // check if negative 3226 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 3227 __ testl(src_pos, src_pos); 3228 __ jcc(Assembler::less, *stub->entry()); 3229 } 3230 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 3231 __ testl(dst_pos, dst_pos); 3232 __ jcc(Assembler::less, *stub->entry()); 3233 } 3234 3235 if (flags & LIR_OpArrayCopy::src_range_check) { 3236 __ lea(tmp, Address(src_pos, length, Address::times_1, 0)); 3237 __ cmpl(tmp, src_length_addr); 3238 __ jcc(Assembler::above, *stub->entry()); 3239 } 3240 if (flags & LIR_OpArrayCopy::dst_range_check) { 3241 __ lea(tmp, Address(dst_pos, length, Address::times_1, 0)); 3242 __ cmpl(tmp, dst_length_addr); 3243 __ jcc(Assembler::above, *stub->entry()); 3244 } 3245 3246 if (flags & LIR_OpArrayCopy::length_positive_check) { 3247 __ testl(length, length); 3248 __ jcc(Assembler::less, *stub->entry()); 3249 __ jcc(Assembler::zero, *stub->continuation()); 3250 } 3251 3252#ifdef _LP64 3253 __ movl2ptr(src_pos, src_pos); //higher 32bits must be null 3254 __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null 3255#endif 3256 3257 if (flags & LIR_OpArrayCopy::type_check) { 3258 // We don't know the array types are compatible 3259 if (basic_type != T_OBJECT) { 3260 // Simple test for basic type arrays 3261 if (UseCompressedOops) { 3262 __ movl(tmp, src_klass_addr); 3263 __ cmpl(tmp, dst_klass_addr); 3264 } else { 3265 __ movptr(tmp, src_klass_addr); 3266 __ cmpptr(tmp, dst_klass_addr); 3267 } 3268 __ jcc(Assembler::notEqual, *stub->entry()); 3269 } else { 3270 // For object arrays, if src is a sub class of dst then we can 3271 // safely do the copy. 3272 Label cont, slow; 3273 3274 __ push(src); 3275 __ push(dst); 3276 3277 __ load_klass(src, src); 3278 __ load_klass(dst, dst); 3279 3280 __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL); 3281 3282 __ push(src); 3283 __ push(dst); 3284 __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id))); 3285 __ pop(dst); 3286 __ pop(src); 3287 3288 __ cmpl(src, 0); 3289 __ jcc(Assembler::notEqual, cont); 3290 3291 __ bind(slow); 3292 __ pop(dst); 3293 __ pop(src); 3294 3295 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 3296 if (copyfunc_addr != NULL) { // use stub if available 3297 // src is not a sub class of dst so we have to do a 3298 // per-element check. 3299 3300 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 3301 if ((flags & mask) != mask) { 3302 // Check that at least both of them object arrays. 3303 assert(flags & mask, "one of the two should be known to be an object array"); 3304 3305 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 3306 __ load_klass(tmp, src); 3307 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 3308 __ load_klass(tmp, dst); 3309 } 3310 int lh_offset = in_bytes(Klass::layout_helper_offset()); 3311 Address klass_lh_addr(tmp, lh_offset); 3312 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 3313 __ cmpl(klass_lh_addr, objArray_lh); 3314 __ jcc(Assembler::notEqual, *stub->entry()); 3315 } 3316 3317 // Spill because stubs can use any register they like and it's 3318 // easier to restore just those that we care about. 3319 store_parameter(dst, 0); 3320 store_parameter(dst_pos, 1); 3321 store_parameter(length, 2); 3322 store_parameter(src_pos, 3); 3323 store_parameter(src, 4); 3324 3325#ifndef _LP64 3326 __ movptr(tmp, dst_klass_addr); 3327 __ movptr(tmp, Address(tmp, objArrayKlass::element_klass_offset())); 3328 __ push(tmp); 3329 __ movl(tmp, Address(tmp, Klass::super_check_offset_offset())); 3330 __ push(tmp); 3331 __ push(length); 3332 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3333 __ push(tmp); 3334 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3335 __ push(tmp); 3336 3337 __ call_VM_leaf(copyfunc_addr, 5); 3338#else 3339 __ movl2ptr(length, length); //higher 32bits must be null 3340 3341 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3342 assert_different_registers(c_rarg0, dst, dst_pos, length); 3343 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3344 assert_different_registers(c_rarg1, dst, length); 3345 3346 __ mov(c_rarg2, length); 3347 assert_different_registers(c_rarg2, dst); 3348 3349#ifdef _WIN64 3350 // Allocate abi space for args but be sure to keep stack aligned 3351 __ subptr(rsp, 6*wordSize); 3352 __ load_klass(c_rarg3, dst); 3353 __ movptr(c_rarg3, Address(c_rarg3, objArrayKlass::element_klass_offset())); 3354 store_parameter(c_rarg3, 4); 3355 __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset())); 3356 __ call(RuntimeAddress(copyfunc_addr)); 3357 __ addptr(rsp, 6*wordSize); 3358#else 3359 __ load_klass(c_rarg4, dst); 3360 __ movptr(c_rarg4, Address(c_rarg4, objArrayKlass::element_klass_offset())); 3361 __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset())); 3362 __ call(RuntimeAddress(copyfunc_addr)); 3363#endif 3364 3365#endif 3366 3367#ifndef PRODUCT 3368 if (PrintC1Statistics) { 3369 Label failed; 3370 __ testl(rax, rax); 3371 __ jcc(Assembler::notZero, failed); 3372 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt)); 3373 __ bind(failed); 3374 } 3375#endif 3376 3377 __ testl(rax, rax); 3378 __ jcc(Assembler::zero, *stub->continuation()); 3379 3380#ifndef PRODUCT 3381 if (PrintC1Statistics) { 3382 __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt)); 3383 } 3384#endif 3385 3386 __ mov(tmp, rax); 3387 3388 __ xorl(tmp, -1); 3389 3390 // Restore previously spilled arguments 3391 __ movptr (dst, Address(rsp, 0*BytesPerWord)); 3392 __ movptr (dst_pos, Address(rsp, 1*BytesPerWord)); 3393 __ movptr (length, Address(rsp, 2*BytesPerWord)); 3394 __ movptr (src_pos, Address(rsp, 3*BytesPerWord)); 3395 __ movptr (src, Address(rsp, 4*BytesPerWord)); 3396 3397 3398 __ subl(length, tmp); 3399 __ addl(src_pos, tmp); 3400 __ addl(dst_pos, tmp); 3401 } 3402 3403 __ jmp(*stub->entry()); 3404 3405 __ bind(cont); 3406 __ pop(dst); 3407 __ pop(src); 3408 } 3409 } 3410 3411#ifdef ASSERT 3412 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 3413 // Sanity check the known type with the incoming class. For the 3414 // primitive case the types must match exactly with src.klass and 3415 // dst.klass each exactly matching the default type. For the 3416 // object array case, if no type check is needed then either the 3417 // dst type is exactly the expected type and the src type is a 3418 // subtype which we can't check or src is the same array as dst 3419 // but not necessarily exactly of type default_type. 3420 Label known_ok, halt; 3421 __ movoop(tmp, default_type->constant_encoding()); 3422#ifdef _LP64 3423 if (UseCompressedOops) { 3424 __ encode_heap_oop(tmp); 3425 } 3426#endif 3427 3428 if (basic_type != T_OBJECT) { 3429 3430 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); 3431 else __ cmpptr(tmp, dst_klass_addr); 3432 __ jcc(Assembler::notEqual, halt); 3433 if (UseCompressedOops) __ cmpl(tmp, src_klass_addr); 3434 else __ cmpptr(tmp, src_klass_addr); 3435 __ jcc(Assembler::equal, known_ok); 3436 } else { 3437 if (UseCompressedOops) __ cmpl(tmp, dst_klass_addr); 3438 else __ cmpptr(tmp, dst_klass_addr); 3439 __ jcc(Assembler::equal, known_ok); 3440 __ cmpptr(src, dst); 3441 __ jcc(Assembler::equal, known_ok); 3442 } 3443 __ bind(halt); 3444 __ stop("incorrect type information in arraycopy"); 3445 __ bind(known_ok); 3446 } 3447#endif 3448 3449#ifndef PRODUCT 3450 if (PrintC1Statistics) { 3451 __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type))); 3452 } 3453#endif 3454 3455#ifdef _LP64 3456 assert_different_registers(c_rarg0, dst, dst_pos, length); 3457 __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3458 assert_different_registers(c_rarg1, length); 3459 __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3460 __ mov(c_rarg2, length); 3461 3462#else 3463 __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3464 store_parameter(tmp, 0); 3465 __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type))); 3466 store_parameter(tmp, 1); 3467 store_parameter(length, 2); 3468#endif // _LP64 3469 3470 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 3471 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 3472 const char *name; 3473 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 3474 __ call_VM_leaf(entry, 0); 3475 3476 __ bind(*stub->continuation()); 3477} 3478 3479 3480void LIR_Assembler::emit_lock(LIR_OpLock* op) { 3481 Register obj = op->obj_opr()->as_register(); // may not be an oop 3482 Register hdr = op->hdr_opr()->as_register(); 3483 Register lock = op->lock_opr()->as_register(); 3484 if (!UseFastLocking) { 3485 __ jmp(*op->stub()->entry()); 3486 } else if (op->code() == lir_lock) { 3487 Register scratch = noreg; 3488 if (UseBiasedLocking) { 3489 scratch = op->scratch_opr()->as_register(); 3490 } 3491 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3492 // add debug info for NullPointerException only if one is possible 3493 int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry()); 3494 if (op->info() != NULL) { 3495 add_debug_info_for_null_check(null_check_offset, op->info()); 3496 } 3497 // done 3498 } else if (op->code() == lir_unlock) { 3499 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 3500 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 3501 } else { 3502 Unimplemented(); 3503 } 3504 __ bind(*op->stub()->continuation()); 3505} 3506 3507 3508void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 3509 ciMethod* method = op->profiled_method(); 3510 int bci = op->profiled_bci(); 3511 3512 // Update counter for all call types 3513 ciMethodData* md = method->method_data_or_null(); 3514 assert(md != NULL, "Sanity"); 3515 ciProfileData* data = md->bci_to_data(bci); 3516 assert(data->is_CounterData(), "need CounterData for calls"); 3517 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 3518 Register mdo = op->mdo()->as_register(); 3519 __ movoop(mdo, md->constant_encoding()); 3520 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset())); 3521 Bytecodes::Code bc = method->java_code_at_bci(bci); 3522 // Perform additional virtual call profiling for invokevirtual and 3523 // invokeinterface bytecodes 3524 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3525 C1ProfileVirtualCalls) { 3526 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3527 Register recv = op->recv()->as_register(); 3528 assert_different_registers(mdo, recv); 3529 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3530 ciKlass* known_klass = op->known_holder(); 3531 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3532 // We know the type that will be seen at this call site; we can 3533 // statically update the methodDataOop rather than needing to do 3534 // dynamic tests on the receiver type 3535 3536 // NOTE: we should probably put a lock around this search to 3537 // avoid collisions by concurrent compilations 3538 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3539 uint i; 3540 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3541 ciKlass* receiver = vc_data->receiver(i); 3542 if (known_klass->equals(receiver)) { 3543 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3544 __ addptr(data_addr, DataLayout::counter_increment); 3545 return; 3546 } 3547 } 3548 3549 // Receiver type not found in profile data; select an empty slot 3550 3551 // Note that this is less efficient than it should be because it 3552 // always does a write to the receiver part of the 3553 // VirtualCallData rather than just the first time 3554 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3555 ciKlass* receiver = vc_data->receiver(i); 3556 if (receiver == NULL) { 3557 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i))); 3558 __ movoop(recv_addr, known_klass->constant_encoding()); 3559 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i))); 3560 __ addptr(data_addr, DataLayout::counter_increment); 3561 return; 3562 } 3563 } 3564 } else { 3565 __ load_klass(recv, recv); 3566 Label update_done; 3567 type_profile_helper(mdo, md, data, recv, &update_done); 3568 // Receiver did not match any saved receiver and there is no empty row for it. 3569 // Increment total counter to indicate polymorphic case. 3570 __ addptr(counter_addr, DataLayout::counter_increment); 3571 3572 __ bind(update_done); 3573 } 3574 } else { 3575 // Static call 3576 __ addptr(counter_addr, DataLayout::counter_increment); 3577 } 3578} 3579 3580void LIR_Assembler::emit_delay(LIR_OpDelay*) { 3581 Unimplemented(); 3582} 3583 3584 3585void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) { 3586 __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no)); 3587} 3588 3589 3590void LIR_Assembler::align_backward_branch_target() { 3591 __ align(BytesPerWord); 3592} 3593 3594 3595void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3596 if (left->is_single_cpu()) { 3597 __ negl(left->as_register()); 3598 move_regs(left->as_register(), dest->as_register()); 3599 3600 } else if (left->is_double_cpu()) { 3601 Register lo = left->as_register_lo(); 3602#ifdef _LP64 3603 Register dst = dest->as_register_lo(); 3604 __ movptr(dst, lo); 3605 __ negptr(dst); 3606#else 3607 Register hi = left->as_register_hi(); 3608 __ lneg(hi, lo); 3609 if (dest->as_register_lo() == hi) { 3610 assert(dest->as_register_hi() != lo, "destroying register"); 3611 move_regs(hi, dest->as_register_hi()); 3612 move_regs(lo, dest->as_register_lo()); 3613 } else { 3614 move_regs(lo, dest->as_register_lo()); 3615 move_regs(hi, dest->as_register_hi()); 3616 } 3617#endif // _LP64 3618 3619 } else if (dest->is_single_xmm()) { 3620 if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) { 3621 __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg()); 3622 } 3623 __ xorps(dest->as_xmm_float_reg(), 3624 ExternalAddress((address)float_signflip_pool)); 3625 3626 } else if (dest->is_double_xmm()) { 3627 if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) { 3628 __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg()); 3629 } 3630 __ xorpd(dest->as_xmm_double_reg(), 3631 ExternalAddress((address)double_signflip_pool)); 3632 3633 } else if (left->is_single_fpu() || left->is_double_fpu()) { 3634 assert(left->fpu() == 0, "arg must be on TOS"); 3635 assert(dest->fpu() == 0, "dest must be TOS"); 3636 __ fchs(); 3637 3638 } else { 3639 ShouldNotReachHere(); 3640 } 3641} 3642 3643 3644void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest) { 3645 assert(addr->is_address() && dest->is_register(), "check"); 3646 Register reg; 3647 reg = dest->as_pointer_register(); 3648 __ lea(reg, as_Address(addr->as_address_ptr())); 3649} 3650 3651 3652 3653void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3654 assert(!tmp->is_valid(), "don't need temporary"); 3655 __ call(RuntimeAddress(dest)); 3656 if (info != NULL) { 3657 add_call_info_here(info); 3658 } 3659} 3660 3661 3662void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3663 assert(type == T_LONG, "only for volatile long fields"); 3664 3665 if (info != NULL) { 3666 add_debug_info_for_null_check_here(info); 3667 } 3668 3669 if (src->is_double_xmm()) { 3670 if (dest->is_double_cpu()) { 3671#ifdef _LP64 3672 __ movdq(dest->as_register_lo(), src->as_xmm_double_reg()); 3673#else 3674 __ movdl(dest->as_register_lo(), src->as_xmm_double_reg()); 3675 __ psrlq(src->as_xmm_double_reg(), 32); 3676 __ movdl(dest->as_register_hi(), src->as_xmm_double_reg()); 3677#endif // _LP64 3678 } else if (dest->is_double_stack()) { 3679 __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg()); 3680 } else if (dest->is_address()) { 3681 __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg()); 3682 } else { 3683 ShouldNotReachHere(); 3684 } 3685 3686 } else if (dest->is_double_xmm()) { 3687 if (src->is_double_stack()) { 3688 __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix())); 3689 } else if (src->is_address()) { 3690 __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr())); 3691 } else { 3692 ShouldNotReachHere(); 3693 } 3694 3695 } else if (src->is_double_fpu()) { 3696 assert(src->fpu_regnrLo() == 0, "must be TOS"); 3697 if (dest->is_double_stack()) { 3698 __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix())); 3699 } else if (dest->is_address()) { 3700 __ fistp_d(as_Address(dest->as_address_ptr())); 3701 } else { 3702 ShouldNotReachHere(); 3703 } 3704 3705 } else if (dest->is_double_fpu()) { 3706 assert(dest->fpu_regnrLo() == 0, "must be TOS"); 3707 if (src->is_double_stack()) { 3708 __ fild_d(frame_map()->address_for_slot(src->double_stack_ix())); 3709 } else if (src->is_address()) { 3710 __ fild_d(as_Address(src->as_address_ptr())); 3711 } else { 3712 ShouldNotReachHere(); 3713 } 3714 } else { 3715 ShouldNotReachHere(); 3716 } 3717} 3718 3719 3720void LIR_Assembler::membar() { 3721 // QQQ sparc TSO uses this, 3722 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3723} 3724 3725void LIR_Assembler::membar_acquire() { 3726 // No x86 machines currently require load fences 3727 // __ load_fence(); 3728} 3729 3730void LIR_Assembler::membar_release() { 3731 // No x86 machines currently require store fences 3732 // __ store_fence(); 3733} 3734 3735void LIR_Assembler::membar_loadload() { 3736 // no-op 3737 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3738} 3739 3740void LIR_Assembler::membar_storestore() { 3741 // no-op 3742 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3743} 3744 3745void LIR_Assembler::membar_loadstore() { 3746 // no-op 3747 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3748} 3749 3750void LIR_Assembler::membar_storeload() { 3751 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3752} 3753 3754void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3755 assert(result_reg->is_register(), "check"); 3756#ifdef _LP64 3757 // __ get_thread(result_reg->as_register_lo()); 3758 __ mov(result_reg->as_register(), r15_thread); 3759#else 3760 __ get_thread(result_reg->as_register()); 3761#endif // _LP64 3762} 3763 3764 3765void LIR_Assembler::peephole(LIR_List*) { 3766 // do nothing for now 3767} 3768 3769 3770#undef __ 3771