assembler_x86.hpp revision 623:9adddb8c0fc8
1/* 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25class BiasedLockingCounters; 26 27// Contains all the definitions needed for x86 assembly code generation. 28 29// Calling convention 30class Argument VALUE_OBJ_CLASS_SPEC { 31 public: 32 enum { 33#ifdef _LP64 34#ifdef _WIN64 35 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 36 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 37#else 38 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 39 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 40#endif // _WIN64 41 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 42 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 43#else 44 n_register_parameters = 0 // 0 registers used to pass arguments 45#endif // _LP64 46 }; 47}; 48 49 50#ifdef _LP64 51// Symbolically name the register arguments used by the c calling convention. 52// Windows is different from linux/solaris. So much for standards... 53 54#ifdef _WIN64 55 56REGISTER_DECLARATION(Register, c_rarg0, rcx); 57REGISTER_DECLARATION(Register, c_rarg1, rdx); 58REGISTER_DECLARATION(Register, c_rarg2, r8); 59REGISTER_DECLARATION(Register, c_rarg3, r9); 60 61REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 62REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 63REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 64REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 65 66#else 67 68REGISTER_DECLARATION(Register, c_rarg0, rdi); 69REGISTER_DECLARATION(Register, c_rarg1, rsi); 70REGISTER_DECLARATION(Register, c_rarg2, rdx); 71REGISTER_DECLARATION(Register, c_rarg3, rcx); 72REGISTER_DECLARATION(Register, c_rarg4, r8); 73REGISTER_DECLARATION(Register, c_rarg5, r9); 74 75REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 76REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 77REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 78REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 79REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 80REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 81REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 82REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 83 84#endif // _WIN64 85 86// Symbolically name the register arguments used by the Java calling convention. 87// We have control over the convention for java so we can do what we please. 88// What pleases us is to offset the java calling convention so that when 89// we call a suitable jni method the arguments are lined up and we don't 90// have to do little shuffling. A suitable jni method is non-static and a 91// small number of arguments (two fewer args on windows) 92// 93// |-------------------------------------------------------| 94// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 95// |-------------------------------------------------------| 96// | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 97// | rdi rsi rdx rcx r8 r9 | solaris/linux 98// |-------------------------------------------------------| 99// | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 100// |-------------------------------------------------------| 101 102REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 103REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 104REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 105// Windows runs out of register args here 106#ifdef _WIN64 107REGISTER_DECLARATION(Register, j_rarg3, rdi); 108REGISTER_DECLARATION(Register, j_rarg4, rsi); 109#else 110REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 111REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 112#endif /* _WIN64 */ 113REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 114 115REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 116REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 117REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 118REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 119REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 120REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 121REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 122REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 123 124REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 125REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 126 127REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 128REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 129 130#else 131// rscratch1 will apear in 32bit code that is dead but of course must compile 132// Using noreg ensures if the dead code is incorrectly live and executed it 133// will cause an assertion failure 134#define rscratch1 noreg 135 136#endif // _LP64 137 138// Address is an abstraction used to represent a memory location 139// using any of the amd64 addressing modes with one object. 140// 141// Note: A register location is represented via a Register, not 142// via an address for efficiency & simplicity reasons. 143 144class ArrayAddress; 145 146class Address VALUE_OBJ_CLASS_SPEC { 147 public: 148 enum ScaleFactor { 149 no_scale = -1, 150 times_1 = 0, 151 times_2 = 1, 152 times_4 = 2, 153 times_8 = 3, 154 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 155 }; 156 static ScaleFactor times(int size) { 157 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 158 if (size == 8) return times_8; 159 if (size == 4) return times_4; 160 if (size == 2) return times_2; 161 return times_1; 162 } 163 static int scale_size(ScaleFactor scale) { 164 assert(scale != no_scale, ""); 165 assert(((1 << (int)times_1) == 1 && 166 (1 << (int)times_2) == 2 && 167 (1 << (int)times_4) == 4 && 168 (1 << (int)times_8) == 8), ""); 169 return (1 << (int)scale); 170 } 171 172 private: 173 Register _base; 174 Register _index; 175 ScaleFactor _scale; 176 int _disp; 177 RelocationHolder _rspec; 178 179 // Easily misused constructors make them private 180 // %%% can we make these go away? 181 NOT_LP64(Address(address loc, RelocationHolder spec);) 182 Address(int disp, address loc, relocInfo::relocType rtype); 183 Address(int disp, address loc, RelocationHolder spec); 184 185 public: 186 187 int disp() { return _disp; } 188 // creation 189 Address() 190 : _base(noreg), 191 _index(noreg), 192 _scale(no_scale), 193 _disp(0) { 194 } 195 196 // No default displacement otherwise Register can be implicitly 197 // converted to 0(Register) which is quite a different animal. 198 199 Address(Register base, int disp) 200 : _base(base), 201 _index(noreg), 202 _scale(no_scale), 203 _disp(disp) { 204 } 205 206 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 207 : _base (base), 208 _index(index), 209 _scale(scale), 210 _disp (disp) { 211 assert(!index->is_valid() == (scale == Address::no_scale), 212 "inconsistent address"); 213 } 214 215 Address(Register base, RegisterConstant index, ScaleFactor scale = times_1, int disp = 0) 216 : _base (base), 217 _index(index.register_or_noreg()), 218 _scale(scale), 219 _disp (disp + (index.constant_or_zero() * scale_size(scale))) { 220 if (!index.is_register()) scale = Address::no_scale; 221 assert(!_index->is_valid() == (scale == Address::no_scale), 222 "inconsistent address"); 223 } 224 225 Address plus_disp(int disp) const { 226 Address a = (*this); 227 a._disp += disp; 228 return a; 229 } 230 231 // The following two overloads are used in connection with the 232 // ByteSize type (see sizes.hpp). They simplify the use of 233 // ByteSize'd arguments in assembly code. Note that their equivalent 234 // for the optimized build are the member functions with int disp 235 // argument since ByteSize is mapped to an int type in that case. 236 // 237 // Note: DO NOT introduce similar overloaded functions for WordSize 238 // arguments as in the optimized mode, both ByteSize and WordSize 239 // are mapped to the same type and thus the compiler cannot make a 240 // distinction anymore (=> compiler errors). 241 242#ifdef ASSERT 243 Address(Register base, ByteSize disp) 244 : _base(base), 245 _index(noreg), 246 _scale(no_scale), 247 _disp(in_bytes(disp)) { 248 } 249 250 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 251 : _base(base), 252 _index(index), 253 _scale(scale), 254 _disp(in_bytes(disp)) { 255 assert(!index->is_valid() == (scale == Address::no_scale), 256 "inconsistent address"); 257 } 258 259 Address(Register base, RegisterConstant index, ScaleFactor scale, ByteSize disp) 260 : _base (base), 261 _index(index.register_or_noreg()), 262 _scale(scale), 263 _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) { 264 if (!index.is_register()) scale = Address::no_scale; 265 assert(!_index->is_valid() == (scale == Address::no_scale), 266 "inconsistent address"); 267 } 268 269#endif // ASSERT 270 271 // accessors 272 bool uses(Register reg) const { return _base == reg || _index == reg; } 273 Register base() const { return _base; } 274 Register index() const { return _index; } 275 ScaleFactor scale() const { return _scale; } 276 int disp() const { return _disp; } 277 278 // Convert the raw encoding form into the form expected by the constructor for 279 // Address. An index of 4 (rsp) corresponds to having no index, so convert 280 // that to noreg for the Address constructor. 281 static Address make_raw(int base, int index, int scale, int disp); 282 283 static Address make_array(ArrayAddress); 284 285 private: 286 bool base_needs_rex() const { 287 return _base != noreg && _base->encoding() >= 8; 288 } 289 290 bool index_needs_rex() const { 291 return _index != noreg &&_index->encoding() >= 8; 292 } 293 294 relocInfo::relocType reloc() const { return _rspec.type(); } 295 296 friend class Assembler; 297 friend class MacroAssembler; 298 friend class LIR_Assembler; // base/index/scale/disp 299}; 300 301// 302// AddressLiteral has been split out from Address because operands of this type 303// need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 304// the few instructions that need to deal with address literals are unique and the 305// MacroAssembler does not have to implement every instruction in the Assembler 306// in order to search for address literals that may need special handling depending 307// on the instruction and the platform. As small step on the way to merging i486/amd64 308// directories. 309// 310class AddressLiteral VALUE_OBJ_CLASS_SPEC { 311 friend class ArrayAddress; 312 RelocationHolder _rspec; 313 // Typically we use AddressLiterals we want to use their rval 314 // However in some situations we want the lval (effect address) of the item. 315 // We provide a special factory for making those lvals. 316 bool _is_lval; 317 318 // If the target is far we'll need to load the ea of this to 319 // a register to reach it. Otherwise if near we can do rip 320 // relative addressing. 321 322 address _target; 323 324 protected: 325 // creation 326 AddressLiteral() 327 : _is_lval(false), 328 _target(NULL) 329 {} 330 331 public: 332 333 334 AddressLiteral(address target, relocInfo::relocType rtype); 335 336 AddressLiteral(address target, RelocationHolder const& rspec) 337 : _rspec(rspec), 338 _is_lval(false), 339 _target(target) 340 {} 341 342 AddressLiteral addr() { 343 AddressLiteral ret = *this; 344 ret._is_lval = true; 345 return ret; 346 } 347 348 349 private: 350 351 address target() { return _target; } 352 bool is_lval() { return _is_lval; } 353 354 relocInfo::relocType reloc() const { return _rspec.type(); } 355 const RelocationHolder& rspec() const { return _rspec; } 356 357 friend class Assembler; 358 friend class MacroAssembler; 359 friend class Address; 360 friend class LIR_Assembler; 361}; 362 363// Convience classes 364class RuntimeAddress: public AddressLiteral { 365 366 public: 367 368 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 369 370}; 371 372class OopAddress: public AddressLiteral { 373 374 public: 375 376 OopAddress(address target) : AddressLiteral(target, relocInfo::oop_type){} 377 378}; 379 380class ExternalAddress: public AddressLiteral { 381 382 public: 383 384 ExternalAddress(address target) : AddressLiteral(target, relocInfo::external_word_type){} 385 386}; 387 388class InternalAddress: public AddressLiteral { 389 390 public: 391 392 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 393 394}; 395 396// x86 can do array addressing as a single operation since disp can be an absolute 397// address amd64 can't. We create a class that expresses the concept but does extra 398// magic on amd64 to get the final result 399 400class ArrayAddress VALUE_OBJ_CLASS_SPEC { 401 private: 402 403 AddressLiteral _base; 404 Address _index; 405 406 public: 407 408 ArrayAddress() {}; 409 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 410 AddressLiteral base() { return _base; } 411 Address index() { return _index; } 412 413}; 414 415const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY( 512 / wordSize); 416 417// The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 418// level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 419// is what you get. The Assembler is generating code into a CodeBuffer. 420 421class Assembler : public AbstractAssembler { 422 friend class AbstractAssembler; // for the non-virtual hack 423 friend class LIR_Assembler; // as_Address() 424 friend class StubGenerator; 425 426 public: 427 enum Condition { // The x86 condition codes used for conditional jumps/moves. 428 zero = 0x4, 429 notZero = 0x5, 430 equal = 0x4, 431 notEqual = 0x5, 432 less = 0xc, 433 lessEqual = 0xe, 434 greater = 0xf, 435 greaterEqual = 0xd, 436 below = 0x2, 437 belowEqual = 0x6, 438 above = 0x7, 439 aboveEqual = 0x3, 440 overflow = 0x0, 441 noOverflow = 0x1, 442 carrySet = 0x2, 443 carryClear = 0x3, 444 negative = 0x8, 445 positive = 0x9, 446 parity = 0xa, 447 noParity = 0xb 448 }; 449 450 enum Prefix { 451 // segment overrides 452 CS_segment = 0x2e, 453 SS_segment = 0x36, 454 DS_segment = 0x3e, 455 ES_segment = 0x26, 456 FS_segment = 0x64, 457 GS_segment = 0x65, 458 459 REX = 0x40, 460 461 REX_B = 0x41, 462 REX_X = 0x42, 463 REX_XB = 0x43, 464 REX_R = 0x44, 465 REX_RB = 0x45, 466 REX_RX = 0x46, 467 REX_RXB = 0x47, 468 469 REX_W = 0x48, 470 471 REX_WB = 0x49, 472 REX_WX = 0x4A, 473 REX_WXB = 0x4B, 474 REX_WR = 0x4C, 475 REX_WRB = 0x4D, 476 REX_WRX = 0x4E, 477 REX_WRXB = 0x4F 478 }; 479 480 enum WhichOperand { 481 // input to locate_operand, and format code for relocations 482 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 483 disp32_operand = 1, // embedded 32-bit displacement or address 484 call32_operand = 2, // embedded 32-bit self-relative displacement 485#ifndef _LP64 486 _WhichOperand_limit = 3 487#else 488 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 489 _WhichOperand_limit = 4 490#endif 491 }; 492 493 494 495 // NOTE: The general philopsophy of the declarations here is that 64bit versions 496 // of instructions are freely declared without the need for wrapping them an ifdef. 497 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 498 // In the .cpp file the implementations are wrapped so that they are dropped out 499 // of the resulting jvm. This is done mostly to keep the footprint of KERNEL 500 // to the size it was prior to merging up the 32bit and 64bit assemblers. 501 // 502 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 503 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 504 505private: 506 507 508 // 64bit prefixes 509 int prefix_and_encode(int reg_enc, bool byteinst = false); 510 int prefixq_and_encode(int reg_enc); 511 512 int prefix_and_encode(int dst_enc, int src_enc, bool byteinst = false); 513 int prefixq_and_encode(int dst_enc, int src_enc); 514 515 void prefix(Register reg); 516 void prefix(Address adr); 517 void prefixq(Address adr); 518 519 void prefix(Address adr, Register reg, bool byteinst = false); 520 void prefixq(Address adr, Register reg); 521 522 void prefix(Address adr, XMMRegister reg); 523 524 void prefetch_prefix(Address src); 525 526 // Helper functions for groups of instructions 527 void emit_arith_b(int op1, int op2, Register dst, int imm8); 528 529 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 530 // only 32bit?? 531 void emit_arith(int op1, int op2, Register dst, jobject obj); 532 void emit_arith(int op1, int op2, Register dst, Register src); 533 534 void emit_operand(Register reg, 535 Register base, Register index, Address::ScaleFactor scale, 536 int disp, 537 RelocationHolder const& rspec, 538 int rip_relative_correction = 0); 539 540 void emit_operand(Register reg, Address adr, int rip_relative_correction = 0); 541 542 // operands that only take the original 32bit registers 543 void emit_operand32(Register reg, Address adr); 544 545 void emit_operand(XMMRegister reg, 546 Register base, Register index, Address::ScaleFactor scale, 547 int disp, 548 RelocationHolder const& rspec); 549 550 void emit_operand(XMMRegister reg, Address adr); 551 552 void emit_operand(MMXRegister reg, Address adr); 553 554 // workaround gcc (3.2.1-7) bug 555 void emit_operand(Address adr, MMXRegister reg); 556 557 558 // Immediate-to-memory forms 559 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 560 561 void emit_farith(int b1, int b2, int i); 562 563 564 protected: 565 #ifdef ASSERT 566 void check_relocation(RelocationHolder const& rspec, int format); 567 #endif 568 569 inline void emit_long64(jlong x); 570 571 void emit_data(jint data, relocInfo::relocType rtype, int format); 572 void emit_data(jint data, RelocationHolder const& rspec, int format); 573 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 574 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 575 576 577 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 578 579 // These are all easily abused and hence protected 580 581 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec, int format = 0); 582 583 // 32BIT ONLY SECTION 584#ifndef _LP64 585 // Make these disappear in 64bit mode since they would never be correct 586 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 587 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 588 589 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 590 591 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 592#else 593 // 64BIT ONLY SECTION 594 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 595#endif // _LP64 596 597 // These are unique in that we are ensured by the caller that the 32bit 598 // relative in these instructions will always be able to reach the potentially 599 // 64bit address described by entry. Since they can take a 64bit address they 600 // don't have the 32 suffix like the other instructions in this class. 601 602 void call_literal(address entry, RelocationHolder const& rspec); 603 void jmp_literal(address entry, RelocationHolder const& rspec); 604 605 // Avoid using directly section 606 // Instructions in this section are actually usable by anyone without danger 607 // of failure but have performance issues that are addressed my enhanced 608 // instructions which will do the proper thing base on the particular cpu. 609 // We protect them because we don't trust you... 610 611 // Don't use next inc() and dec() methods directly. INC & DEC instructions 612 // could cause a partial flag stall since they don't set CF flag. 613 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 614 // which call inc() & dec() or add() & sub() in accordance with 615 // the product flag UseIncDec value. 616 617 void decl(Register dst); 618 void decl(Address dst); 619 void decq(Register dst); 620 void decq(Address dst); 621 622 void incl(Register dst); 623 void incl(Address dst); 624 void incq(Register dst); 625 void incq(Address dst); 626 627 // New cpus require use of movsd and movss to avoid partial register stall 628 // when loading from memory. But for old Opteron use movlpd instead of movsd. 629 // The selection is done in MacroAssembler::movdbl() and movflt(). 630 631 // Move Scalar Single-Precision Floating-Point Values 632 void movss(XMMRegister dst, Address src); 633 void movss(XMMRegister dst, XMMRegister src); 634 void movss(Address dst, XMMRegister src); 635 636 // Move Scalar Double-Precision Floating-Point Values 637 void movsd(XMMRegister dst, Address src); 638 void movsd(XMMRegister dst, XMMRegister src); 639 void movsd(Address dst, XMMRegister src); 640 void movlpd(XMMRegister dst, Address src); 641 642 // New cpus require use of movaps and movapd to avoid partial register stall 643 // when moving between registers. 644 void movaps(XMMRegister dst, XMMRegister src); 645 void movapd(XMMRegister dst, XMMRegister src); 646 647 // End avoid using directly 648 649 650 // Instruction prefixes 651 void prefix(Prefix p); 652 653 public: 654 655 // Creation 656 Assembler(CodeBuffer* code) : AbstractAssembler(code) {} 657 658 // Decoding 659 static address locate_operand(address inst, WhichOperand which); 660 static address locate_next_instruction(address inst); 661 662 // Utilities 663 664#ifdef _LP64 665 static bool is_simm(int64_t x, int nbits) { return -( CONST64(1) << (nbits-1) ) <= x && x < ( CONST64(1) << (nbits-1) ); } 666 static bool is_simm32(int64_t x) { return x == (int64_t)(int32_t)x; } 667#else 668 static bool is_simm(int32_t x, int nbits) { return -( 1 << (nbits-1) ) <= x && x < ( 1 << (nbits-1) ); } 669 static bool is_simm32(int32_t x) { return true; } 670#endif // LP64 671 672 // Generic instructions 673 // Does 32bit or 64bit as needed for the platform. In some sense these 674 // belong in macro assembler but there is no need for both varieties to exist 675 676 void lea(Register dst, Address src); 677 678 void mov(Register dst, Register src); 679 680 void pusha(); 681 void popa(); 682 683 void pushf(); 684 void popf(); 685 686 void push(int32_t imm32); 687 688 void push(Register src); 689 690 void pop(Register dst); 691 692 // These are dummies to prevent surprise implicit conversions to Register 693 void push(void* v); 694 void pop(void* v); 695 696 697 // These do register sized moves/scans 698 void rep_mov(); 699 void rep_set(); 700 void repne_scan(); 701#ifdef _LP64 702 void repne_scanl(); 703#endif 704 705 // Vanilla instructions in lexical order 706 707 void adcl(Register dst, int32_t imm32); 708 void adcl(Register dst, Address src); 709 void adcl(Register dst, Register src); 710 711 void adcq(Register dst, int32_t imm32); 712 void adcq(Register dst, Address src); 713 void adcq(Register dst, Register src); 714 715 716 void addl(Address dst, int32_t imm32); 717 void addl(Address dst, Register src); 718 void addl(Register dst, int32_t imm32); 719 void addl(Register dst, Address src); 720 void addl(Register dst, Register src); 721 722 void addq(Address dst, int32_t imm32); 723 void addq(Address dst, Register src); 724 void addq(Register dst, int32_t imm32); 725 void addq(Register dst, Address src); 726 void addq(Register dst, Register src); 727 728 729 void addr_nop_4(); 730 void addr_nop_5(); 731 void addr_nop_7(); 732 void addr_nop_8(); 733 734 // Add Scalar Double-Precision Floating-Point Values 735 void addsd(XMMRegister dst, Address src); 736 void addsd(XMMRegister dst, XMMRegister src); 737 738 // Add Scalar Single-Precision Floating-Point Values 739 void addss(XMMRegister dst, Address src); 740 void addss(XMMRegister dst, XMMRegister src); 741 742 void andl(Register dst, int32_t imm32); 743 void andl(Register dst, Address src); 744 void andl(Register dst, Register src); 745 746 void andq(Register dst, int32_t imm32); 747 void andq(Register dst, Address src); 748 void andq(Register dst, Register src); 749 750 751 // Bitwise Logical AND of Packed Double-Precision Floating-Point Values 752 void andpd(XMMRegister dst, Address src); 753 void andpd(XMMRegister dst, XMMRegister src); 754 755 void bswapl(Register reg); 756 757 void bswapq(Register reg); 758 759 void call(Label& L, relocInfo::relocType rtype); 760 void call(Register reg); // push pc; pc <- reg 761 void call(Address adr); // push pc; pc <- adr 762 763 void cdql(); 764 765 void cdqq(); 766 767 void cld() { emit_byte(0xfc); } 768 769 void clflush(Address adr); 770 771 void cmovl(Condition cc, Register dst, Register src); 772 void cmovl(Condition cc, Register dst, Address src); 773 774 void cmovq(Condition cc, Register dst, Register src); 775 void cmovq(Condition cc, Register dst, Address src); 776 777 778 void cmpb(Address dst, int imm8); 779 780 void cmpl(Address dst, int32_t imm32); 781 782 void cmpl(Register dst, int32_t imm32); 783 void cmpl(Register dst, Register src); 784 void cmpl(Register dst, Address src); 785 786 void cmpq(Address dst, int32_t imm32); 787 void cmpq(Address dst, Register src); 788 789 void cmpq(Register dst, int32_t imm32); 790 void cmpq(Register dst, Register src); 791 void cmpq(Register dst, Address src); 792 793 // these are dummies used to catch attempting to convert NULL to Register 794 void cmpl(Register dst, void* junk); // dummy 795 void cmpq(Register dst, void* junk); // dummy 796 797 void cmpw(Address dst, int imm16); 798 799 void cmpxchg8 (Address adr); 800 801 void cmpxchgl(Register reg, Address adr); 802 803 void cmpxchgq(Register reg, Address adr); 804 805 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 806 void comisd(XMMRegister dst, Address src); 807 808 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 809 void comiss(XMMRegister dst, Address src); 810 811 // Identify processor type and features 812 void cpuid() { 813 emit_byte(0x0F); 814 emit_byte(0xA2); 815 } 816 817 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 818 void cvtsd2ss(XMMRegister dst, XMMRegister src); 819 820 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 821 void cvtsi2sdl(XMMRegister dst, Register src); 822 void cvtsi2sdq(XMMRegister dst, Register src); 823 824 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 825 void cvtsi2ssl(XMMRegister dst, Register src); 826 void cvtsi2ssq(XMMRegister dst, Register src); 827 828 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 829 void cvtdq2pd(XMMRegister dst, XMMRegister src); 830 831 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 832 void cvtdq2ps(XMMRegister dst, XMMRegister src); 833 834 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 835 void cvtss2sd(XMMRegister dst, XMMRegister src); 836 837 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 838 void cvttsd2sil(Register dst, Address src); 839 void cvttsd2sil(Register dst, XMMRegister src); 840 void cvttsd2siq(Register dst, XMMRegister src); 841 842 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 843 void cvttss2sil(Register dst, XMMRegister src); 844 void cvttss2siq(Register dst, XMMRegister src); 845 846 // Divide Scalar Double-Precision Floating-Point Values 847 void divsd(XMMRegister dst, Address src); 848 void divsd(XMMRegister dst, XMMRegister src); 849 850 // Divide Scalar Single-Precision Floating-Point Values 851 void divss(XMMRegister dst, Address src); 852 void divss(XMMRegister dst, XMMRegister src); 853 854 void emms(); 855 856 void fabs(); 857 858 void fadd(int i); 859 860 void fadd_d(Address src); 861 void fadd_s(Address src); 862 863 // "Alternate" versions of x87 instructions place result down in FPU 864 // stack instead of on TOS 865 866 void fadda(int i); // "alternate" fadd 867 void faddp(int i = 1); 868 869 void fchs(); 870 871 void fcom(int i); 872 873 void fcomp(int i = 1); 874 void fcomp_d(Address src); 875 void fcomp_s(Address src); 876 877 void fcompp(); 878 879 void fcos(); 880 881 void fdecstp(); 882 883 void fdiv(int i); 884 void fdiv_d(Address src); 885 void fdivr_s(Address src); 886 void fdiva(int i); // "alternate" fdiv 887 void fdivp(int i = 1); 888 889 void fdivr(int i); 890 void fdivr_d(Address src); 891 void fdiv_s(Address src); 892 893 void fdivra(int i); // "alternate" reversed fdiv 894 895 void fdivrp(int i = 1); 896 897 void ffree(int i = 0); 898 899 void fild_d(Address adr); 900 void fild_s(Address adr); 901 902 void fincstp(); 903 904 void finit(); 905 906 void fist_s (Address adr); 907 void fistp_d(Address adr); 908 void fistp_s(Address adr); 909 910 void fld1(); 911 912 void fld_d(Address adr); 913 void fld_s(Address adr); 914 void fld_s(int index); 915 void fld_x(Address adr); // extended-precision (80-bit) format 916 917 void fldcw(Address src); 918 919 void fldenv(Address src); 920 921 void fldlg2(); 922 923 void fldln2(); 924 925 void fldz(); 926 927 void flog(); 928 void flog10(); 929 930 void fmul(int i); 931 932 void fmul_d(Address src); 933 void fmul_s(Address src); 934 935 void fmula(int i); // "alternate" fmul 936 937 void fmulp(int i = 1); 938 939 void fnsave(Address dst); 940 941 void fnstcw(Address src); 942 943 void fnstsw_ax(); 944 945 void fprem(); 946 void fprem1(); 947 948 void frstor(Address src); 949 950 void fsin(); 951 952 void fsqrt(); 953 954 void fst_d(Address adr); 955 void fst_s(Address adr); 956 957 void fstp_d(Address adr); 958 void fstp_d(int index); 959 void fstp_s(Address adr); 960 void fstp_x(Address adr); // extended-precision (80-bit) format 961 962 void fsub(int i); 963 void fsub_d(Address src); 964 void fsub_s(Address src); 965 966 void fsuba(int i); // "alternate" fsub 967 968 void fsubp(int i = 1); 969 970 void fsubr(int i); 971 void fsubr_d(Address src); 972 void fsubr_s(Address src); 973 974 void fsubra(int i); // "alternate" reversed fsub 975 976 void fsubrp(int i = 1); 977 978 void ftan(); 979 980 void ftst(); 981 982 void fucomi(int i = 1); 983 void fucomip(int i = 1); 984 985 void fwait(); 986 987 void fxch(int i = 1); 988 989 void fxrstor(Address src); 990 991 void fxsave(Address dst); 992 993 void fyl2x(); 994 995 void hlt(); 996 997 void idivl(Register src); 998 999 void idivq(Register src); 1000 1001 void imull(Register dst, Register src); 1002 void imull(Register dst, Register src, int value); 1003 1004 void imulq(Register dst, Register src); 1005 void imulq(Register dst, Register src, int value); 1006 1007 1008 // jcc is the generic conditional branch generator to run- 1009 // time routines, jcc is used for branches to labels. jcc 1010 // takes a branch opcode (cc) and a label (L) and generates 1011 // either a backward branch or a forward branch and links it 1012 // to the label fixup chain. Usage: 1013 // 1014 // Label L; // unbound label 1015 // jcc(cc, L); // forward branch to unbound label 1016 // bind(L); // bind label to the current pc 1017 // jcc(cc, L); // backward branch to bound label 1018 // bind(L); // illegal: a label may be bound only once 1019 // 1020 // Note: The same Label can be used for forward and backward branches 1021 // but it may be bound only once. 1022 1023 void jcc(Condition cc, Label& L, 1024 relocInfo::relocType rtype = relocInfo::none); 1025 1026 // Conditional jump to a 8-bit offset to L. 1027 // WARNING: be very careful using this for forward jumps. If the label is 1028 // not bound within an 8-bit offset of this instruction, a run-time error 1029 // will occur. 1030 void jccb(Condition cc, Label& L); 1031 1032 void jmp(Address entry); // pc <- entry 1033 1034 // Label operations & relative jumps (PPUM Appendix D) 1035 void jmp(Label& L, relocInfo::relocType rtype = relocInfo::none); // unconditional jump to L 1036 1037 void jmp(Register entry); // pc <- entry 1038 1039 // Unconditional 8-bit offset jump to L. 1040 // WARNING: be very careful using this for forward jumps. If the label is 1041 // not bound within an 8-bit offset of this instruction, a run-time error 1042 // will occur. 1043 void jmpb(Label& L); 1044 1045 void ldmxcsr( Address src ); 1046 1047 void leal(Register dst, Address src); 1048 1049 void leaq(Register dst, Address src); 1050 1051 void lfence() { 1052 emit_byte(0x0F); 1053 emit_byte(0xAE); 1054 emit_byte(0xE8); 1055 } 1056 1057 void lock(); 1058 1059 enum Membar_mask_bits { 1060 StoreStore = 1 << 3, 1061 LoadStore = 1 << 2, 1062 StoreLoad = 1 << 1, 1063 LoadLoad = 1 << 0 1064 }; 1065 1066 // Serializes memory. 1067 void membar(Membar_mask_bits order_constraint) { 1068 // We only have to handle StoreLoad and LoadLoad 1069 if (order_constraint & StoreLoad) { 1070 // MFENCE subsumes LFENCE 1071 mfence(); 1072 } /* [jk] not needed currently: else if (order_constraint & LoadLoad) { 1073 lfence(); 1074 } */ 1075 } 1076 1077 void mfence(); 1078 1079 // Moves 1080 1081 void mov64(Register dst, int64_t imm64); 1082 1083 void movb(Address dst, Register src); 1084 void movb(Address dst, int imm8); 1085 void movb(Register dst, Address src); 1086 1087 void movdl(XMMRegister dst, Register src); 1088 void movdl(Register dst, XMMRegister src); 1089 1090 // Move Double Quadword 1091 void movdq(XMMRegister dst, Register src); 1092 void movdq(Register dst, XMMRegister src); 1093 1094 // Move Aligned Double Quadword 1095 void movdqa(Address dst, XMMRegister src); 1096 void movdqa(XMMRegister dst, Address src); 1097 void movdqa(XMMRegister dst, XMMRegister src); 1098 1099 // Move Unaligned Double Quadword 1100 void movdqu(Address dst, XMMRegister src); 1101 void movdqu(XMMRegister dst, Address src); 1102 void movdqu(XMMRegister dst, XMMRegister src); 1103 1104 void movl(Register dst, int32_t imm32); 1105 void movl(Address dst, int32_t imm32); 1106 void movl(Register dst, Register src); 1107 void movl(Register dst, Address src); 1108 void movl(Address dst, Register src); 1109 1110 // These dummies prevent using movl from converting a zero (like NULL) into Register 1111 // by giving the compiler two choices it can't resolve 1112 1113 void movl(Address dst, void* junk); 1114 void movl(Register dst, void* junk); 1115 1116#ifdef _LP64 1117 void movq(Register dst, Register src); 1118 void movq(Register dst, Address src); 1119 void movq(Address dst, Register src); 1120#endif 1121 1122 void movq(Address dst, MMXRegister src ); 1123 void movq(MMXRegister dst, Address src ); 1124 1125#ifdef _LP64 1126 // These dummies prevent using movq from converting a zero (like NULL) into Register 1127 // by giving the compiler two choices it can't resolve 1128 1129 void movq(Address dst, void* dummy); 1130 void movq(Register dst, void* dummy); 1131#endif 1132 1133 // Move Quadword 1134 void movq(Address dst, XMMRegister src); 1135 void movq(XMMRegister dst, Address src); 1136 1137 void movsbl(Register dst, Address src); 1138 void movsbl(Register dst, Register src); 1139 1140#ifdef _LP64 1141 // Move signed 32bit immediate to 64bit extending sign 1142 void movslq(Address dst, int32_t imm64); 1143 void movslq(Register dst, int32_t imm64); 1144 1145 void movslq(Register dst, Address src); 1146 void movslq(Register dst, Register src); 1147 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1148#endif 1149 1150 void movswl(Register dst, Address src); 1151 void movswl(Register dst, Register src); 1152 1153 void movw(Address dst, int imm16); 1154 void movw(Register dst, Address src); 1155 void movw(Address dst, Register src); 1156 1157 void movzbl(Register dst, Address src); 1158 void movzbl(Register dst, Register src); 1159 1160 void movzwl(Register dst, Address src); 1161 void movzwl(Register dst, Register src); 1162 1163 void mull(Address src); 1164 void mull(Register src); 1165 1166 // Multiply Scalar Double-Precision Floating-Point Values 1167 void mulsd(XMMRegister dst, Address src); 1168 void mulsd(XMMRegister dst, XMMRegister src); 1169 1170 // Multiply Scalar Single-Precision Floating-Point Values 1171 void mulss(XMMRegister dst, Address src); 1172 void mulss(XMMRegister dst, XMMRegister src); 1173 1174 void negl(Register dst); 1175 1176#ifdef _LP64 1177 void negq(Register dst); 1178#endif 1179 1180 void nop(int i = 1); 1181 1182 void notl(Register dst); 1183 1184#ifdef _LP64 1185 void notq(Register dst); 1186#endif 1187 1188 void orl(Address dst, int32_t imm32); 1189 void orl(Register dst, int32_t imm32); 1190 void orl(Register dst, Address src); 1191 void orl(Register dst, Register src); 1192 1193 void orq(Address dst, int32_t imm32); 1194 void orq(Register dst, int32_t imm32); 1195 void orq(Register dst, Address src); 1196 void orq(Register dst, Register src); 1197 1198 void popl(Address dst); 1199 1200#ifdef _LP64 1201 void popq(Address dst); 1202#endif 1203 1204 // Prefetches (SSE, SSE2, 3DNOW only) 1205 1206 void prefetchnta(Address src); 1207 void prefetchr(Address src); 1208 void prefetcht0(Address src); 1209 void prefetcht1(Address src); 1210 void prefetcht2(Address src); 1211 void prefetchw(Address src); 1212 1213 // Shuffle Packed Doublewords 1214 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1215 void pshufd(XMMRegister dst, Address src, int mode); 1216 1217 // Shuffle Packed Low Words 1218 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1219 void pshuflw(XMMRegister dst, Address src, int mode); 1220 1221 // Shift Right Logical Quadword Immediate 1222 void psrlq(XMMRegister dst, int shift); 1223 1224 // Interleave Low Bytes 1225 void punpcklbw(XMMRegister dst, XMMRegister src); 1226 1227 void pushl(Address src); 1228 1229 void pushq(Address src); 1230 1231 // Xor Packed Byte Integer Values 1232 void pxor(XMMRegister dst, Address src); 1233 void pxor(XMMRegister dst, XMMRegister src); 1234 1235 void rcll(Register dst, int imm8); 1236 1237 void rclq(Register dst, int imm8); 1238 1239 void ret(int imm16); 1240 1241 void sahf(); 1242 1243 void sarl(Register dst, int imm8); 1244 void sarl(Register dst); 1245 1246 void sarq(Register dst, int imm8); 1247 void sarq(Register dst); 1248 1249 void sbbl(Address dst, int32_t imm32); 1250 void sbbl(Register dst, int32_t imm32); 1251 void sbbl(Register dst, Address src); 1252 void sbbl(Register dst, Register src); 1253 1254 void sbbq(Address dst, int32_t imm32); 1255 void sbbq(Register dst, int32_t imm32); 1256 void sbbq(Register dst, Address src); 1257 void sbbq(Register dst, Register src); 1258 1259 void setb(Condition cc, Register dst); 1260 1261 void shldl(Register dst, Register src); 1262 1263 void shll(Register dst, int imm8); 1264 void shll(Register dst); 1265 1266 void shlq(Register dst, int imm8); 1267 void shlq(Register dst); 1268 1269 void shrdl(Register dst, Register src); 1270 1271 void shrl(Register dst, int imm8); 1272 void shrl(Register dst); 1273 1274 void shrq(Register dst, int imm8); 1275 void shrq(Register dst); 1276 1277 void smovl(); // QQQ generic? 1278 1279 // Compute Square Root of Scalar Double-Precision Floating-Point Value 1280 void sqrtsd(XMMRegister dst, Address src); 1281 void sqrtsd(XMMRegister dst, XMMRegister src); 1282 1283 void std() { emit_byte(0xfd); } 1284 1285 void stmxcsr( Address dst ); 1286 1287 void subl(Address dst, int32_t imm32); 1288 void subl(Address dst, Register src); 1289 void subl(Register dst, int32_t imm32); 1290 void subl(Register dst, Address src); 1291 void subl(Register dst, Register src); 1292 1293 void subq(Address dst, int32_t imm32); 1294 void subq(Address dst, Register src); 1295 void subq(Register dst, int32_t imm32); 1296 void subq(Register dst, Address src); 1297 void subq(Register dst, Register src); 1298 1299 1300 // Subtract Scalar Double-Precision Floating-Point Values 1301 void subsd(XMMRegister dst, Address src); 1302 void subsd(XMMRegister dst, XMMRegister src); 1303 1304 // Subtract Scalar Single-Precision Floating-Point Values 1305 void subss(XMMRegister dst, Address src); 1306 void subss(XMMRegister dst, XMMRegister src); 1307 1308 void testb(Register dst, int imm8); 1309 1310 void testl(Register dst, int32_t imm32); 1311 void testl(Register dst, Register src); 1312 void testl(Register dst, Address src); 1313 1314 void testq(Register dst, int32_t imm32); 1315 void testq(Register dst, Register src); 1316 1317 1318 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1319 void ucomisd(XMMRegister dst, Address src); 1320 void ucomisd(XMMRegister dst, XMMRegister src); 1321 1322 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1323 void ucomiss(XMMRegister dst, Address src); 1324 void ucomiss(XMMRegister dst, XMMRegister src); 1325 1326 void xaddl(Address dst, Register src); 1327 1328 void xaddq(Address dst, Register src); 1329 1330 void xchgl(Register reg, Address adr); 1331 void xchgl(Register dst, Register src); 1332 1333 void xchgq(Register reg, Address adr); 1334 void xchgq(Register dst, Register src); 1335 1336 void xorl(Register dst, int32_t imm32); 1337 void xorl(Register dst, Address src); 1338 void xorl(Register dst, Register src); 1339 1340 void xorq(Register dst, Address src); 1341 void xorq(Register dst, Register src); 1342 1343 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 1344 void xorpd(XMMRegister dst, Address src); 1345 void xorpd(XMMRegister dst, XMMRegister src); 1346 1347 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 1348 void xorps(XMMRegister dst, Address src); 1349 void xorps(XMMRegister dst, XMMRegister src); 1350 1351 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 1352}; 1353 1354 1355// MacroAssembler extends Assembler by frequently used macros. 1356// 1357// Instructions for which a 'better' code sequence exists depending 1358// on arguments should also go in here. 1359 1360class MacroAssembler: public Assembler { 1361 friend class LIR_Assembler; 1362 friend class Runtime1; // as_Address() 1363 protected: 1364 1365 Address as_Address(AddressLiteral adr); 1366 Address as_Address(ArrayAddress adr); 1367 1368 // Support for VM calls 1369 // 1370 // This is the base routine called by the different versions of call_VM_leaf. The interpreter 1371 // may customize this version by overriding it for its purposes (e.g., to save/restore 1372 // additional registers when doing a VM call). 1373#ifdef CC_INTERP 1374 // c++ interpreter never wants to use interp_masm version of call_VM 1375 #define VIRTUAL 1376#else 1377 #define VIRTUAL virtual 1378#endif 1379 1380 VIRTUAL void call_VM_leaf_base( 1381 address entry_point, // the entry point 1382 int number_of_arguments // the number of arguments to pop after the call 1383 ); 1384 1385 // This is the base routine called by the different versions of call_VM. The interpreter 1386 // may customize this version by overriding it for its purposes (e.g., to save/restore 1387 // additional registers when doing a VM call). 1388 // 1389 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base 1390 // returns the register which contains the thread upon return. If a thread register has been 1391 // specified, the return value will correspond to that register. If no last_java_sp is specified 1392 // (noreg) than rsp will be used instead. 1393 VIRTUAL void call_VM_base( // returns the register containing the thread upon return 1394 Register oop_result, // where an oop-result ends up if any; use noreg otherwise 1395 Register java_thread, // the thread if computed before ; use noreg otherwise 1396 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise 1397 address entry_point, // the entry point 1398 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call 1399 bool check_exceptions // whether to check for pending exceptions after return 1400 ); 1401 1402 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 1403 // The implementation is only non-empty for the InterpreterMacroAssembler, 1404 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 1405 virtual void check_and_handle_popframe(Register java_thread); 1406 virtual void check_and_handle_earlyret(Register java_thread); 1407 1408 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true); 1409 1410 // helpers for FPU flag access 1411 // tmp is a temporary register, if none is available use noreg 1412 void save_rax (Register tmp); 1413 void restore_rax(Register tmp); 1414 1415 public: 1416 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 1417 1418 // Support for NULL-checks 1419 // 1420 // Generates code that causes a NULL OS exception if the content of reg is NULL. 1421 // If the accessed location is M[reg + offset] and the offset is known, provide the 1422 // offset. No explicit code generation is needed if the offset is within a certain 1423 // range (0 <= offset <= page_size). 1424 1425 void null_check(Register reg, int offset = -1); 1426 static bool needs_explicit_null_check(intptr_t offset); 1427 1428 // Required platform-specific helpers for Label::patch_instructions. 1429 // They _shadow_ the declarations in AbstractAssembler, which are undefined. 1430 void pd_patch_instruction(address branch, address target); 1431#ifndef PRODUCT 1432 static void pd_print_patched_instruction(address branch); 1433#endif 1434 1435 // The following 4 methods return the offset of the appropriate move instruction 1436 1437 // Support for fast byte/short loading with zero extension (depending on particular CPU) 1438 int load_unsigned_byte(Register dst, Address src); 1439 int load_unsigned_short(Register dst, Address src); 1440 1441 // Support for fast byte/short loading with sign extension (depending on particular CPU) 1442 int load_signed_byte(Register dst, Address src); 1443 int load_signed_short(Register dst, Address src); 1444 1445 // Support for sign-extension (hi:lo = extend_sign(lo)) 1446 void extend_sign(Register hi, Register lo); 1447 1448 // Loading values by size and signed-ness 1449 void load_sized_value(Register dst, Address src, int size_in_bytes, bool is_signed); 1450 1451 // Support for inc/dec with optimal instruction selection depending on value 1452 1453 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; } 1454 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; } 1455 1456 void decrementl(Address dst, int value = 1); 1457 void decrementl(Register reg, int value = 1); 1458 1459 void decrementq(Register reg, int value = 1); 1460 void decrementq(Address dst, int value = 1); 1461 1462 void incrementl(Address dst, int value = 1); 1463 void incrementl(Register reg, int value = 1); 1464 1465 void incrementq(Register reg, int value = 1); 1466 void incrementq(Address dst, int value = 1); 1467 1468 1469 // Support optimal SSE move instructions. 1470 void movflt(XMMRegister dst, XMMRegister src) { 1471 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; } 1472 else { movss (dst, src); return; } 1473 } 1474 void movflt(XMMRegister dst, Address src) { movss(dst, src); } 1475 void movflt(XMMRegister dst, AddressLiteral src); 1476 void movflt(Address dst, XMMRegister src) { movss(dst, src); } 1477 1478 void movdbl(XMMRegister dst, XMMRegister src) { 1479 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; } 1480 else { movsd (dst, src); return; } 1481 } 1482 1483 void movdbl(XMMRegister dst, AddressLiteral src); 1484 1485 void movdbl(XMMRegister dst, Address src) { 1486 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; } 1487 else { movlpd(dst, src); return; } 1488 } 1489 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); } 1490 1491 void incrementl(AddressLiteral dst); 1492 void incrementl(ArrayAddress dst); 1493 1494 // Alignment 1495 void align(int modulus); 1496 1497 // Misc 1498 void fat_nop(); // 5 byte nop 1499 1500 // Stack frame creation/removal 1501 void enter(); 1502 void leave(); 1503 1504 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information) 1505 // The pointer will be loaded into the thread register. 1506 void get_thread(Register thread); 1507 1508 1509 // Support for VM calls 1510 // 1511 // It is imperative that all calls into the VM are handled via the call_VM macros. 1512 // They make sure that the stack linkage is setup correctly. call_VM's correspond 1513 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points. 1514 1515 1516 void call_VM(Register oop_result, 1517 address entry_point, 1518 bool check_exceptions = true); 1519 void call_VM(Register oop_result, 1520 address entry_point, 1521 Register arg_1, 1522 bool check_exceptions = true); 1523 void call_VM(Register oop_result, 1524 address entry_point, 1525 Register arg_1, Register arg_2, 1526 bool check_exceptions = true); 1527 void call_VM(Register oop_result, 1528 address entry_point, 1529 Register arg_1, Register arg_2, Register arg_3, 1530 bool check_exceptions = true); 1531 1532 // Overloadings with last_Java_sp 1533 void call_VM(Register oop_result, 1534 Register last_java_sp, 1535 address entry_point, 1536 int number_of_arguments = 0, 1537 bool check_exceptions = true); 1538 void call_VM(Register oop_result, 1539 Register last_java_sp, 1540 address entry_point, 1541 Register arg_1, bool 1542 check_exceptions = true); 1543 void call_VM(Register oop_result, 1544 Register last_java_sp, 1545 address entry_point, 1546 Register arg_1, Register arg_2, 1547 bool check_exceptions = true); 1548 void call_VM(Register oop_result, 1549 Register last_java_sp, 1550 address entry_point, 1551 Register arg_1, Register arg_2, Register arg_3, 1552 bool check_exceptions = true); 1553 1554 void call_VM_leaf(address entry_point, 1555 int number_of_arguments = 0); 1556 void call_VM_leaf(address entry_point, 1557 Register arg_1); 1558 void call_VM_leaf(address entry_point, 1559 Register arg_1, Register arg_2); 1560 void call_VM_leaf(address entry_point, 1561 Register arg_1, Register arg_2, Register arg_3); 1562 1563 // last Java Frame (fills frame anchor) 1564 void set_last_Java_frame(Register thread, 1565 Register last_java_sp, 1566 Register last_java_fp, 1567 address last_java_pc); 1568 1569 // thread in the default location (r15_thread on 64bit) 1570 void set_last_Java_frame(Register last_java_sp, 1571 Register last_java_fp, 1572 address last_java_pc); 1573 1574 void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc); 1575 1576 // thread in the default location (r15_thread on 64bit) 1577 void reset_last_Java_frame(bool clear_fp, bool clear_pc); 1578 1579 // Stores 1580 void store_check(Register obj); // store check for obj - register is destroyed afterwards 1581 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed) 1582 1583 void g1_write_barrier_pre(Register obj, 1584#ifndef _LP64 1585 Register thread, 1586#endif 1587 Register tmp, 1588 Register tmp2, 1589 bool tosca_live); 1590 void g1_write_barrier_post(Register store_addr, 1591 Register new_val, 1592#ifndef _LP64 1593 Register thread, 1594#endif 1595 Register tmp, 1596 Register tmp2); 1597 1598 1599 // split store_check(Register obj) to enhance instruction interleaving 1600 void store_check_part_1(Register obj); 1601 void store_check_part_2(Register obj); 1602 1603 // C 'boolean' to Java boolean: x == 0 ? 0 : 1 1604 void c2bool(Register x); 1605 1606 // C++ bool manipulation 1607 1608 void movbool(Register dst, Address src); 1609 void movbool(Address dst, bool boolconst); 1610 void movbool(Address dst, Register src); 1611 void testbool(Register dst); 1612 1613 // oop manipulations 1614 void load_klass(Register dst, Register src); 1615 void store_klass(Register dst, Register src); 1616 1617 void load_prototype_header(Register dst, Register src); 1618 1619#ifdef _LP64 1620 void store_klass_gap(Register dst, Register src); 1621 1622 void load_heap_oop(Register dst, Address src); 1623 void store_heap_oop(Address dst, Register src); 1624 void encode_heap_oop(Register r); 1625 void decode_heap_oop(Register r); 1626 void encode_heap_oop_not_null(Register r); 1627 void decode_heap_oop_not_null(Register r); 1628 void encode_heap_oop_not_null(Register dst, Register src); 1629 void decode_heap_oop_not_null(Register dst, Register src); 1630 1631 void set_narrow_oop(Register dst, jobject obj); 1632 1633 // if heap base register is used - reinit it with the correct value 1634 void reinit_heapbase(); 1635#endif // _LP64 1636 1637 // Int division/remainder for Java 1638 // (as idivl, but checks for special case as described in JVM spec.) 1639 // returns idivl instruction offset for implicit exception handling 1640 int corrected_idivl(Register reg); 1641 1642 // Long division/remainder for Java 1643 // (as idivq, but checks for special case as described in JVM spec.) 1644 // returns idivq instruction offset for implicit exception handling 1645 int corrected_idivq(Register reg); 1646 1647 void int3(); 1648 1649 // Long operation macros for a 32bit cpu 1650 // Long negation for Java 1651 void lneg(Register hi, Register lo); 1652 1653 // Long multiplication for Java 1654 // (destroys contents of eax, ebx, ecx and edx) 1655 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y 1656 1657 // Long shifts for Java 1658 // (semantics as described in JVM spec.) 1659 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f) 1660 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f) 1661 1662 // Long compare for Java 1663 // (semantics as described in JVM spec.) 1664 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y) 1665 1666 1667 // misc 1668 1669 // Sign extension 1670 void sign_extend_short(Register reg); 1671 void sign_extend_byte(Register reg); 1672 1673 // Division by power of 2, rounding towards 0 1674 void division_with_shift(Register reg, int shift_value); 1675 1676 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows: 1677 // 1678 // CF (corresponds to C0) if x < y 1679 // PF (corresponds to C2) if unordered 1680 // ZF (corresponds to C3) if x = y 1681 // 1682 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 1683 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code) 1684 void fcmp(Register tmp); 1685 // Variant of the above which allows y to be further down the stack 1686 // and which only pops x and y if specified. If pop_right is 1687 // specified then pop_left must also be specified. 1688 void fcmp(Register tmp, int index, bool pop_left, bool pop_right); 1689 1690 // Floating-point comparison for Java 1691 // Compares the top-most stack entries on the FPU stack and stores the result in dst. 1692 // The arguments are in reversed order on the stack (i.e., top of stack is first argument). 1693 // (semantics as described in JVM spec.) 1694 void fcmp2int(Register dst, bool unordered_is_less); 1695 // Variant of the above which allows y to be further down the stack 1696 // and which only pops x and y if specified. If pop_right is 1697 // specified then pop_left must also be specified. 1698 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right); 1699 1700 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards) 1701 // tmp is a temporary register, if none is available use noreg 1702 void fremr(Register tmp); 1703 1704 1705 // same as fcmp2int, but using SSE2 1706 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 1707 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less); 1708 1709 // Inlined sin/cos generator for Java; must not use CPU instruction 1710 // directly on Intel as it does not have high enough precision 1711 // outside of the range [-pi/4, pi/4]. Extra argument indicate the 1712 // number of FPU stack slots in use; all but the topmost will 1713 // require saving if a slow case is necessary. Assumes argument is 1714 // on FP TOS; result is on FP TOS. No cpu registers are changed by 1715 // this code. 1716 void trigfunc(char trig, int num_fpu_regs_in_use = 1); 1717 1718 // branch to L if FPU flag C2 is set/not set 1719 // tmp is a temporary register, if none is available use noreg 1720 void jC2 (Register tmp, Label& L); 1721 void jnC2(Register tmp, Label& L); 1722 1723 // Pop ST (ffree & fincstp combined) 1724 void fpop(); 1725 1726 // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack 1727 void push_fTOS(); 1728 1729 // pops double TOS element from CPU stack and pushes on FPU stack 1730 void pop_fTOS(); 1731 1732 void empty_FPU_stack(); 1733 1734 void push_IU_state(); 1735 void pop_IU_state(); 1736 1737 void push_FPU_state(); 1738 void pop_FPU_state(); 1739 1740 void push_CPU_state(); 1741 void pop_CPU_state(); 1742 1743 // Round up to a power of two 1744 void round_to(Register reg, int modulus); 1745 1746 // Callee saved registers handling 1747 void push_callee_saved_registers(); 1748 void pop_callee_saved_registers(); 1749 1750 // allocation 1751 void eden_allocate( 1752 Register obj, // result: pointer to object after successful allocation 1753 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1754 int con_size_in_bytes, // object size in bytes if known at compile time 1755 Register t1, // temp register 1756 Label& slow_case // continuation point if fast allocation fails 1757 ); 1758 void tlab_allocate( 1759 Register obj, // result: pointer to object after successful allocation 1760 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise 1761 int con_size_in_bytes, // object size in bytes if known at compile time 1762 Register t1, // temp register 1763 Register t2, // temp register 1764 Label& slow_case // continuation point if fast allocation fails 1765 ); 1766 void tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); 1767 1768 // interface method calling 1769 void lookup_interface_method(Register recv_klass, 1770 Register intf_klass, 1771 RegisterConstant itable_index, 1772 Register method_result, 1773 Register scan_temp, 1774 Label& no_such_interface); 1775 1776 //---- 1777 void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0 1778 1779 // Debugging 1780 1781 // only if +VerifyOops 1782 void verify_oop(Register reg, const char* s = "broken oop"); 1783 void verify_oop_addr(Address addr, const char * s = "broken oop addr"); 1784 1785 // only if +VerifyFPU 1786 void verify_FPU(int stack_depth, const char* s = "illegal FPU state"); 1787 1788 // prints msg, dumps registers and stops execution 1789 void stop(const char* msg); 1790 1791 // prints msg and continues 1792 void warn(const char* msg); 1793 1794 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg); 1795 static void debug64(char* msg, int64_t pc, int64_t regs[]); 1796 1797 void os_breakpoint(); 1798 1799 void untested() { stop("untested"); } 1800 1801 void unimplemented(const char* what = "") { char* b = new char[1024]; jio_snprintf(b, sizeof(b), "unimplemented: %s", what); stop(b); } 1802 1803 void should_not_reach_here() { stop("should not reach here"); } 1804 1805 void print_CPU_state(); 1806 1807 // Stack overflow checking 1808 void bang_stack_with_offset(int offset) { 1809 // stack grows down, caller passes positive offset 1810 assert(offset > 0, "must bang with negative offset"); 1811 movl(Address(rsp, (-offset)), rax); 1812 } 1813 1814 // Writes to stack successive pages until offset reached to check for 1815 // stack overflow + shadow pages. Also, clobbers tmp 1816 void bang_stack_size(Register size, Register tmp); 1817 1818 virtual RegisterConstant delayed_value(intptr_t* delayed_value_addr, 1819 Register tmp, 1820 int offset); 1821 1822 // Support for serializing memory accesses between threads 1823 void serialize_memory(Register thread, Register tmp); 1824 1825 void verify_tlab(); 1826 1827 // Biased locking support 1828 // lock_reg and obj_reg must be loaded up with the appropriate values. 1829 // swap_reg must be rax, and is killed. 1830 // tmp_reg is optional. If it is supplied (i.e., != noreg) it will 1831 // be killed; if not supplied, push/pop will be used internally to 1832 // allocate a temporary (inefficient, avoid if possible). 1833 // Optional slow case is for implementations (interpreter and C1) which branch to 1834 // slow case directly. Leaves condition codes set for C2's Fast_Lock node. 1835 // Returns offset of first potentially-faulting instruction for null 1836 // check info (currently consumed only by C1). If 1837 // swap_reg_contains_mark is true then returns -1 as it is assumed 1838 // the calling code has already passed any potential faults. 1839 int biased_locking_enter(Register lock_reg, Register obj_reg, 1840 Register swap_reg, Register tmp_reg, 1841 bool swap_reg_contains_mark, 1842 Label& done, Label* slow_case = NULL, 1843 BiasedLockingCounters* counters = NULL); 1844 void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done); 1845 1846 1847 Condition negate_condition(Condition cond); 1848 1849 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit 1850 // operands. In general the names are modified to avoid hiding the instruction in Assembler 1851 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers 1852 // here in MacroAssembler. The major exception to this rule is call 1853 1854 // Arithmetics 1855 1856 1857 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; } 1858 void addptr(Address dst, Register src); 1859 1860 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); } 1861 void addptr(Register dst, int32_t src); 1862 void addptr(Register dst, Register src); 1863 1864 void andptr(Register dst, int32_t src); 1865 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; } 1866 1867 void cmp8(AddressLiteral src1, int imm); 1868 1869 // renamed to drag out the casting of address to int32_t/intptr_t 1870 void cmp32(Register src1, int32_t imm); 1871 1872 void cmp32(AddressLiteral src1, int32_t imm); 1873 // compare reg - mem, or reg - &mem 1874 void cmp32(Register src1, AddressLiteral src2); 1875 1876 void cmp32(Register src1, Address src2); 1877 1878#ifndef _LP64 1879 void cmpoop(Address dst, jobject obj); 1880 void cmpoop(Register dst, jobject obj); 1881#endif // _LP64 1882 1883 // NOTE src2 must be the lval. This is NOT an mem-mem compare 1884 void cmpptr(Address src1, AddressLiteral src2); 1885 1886 void cmpptr(Register src1, AddressLiteral src2); 1887 1888 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 1889 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 1890 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 1891 1892 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 1893 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; } 1894 1895 // cmp64 to avoild hiding cmpq 1896 void cmp64(Register src1, AddressLiteral src); 1897 1898 void cmpxchgptr(Register reg, Address adr); 1899 1900 void locked_cmpxchgptr(Register reg, AddressLiteral adr); 1901 1902 1903 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); } 1904 1905 1906 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); } 1907 1908 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); } 1909 1910 void shlptr(Register dst, int32_t shift); 1911 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); } 1912 1913 void shrptr(Register dst, int32_t shift); 1914 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); } 1915 1916 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); } 1917 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); } 1918 1919 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 1920 1921 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); } 1922 void subptr(Register dst, int32_t src); 1923 void subptr(Register dst, Register src); 1924 1925 1926 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 1927 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); } 1928 1929 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 1930 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; } 1931 1932 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; } 1933 1934 1935 1936 // Helper functions for statistics gathering. 1937 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes. 1938 void cond_inc32(Condition cond, AddressLiteral counter_addr); 1939 // Unconditional atomic increment. 1940 void atomic_incl(AddressLiteral counter_addr); 1941 1942 void lea(Register dst, AddressLiteral adr); 1943 void lea(Address dst, AddressLiteral adr); 1944 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); } 1945 1946 void leal32(Register dst, Address src) { leal(dst, src); } 1947 1948 void test32(Register src1, AddressLiteral src2); 1949 1950 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 1951 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 1952 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); } 1953 1954 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); } 1955 void testptr(Register src1, Register src2); 1956 1957 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 1958 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); } 1959 1960 // Calls 1961 1962 void call(Label& L, relocInfo::relocType rtype); 1963 void call(Register entry); 1964 1965 // NOTE: this call tranfers to the effective address of entry NOT 1966 // the address contained by entry. This is because this is more natural 1967 // for jumps/calls. 1968 void call(AddressLiteral entry); 1969 1970 // Jumps 1971 1972 // NOTE: these jumps tranfer to the effective address of dst NOT 1973 // the address contained by dst. This is because this is more natural 1974 // for jumps/calls. 1975 void jump(AddressLiteral dst); 1976 void jump_cc(Condition cc, AddressLiteral dst); 1977 1978 // 32bit can do a case table jump in one instruction but we no longer allow the base 1979 // to be installed in the Address class. This jump will tranfers to the address 1980 // contained in the location described by entry (not the address of entry) 1981 void jump(ArrayAddress entry); 1982 1983 // Floating 1984 1985 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); } 1986 void andpd(XMMRegister dst, AddressLiteral src); 1987 1988 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); } 1989 void comiss(XMMRegister dst, AddressLiteral src); 1990 1991 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); } 1992 void comisd(XMMRegister dst, AddressLiteral src); 1993 1994 void fldcw(Address src) { Assembler::fldcw(src); } 1995 void fldcw(AddressLiteral src); 1996 1997 void fld_s(int index) { Assembler::fld_s(index); } 1998 void fld_s(Address src) { Assembler::fld_s(src); } 1999 void fld_s(AddressLiteral src); 2000 2001 void fld_d(Address src) { Assembler::fld_d(src); } 2002 void fld_d(AddressLiteral src); 2003 2004 void fld_x(Address src) { Assembler::fld_x(src); } 2005 void fld_x(AddressLiteral src); 2006 2007 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); } 2008 void ldmxcsr(AddressLiteral src); 2009 2010private: 2011 // these are private because users should be doing movflt/movdbl 2012 2013 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); } 2014 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); } 2015 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); } 2016 void movss(XMMRegister dst, AddressLiteral src); 2017 2018 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); } 2019 void movlpd(XMMRegister dst, AddressLiteral src); 2020 2021public: 2022 2023 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); } 2024 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); } 2025 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); } 2026 void movsd(XMMRegister dst, AddressLiteral src); 2027 2028 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); } 2029 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); } 2030 void ucomiss(XMMRegister dst, AddressLiteral src); 2031 2032 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); } 2033 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); } 2034 void ucomisd(XMMRegister dst, AddressLiteral src); 2035 2036 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values 2037 void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); } 2038 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); } 2039 void xorpd(XMMRegister dst, AddressLiteral src); 2040 2041 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values 2042 void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); } 2043 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); } 2044 void xorps(XMMRegister dst, AddressLiteral src); 2045 2046 // Data 2047 2048 void cmov(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2049 2050 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2051 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmovl(cc, dst, src)); } 2052 2053 void movoop(Register dst, jobject obj); 2054 void movoop(Address dst, jobject obj); 2055 2056 void movptr(ArrayAddress dst, Register src); 2057 // can this do an lea? 2058 void movptr(Register dst, ArrayAddress src); 2059 2060 void movptr(Register dst, Address src); 2061 2062 void movptr(Register dst, AddressLiteral src); 2063 2064 void movptr(Register dst, intptr_t src); 2065 void movptr(Register dst, Register src); 2066 void movptr(Address dst, intptr_t src); 2067 2068 void movptr(Address dst, Register src); 2069 2070#ifdef _LP64 2071 // Generally the next two are only used for moving NULL 2072 // Although there are situations in initializing the mark word where 2073 // they could be used. They are dangerous. 2074 2075 // They only exist on LP64 so that int32_t and intptr_t are not the same 2076 // and we have ambiguous declarations. 2077 2078 void movptr(Address dst, int32_t imm32); 2079 void movptr(Register dst, int32_t imm32); 2080#endif // _LP64 2081 2082 // to avoid hiding movl 2083 void mov32(AddressLiteral dst, Register src); 2084 void mov32(Register dst, AddressLiteral src); 2085 2086 // to avoid hiding movb 2087 void movbyte(ArrayAddress dst, int src); 2088 2089 // Can push value or effective address 2090 void pushptr(AddressLiteral src); 2091 2092 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); } 2093 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); } 2094 2095 void pushoop(jobject obj); 2096 2097 // sign extend as need a l to ptr sized element 2098 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); } 2099 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); } 2100 2101 2102#undef VIRTUAL 2103 2104}; 2105 2106/** 2107 * class SkipIfEqual: 2108 * 2109 * Instantiating this class will result in assembly code being output that will 2110 * jump around any code emitted between the creation of the instance and it's 2111 * automatic destruction at the end of a scope block, depending on the value of 2112 * the flag passed to the constructor, which will be checked at run-time. 2113 */ 2114class SkipIfEqual { 2115 private: 2116 MacroAssembler* _masm; 2117 Label _label; 2118 2119 public: 2120 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value); 2121 ~SkipIfEqual(); 2122}; 2123 2124#ifdef ASSERT 2125inline bool AbstractAssembler::pd_check_instruction_mark() { return true; } 2126#endif 2127