1/* 2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_S390_VM_MACROASSEMBLER_S390_HPP 27#define CPU_S390_VM_MACROASSEMBLER_S390_HPP 28 29#include "asm/assembler.hpp" 30 31#define MODERN_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name) 32#define CLASSIC_IFUN(name) ((void (MacroAssembler::*)(Register, int64_t, Register, Register))&MacroAssembler::name) 33#define MODERN_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name) 34#define CLASSIC_FFUN(name) ((void (MacroAssembler::*)(FloatRegister, int64_t, Register, Register))&MacroAssembler::name) 35 36class MacroAssembler: public Assembler { 37 public: 38 MacroAssembler(CodeBuffer* code) : Assembler(code) {} 39 40 // 41 // Optimized instruction emitters 42 // 43 44 // Move register if destination register and target register are different. 45 void lr_if_needed(Register rd, Register rs); 46 void lgr_if_needed(Register rd, Register rs); 47 void llgfr_if_needed(Register rd, Register rs); 48 void ldr_if_needed(FloatRegister rd, FloatRegister rs); 49 50 void move_reg_if_needed(Register dest, BasicType dest_type, Register src, BasicType src_type); 51 void move_freg_if_needed(FloatRegister dest, BasicType dest_type, FloatRegister src, BasicType src_type); 52 53 void freg2mem_opt(FloatRegister reg, 54 int64_t disp, 55 Register index, 56 Register base, 57 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register), 58 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register), 59 Register scratch = Z_R0); 60 void freg2mem_opt(FloatRegister reg, 61 const Address &a, bool is_double = true); 62 63 void mem2freg_opt(FloatRegister reg, 64 int64_t disp, 65 Register index, 66 Register base, 67 void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register), 68 void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register), 69 Register scratch = Z_R0); 70 void mem2freg_opt(FloatRegister reg, 71 const Address &a, bool is_double = true); 72 73 void reg2mem_opt(Register reg, 74 int64_t disp, 75 Register index, 76 Register base, 77 void (MacroAssembler::*modern) (Register, int64_t, Register, Register), 78 void (MacroAssembler::*classic)(Register, int64_t, Register, Register), 79 Register scratch = Z_R0); 80 // returns offset of the store instruction 81 int reg2mem_opt(Register reg, const Address &a, bool is_double = true); 82 83 void mem2reg_opt(Register reg, 84 int64_t disp, 85 Register index, 86 Register base, 87 void (MacroAssembler::*modern) (Register, int64_t, Register, Register), 88 void (MacroAssembler::*classic)(Register, int64_t, Register, Register)); 89 void mem2reg_opt(Register reg, const Address &a, bool is_double = true); 90 void mem2reg_signed_opt(Register reg, const Address &a); 91 92 // AND immediate and set condition code, works for 64 bit immediates/operation as well. 93 void and_imm(Register r, long mask, Register tmp = Z_R0, bool wide = false); 94 95 // 1's complement, 32bit or 64bit. Optimized to exploit distinct operands facility. 96 // Note: The condition code is neither preserved nor correctly set by this code!!! 97 // Note: (wide == false) does not protect the high order half of the target register 98 // from alternation. It only serves as optimization hint for 32-bit results. 99 void not_(Register r1, Register r2 = noreg, bool wide = false); // r1 = ~r2 100 101 // Expanded support of all "rotate_then_<logicalOP>" instructions. 102 // 103 // Generalize and centralize rotate_then_<logicalOP> emitter. 104 // Functional description. For details, see Principles of Operation, Chapter 7, "Rotate Then Insert..." 105 // - Bits in a register are numbered left (most significant) to right (least significant), i.e. [0..63]. 106 // - Bytes in a register are numbered left (most significant) to right (least significant), i.e. [0..7]. 107 // - Register src is rotated to the left by (nRotate&0x3f) positions. 108 // - Negative values for nRotate result in a rotation to the right by abs(nRotate) positions. 109 // - The bits in positions [lBitPos..rBitPos] of the _ROTATED_ src operand take part in the 110 // logical operation performed on the contents (in those positions) of the dst operand. 111 // - The logical operation that is performed on the dst operand is one of 112 // o insert the selected bits (replacing the original contents of those bit positions) 113 // o and the selected bits with the corresponding bits of the dst operand 114 // o or the selected bits with the corresponding bits of the dst operand 115 // o xor the selected bits with the corresponding bits of the dst operand 116 // - For clear_dst == true, the destination register is cleared before the bits are inserted. 117 // For clear_dst == false, only the bit positions that get data inserted from src 118 // are changed. All other bit positions remain unchanged. 119 // - For test_only == true, the result of the logicalOP is only used to set the condition code, dst remains unchanged. 120 // For test_only == false, the result of the logicalOP replaces the selected bits of dst. 121 // - src32bit and dst32bit indicate the respective register is used as 32bit value only. 122 // Knowledge can simplify code generation. 123 // 124 // Here is an important performance note, valid for all <logicalOP>s except "insert": 125 // Due to the too complex nature of the operation, it cannot be done in a single cycle. 126 // Timing constraints require the instructions to be cracked into two micro-ops, taking 127 // one or two cycles each to execute. In some cases, an additional pipeline bubble might get added. 128 // Macroscopically, that makes up for a three- or four-cycle instruction where you would 129 // expect just a single cycle. 130 // It is thus not beneficial from a performance point of view to exploit those instructions. 131 // Other reasons (code compactness, register pressure, ...) might outweigh this penalty. 132 // 133 unsigned long create_mask(int lBitPos, int rBitPos); 134 void rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos, 135 int nRotate, bool src32bit, bool dst32bit, bool oneBits); 136 void rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, 137 bool clear_dst); 138 void rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, 139 bool test_only); 140 void rotate_then_or(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, 141 bool test_onlyt); 142 void rotate_then_xor(Register dst, Register src, int lBitPos, int rBitPos, int nRotate, 143 bool test_only); 144 145 void add64(Register r1, RegisterOrConstant inc); 146 147 // Helper function to multiply the 64bit contents of a register by a 16bit constant. 148 // The optimization tries to avoid the mghi instruction, since it uses the FPU for 149 // calculation and is thus rather slow. 150 // 151 // There is no handling for special cases, e.g. cval==0 or cval==1. 152 // 153 // Returns len of generated code block. 154 unsigned int mul_reg64_const16(Register rval, Register work, int cval); 155 156 // Generic operation r1 := r2 + imm. 157 void add2reg(Register r1, int64_t imm, Register r2 = noreg); 158 // Generic operation r := b + x + d. 159 void add2reg_with_index(Register r, int64_t d, Register x, Register b = noreg); 160 161 // Add2mem* methods for direct memory increment. 162 void add2mem_32(const Address &a, int64_t imm, Register tmp); 163 void add2mem_64(const Address &a, int64_t imm, Register tmp); 164 165 // *((int8_t*)(dst)) |= imm8 166 inline void or2mem_8(Address& dst, int64_t imm8); 167 168 // Load values by size and signedness. 169 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed); 170 void store_sized_value(Register src, Address dst, size_t size_in_bytes); 171 172 // Load values with large offsets to base address. 173 private: 174 int split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate); 175 public: 176 void load_long_largeoffset(Register t, int64_t si20, Register a, Register tmp); 177 void load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp); 178 void load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp); 179 180 private: 181 long toc_distance(); 182 public: 183 void load_toc(Register Rtoc); 184 void load_long_pcrelative(Register Rdst, address dataLocation); 185 static int load_long_pcrelative_size() { return 6; } 186 void load_addr_pcrelative(Register Rdst, address dataLocation); 187 static int load_addr_pcrel_size() { return 6; } // Just a LARL. 188 189 // Load a value from memory and test (set CC). 190 void load_and_test_byte (Register dst, const Address &a); 191 void load_and_test_short (Register dst, const Address &a); 192 void load_and_test_int (Register dst, const Address &a); 193 void load_and_test_int2long(Register dst, const Address &a); 194 void load_and_test_long (Register dst, const Address &a); 195 196 // Test a bit in memory. Result is reflected in CC. 197 void testbit(const Address &a, unsigned int bit); 198 // Test a bit in a register. Result is reflected in CC. 199 void testbit(Register r, unsigned int bitPos); 200 201 // Clear a register, i.e. load const zero into reg. Return len (in bytes) of 202 // generated instruction(s). 203 // whole_reg: Clear 64 bits if true, 32 bits otherwise. 204 // set_cc: Use instruction that sets the condition code, if true. 205 int clear_reg(Register r, bool whole_reg = true, bool set_cc = true); 206 207#ifdef ASSERT 208 int preset_reg(Register r, unsigned long pattern, int pattern_len); 209#endif 210 211 // Clear (store zeros) a small piece of memory. 212 // CAUTION: Do not use this for atomic memory clearing. Use store_const() instead. 213 // addr: Address descriptor of memory to clear. 214 // Index register will not be used! 215 // size: Number of bytes to clear. 216 void clear_mem(const Address& addr, unsigned size); 217 218 // Move immediate values to memory. Currently supports 32 and 64 bit stores, 219 // but may be extended to 16 bit store operation, if needed. 220 // For details, see implementation in *.cpp file. 221 int store_const(const Address &dest, long imm, 222 unsigned int lm, unsigned int lc, 223 Register scratch = Z_R0); 224 inline int store_const(const Address &dest, long imm, 225 Register scratch = Z_R0, bool is_long = true); 226 227 // Move/initialize arbitrarily large memory area. No check for destructive overlap. 228 // Being interruptible, these instructions need a retry-loop. 229 void move_long_ext(Register dst, Register src, unsigned int pad); 230 231 void compare_long_ext(Register left, Register right, unsigned int pad); 232 void compare_long_uni(Register left, Register right, unsigned int pad); 233 234 void search_string(Register end, Register start); 235 void search_string_uni(Register end, Register start); 236 237 // Translate instructions 238 // Being interruptible, these instructions need a retry-loop. 239 void translate_oo(Register dst, Register src, uint mask); 240 void translate_ot(Register dst, Register src, uint mask); 241 void translate_to(Register dst, Register src, uint mask); 242 void translate_tt(Register dst, Register src, uint mask); 243 244 // Crypto instructions. 245 // Being interruptible, these instructions need a retry-loop. 246 void cksm(Register crcBuff, Register srcBuff); 247 void km( Register dstBuff, Register srcBuff); 248 void kmc(Register dstBuff, Register srcBuff); 249 void kimd(Register srcBuff); 250 void klmd(Register srcBuff); 251 void kmac(Register srcBuff); 252 253 // nop padding 254 void align(int modulus); 255 void align_address(int modulus); 256 257 // 258 // Constants, loading constants, TOC support 259 // 260 // Safepoint check factored out. 261 void generate_safepoint_check(Label& slow_path, Register scratch = noreg, bool may_relocate = true); 262 263 // Load generic address: d <- base(a) + index(a) + disp(a). 264 inline void load_address(Register d, const Address &a); 265 // Load absolute address (and try to optimize). 266 void load_absolute_address(Register d, address addr); 267 268 // Address of Z_ARG1 and argument_offset. 269 // If temp_reg == arg_slot, arg_slot will be overwritten. 270 Address argument_address(RegisterOrConstant arg_slot, 271 Register temp_reg = noreg, 272 int64_t extra_slot_offset = 0); 273 274 // Load a narrow ptr constant (oop or klass ptr). 275 void load_narrow_oop( Register t, narrowOop a); 276 void load_narrow_klass(Register t, Klass* k); 277 278 static bool is_load_const_32to64(address pos); 279 static bool is_load_narrow_oop(address pos) { return is_load_const_32to64(pos); } 280 static bool is_load_narrow_klass(address pos) { return is_load_const_32to64(pos); } 281 282 static int load_const_32to64_size() { return 6; } 283 static bool load_narrow_oop_size() { return load_const_32to64_size(); } 284 static bool load_narrow_klass_size() { return load_const_32to64_size(); } 285 286 static int patch_load_const_32to64(address pos, int64_t a); 287 static int patch_load_narrow_oop(address pos, oop o); 288 static int patch_load_narrow_klass(address pos, Klass* k); 289 290 // cOops. CLFI exploit. 291 void compare_immediate_narrow_oop(Register oop1, narrowOop oop2); 292 void compare_immediate_narrow_klass(Register op1, Klass* op2); 293 static bool is_compare_immediate32(address pos); 294 static bool is_compare_immediate_narrow_oop(address pos); 295 static bool is_compare_immediate_narrow_klass(address pos); 296 static int compare_immediate_narrow_size() { return 6; } 297 static int compare_immediate_narrow_oop_size() { return compare_immediate_narrow_size(); } 298 static int compare_immediate_narrow_klass_size() { return compare_immediate_narrow_size(); } 299 static int patch_compare_immediate_32(address pos, int64_t a); 300 static int patch_compare_immediate_narrow_oop(address pos, oop o); 301 static int patch_compare_immediate_narrow_klass(address pos, Klass* k); 302 303 // Load a 32bit constant into a 64bit register. 304 void load_const_32to64(Register t, int64_t x, bool sign_extend=true); 305 // Load a 64 bit constant. 306 void load_const(Register t, long a); 307 inline void load_const(Register t, void* a); 308 inline void load_const(Register t, Label& L); 309 inline void load_const(Register t, const AddressLiteral& a); 310 // Get the 64 bit constant from a `load_const' sequence. 311 static long get_const(address load_const); 312 // Patch the 64 bit constant of a `load_const' sequence. This is a low level 313 // procedure. It neither flushes the instruction cache nor is it atomic. 314 static void patch_const(address load_const, long x); 315 static int load_const_size() { return 12; } 316 317 // Turn a char into boolean. NOTE: destroys r. 318 void c2bool(Register r, Register t = Z_R0); 319 320 // Optimized version of load_const for constants that do not need to be 321 // loaded by a sequence of instructions of fixed length and that do not 322 // need to be patched. 323 int load_const_optimized_rtn_len(Register t, long x, bool emit); 324 inline void load_const_optimized(Register t, long x); 325 inline void load_const_optimized(Register t, void* a); 326 inline void load_const_optimized(Register t, Label& L); 327 inline void load_const_optimized(Register t, const AddressLiteral& a); 328 329 public: 330 331 //---------------------------------------------------------- 332 // oops in code ------------- 333 // including compressed oops support ------------- 334 //---------------------------------------------------------- 335 336 // Metadata in code that we have to keep track of. 337 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index 338 AddressLiteral constant_metadata_address(Metadata* obj); // find_index 339 340 // allocate_index 341 AddressLiteral allocate_oop_address(jobject obj); 342 // find_index 343 AddressLiteral constant_oop_address(jobject obj); 344 // Uses allocate_oop_address. 345 inline void set_oop (jobject obj, Register d); 346 // Uses constant_oop_address. 347 inline void set_oop_constant(jobject obj, Register d); 348 // Uses constant_metadata_address. 349 inline bool set_metadata_constant(Metadata* md, Register d); 350 351 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 352 Register tmp, 353 int offset); 354 // 355 // branch, jump 356 // 357 358 // Use one generic function for all branch patches. 359 static unsigned long patched_branch(address dest_pos, unsigned long inst, address inst_pos); 360 361 void pd_patch_instruction(address branch, address target); 362 363 // Extract relative address from "relative" instructions. 364 static long get_pcrel_offset(unsigned long inst); 365 static long get_pcrel_offset(address pc); 366 static address get_target_addr_pcrel(address pc); 367 368 static inline bool is_call_pcrelative_short(unsigned long inst); 369 static inline bool is_call_pcrelative_long(unsigned long inst); 370 static inline bool is_branch_pcrelative_short(unsigned long inst); 371 static inline bool is_branch_pcrelative_long(unsigned long inst); 372 static inline bool is_compareandbranch_pcrelative_short(unsigned long inst); 373 static inline bool is_branchoncount_pcrelative_short(unsigned long inst); 374 static inline bool is_branchonindex32_pcrelative_short(unsigned long inst); 375 static inline bool is_branchonindex64_pcrelative_short(unsigned long inst); 376 static inline bool is_branchonindex_pcrelative_short(unsigned long inst); 377 static inline bool is_branch_pcrelative16(unsigned long inst); 378 static inline bool is_branch_pcrelative32(unsigned long inst); 379 static inline bool is_branch_pcrelative(unsigned long inst); 380 static inline bool is_load_pcrelative_long(unsigned long inst); 381 static inline bool is_misc_pcrelative_long(unsigned long inst); 382 static inline bool is_pcrelative_short(unsigned long inst); 383 static inline bool is_pcrelative_long(unsigned long inst); 384 // PCrelative TOC access. Variants with address argument. 385 static inline bool is_load_pcrelative_long(address iLoc); 386 static inline bool is_pcrelative_short(address iLoc); 387 static inline bool is_pcrelative_long(address iLoc); 388 389 static inline bool is_pcrelative_instruction(address iloc); 390 static inline bool is_load_addr_pcrel(address a); 391 392 static void patch_target_addr_pcrel(address pc, address con); 393 static void patch_addr_pcrel(address pc, address con) { 394 patch_target_addr_pcrel(pc, con); // Just delegate. This is only for nativeInst_s390.cpp. 395 } 396 397 //--------------------------------------------------------- 398 // Some macros for more comfortable assembler programming. 399 //--------------------------------------------------------- 400 401 // NOTE: pass NearLabel T to signal that the branch target T will be bound to a near address. 402 403 void compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target); 404 void compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target); 405 void compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target); 406 void compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& target); 407 408 void branch_optimized(Assembler::branch_condition cond, address branch_target); 409 void branch_optimized(Assembler::branch_condition cond, Label& branch_target); 410 void compare_and_branch_optimized(Register r1, 411 Register r2, 412 Assembler::branch_condition cond, 413 address branch_addr, 414 bool len64, 415 bool has_sign); 416 void compare_and_branch_optimized(Register r1, 417 jlong x2, 418 Assembler::branch_condition cond, 419 Label& branch_target, 420 bool len64, 421 bool has_sign); 422 void compare_and_branch_optimized(Register r1, 423 Register r2, 424 Assembler::branch_condition cond, 425 Label& branch_target, 426 bool len64, 427 bool has_sign); 428 429 // 430 // Support for frame handling 431 // 432 // Specify the register that should be stored as the return pc in the 433 // current frame (default is R14). 434 inline void save_return_pc(Register pc = Z_R14); 435 inline void restore_return_pc(); 436 437 // Get current PC. 438 address get_PC(Register result); 439 440 // Get current PC + offset. Offset given in bytes, must be even! 441 address get_PC(Register result, int64_t offset); 442 443 // Resize current frame either relatively wrt to current SP or absolute. 444 void resize_frame_sub(Register offset, Register fp, bool load_fp=true); 445 void resize_frame_absolute(Register addr, Register fp, bool load_fp=true); 446 void resize_frame(RegisterOrConstant offset, Register fp, bool load_fp=true); 447 448 // Push a frame of size bytes, if copy_sp is false, old_sp must already 449 // contain a copy of Z_SP. 450 void push_frame(Register bytes, Register old_sp, bool copy_sp = true, bool bytes_with_inverted_sign = false); 451 452 // Push a frame of size `bytes'. no abi space provided. 453 // Don't rely on register locking, instead pass a scratch register 454 // (Z_R0 by default). 455 // CAUTION! passing registers >= Z_R2 may produce bad results on 456 // old CPUs! 457 unsigned int push_frame(unsigned int bytes, Register scratch = Z_R0); 458 459 // Push a frame of size `bytes' with abi160 on top. 460 unsigned int push_frame_abi160(unsigned int bytes); 461 462 // Pop current C frame. 463 void pop_frame(); 464 465 // 466 // Calls 467 // 468 469 private: 470 address _last_calls_return_pc; 471 472 public: 473 // Support for VM calls. This is the base routine called by the 474 // different versions of call_VM_leaf. The interpreter may customize 475 // this version by overriding it for its purposes (e.g., to 476 // save/restore additional registers when doing a VM call). 477 void call_VM_leaf_base(address entry_point); 478 void call_VM_leaf_base(address entry_point, bool allow_relocation); 479 480 // It is imperative that all calls into the VM are handled via the 481 // call_VM macros. They make sure that the stack linkage is setup 482 // correctly. Call_VM's correspond to ENTRY/ENTRY_X entry points 483 // while call_VM_leaf's correspond to LEAF entry points. 484 // 485 // This is the base routine called by the different versions of 486 // call_VM. The interpreter may customize this version by overriding 487 // it for its purposes (e.g., to save/restore additional registers 488 // when doing a VM call). 489 490 // If no last_java_sp is specified (noreg) then SP will be used instead. 491 492 virtual void call_VM_base( 493 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise. 494 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise. 495 address entry_point, // The entry point. 496 bool check_exception); // Flag which indicates if exception should be checked. 497 virtual void call_VM_base( 498 Register oop_result, // Where an oop-result ends up if any; use noreg otherwise. 499 Register last_java_sp, // To set up last_Java_frame in stubs; use noreg otherwise. 500 address entry_point, // The entry point. 501 bool allow_relocation, // Flag to request generation of relocatable code. 502 bool check_exception); // Flag which indicates if exception should be checked. 503 504 // Call into the VM. 505 // Passes the thread pointer (in Z_ARG1) as a prepended argument. 506 // Makes sure oop return values are visible to the GC. 507 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true); 508 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true); 509 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true); 510 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, 511 Register arg_3, bool check_exceptions = true); 512 513 void call_VM_static(Register oop_result, address entry_point, bool check_exceptions = true); 514 void call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2, 515 Register arg_3, bool check_exceptions = true); 516 517 // Overloaded with last_java_sp. 518 void call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions = true); 519 void call_VM(Register oop_result, Register last_java_sp, address entry_point, 520 Register arg_1, bool check_exceptions = true); 521 void call_VM(Register oop_result, Register last_java_sp, address entry_point, 522 Register arg_1, Register arg_2, bool check_exceptions = true); 523 void call_VM(Register oop_result, Register last_java_sp, address entry_point, 524 Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true); 525 526 void call_VM_leaf(address entry_point); 527 void call_VM_leaf(address entry_point, Register arg_1); 528 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2); 529 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3); 530 531 // Really static VM leaf call (never patched). 532 void call_VM_leaf_static(address entry_point); 533 void call_VM_leaf_static(address entry_point, Register arg_1); 534 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2); 535 void call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3); 536 537 // Call a C function via its function entry. Updates and returns _last_calls_return_pc. 538 inline address call(Register function_entry); 539 inline address call_c(Register function_entry); 540 address call_c(address function_entry); 541 // Variant for really static (non-relocatable) calls which are never patched. 542 address call_c_static(address function_entry); 543 // TOC or pc-relative call + emits a runtime_call relocation. 544 address call_c_opt(address function_entry); 545 546 inline address call_stub(Register function_entry); 547 inline address call_stub(address function_entry); 548 549 // Get the pc where the last call will return to. Returns _last_calls_return_pc. 550 inline address last_calls_return_pc(); 551 552 private: 553 static bool is_call_far_patchable_variant0_at(address instruction_addr); // Dynamic TOC: load target addr from CP and call. 554 static bool is_call_far_patchable_variant2_at(address instruction_addr); // PC-relative call, prefixed with NOPs. 555 556 557 public: 558 bool call_far_patchable(address target, int64_t toc_offset); 559 static bool is_call_far_patchable_at(address inst_start); // All supported forms of patchable calls. 560 static bool is_call_far_patchable_pcrelative_at(address inst_start); // Pc-relative call with leading nops. 561 static bool is_call_far_pcrelative(address instruction_addr); // Pure far pc-relative call, with one leading size adjustment nop. 562 static void set_dest_of_call_far_patchable_at(address inst_start, address target, int64_t toc_offset); 563 static address get_dest_of_call_far_patchable_at(address inst_start, address toc_start); 564 565 void align_call_far_patchable(address pc); 566 567 // PCrelative TOC access. 568 569 // This value is independent of code position - constant for the lifetime of the VM. 570 static int call_far_patchable_size() { 571 return load_const_from_toc_size() + call_byregister_size(); 572 } 573 574 static int call_far_patchable_ret_addr_offset() { return call_far_patchable_size(); } 575 576 static bool call_far_patchable_requires_alignment_nop(address pc) { 577 if (!os::is_MP()) return false; 578 int size = call_far_patchable_size(); 579 return ((intptr_t)(pc + size) & 0x03L) != 0; 580 } 581 582 // END OF PCrelative TOC access. 583 584 static int jump_byregister_size() { return 2; } 585 static int jump_pcrelative_size() { return 4; } 586 static int jump_far_pcrelative_size() { return 6; } 587 static int call_byregister_size() { return 2; } 588 static int call_pcrelative_size() { return 4; } 589 static int call_far_pcrelative_size() { return 2 + 6; } // Prepend each BRASL with a nop. 590 static int call_far_pcrelative_size_raw() { return 6; } // Prepend each BRASL with a nop. 591 592 // 593 // Java utilities 594 // 595 596 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code. 597 // The implementation is only non-empty for the InterpreterMacroAssembler, 598 // as only the interpreter handles PopFrame and ForceEarlyReturn requests. 599 virtual void check_and_handle_popframe(Register java_thread); 600 virtual void check_and_handle_earlyret(Register java_thread); 601 602 // Polling page support. 603 enum poll_mask { 604 mask_stackbang = 0xde, // 222 (dec) 605 mask_safepoint = 0x6f, // 111 (dec) 606 mask_profiling = 0xba // 186 (dec) 607 }; 608 609 // Read from the polling page. 610 void load_from_polling_page(Register polling_page_address, int64_t offset = 0); 611 612 // Check if given instruction is a read from the polling page 613 // as emitted by load_from_polling_page. 614 static bool is_load_from_polling_page(address instr_loc); 615 // Extract poll address from instruction and ucontext. 616 static address get_poll_address(address instr_loc, void* ucontext); 617 // Extract poll register from instruction. 618 static uint get_poll_register(address instr_loc); 619 620 // Check if instruction is a write access to the memory serialization page 621 // realized by one of the instructions stw, stwu, stwx, or stwux. 622 static bool is_memory_serialization(int instruction, JavaThread* thread, void* ucontext); 623 624 // Support for serializing memory accesses between threads. 625 void serialize_memory(Register thread, Register tmp1, Register tmp2); 626 627 // Stack overflow checking 628 void bang_stack_with_offset(int offset); 629 630 // Check for reserved stack access in method being exited. If the reserved 631 // stack area was accessed, protect it again and throw StackOverflowError. 632 // Uses Z_R1. 633 void reserved_stack_check(Register return_pc); 634 635 // Atomics 636 // -- none? 637 638 void tlab_allocate(Register obj, // Result: pointer to object after successful allocation 639 Register var_size_in_bytes, // Object size in bytes if unknown at compile time; invalid otherwise. 640 int con_size_in_bytes, // Object size in bytes if known at compile time. 641 Register t1, // temp register 642 Label& slow_case); // Continuation point if fast allocation fails. 643 644 // Emitter for interface method lookup. 645 // input: recv_klass, intf_klass, itable_index 646 // output: method_result 647 // kills: itable_index, temp1_reg, Z_R0, Z_R1 648 void lookup_interface_method(Register recv_klass, 649 Register intf_klass, 650 RegisterOrConstant itable_index, 651 Register method_result, 652 Register temp1_reg, 653 Register temp2_reg, 654 Label& no_such_interface); 655 656 // virtual method calling 657 void lookup_virtual_method(Register recv_klass, 658 RegisterOrConstant vtable_index, 659 Register method_result); 660 661 // Factor out code to call ic_miss_handler. 662 unsigned int call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch); 663 void nmethod_UEP(Label& ic_miss); 664 665 // Emitters for "partial subtype" checks. 666 667 // Test sub_klass against super_klass, with fast and slow paths. 668 669 // The fast path produces a tri-state answer: yes / no / maybe-slow. 670 // One of the three labels can be NULL, meaning take the fall-through. 671 // If super_check_offset is -1, the value is loaded up from super_klass. 672 // No registers are killed, except temp_reg and temp2_reg. 673 // If super_check_offset is not -1, temp1_reg is not used and can be noreg. 674 void check_klass_subtype_fast_path(Register sub_klass, 675 Register super_klass, 676 Register temp1_reg, 677 Label* L_success, 678 Label* L_failure, 679 Label* L_slow_path, 680 RegisterOrConstant super_check_offset = RegisterOrConstant(-1)); 681 682 // The rest of the type check; must be wired to a corresponding fast path. 683 // It does not repeat the fast path logic, so don't use it standalone. 684 // The temp_reg can be noreg, if no temps are available. 685 // It can also be sub_klass or super_klass, meaning it's OK to kill that one. 686 // Updates the sub's secondary super cache as necessary. 687 void check_klass_subtype_slow_path(Register Rsubklass, 688 Register Rsuperklas, 689 Register Rarray_ptr, // tmp 690 Register Rlength, // tmp 691 Label* L_success, 692 Label* L_failure); 693 694 // Simplified, combined version, good for typical uses. 695 // Falls through on failure. 696 void check_klass_subtype(Register sub_klass, 697 Register super_klass, 698 Register temp1_reg, 699 Register temp2_reg, 700 Label& L_success); 701 702 // Increment a counter at counter_address when the eq condition code is set. 703 // Kills registers tmp1_reg and tmp2_reg and preserves the condition code. 704 void increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg); 705 // Biased locking support 706 // Upon entry,obj_reg must contain the target object, and mark_reg 707 // must contain the target object's header. 708 // Destroys mark_reg if an attempt is made to bias an anonymously 709 // biased lock. In this case a failure will go either to the slow 710 // case or fall through with the notEqual condition code set with 711 // the expectation that the slow case in the runtime will be called. 712 // In the fall-through case where the CAS-based lock is done, 713 // mark_reg is not destroyed. 714 void biased_locking_enter(Register obj_reg, Register mark_reg, Register temp_reg, 715 Register temp2_reg, Label& done, Label* slow_case = NULL); 716 // Upon entry, the base register of mark_addr must contain the oop. 717 // Destroys temp_reg. 718 // If allow_delay_slot_filling is set to true, the next instruction 719 // emitted after this one will go in an annulled delay slot if the 720 // biased locking exit case failed. 721 void biased_locking_exit(Register mark_addr, Register temp_reg, Label& done); 722 723 void compiler_fast_lock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias = UseBiasedLocking); 724 void compiler_fast_unlock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias = UseBiasedLocking); 725 726 // Write to card table for modification at store_addr - register is destroyed afterwards. 727 void card_write_barrier_post(Register store_addr, Register tmp); 728 729 void resolve_jobject(Register value, Register tmp1, Register tmp2); 730 731#if INCLUDE_ALL_GCS 732 // General G1 pre-barrier generator. 733 // Purpose: record the previous value if it is not null. 734 // All non-tmps are preserved. 735 void g1_write_barrier_pre(Register Robj, 736 RegisterOrConstant offset, 737 Register Rpre_val, // Ideally, this is a non-volatile register. 738 Register Rval, // Will be preserved. 739 Register Rtmp1, // If Rpre_val is volatile, either Rtmp1 740 Register Rtmp2, // or Rtmp2 has to be non-volatile. 741 bool pre_val_needed); // Save Rpre_val across runtime call, caller uses it. 742 743 // General G1 post-barrier generator. 744 // Purpose: Store cross-region card. 745 void g1_write_barrier_post(Register Rstore_addr, 746 Register Rnew_val, 747 Register Rtmp1, 748 Register Rtmp2, 749 Register Rtmp3); 750#endif // INCLUDE_ALL_GCS 751 752 // Support for last Java frame (but use call_VM instead where possible). 753 private: 754 void set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation); 755 void reset_last_Java_frame(bool allow_relocation); 756 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation); 757 public: 758 inline void set_last_Java_frame(Register last_java_sp, Register last_Java_pc); 759 inline void set_last_Java_frame_static(Register last_java_sp, Register last_Java_pc); 760 inline void reset_last_Java_frame(void); 761 inline void reset_last_Java_frame_static(void); 762 inline void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1); 763 inline void set_top_ijava_frame_at_SP_as_last_Java_frame_static(Register sp, Register tmp1); 764 765 void set_thread_state(JavaThreadState new_state); 766 767 // Read vm result from thread. 768 void get_vm_result (Register oop_result); 769 void get_vm_result_2(Register result); 770 771 // Vm result is currently getting hijacked to for oop preservation. 772 void set_vm_result(Register oop_result); 773 774 // Support for NULL-checks 775 // 776 // Generates code that causes a NULL OS exception if the content of reg is NULL. 777 // If the accessed location is M[reg + offset] and the offset is known, provide the 778 // offset. No explicit code generation is needed if the offset is within a certain 779 // range (0 <= offset <= page_size). 780 // 781 // %%%%%% Currently not done for z/Architecture 782 783 void null_check(Register reg, Register tmp = Z_R0, int64_t offset = -1); 784 static bool needs_explicit_null_check(intptr_t offset); // Implemented in shared file ?! 785 786 // Klass oop manipulations if compressed. 787 void encode_klass_not_null(Register dst, Register src = noreg); 788 void decode_klass_not_null(Register dst, Register src); 789 void decode_klass_not_null(Register dst); 790 void load_klass(Register klass, Address mem); 791 void load_klass(Register klass, Register src_oop); 792 void load_prototype_header(Register Rheader, Register Rsrc_oop); 793 void store_klass(Register klass, Register dst_oop, Register ck = noreg); // Klass will get compressed if ck not provided. 794 void store_klass_gap(Register s, Register dst_oop); 795 796 // This function calculates the size of the code generated by 797 // decode_klass_not_null(register dst) 798 // when (Universe::heap() != NULL). Hence, if the instructions 799 // it generates change, then this method needs to be updated. 800 static int instr_size_for_decode_klass_not_null(); 801 802 void encode_heap_oop(Register oop); 803 void encode_heap_oop_not_null(Register oop); 804 805 static int get_oop_base_pow2_offset(uint64_t oop_base); 806 int get_oop_base(Register Rbase, uint64_t oop_base); 807 int get_oop_base_complement(Register Rbase, uint64_t oop_base); 808 void compare_heap_oop(Register Rop1, Address mem, bool maybeNULL); 809 void compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL); 810 void load_heap_oop(Register dest, const Address &a); 811 void load_heap_oop(Register d, int64_t si16, Register s1); 812 void load_heap_oop_not_null(Register d, int64_t si16, Register s1); 813 void store_heap_oop(Register Roop, RegisterOrConstant offset, Register base); 814 void store_heap_oop_not_null(Register Roop, RegisterOrConstant offset, Register base); 815 void store_heap_oop_null(Register zero, RegisterOrConstant offset, Register base); 816 void oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL, 817 Register Rbase = Z_R1, int pow2_offset = -1, bool only32bitValid = false); 818 void oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL, 819 Register Rbase = Z_R1, int pow2_offset = -1); 820 821 void load_mirror(Register mirror, Register method); 822 823 //-------------------------- 824 //--- perations on arrays. 825 //-------------------------- 826 unsigned int Clear_Array(Register cnt_arg, Register base_pointer_arg, Register src_addr, Register src_len); 827 unsigned int Clear_Array_Const(long cnt, Register base); 828 unsigned int Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register src_addr, Register src_len); 829 unsigned int CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg, 830 Register cnt_reg, 831 Register tmp1_reg, Register tmp2_reg); 832 833 //------------------------------------------- 834 // Special String Intrinsics Implementation. 835 //------------------------------------------- 836 // Intrinsics for CompactStrings 837 // Compress char[] to byte[]. odd_reg contains cnt. tmp3 is only needed for precise behavior in failure case. Kills dst. 838 unsigned int string_compress(Register result, Register src, Register dst, Register odd_reg, 839 Register even_reg, Register tmp, Register tmp2 = noreg); 840 841 // Kills src. 842 unsigned int has_negatives(Register result, Register src, Register cnt, 843 Register odd_reg, Register even_reg, Register tmp); 844 845 // Inflate byte[] to char[]. 846 unsigned int string_inflate_trot(Register src, Register dst, Register cnt, Register tmp); 847 // Odd_reg contains cnt. Kills src. 848 unsigned int string_inflate(Register src, Register dst, Register odd_reg, 849 Register even_reg, Register tmp); 850 851 unsigned int string_compare(Register str1, Register str2, Register cnt1, Register cnt2, 852 Register odd_reg, Register even_reg, Register result, int ae); 853 854 unsigned int array_equals(bool is_array_equ, Register ary1, Register ary2, Register limit, 855 Register odd_reg, Register even_reg, Register result, bool is_byte); 856 857 unsigned int string_indexof(Register result, Register haystack, Register haycnt, 858 Register needle, Register needlecnt, int needlecntval, 859 Register odd_reg, Register even_reg, int ae); 860 861 unsigned int string_indexof_char(Register result, Register haystack, Register haycnt, 862 Register needle, jchar needleChar, Register odd_reg, Register even_reg, bool is_byte); 863 864 // Emit an oop const to the constant pool and set a relocation info 865 // with address current_pc. Return the TOC offset of the constant. 866 int store_const_in_toc(AddressLiteral& val); 867 int store_oop_in_toc(AddressLiteral& oop); 868 // Emit an oop const to the constant pool via store_oop_in_toc, or 869 // emit a scalar const to the constant pool via store_const_in_toc, 870 // and load the constant into register dst. 871 bool load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg); 872 // Get CPU version dependent size of load_const sequence. 873 // The returned value is valid only for code sequences 874 // generated by load_const, not load_const_optimized. 875 static int load_const_from_toc_size() { 876 return load_long_pcrelative_size(); 877 } 878 bool load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc = noreg); 879 static intptr_t get_const_from_toc(address pc); 880 static void set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb); 881 882 // Dynamic TOC. 883 static bool is_load_const(address a); 884 static bool is_load_const_from_toc_pcrelative(address a); 885 static bool is_load_const_from_toc(address a) { return is_load_const_from_toc_pcrelative(a); } 886 887 // PCrelative TOC access. 888 static bool is_call_byregister(address a) { return is_z_basr(*(short*)a); } 889 static bool is_load_const_from_toc_call(address a); 890 static bool is_load_const_call(address a); 891 static int load_const_call_size() { return load_const_size() + call_byregister_size(); } 892 static int load_const_from_toc_call_size() { return load_const_from_toc_size() + call_byregister_size(); } 893 // Offset is +/- 2**32 -> use long. 894 static long get_load_const_from_toc_offset(address a); 895 896 897 void generate_type_profiling(const Register Rdata, 898 const Register Rreceiver_klass, 899 const Register Rwanted_receiver_klass, 900 const Register Rmatching_row, 901 bool is_virtual_call); 902 903 // Bit operations for single register operands. 904 inline void lshift(Register r, int places, bool doubl = true); // << 905 inline void rshift(Register r, int places, bool doubl = true); // >> 906 907 // 908 // Debugging 909 // 910 911 // Assert on CC (condition code in CPU state). 912 void asm_assert(bool check_equal, const char* msg, int id) PRODUCT_RETURN; 913 void asm_assert_low(const char *msg, int id) PRODUCT_RETURN; 914 void asm_assert_high(const char *msg, int id) PRODUCT_RETURN; 915 void asm_assert_eq(const char* msg, int id) { asm_assert(true, msg, id); } 916 void asm_assert_ne(const char* msg, int id) { asm_assert(false, msg, id); } 917 918 void asm_assert_static(bool check_equal, const char* msg, int id) PRODUCT_RETURN; 919 920 private: 921 // Emit assertions. 922 void asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset, 923 Register mem_base, const char* msg, int id) PRODUCT_RETURN; 924 925 public: 926 inline void asm_assert_mem4_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) { 927 asm_assert_mems_zero(true, true, 4, mem_offset, mem_base, msg, id); 928 } 929 inline void asm_assert_mem8_is_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) { 930 asm_assert_mems_zero(true, true, 8, mem_offset, mem_base, msg, id); 931 } 932 inline void asm_assert_mem4_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) { 933 asm_assert_mems_zero(false, true, 4, mem_offset, mem_base, msg, id); 934 } 935 inline void asm_assert_mem8_isnot_zero(int64_t mem_offset, Register mem_base, const char* msg, int id) { 936 asm_assert_mems_zero(false, true, 8, mem_offset, mem_base, msg, id); 937 } 938 939 inline void asm_assert_mem4_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) { 940 asm_assert_mems_zero(true, false, 4, mem_offset, mem_base, msg, id); 941 } 942 inline void asm_assert_mem8_is_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) { 943 asm_assert_mems_zero(true, false, 8, mem_offset, mem_base, msg, id); 944 } 945 inline void asm_assert_mem4_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) { 946 asm_assert_mems_zero(false, false, 4, mem_offset, mem_base, msg, id); 947 } 948 inline void asm_assert_mem8_isnot_zero_static(int64_t mem_offset, Register mem_base, const char* msg, int id) { 949 asm_assert_mems_zero(false, false, 8, mem_offset, mem_base, msg, id); 950 } 951 void asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id) PRODUCT_RETURN; 952 953 // Verify Z_thread contents. 954 void verify_thread(); 955 956 // Only if +VerifyOops. 957 void verify_oop(Register reg, const char* s = "broken oop"); 958 959 // TODO: verify_method and klass metadata (compare against vptr?). 960 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {} 961 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {} 962 963#define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__) 964#define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__) 965 966 private: 967 // Generate printout in stop(). 968 static const char* stop_types[]; 969 enum { 970 stop_stop = 0, 971 stop_untested = 1, 972 stop_unimplemented = 2, 973 stop_shouldnotreachhere = 3, 974 stop_end = 4 975 }; 976 // Prints msg and stops execution. 977 void stop(int type, const char* msg, int id = 0); 978 address stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation); // Non-relocateable code only!! 979 void stop_static(int type, const char* msg, int id); // Non-relocateable code only!! 980 981 public: 982 983 // Prints msg and stops. 984 address stop_chain( address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, true); } 985 address stop_chain_static(address reentry, const char* msg = "", int id = 0) { return stop_chain(reentry, stop_stop, msg, id, false); } 986 void stop_static (const char* msg = "", int id = 0) { stop_static(stop_stop, msg, id); } 987 void stop (const char* msg = "", int id = 0) { stop(stop_stop, msg, id); } 988 void untested (const char* msg = "", int id = 0) { stop(stop_untested, msg, id); } 989 void unimplemented(const char* msg = "", int id = 0) { stop(stop_unimplemented, msg, id); } 990 void should_not_reach_here(const char* msg = "", int id = -1) { stop(stop_shouldnotreachhere, msg, id); } 991 992 // Factor out part of stop into subroutine to save space. 993 void stop_subroutine(); 994 995 // Prints msg, but don't stop. 996 void warn(const char* msg); 997 998 //----------------------------- 999 //--- basic block tracing code 1000 //----------------------------- 1001 void trace_basic_block(uint i); 1002 void init_basic_block_trace(); 1003 // Number of bytes a basic block gets larger due to the tracing code macro (worst case). 1004 // Currently, worst case is 48 bytes. 64 puts us securely on the safe side. 1005 static int basic_blck_trace_blk_size_incr() { return 64; } 1006 1007 // Write pattern 0x0101010101010101 in region [low-before, high+after]. 1008 // Low and high may be the same registers. Before and after are 1009 // the numbers of 8-byte words. 1010 void zap_from_to(Register low, Register high, Register tmp1 = Z_R0, Register tmp2 = Z_R1, 1011 int before = 0, int after = 0) PRODUCT_RETURN; 1012 1013 // Emitters for CRC32 calculation. 1014 private: 1015 void fold_byte_crc32(Register crc, Register table, Register val, Register tmp); 1016 void fold_8bit_crc32(Register crc, Register table, Register tmp); 1017 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, 1018 Register data, bool invertCRC); 1019 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc, 1020 Register t0, Register t1, Register t2, Register t3); 1021 public: 1022 void update_byte_crc32( Register crc, Register val, Register table); 1023 void kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp); 1024 void kernel_crc32_1byte(Register crc, Register buf, Register len, Register table, 1025 Register t0, Register t1, Register t2, Register t3); 1026 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table, 1027 Register t0, Register t1, Register t2, Register t3); 1028 void kernel_crc32_2word(Register crc, Register buf, Register len, Register table, 1029 Register t0, Register t1, Register t2, Register t3); 1030 1031 // Emitters for BigInteger.multiplyToLen intrinsic 1032 // note: length of result array (zlen) is passed on the stack 1033 private: 1034 void add2_with_carry(Register dest_hi, Register dest_lo, 1035 Register src1, Register src2); 1036 void multiply_64_x_64_loop(Register x, Register xstart, 1037 Register x_xstart, 1038 Register y, Register y_idx, Register z, 1039 Register carry, Register product, 1040 Register idx, Register kdx); 1041 void multiply_add_128_x_128(Register x_xstart, Register y, Register z, 1042 Register yz_idx, Register idx, 1043 Register carry, Register product, int offset); 1044 void multiply_128_x_128_loop(Register x_xstart, 1045 Register y, Register z, 1046 Register yz_idx, Register idx, 1047 Register jdx, 1048 Register carry, Register product, 1049 Register carry2); 1050 public: 1051 void multiply_to_len(Register x, Register xlen, 1052 Register y, Register ylen, 1053 Register z, 1054 Register tmp1, Register tmp2, 1055 Register tmp3, Register tmp4, Register tmp5); 1056}; 1057 1058/** 1059 * class SkipIfEqual: 1060 * 1061 * Instantiating this class will result in assembly code being output that will 1062 * jump around any code emitted between the creation of the instance and it's 1063 * automatic destruction at the end of a scope block, depending on the value of 1064 * the flag passed to the constructor, which will be checked at run-time. 1065 */ 1066class SkipIfEqual { 1067 private: 1068 MacroAssembler* _masm; 1069 Label _label; 1070 1071 public: 1072 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value, Register _rscratch); 1073 ~SkipIfEqual(); 1074}; 1075 1076#ifdef ASSERT 1077// Return false (e.g. important for our impl. of virtual calls). 1078inline bool AbstractAssembler::pd_check_instruction_mark() { return false; } 1079#endif 1080 1081#endif // CPU_S390_VM_MACROASSEMBLER_S390_HPP 1082