1/* 2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 27#define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 28 29#include "asm/register.hpp" 30 31// definitions of various symbolic names for machine registers 32 33// First intercalls between C and Java which use 8 general registers 34// and 8 floating registers 35 36// we also have to copy between x86 and ARM registers but that's a 37// secondary complication -- not all code employing C call convention 38// executes as x86 code though -- we generate some of it 39 40class Argument VALUE_OBJ_CLASS_SPEC { 41 public: 42 enum { 43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...) 44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... ) 45 46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ... 47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ... 48 }; 49}; 50 51REGISTER_DECLARATION(Register, c_rarg0, r0); 52REGISTER_DECLARATION(Register, c_rarg1, r1); 53REGISTER_DECLARATION(Register, c_rarg2, r2); 54REGISTER_DECLARATION(Register, c_rarg3, r3); 55REGISTER_DECLARATION(Register, c_rarg4, r4); 56REGISTER_DECLARATION(Register, c_rarg5, r5); 57REGISTER_DECLARATION(Register, c_rarg6, r6); 58REGISTER_DECLARATION(Register, c_rarg7, r7); 59 60REGISTER_DECLARATION(FloatRegister, c_farg0, v0); 61REGISTER_DECLARATION(FloatRegister, c_farg1, v1); 62REGISTER_DECLARATION(FloatRegister, c_farg2, v2); 63REGISTER_DECLARATION(FloatRegister, c_farg3, v3); 64REGISTER_DECLARATION(FloatRegister, c_farg4, v4); 65REGISTER_DECLARATION(FloatRegister, c_farg5, v5); 66REGISTER_DECLARATION(FloatRegister, c_farg6, v6); 67REGISTER_DECLARATION(FloatRegister, c_farg7, v7); 68 69// Symbolically name the register arguments used by the Java calling convention. 70// We have control over the convention for java so we can do what we please. 71// What pleases us is to offset the java calling convention so that when 72// we call a suitable jni method the arguments are lined up and we don't 73// have to do much shuffling. A suitable jni method is non-static and a 74// small number of arguments 75// 76// |--------------------------------------------------------------------| 77// | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 | 78// |--------------------------------------------------------------------| 79// | r0 r1 r2 r3 r4 r5 r6 r7 | 80// |--------------------------------------------------------------------| 81// | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 | 82// |--------------------------------------------------------------------| 83 84 85REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 86REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 87REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 88REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 89REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 90REGISTER_DECLARATION(Register, j_rarg5, c_rarg6); 91REGISTER_DECLARATION(Register, j_rarg6, c_rarg7); 92REGISTER_DECLARATION(Register, j_rarg7, c_rarg0); 93 94// Java floating args are passed as per C 95 96REGISTER_DECLARATION(FloatRegister, j_farg0, v0); 97REGISTER_DECLARATION(FloatRegister, j_farg1, v1); 98REGISTER_DECLARATION(FloatRegister, j_farg2, v2); 99REGISTER_DECLARATION(FloatRegister, j_farg3, v3); 100REGISTER_DECLARATION(FloatRegister, j_farg4, v4); 101REGISTER_DECLARATION(FloatRegister, j_farg5, v5); 102REGISTER_DECLARATION(FloatRegister, j_farg6, v6); 103REGISTER_DECLARATION(FloatRegister, j_farg7, v7); 104 105// registers used to hold VM data either temporarily within a method 106// or across method calls 107 108// volatile (caller-save) registers 109 110// r8 is used for indirect result location return 111// we use it and r9 as scratch registers 112REGISTER_DECLARATION(Register, rscratch1, r8); 113REGISTER_DECLARATION(Register, rscratch2, r9); 114 115// current method -- must be in a call-clobbered register 116REGISTER_DECLARATION(Register, rmethod, r12); 117 118// non-volatile (callee-save) registers are r16-29 119// of which the following are dedicated global state 120 121// link register 122REGISTER_DECLARATION(Register, lr, r30); 123// frame pointer 124REGISTER_DECLARATION(Register, rfp, r29); 125// current thread 126REGISTER_DECLARATION(Register, rthread, r28); 127// base of heap 128REGISTER_DECLARATION(Register, rheapbase, r27); 129// constant pool cache 130REGISTER_DECLARATION(Register, rcpool, r26); 131// monitors allocated on stack 132REGISTER_DECLARATION(Register, rmonitors, r25); 133// locals on stack 134REGISTER_DECLARATION(Register, rlocals, r24); 135// bytecode pointer 136REGISTER_DECLARATION(Register, rbcp, r22); 137// Dispatch table base 138REGISTER_DECLARATION(Register, rdispatch, r21); 139// Java stack pointer 140REGISTER_DECLARATION(Register, esp, r20); 141 142#define assert_cond(ARG1) assert(ARG1, #ARG1) 143 144namespace asm_util { 145 uint32_t encode_logical_immediate(bool is32, uint64_t imm); 146}; 147 148using namespace asm_util; 149 150 151class Assembler; 152 153class Instruction_aarch64 { 154 unsigned insn; 155#ifdef ASSERT 156 unsigned bits; 157#endif 158 Assembler *assem; 159 160public: 161 162 Instruction_aarch64(class Assembler *as) { 163#ifdef ASSERT 164 bits = 0; 165#endif 166 insn = 0; 167 assem = as; 168 } 169 170 inline ~Instruction_aarch64(); 171 172 unsigned &get_insn() { return insn; } 173#ifdef ASSERT 174 unsigned &get_bits() { return bits; } 175#endif 176 177 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) { 178 union { 179 unsigned u; 180 int n; 181 }; 182 183 u = val << (31 - hi); 184 n = n >> (31 - hi + lo); 185 return n; 186 } 187 188 static inline uint32_t extract(uint32_t val, int msb, int lsb) { 189 int nbits = msb - lsb + 1; 190 assert_cond(msb >= lsb); 191 uint32_t mask = (1U << nbits) - 1; 192 uint32_t result = val >> lsb; 193 result &= mask; 194 return result; 195 } 196 197 static inline int32_t sextract(uint32_t val, int msb, int lsb) { 198 uint32_t uval = extract(val, msb, lsb); 199 return extend(uval, msb - lsb); 200 } 201 202 static void patch(address a, int msb, int lsb, unsigned long val) { 203 int nbits = msb - lsb + 1; 204 guarantee(val < (1U << nbits), "Field too big for insn"); 205 assert_cond(msb >= lsb); 206 unsigned mask = (1U << nbits) - 1; 207 val <<= lsb; 208 mask <<= lsb; 209 unsigned target = *(unsigned *)a; 210 target &= ~mask; 211 target |= val; 212 *(unsigned *)a = target; 213 } 214 215 static void spatch(address a, int msb, int lsb, long val) { 216 int nbits = msb - lsb + 1; 217 long chk = val >> (nbits - 1); 218 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 219 unsigned uval = val; 220 unsigned mask = (1U << nbits) - 1; 221 uval &= mask; 222 uval <<= lsb; 223 mask <<= lsb; 224 unsigned target = *(unsigned *)a; 225 target &= ~mask; 226 target |= uval; 227 *(unsigned *)a = target; 228 } 229 230 void f(unsigned val, int msb, int lsb) { 231 int nbits = msb - lsb + 1; 232 guarantee(val < (1U << nbits), "Field too big for insn"); 233 assert_cond(msb >= lsb); 234 unsigned mask = (1U << nbits) - 1; 235 val <<= lsb; 236 mask <<= lsb; 237 insn |= val; 238 assert_cond((bits & mask) == 0); 239#ifdef ASSERT 240 bits |= mask; 241#endif 242 } 243 244 void f(unsigned val, int bit) { 245 f(val, bit, bit); 246 } 247 248 void sf(long val, int msb, int lsb) { 249 int nbits = msb - lsb + 1; 250 long chk = val >> (nbits - 1); 251 guarantee (chk == -1 || chk == 0, "Field too big for insn"); 252 unsigned uval = val; 253 unsigned mask = (1U << nbits) - 1; 254 uval &= mask; 255 f(uval, lsb + nbits - 1, lsb); 256 } 257 258 void rf(Register r, int lsb) { 259 f(r->encoding_nocheck(), lsb + 4, lsb); 260 } 261 262 // reg|ZR 263 void zrf(Register r, int lsb) { 264 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb); 265 } 266 267 // reg|SP 268 void srf(Register r, int lsb) { 269 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb); 270 } 271 272 void rf(FloatRegister r, int lsb) { 273 f(r->encoding_nocheck(), lsb + 4, lsb); 274 } 275 276 unsigned get(int msb = 31, int lsb = 0) { 277 int nbits = msb - lsb + 1; 278 unsigned mask = ((1U << nbits) - 1) << lsb; 279 assert_cond(bits & mask == mask); 280 return (insn & mask) >> lsb; 281 } 282 283 void fixed(unsigned value, unsigned mask) { 284 assert_cond ((mask & bits) == 0); 285#ifdef ASSERT 286 bits |= mask; 287#endif 288 insn |= value; 289 } 290}; 291 292#define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use) 293 294class PrePost { 295 int _offset; 296 Register _r; 297public: 298 PrePost(Register reg, int o) : _r(reg), _offset(o) { } 299 int offset() { return _offset; } 300 Register reg() { return _r; } 301}; 302 303class Pre : public PrePost { 304public: 305 Pre(Register reg, int o) : PrePost(reg, o) { } 306}; 307class Post : public PrePost { 308public: 309 Post(Register reg, int o) : PrePost(reg, o) { } 310}; 311 312namespace ext 313{ 314 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx }; 315}; 316 317// abs methods which cannot overflow and so are well-defined across 318// the entire domain of integer types. 319static inline unsigned int uabs(unsigned int n) { 320 union { 321 unsigned int result; 322 int value; 323 }; 324 result = n; 325 if (value < 0) result = -result; 326 return result; 327} 328static inline unsigned long uabs(unsigned long n) { 329 union { 330 unsigned long result; 331 long value; 332 }; 333 result = n; 334 if (value < 0) result = -result; 335 return result; 336} 337static inline unsigned long uabs(long n) { return uabs((unsigned long)n); } 338static inline unsigned long uabs(int n) { return uabs((unsigned int)n); } 339 340// Addressing modes 341class Address VALUE_OBJ_CLASS_SPEC { 342 public: 343 344 enum mode { no_mode, base_plus_offset, pre, post, pcrel, 345 base_plus_offset_reg, literal }; 346 347 // Shift and extend for base reg + reg offset addressing 348 class extend { 349 int _option, _shift; 350 ext::operation _op; 351 public: 352 extend() { } 353 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { } 354 int option() const{ return _option; } 355 int shift() const { return _shift; } 356 ext::operation op() const { return _op; } 357 }; 358 class uxtw : public extend { 359 public: 360 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { } 361 }; 362 class lsl : public extend { 363 public: 364 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { } 365 }; 366 class sxtw : public extend { 367 public: 368 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { } 369 }; 370 class sxtx : public extend { 371 public: 372 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { } 373 }; 374 375 private: 376 Register _base; 377 Register _index; 378 long _offset; 379 enum mode _mode; 380 extend _ext; 381 382 RelocationHolder _rspec; 383 384 // Typically we use AddressLiterals we want to use their rval 385 // However in some situations we want the lval (effect address) of 386 // the item. We provide a special factory for making those lvals. 387 bool _is_lval; 388 389 // If the target is far we'll need to load the ea of this to a 390 // register to reach it. Otherwise if near we can do PC-relative 391 // addressing. 392 address _target; 393 394 public: 395 Address() 396 : _mode(no_mode) { } 397 Address(Register r) 398 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { } 399 Address(Register r, int o) 400 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 401 Address(Register r, long o) 402 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 403 Address(Register r, unsigned long o) 404 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { } 405#ifdef ASSERT 406 Address(Register r, ByteSize disp) 407 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)), 408 _index(noreg), _target(0) { } 409#endif 410 Address(Register r, Register r1, extend ext = lsl()) 411 : _mode(base_plus_offset_reg), _base(r), _index(r1), 412 _ext(ext), _offset(0), _target(0) { } 413 Address(Pre p) 414 : _mode(pre), _base(p.reg()), _offset(p.offset()) { } 415 Address(Post p) 416 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { } 417 Address(address target, RelocationHolder const& rspec) 418 : _mode(literal), 419 _rspec(rspec), 420 _is_lval(false), 421 _target(target) { } 422 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type); 423 Address(Register base, RegisterOrConstant index, extend ext = lsl()) 424 : _base (base), 425 _ext(ext), _offset(0), _target(0) { 426 if (index.is_register()) { 427 _mode = base_plus_offset_reg; 428 _index = index.as_register(); 429 } else { 430 guarantee(ext.option() == ext::uxtx, "should be"); 431 assert(index.is_constant(), "should be"); 432 _mode = base_plus_offset; 433 _offset = index.as_constant() << ext.shift(); 434 } 435 } 436 437 Register base() const { 438 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg 439 | _mode == post), 440 "wrong mode"); 441 return _base; 442 } 443 long offset() const { 444 return _offset; 445 } 446 Register index() const { 447 return _index; 448 } 449 mode getMode() const { 450 return _mode; 451 } 452 bool uses(Register reg) const { return _base == reg || _index == reg; } 453 address target() const { return _target; } 454 const RelocationHolder& rspec() const { return _rspec; } 455 456 void encode(Instruction_aarch64 *i) const { 457 i->f(0b111, 29, 27); 458 i->srf(_base, 5); 459 460 switch(_mode) { 461 case base_plus_offset: 462 { 463 unsigned size = i->get(31, 30); 464 if (i->get(26, 26) && i->get(23, 23)) { 465 // SIMD Q Type - Size = 128 bits 466 assert(size == 0, "bad size"); 467 size = 0b100; 468 } 469 unsigned mask = (1 << size) - 1; 470 if (_offset < 0 || _offset & mask) 471 { 472 i->f(0b00, 25, 24); 473 i->f(0, 21), i->f(0b00, 11, 10); 474 i->sf(_offset, 20, 12); 475 } else { 476 i->f(0b01, 25, 24); 477 i->f(_offset >> size, 21, 10); 478 } 479 } 480 break; 481 482 case base_plus_offset_reg: 483 { 484 i->f(0b00, 25, 24); 485 i->f(1, 21); 486 i->rf(_index, 16); 487 i->f(_ext.option(), 15, 13); 488 unsigned size = i->get(31, 30); 489 if (i->get(26, 26) && i->get(23, 23)) { 490 // SIMD Q Type - Size = 128 bits 491 assert(size == 0, "bad size"); 492 size = 0b100; 493 } 494 if (size == 0) // It's a byte 495 i->f(_ext.shift() >= 0, 12); 496 else { 497 if (_ext.shift() > 0) 498 assert(_ext.shift() == (int)size, "bad shift"); 499 i->f(_ext.shift() > 0, 12); 500 } 501 i->f(0b10, 11, 10); 502 } 503 break; 504 505 case pre: 506 i->f(0b00, 25, 24); 507 i->f(0, 21), i->f(0b11, 11, 10); 508 i->sf(_offset, 20, 12); 509 break; 510 511 case post: 512 i->f(0b00, 25, 24); 513 i->f(0, 21), i->f(0b01, 11, 10); 514 i->sf(_offset, 20, 12); 515 break; 516 517 default: 518 ShouldNotReachHere(); 519 } 520 } 521 522 void encode_pair(Instruction_aarch64 *i) const { 523 switch(_mode) { 524 case base_plus_offset: 525 i->f(0b010, 25, 23); 526 break; 527 case pre: 528 i->f(0b011, 25, 23); 529 break; 530 case post: 531 i->f(0b001, 25, 23); 532 break; 533 default: 534 ShouldNotReachHere(); 535 } 536 537 unsigned size; // Operand shift in 32-bit words 538 539 if (i->get(26, 26)) { // float 540 switch(i->get(31, 30)) { 541 case 0b10: 542 size = 2; break; 543 case 0b01: 544 size = 1; break; 545 case 0b00: 546 size = 0; break; 547 default: 548 ShouldNotReachHere(); 549 size = 0; // unreachable 550 } 551 } else { 552 size = i->get(31, 31); 553 } 554 555 size = 4 << size; 556 guarantee(_offset % size == 0, "bad offset"); 557 i->sf(_offset / size, 21, 15); 558 i->srf(_base, 5); 559 } 560 561 void encode_nontemporal_pair(Instruction_aarch64 *i) const { 562 // Only base + offset is allowed 563 i->f(0b000, 25, 23); 564 unsigned size = i->get(31, 31); 565 size = 4 << size; 566 guarantee(_offset % size == 0, "bad offset"); 567 i->sf(_offset / size, 21, 15); 568 i->srf(_base, 5); 569 guarantee(_mode == Address::base_plus_offset, 570 "Bad addressing mode for non-temporal op"); 571 } 572 573 void lea(MacroAssembler *, Register) const; 574 575 static bool offset_ok_for_immed(long offset, int shift = 0) { 576 unsigned mask = (1 << shift) - 1; 577 if (offset < 0 || offset & mask) { 578 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset 579 } else { 580 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset 581 } 582 } 583}; 584 585// Convience classes 586class RuntimeAddress: public Address { 587 588 public: 589 590 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {} 591 592}; 593 594class OopAddress: public Address { 595 596 public: 597 598 OopAddress(address target) : Address(target, relocInfo::oop_type){} 599 600}; 601 602class ExternalAddress: public Address { 603 private: 604 static relocInfo::relocType reloc_for_target(address target) { 605 // Sometimes ExternalAddress is used for values which aren't 606 // exactly addresses, like the card table base. 607 // external_word_type can't be used for values in the first page 608 // so just skip the reloc in that case. 609 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 610 } 611 612 public: 613 614 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {} 615 616}; 617 618class InternalAddress: public Address { 619 620 public: 621 622 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {} 623}; 624 625const int FPUStateSizeInWords = 32 * 2; 626typedef enum { 627 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM, 628 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM, 629 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM 630} prfop; 631 632class Assembler : public AbstractAssembler { 633 634#ifndef PRODUCT 635 static const unsigned long asm_bp; 636 637 void emit_long(jint x) { 638 if ((unsigned long)pc() == asm_bp) 639 asm volatile ("nop"); 640 AbstractAssembler::emit_int32(x); 641 } 642#else 643 void emit_long(jint x) { 644 AbstractAssembler::emit_int32(x); 645 } 646#endif 647 648public: 649 650 enum { instruction_size = 4 }; 651 652 Address adjust(Register base, int offset, bool preIncrement) { 653 if (preIncrement) 654 return Address(Pre(base, offset)); 655 else 656 return Address(Post(base, offset)); 657 } 658 659 Address pre(Register base, int offset) { 660 return adjust(base, offset, true); 661 } 662 663 Address post (Register base, int offset) { 664 return adjust(base, offset, false); 665 } 666 667 Instruction_aarch64* current; 668 669 void set_current(Instruction_aarch64* i) { current = i; } 670 671 void f(unsigned val, int msb, int lsb) { 672 current->f(val, msb, lsb); 673 } 674 void f(unsigned val, int msb) { 675 current->f(val, msb, msb); 676 } 677 void sf(long val, int msb, int lsb) { 678 current->sf(val, msb, lsb); 679 } 680 void rf(Register reg, int lsb) { 681 current->rf(reg, lsb); 682 } 683 void srf(Register reg, int lsb) { 684 current->srf(reg, lsb); 685 } 686 void zrf(Register reg, int lsb) { 687 current->zrf(reg, lsb); 688 } 689 void rf(FloatRegister reg, int lsb) { 690 current->rf(reg, lsb); 691 } 692 void fixed(unsigned value, unsigned mask) { 693 current->fixed(value, mask); 694 } 695 696 void emit() { 697 emit_long(current->get_insn()); 698 assert_cond(current->get_bits() == 0xffffffff); 699 current = NULL; 700 } 701 702 typedef void (Assembler::* uncond_branch_insn)(address dest); 703 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest); 704 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest); 705 typedef void (Assembler::* prefetch_insn)(address target, prfop); 706 707 void wrap_label(Label &L, uncond_branch_insn insn); 708 void wrap_label(Register r, Label &L, compare_and_branch_insn insn); 709 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn); 710 void wrap_label(Label &L, prfop, prefetch_insn insn); 711 712 // PC-rel. addressing 713 714 void adr(Register Rd, address dest); 715 void _adrp(Register Rd, address dest); 716 717 void adr(Register Rd, const Address &dest); 718 void _adrp(Register Rd, const Address &dest); 719 720 void adr(Register Rd, Label &L) { 721 wrap_label(Rd, L, &Assembler::Assembler::adr); 722 } 723 void _adrp(Register Rd, Label &L) { 724 wrap_label(Rd, L, &Assembler::_adrp); 725 } 726 727 void adrp(Register Rd, const Address &dest, unsigned long &offset); 728 729#undef INSN 730 731 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op, 732 int negated_op); 733 734 // Add/subtract (immediate) 735#define INSN(NAME, decode, negated) \ 736 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \ 737 starti; \ 738 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \ 739 zrf(Rd, 0), srf(Rn, 5); \ 740 } \ 741 \ 742 void NAME(Register Rd, Register Rn, unsigned imm) { \ 743 starti; \ 744 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 745 } 746 747 INSN(addsw, 0b001, 0b011); 748 INSN(subsw, 0b011, 0b001); 749 INSN(adds, 0b101, 0b111); 750 INSN(subs, 0b111, 0b101); 751 752#undef INSN 753 754#define INSN(NAME, decode, negated) \ 755 void NAME(Register Rd, Register Rn, unsigned imm) { \ 756 starti; \ 757 add_sub_immediate(Rd, Rn, imm, decode, negated); \ 758 } 759 760 INSN(addw, 0b000, 0b010); 761 INSN(subw, 0b010, 0b000); 762 INSN(add, 0b100, 0b110); 763 INSN(sub, 0b110, 0b100); 764 765#undef INSN 766 767 // Logical (immediate) 768#define INSN(NAME, decode, is32) \ 769 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 770 starti; \ 771 uint32_t val = encode_logical_immediate(is32, imm); \ 772 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 773 srf(Rd, 0), zrf(Rn, 5); \ 774 } 775 776 INSN(andw, 0b000, true); 777 INSN(orrw, 0b001, true); 778 INSN(eorw, 0b010, true); 779 INSN(andr, 0b100, false); 780 INSN(orr, 0b101, false); 781 INSN(eor, 0b110, false); 782 783#undef INSN 784 785#define INSN(NAME, decode, is32) \ 786 void NAME(Register Rd, Register Rn, uint64_t imm) { \ 787 starti; \ 788 uint32_t val = encode_logical_immediate(is32, imm); \ 789 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \ 790 zrf(Rd, 0), zrf(Rn, 5); \ 791 } 792 793 INSN(ands, 0b111, false); 794 INSN(andsw, 0b011, true); 795 796#undef INSN 797 798 // Move wide (immediate) 799#define INSN(NAME, opcode) \ 800 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \ 801 assert_cond((shift/16)*16 == shift); \ 802 starti; \ 803 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \ 804 f(imm, 20, 5); \ 805 rf(Rd, 0); \ 806 } 807 808 INSN(movnw, 0b000); 809 INSN(movzw, 0b010); 810 INSN(movkw, 0b011); 811 INSN(movn, 0b100); 812 INSN(movz, 0b110); 813 INSN(movk, 0b111); 814 815#undef INSN 816 817 // Bitfield 818#define INSN(NAME, opcode) \ 819 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \ 820 starti; \ 821 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \ 822 rf(Rn, 5), rf(Rd, 0); \ 823 } 824 825 INSN(sbfmw, 0b0001001100); 826 INSN(bfmw, 0b0011001100); 827 INSN(ubfmw, 0b0101001100); 828 INSN(sbfm, 0b1001001101); 829 INSN(bfm, 0b1011001101); 830 INSN(ubfm, 0b1101001101); 831 832#undef INSN 833 834 // Extract 835#define INSN(NAME, opcode) \ 836 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \ 837 starti; \ 838 f(opcode, 31, 21), f(imms, 15, 10); \ 839 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 840 } 841 842 INSN(extrw, 0b00010011100); 843 INSN(extr, 0b10010011110); 844 845#undef INSN 846 847 // The maximum range of a branch is fixed for the AArch64 848 // architecture. In debug mode we shrink it in order to test 849 // trampolines, but not so small that branches in the interpreter 850 // are out of range. 851 static const unsigned long branch_range = INCLUDE_JVMCI ? 128 * M : NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M); 852 853 static bool reachable_from_branch_at(address branch, address target) { 854 return uabs(target - branch) < branch_range; 855 } 856 857 // Unconditional branch (immediate) 858#define INSN(NAME, opcode) \ 859 void NAME(address dest) { \ 860 starti; \ 861 long offset = (dest - pc()) >> 2; \ 862 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \ 863 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \ 864 } \ 865 void NAME(Label &L) { \ 866 wrap_label(L, &Assembler::NAME); \ 867 } \ 868 void NAME(const Address &dest); 869 870 INSN(b, 0); 871 INSN(bl, 1); 872 873#undef INSN 874 875 // Compare & branch (immediate) 876#define INSN(NAME, opcode) \ 877 void NAME(Register Rt, address dest) { \ 878 long offset = (dest - pc()) >> 2; \ 879 starti; \ 880 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \ 881 } \ 882 void NAME(Register Rt, Label &L) { \ 883 wrap_label(Rt, L, &Assembler::NAME); \ 884 } 885 886 INSN(cbzw, 0b00110100); 887 INSN(cbnzw, 0b00110101); 888 INSN(cbz, 0b10110100); 889 INSN(cbnz, 0b10110101); 890 891#undef INSN 892 893 // Test & branch (immediate) 894#define INSN(NAME, opcode) \ 895 void NAME(Register Rt, int bitpos, address dest) { \ 896 long offset = (dest - pc()) >> 2; \ 897 int b5 = bitpos >> 5; \ 898 bitpos &= 0x1f; \ 899 starti; \ 900 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \ 901 rf(Rt, 0); \ 902 } \ 903 void NAME(Register Rt, int bitpos, Label &L) { \ 904 wrap_label(Rt, bitpos, L, &Assembler::NAME); \ 905 } 906 907 INSN(tbz, 0b0110110); 908 INSN(tbnz, 0b0110111); 909 910#undef INSN 911 912 // Conditional branch (immediate) 913 enum Condition 914 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV}; 915 916 void br(Condition cond, address dest) { 917 long offset = (dest - pc()) >> 2; 918 starti; 919 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0); 920 } 921 922#define INSN(NAME, cond) \ 923 void NAME(address dest) { \ 924 br(cond, dest); \ 925 } 926 927 INSN(beq, EQ); 928 INSN(bne, NE); 929 INSN(bhs, HS); 930 INSN(bcs, CS); 931 INSN(blo, LO); 932 INSN(bcc, CC); 933 INSN(bmi, MI); 934 INSN(bpl, PL); 935 INSN(bvs, VS); 936 INSN(bvc, VC); 937 INSN(bhi, HI); 938 INSN(bls, LS); 939 INSN(bge, GE); 940 INSN(blt, LT); 941 INSN(bgt, GT); 942 INSN(ble, LE); 943 INSN(bal, AL); 944 INSN(bnv, NV); 945 946 void br(Condition cc, Label &L); 947 948#undef INSN 949 950 // Exception generation 951 void generate_exception(int opc, int op2, int LL, unsigned imm) { 952 starti; 953 f(0b11010100, 31, 24); 954 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0); 955 } 956 957#define INSN(NAME, opc, op2, LL) \ 958 void NAME(unsigned imm) { \ 959 generate_exception(opc, op2, LL, imm); \ 960 } 961 962 INSN(svc, 0b000, 0, 0b01); 963 INSN(hvc, 0b000, 0, 0b10); 964 INSN(smc, 0b000, 0, 0b11); 965 INSN(brk, 0b001, 0, 0b00); 966 INSN(hlt, 0b010, 0, 0b00); 967 INSN(dpcs1, 0b101, 0, 0b01); 968 INSN(dpcs2, 0b101, 0, 0b10); 969 INSN(dpcs3, 0b101, 0, 0b11); 970 971#undef INSN 972 973 // System 974 void system(int op0, int op1, int CRn, int CRm, int op2, 975 Register rt = dummy_reg) 976 { 977 starti; 978 f(0b11010101000, 31, 21); 979 f(op0, 20, 19); 980 f(op1, 18, 16); 981 f(CRn, 15, 12); 982 f(CRm, 11, 8); 983 f(op2, 7, 5); 984 rf(rt, 0); 985 } 986 987 void hint(int imm) { 988 system(0b00, 0b011, 0b0010, imm, 0b000); 989 } 990 991 void nop() { 992 hint(0); 993 } 994 // we only provide mrs and msr for the special purpose system 995 // registers where op1 (instr[20:19]) == 11 and, (currently) only 996 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1 997 998 void msr(int op1, int CRn, int CRm, int op2, Register rt) { 999 starti; 1000 f(0b1101010100011, 31, 19); 1001 f(op1, 18, 16); 1002 f(CRn, 15, 12); 1003 f(CRm, 11, 8); 1004 f(op2, 7, 5); 1005 // writing zr is ok 1006 zrf(rt, 0); 1007 } 1008 1009 void mrs(int op1, int CRn, int CRm, int op2, Register rt) { 1010 starti; 1011 f(0b1101010100111, 31, 19); 1012 f(op1, 18, 16); 1013 f(CRn, 15, 12); 1014 f(CRm, 11, 8); 1015 f(op2, 7, 5); 1016 // reading to zr is a mistake 1017 rf(rt, 0); 1018 } 1019 1020 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH, 1021 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY}; 1022 1023 void dsb(barrier imm) { 1024 system(0b00, 0b011, 0b00011, imm, 0b100); 1025 } 1026 1027 void dmb(barrier imm) { 1028 system(0b00, 0b011, 0b00011, imm, 0b101); 1029 } 1030 1031 void isb() { 1032 system(0b00, 0b011, 0b00011, SY, 0b110); 1033 } 1034 1035 void sys(int op1, int CRn, int CRm, int op2, 1036 Register rt = (Register)0b11111) { 1037 system(0b01, op1, CRn, CRm, op2, rt); 1038 } 1039 1040 // Only implement operations accessible from EL0 or higher, i.e., 1041 // op1 CRn CRm op2 1042 // IC IVAU 3 7 5 1 1043 // DC CVAC 3 7 10 1 1044 // DC CVAU 3 7 11 1 1045 // DC CIVAC 3 7 14 1 1046 // DC ZVA 3 7 4 1 1047 // So only deal with the CRm field. 1048 enum icache_maintenance {IVAU = 0b0101}; 1049 enum dcache_maintenance {CVAC = 0b1010, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100}; 1050 1051 void dc(dcache_maintenance cm, Register Rt) { 1052 sys(0b011, 0b0111, cm, 0b001, Rt); 1053 } 1054 1055 void ic(icache_maintenance cm, Register Rt) { 1056 sys(0b011, 0b0111, cm, 0b001, Rt); 1057 } 1058 1059 // A more convenient access to dmb for our purposes 1060 enum Membar_mask_bits { 1061 // We can use ISH for a barrier because the ARM ARM says "This 1062 // architecture assumes that all Processing Elements that use the 1063 // same operating system or hypervisor are in the same Inner 1064 // Shareable shareability domain." 1065 StoreStore = ISHST, 1066 LoadStore = ISHLD, 1067 LoadLoad = ISHLD, 1068 StoreLoad = ISH, 1069 AnyAny = ISH 1070 }; 1071 1072 void membar(Membar_mask_bits order_constraint) { 1073 dmb(Assembler::barrier(order_constraint)); 1074 } 1075 1076 // Unconditional branch (register) 1077 void branch_reg(Register R, int opc) { 1078 starti; 1079 f(0b1101011, 31, 25); 1080 f(opc, 24, 21); 1081 f(0b11111000000, 20, 10); 1082 rf(R, 5); 1083 f(0b00000, 4, 0); 1084 } 1085 1086#define INSN(NAME, opc) \ 1087 void NAME(Register R) { \ 1088 branch_reg(R, opc); \ 1089 } 1090 1091 INSN(br, 0b0000); 1092 INSN(blr, 0b0001); 1093 INSN(ret, 0b0010); 1094 1095 void ret(void *p); // This forces a compile-time error for ret(0) 1096 1097#undef INSN 1098 1099#define INSN(NAME, opc) \ 1100 void NAME() { \ 1101 branch_reg(dummy_reg, opc); \ 1102 } 1103 1104 INSN(eret, 0b0100); 1105 INSN(drps, 0b0101); 1106 1107#undef INSN 1108 1109 // Load/store exclusive 1110 enum operand_size { byte, halfword, word, xword }; 1111 1112 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2, 1113 Register Rn, enum operand_size sz, int op, bool ordered) { 1114 starti; 1115 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21); 1116 rf(Rs, 16), f(ordered, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0); 1117 } 1118 1119 void load_exclusive(Register dst, Register addr, 1120 enum operand_size sz, bool ordered) { 1121 load_store_exclusive(dummy_reg, dst, dummy_reg, addr, 1122 sz, 0b010, ordered); 1123 } 1124 1125 void store_exclusive(Register status, Register new_val, Register addr, 1126 enum operand_size sz, bool ordered) { 1127 load_store_exclusive(status, new_val, dummy_reg, addr, 1128 sz, 0b000, ordered); 1129 } 1130 1131#define INSN4(NAME, sz, op, o0) /* Four registers */ \ 1132 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \ 1133 guarantee(Rs != Rn && Rs != Rt1 && Rs != Rt2, "unpredictable instruction"); \ 1134 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \ 1135 } 1136 1137#define INSN3(NAME, sz, op, o0) /* Three registers */ \ 1138 void NAME(Register Rs, Register Rt, Register Rn) { \ 1139 guarantee(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ 1140 load_store_exclusive(Rs, Rt, dummy_reg, Rn, sz, op, o0); \ 1141 } 1142 1143#define INSN2(NAME, sz, op, o0) /* Two registers */ \ 1144 void NAME(Register Rt, Register Rn) { \ 1145 load_store_exclusive(dummy_reg, Rt, dummy_reg, \ 1146 Rn, sz, op, o0); \ 1147 } 1148 1149#define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \ 1150 void NAME(Register Rt1, Register Rt2, Register Rn) { \ 1151 guarantee(Rt1 != Rt2, "unpredictable instruction"); \ 1152 load_store_exclusive(dummy_reg, Rt1, Rt2, Rn, sz, op, o0); \ 1153 } 1154 1155 // bytes 1156 INSN3(stxrb, byte, 0b000, 0); 1157 INSN3(stlxrb, byte, 0b000, 1); 1158 INSN2(ldxrb, byte, 0b010, 0); 1159 INSN2(ldaxrb, byte, 0b010, 1); 1160 INSN2(stlrb, byte, 0b100, 1); 1161 INSN2(ldarb, byte, 0b110, 1); 1162 1163 // halfwords 1164 INSN3(stxrh, halfword, 0b000, 0); 1165 INSN3(stlxrh, halfword, 0b000, 1); 1166 INSN2(ldxrh, halfword, 0b010, 0); 1167 INSN2(ldaxrh, halfword, 0b010, 1); 1168 INSN2(stlrh, halfword, 0b100, 1); 1169 INSN2(ldarh, halfword, 0b110, 1); 1170 1171 // words 1172 INSN3(stxrw, word, 0b000, 0); 1173 INSN3(stlxrw, word, 0b000, 1); 1174 INSN4(stxpw, word, 0b001, 0); 1175 INSN4(stlxpw, word, 0b001, 1); 1176 INSN2(ldxrw, word, 0b010, 0); 1177 INSN2(ldaxrw, word, 0b010, 1); 1178 INSN_FOO(ldxpw, word, 0b011, 0); 1179 INSN_FOO(ldaxpw, word, 0b011, 1); 1180 INSN2(stlrw, word, 0b100, 1); 1181 INSN2(ldarw, word, 0b110, 1); 1182 1183 // xwords 1184 INSN3(stxr, xword, 0b000, 0); 1185 INSN3(stlxr, xword, 0b000, 1); 1186 INSN4(stxp, xword, 0b001, 0); 1187 INSN4(stlxp, xword, 0b001, 1); 1188 INSN2(ldxr, xword, 0b010, 0); 1189 INSN2(ldaxr, xword, 0b010, 1); 1190 INSN_FOO(ldxp, xword, 0b011, 0); 1191 INSN_FOO(ldaxp, xword, 0b011, 1); 1192 INSN2(stlr, xword, 0b100, 1); 1193 INSN2(ldar, xword, 0b110, 1); 1194 1195#undef INSN2 1196#undef INSN3 1197#undef INSN4 1198#undef INSN_FOO 1199 1200 // 8.1 Compare and swap extensions 1201 void lse_cas(Register Rs, Register Rt, Register Rn, 1202 enum operand_size sz, bool a, bool r, bool not_pair) { 1203 starti; 1204 if (! not_pair) { // Pair 1205 assert(sz == word || sz == xword, "invalid size"); 1206 /* The size bit is in bit 30, not 31 */ 1207 sz = (operand_size)(sz == word ? 0b00:0b01); 1208 } 1209 f(sz, 31, 30), f(0b001000, 29, 24), f(1, 23), f(a, 22), f(1, 21); 1210 rf(Rs, 16), f(r, 15), f(0b11111, 14, 10), rf(Rn, 5), rf(Rt, 0); 1211 } 1212 1213 // CAS 1214#define INSN(NAME, a, r) \ 1215 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \ 1216 assert(Rs != Rn && Rs != Rt, "unpredictable instruction"); \ 1217 lse_cas(Rs, Rt, Rn, sz, a, r, true); \ 1218 } 1219 INSN(cas, false, false) 1220 INSN(casa, true, false) 1221 INSN(casl, false, true) 1222 INSN(casal, true, true) 1223#undef INSN 1224 1225 // CASP 1226#define INSN(NAME, a, r) \ 1227 void NAME(operand_size sz, Register Rs, Register Rs1, \ 1228 Register Rt, Register Rt1, Register Rn) { \ 1229 assert((Rs->encoding() & 1) == 0 && (Rt->encoding() & 1) == 0 && \ 1230 Rs->successor() == Rs1 && Rt->successor() == Rt1 && \ 1231 Rs != Rn && Rs1 != Rn && Rs != Rt, "invalid registers"); \ 1232 lse_cas(Rs, Rt, Rn, sz, a, r, false); \ 1233 } 1234 INSN(casp, false, false) 1235 INSN(caspa, true, false) 1236 INSN(caspl, false, true) 1237 INSN(caspal, true, true) 1238#undef INSN 1239 1240 // 8.1 Atomic operations 1241 void lse_atomic(Register Rs, Register Rt, Register Rn, 1242 enum operand_size sz, int op1, int op2, bool a, bool r) { 1243 starti; 1244 f(sz, 31, 30), f(0b111000, 29, 24), f(a, 23), f(r, 22), f(1, 21); 1245 rf(Rs, 16), f(op1, 15), f(op2, 14, 12), f(0, 11, 10), rf(Rn, 5), zrf(Rt, 0); 1246 } 1247 1248#define INSN(NAME, NAME_A, NAME_L, NAME_AL, op1, op2) \ 1249 void NAME(operand_size sz, Register Rs, Register Rt, Register Rn) { \ 1250 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, false); \ 1251 } \ 1252 void NAME_A(operand_size sz, Register Rs, Register Rt, Register Rn) { \ 1253 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, false); \ 1254 } \ 1255 void NAME_L(operand_size sz, Register Rs, Register Rt, Register Rn) { \ 1256 lse_atomic(Rs, Rt, Rn, sz, op1, op2, false, true); \ 1257 } \ 1258 void NAME_AL(operand_size sz, Register Rs, Register Rt, Register Rn) {\ 1259 lse_atomic(Rs, Rt, Rn, sz, op1, op2, true, true); \ 1260 } 1261 INSN(ldadd, ldadda, ldaddl, ldaddal, 0, 0b000); 1262 INSN(ldbic, ldbica, ldbicl, ldbical, 0, 0b001); 1263 INSN(ldeor, ldeora, ldeorl, ldeoral, 0, 0b010); 1264 INSN(ldorr, ldorra, ldorrl, ldorral, 0, 0b011); 1265 INSN(ldsmax, ldsmaxa, ldsmaxl, ldsmaxal, 0, 0b100); 1266 INSN(ldsmin, ldsmina, ldsminl, ldsminal, 0, 0b101); 1267 INSN(ldumax, ldumaxa, ldumaxl, ldumaxal, 0, 0b110); 1268 INSN(ldumin, ldumina, lduminl, lduminal, 0, 0b111); 1269 INSN(swp, swpa, swpl, swpal, 1, 0b000); 1270#undef INSN 1271 1272 // Load register (literal) 1273#define INSN(NAME, opc, V) \ 1274 void NAME(Register Rt, address dest) { \ 1275 long offset = (dest - pc()) >> 2; \ 1276 starti; \ 1277 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1278 sf(offset, 23, 5); \ 1279 rf(Rt, 0); \ 1280 } \ 1281 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \ 1282 InstructionMark im(this); \ 1283 guarantee(rtype == relocInfo::internal_word_type, \ 1284 "only internal_word_type relocs make sense here"); \ 1285 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \ 1286 NAME(Rt, dest); \ 1287 } \ 1288 void NAME(Register Rt, Label &L) { \ 1289 wrap_label(Rt, L, &Assembler::NAME); \ 1290 } 1291 1292 INSN(ldrw, 0b00, 0); 1293 INSN(ldr, 0b01, 0); 1294 INSN(ldrsw, 0b10, 0); 1295 1296#undef INSN 1297 1298#define INSN(NAME, opc, V) \ 1299 void NAME(FloatRegister Rt, address dest) { \ 1300 long offset = (dest - pc()) >> 2; \ 1301 starti; \ 1302 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1303 sf(offset, 23, 5); \ 1304 rf((Register)Rt, 0); \ 1305 } 1306 1307 INSN(ldrs, 0b00, 1); 1308 INSN(ldrd, 0b01, 1); 1309 INSN(ldrq, 0b10, 1); 1310 1311#undef INSN 1312 1313#define INSN(NAME, opc, V) \ 1314 void NAME(address dest, prfop op = PLDL1KEEP) { \ 1315 long offset = (dest - pc()) >> 2; \ 1316 starti; \ 1317 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \ 1318 sf(offset, 23, 5); \ 1319 f(op, 4, 0); \ 1320 } \ 1321 void NAME(Label &L, prfop op = PLDL1KEEP) { \ 1322 wrap_label(L, op, &Assembler::NAME); \ 1323 } 1324 1325 INSN(prfm, 0b11, 0); 1326 1327#undef INSN 1328 1329 // Load/store 1330 void ld_st1(int opc, int p1, int V, int L, 1331 Register Rt1, Register Rt2, Address adr, bool no_allocate) { 1332 starti; 1333 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22); 1334 zrf(Rt2, 10), zrf(Rt1, 0); 1335 if (no_allocate) { 1336 adr.encode_nontemporal_pair(current); 1337 } else { 1338 adr.encode_pair(current); 1339 } 1340 } 1341 1342 // Load/store register pair (offset) 1343#define INSN(NAME, size, p1, V, L, no_allocate) \ 1344 void NAME(Register Rt1, Register Rt2, Address adr) { \ 1345 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \ 1346 } 1347 1348 INSN(stpw, 0b00, 0b101, 0, 0, false); 1349 INSN(ldpw, 0b00, 0b101, 0, 1, false); 1350 INSN(ldpsw, 0b01, 0b101, 0, 1, false); 1351 INSN(stp, 0b10, 0b101, 0, 0, false); 1352 INSN(ldp, 0b10, 0b101, 0, 1, false); 1353 1354 // Load/store no-allocate pair (offset) 1355 INSN(stnpw, 0b00, 0b101, 0, 0, true); 1356 INSN(ldnpw, 0b00, 0b101, 0, 1, true); 1357 INSN(stnp, 0b10, 0b101, 0, 0, true); 1358 INSN(ldnp, 0b10, 0b101, 0, 1, true); 1359 1360#undef INSN 1361 1362#define INSN(NAME, size, p1, V, L, no_allocate) \ 1363 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \ 1364 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \ 1365 } 1366 1367 INSN(stps, 0b00, 0b101, 1, 0, false); 1368 INSN(ldps, 0b00, 0b101, 1, 1, false); 1369 INSN(stpd, 0b01, 0b101, 1, 0, false); 1370 INSN(ldpd, 0b01, 0b101, 1, 1, false); 1371 INSN(stpq, 0b10, 0b101, 1, 0, false); 1372 INSN(ldpq, 0b10, 0b101, 1, 1, false); 1373 1374#undef INSN 1375 1376 // Load/store register (all modes) 1377 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) { 1378 starti; 1379 1380 f(V, 26); // general reg? 1381 zrf(Rt, 0); 1382 1383 // Encoding for literal loads is done here (rather than pushed 1384 // down into Address::encode) because the encoding of this 1385 // instruction is too different from all of the other forms to 1386 // make it worth sharing. 1387 if (adr.getMode() == Address::literal) { 1388 assert(size == 0b10 || size == 0b11, "bad operand size in ldr"); 1389 assert(op == 0b01, "literal form can only be used with loads"); 1390 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24); 1391 long offset = (adr.target() - pc()) >> 2; 1392 sf(offset, 23, 5); 1393 code_section()->relocate(pc(), adr.rspec()); 1394 return; 1395 } 1396 1397 f(size, 31, 30); 1398 f(op, 23, 22); // str 1399 adr.encode(current); 1400 } 1401 1402#define INSN(NAME, size, op) \ 1403 void NAME(Register Rt, const Address &adr) { \ 1404 ld_st2(Rt, adr, size, op); \ 1405 } \ 1406 1407 INSN(str, 0b11, 0b00); 1408 INSN(strw, 0b10, 0b00); 1409 INSN(strb, 0b00, 0b00); 1410 INSN(strh, 0b01, 0b00); 1411 1412 INSN(ldr, 0b11, 0b01); 1413 INSN(ldrw, 0b10, 0b01); 1414 INSN(ldrb, 0b00, 0b01); 1415 INSN(ldrh, 0b01, 0b01); 1416 1417 INSN(ldrsb, 0b00, 0b10); 1418 INSN(ldrsbw, 0b00, 0b11); 1419 INSN(ldrsh, 0b01, 0b10); 1420 INSN(ldrshw, 0b01, 0b11); 1421 INSN(ldrsw, 0b10, 0b10); 1422 1423#undef INSN 1424 1425#define INSN(NAME, size, op) \ 1426 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \ 1427 ld_st2((Register)pfop, adr, size, op); \ 1428 } 1429 1430 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with 1431 // writeback modes, but the assembler 1432 // doesn't enfore that. 1433 1434#undef INSN 1435 1436#define INSN(NAME, size, op) \ 1437 void NAME(FloatRegister Rt, const Address &adr) { \ 1438 ld_st2((Register)Rt, adr, size, op, 1); \ 1439 } 1440 1441 INSN(strd, 0b11, 0b00); 1442 INSN(strs, 0b10, 0b00); 1443 INSN(ldrd, 0b11, 0b01); 1444 INSN(ldrs, 0b10, 0b01); 1445 INSN(strq, 0b00, 0b10); 1446 INSN(ldrq, 0x00, 0b11); 1447 1448#undef INSN 1449 1450 enum shift_kind { LSL, LSR, ASR, ROR }; 1451 1452 void op_shifted_reg(unsigned decode, 1453 enum shift_kind kind, unsigned shift, 1454 unsigned size, unsigned op) { 1455 f(size, 31); 1456 f(op, 30, 29); 1457 f(decode, 28, 24); 1458 f(shift, 15, 10); 1459 f(kind, 23, 22); 1460 } 1461 1462 // Logical (shifted register) 1463#define INSN(NAME, size, op, N) \ 1464 void NAME(Register Rd, Register Rn, Register Rm, \ 1465 enum shift_kind kind = LSL, unsigned shift = 0) { \ 1466 starti; \ 1467 f(N, 21); \ 1468 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \ 1469 op_shifted_reg(0b01010, kind, shift, size, op); \ 1470 } 1471 1472 INSN(andr, 1, 0b00, 0); 1473 INSN(orr, 1, 0b01, 0); 1474 INSN(eor, 1, 0b10, 0); 1475 INSN(ands, 1, 0b11, 0); 1476 INSN(andw, 0, 0b00, 0); 1477 INSN(orrw, 0, 0b01, 0); 1478 INSN(eorw, 0, 0b10, 0); 1479 INSN(andsw, 0, 0b11, 0); 1480 1481 INSN(bic, 1, 0b00, 1); 1482 INSN(orn, 1, 0b01, 1); 1483 INSN(eon, 1, 0b10, 1); 1484 INSN(bics, 1, 0b11, 1); 1485 INSN(bicw, 0, 0b00, 1); 1486 INSN(ornw, 0, 0b01, 1); 1487 INSN(eonw, 0, 0b10, 1); 1488 INSN(bicsw, 0, 0b11, 1); 1489 1490#undef INSN 1491 1492 // Add/subtract (shifted register) 1493#define INSN(NAME, size, op) \ 1494 void NAME(Register Rd, Register Rn, Register Rm, \ 1495 enum shift_kind kind, unsigned shift = 0) { \ 1496 starti; \ 1497 f(0, 21); \ 1498 assert_cond(kind != ROR); \ 1499 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \ 1500 op_shifted_reg(0b01011, kind, shift, size, op); \ 1501 } 1502 1503 INSN(add, 1, 0b000); 1504 INSN(sub, 1, 0b10); 1505 INSN(addw, 0, 0b000); 1506 INSN(subw, 0, 0b10); 1507 1508 INSN(adds, 1, 0b001); 1509 INSN(subs, 1, 0b11); 1510 INSN(addsw, 0, 0b001); 1511 INSN(subsw, 0, 0b11); 1512 1513#undef INSN 1514 1515 // Add/subtract (extended register) 1516#define INSN(NAME, op) \ 1517 void NAME(Register Rd, Register Rn, Register Rm, \ 1518 ext::operation option, int amount = 0) { \ 1519 starti; \ 1520 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \ 1521 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1522 } 1523 1524 void add_sub_extended_reg(unsigned op, unsigned decode, 1525 Register Rd, Register Rn, Register Rm, 1526 unsigned opt, ext::operation option, unsigned imm) { 1527 guarantee(imm <= 4, "shift amount must be < 4"); 1528 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21); 1529 f(option, 15, 13), f(imm, 12, 10); 1530 } 1531 1532 INSN(addw, 0b000); 1533 INSN(subw, 0b010); 1534 INSN(add, 0b100); 1535 INSN(sub, 0b110); 1536 1537#undef INSN 1538 1539#define INSN(NAME, op) \ 1540 void NAME(Register Rd, Register Rn, Register Rm, \ 1541 ext::operation option, int amount = 0) { \ 1542 starti; \ 1543 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \ 1544 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \ 1545 } 1546 1547 INSN(addsw, 0b001); 1548 INSN(subsw, 0b011); 1549 INSN(adds, 0b101); 1550 INSN(subs, 0b111); 1551 1552#undef INSN 1553 1554 // Aliases for short forms of add and sub 1555#define INSN(NAME) \ 1556 void NAME(Register Rd, Register Rn, Register Rm) { \ 1557 if (Rd == sp || Rn == sp) \ 1558 NAME(Rd, Rn, Rm, ext::uxtx); \ 1559 else \ 1560 NAME(Rd, Rn, Rm, LSL); \ 1561 } 1562 1563 INSN(addw); 1564 INSN(subw); 1565 INSN(add); 1566 INSN(sub); 1567 1568 INSN(addsw); 1569 INSN(subsw); 1570 INSN(adds); 1571 INSN(subs); 1572 1573#undef INSN 1574 1575 // Add/subtract (with carry) 1576 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) { 1577 starti; 1578 f(op, 31, 29); 1579 f(0b11010000, 28, 21); 1580 f(0b000000, 15, 10); 1581 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); 1582 } 1583 1584 #define INSN(NAME, op) \ 1585 void NAME(Register Rd, Register Rn, Register Rm) { \ 1586 add_sub_carry(op, Rd, Rn, Rm); \ 1587 } 1588 1589 INSN(adcw, 0b000); 1590 INSN(adcsw, 0b001); 1591 INSN(sbcw, 0b010); 1592 INSN(sbcsw, 0b011); 1593 INSN(adc, 0b100); 1594 INSN(adcs, 0b101); 1595 INSN(sbc,0b110); 1596 INSN(sbcs, 0b111); 1597 1598#undef INSN 1599 1600 // Conditional compare (both kinds) 1601 void conditional_compare(unsigned op, int o2, int o3, 1602 Register Rn, unsigned imm5, unsigned nzcv, 1603 unsigned cond) { 1604 f(op, 31, 29); 1605 f(0b11010010, 28, 21); 1606 f(cond, 15, 12); 1607 f(o2, 10); 1608 f(o3, 4); 1609 f(nzcv, 3, 0); 1610 f(imm5, 20, 16), rf(Rn, 5); 1611 } 1612 1613#define INSN(NAME, op) \ 1614 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \ 1615 starti; \ 1616 f(0, 11); \ 1617 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \ 1618 } \ 1619 \ 1620 void NAME(Register Rn, int imm5, int imm, Condition cond) { \ 1621 starti; \ 1622 f(1, 11); \ 1623 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \ 1624 } 1625 1626 INSN(ccmnw, 0b001); 1627 INSN(ccmpw, 0b011); 1628 INSN(ccmn, 0b101); 1629 INSN(ccmp, 0b111); 1630 1631#undef INSN 1632 1633 // Conditional select 1634 void conditional_select(unsigned op, unsigned op2, 1635 Register Rd, Register Rn, Register Rm, 1636 unsigned cond) { 1637 starti; 1638 f(op, 31, 29); 1639 f(0b11010100, 28, 21); 1640 f(cond, 15, 12); 1641 f(op2, 11, 10); 1642 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0); 1643 } 1644 1645#define INSN(NAME, op, op2) \ 1646 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \ 1647 conditional_select(op, op2, Rd, Rn, Rm, cond); \ 1648 } 1649 1650 INSN(cselw, 0b000, 0b00); 1651 INSN(csincw, 0b000, 0b01); 1652 INSN(csinvw, 0b010, 0b00); 1653 INSN(csnegw, 0b010, 0b01); 1654 INSN(csel, 0b100, 0b00); 1655 INSN(csinc, 0b100, 0b01); 1656 INSN(csinv, 0b110, 0b00); 1657 INSN(csneg, 0b110, 0b01); 1658 1659#undef INSN 1660 1661 // Data processing 1662 void data_processing(unsigned op29, unsigned opcode, 1663 Register Rd, Register Rn) { 1664 f(op29, 31, 29), f(0b11010110, 28, 21); 1665 f(opcode, 15, 10); 1666 rf(Rn, 5), rf(Rd, 0); 1667 } 1668 1669 // (1 source) 1670#define INSN(NAME, op29, opcode2, opcode) \ 1671 void NAME(Register Rd, Register Rn) { \ 1672 starti; \ 1673 f(opcode2, 20, 16); \ 1674 data_processing(op29, opcode, Rd, Rn); \ 1675 } 1676 1677 INSN(rbitw, 0b010, 0b00000, 0b00000); 1678 INSN(rev16w, 0b010, 0b00000, 0b00001); 1679 INSN(revw, 0b010, 0b00000, 0b00010); 1680 INSN(clzw, 0b010, 0b00000, 0b00100); 1681 INSN(clsw, 0b010, 0b00000, 0b00101); 1682 1683 INSN(rbit, 0b110, 0b00000, 0b00000); 1684 INSN(rev16, 0b110, 0b00000, 0b00001); 1685 INSN(rev32, 0b110, 0b00000, 0b00010); 1686 INSN(rev, 0b110, 0b00000, 0b00011); 1687 INSN(clz, 0b110, 0b00000, 0b00100); 1688 INSN(cls, 0b110, 0b00000, 0b00101); 1689 1690#undef INSN 1691 1692 // (2 sources) 1693#define INSN(NAME, op29, opcode) \ 1694 void NAME(Register Rd, Register Rn, Register Rm) { \ 1695 starti; \ 1696 rf(Rm, 16); \ 1697 data_processing(op29, opcode, Rd, Rn); \ 1698 } 1699 1700 INSN(udivw, 0b000, 0b000010); 1701 INSN(sdivw, 0b000, 0b000011); 1702 INSN(lslvw, 0b000, 0b001000); 1703 INSN(lsrvw, 0b000, 0b001001); 1704 INSN(asrvw, 0b000, 0b001010); 1705 INSN(rorvw, 0b000, 0b001011); 1706 1707 INSN(udiv, 0b100, 0b000010); 1708 INSN(sdiv, 0b100, 0b000011); 1709 INSN(lslv, 0b100, 0b001000); 1710 INSN(lsrv, 0b100, 0b001001); 1711 INSN(asrv, 0b100, 0b001010); 1712 INSN(rorv, 0b100, 0b001011); 1713 1714#undef INSN 1715 1716 // (3 sources) 1717 void data_processing(unsigned op54, unsigned op31, unsigned o0, 1718 Register Rd, Register Rn, Register Rm, 1719 Register Ra) { 1720 starti; 1721 f(op54, 31, 29), f(0b11011, 28, 24); 1722 f(op31, 23, 21), f(o0, 15); 1723 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0); 1724 } 1725 1726#define INSN(NAME, op54, op31, o0) \ 1727 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \ 1728 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \ 1729 } 1730 1731 INSN(maddw, 0b000, 0b000, 0); 1732 INSN(msubw, 0b000, 0b000, 1); 1733 INSN(madd, 0b100, 0b000, 0); 1734 INSN(msub, 0b100, 0b000, 1); 1735 INSN(smaddl, 0b100, 0b001, 0); 1736 INSN(smsubl, 0b100, 0b001, 1); 1737 INSN(umaddl, 0b100, 0b101, 0); 1738 INSN(umsubl, 0b100, 0b101, 1); 1739 1740#undef INSN 1741 1742#define INSN(NAME, op54, op31, o0) \ 1743 void NAME(Register Rd, Register Rn, Register Rm) { \ 1744 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \ 1745 } 1746 1747 INSN(smulh, 0b100, 0b010, 0); 1748 INSN(umulh, 0b100, 0b110, 0); 1749 1750#undef INSN 1751 1752 // Floating-point data-processing (1 source) 1753 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1754 FloatRegister Vd, FloatRegister Vn) { 1755 starti; 1756 f(op31, 31, 29); 1757 f(0b11110, 28, 24); 1758 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10); 1759 rf(Vn, 5), rf(Vd, 0); 1760 } 1761 1762#define INSN(NAME, op31, type, opcode) \ 1763 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 1764 data_processing(op31, type, opcode, Vd, Vn); \ 1765 } 1766 1767private: 1768 INSN(i_fmovs, 0b000, 0b00, 0b000000); 1769public: 1770 INSN(fabss, 0b000, 0b00, 0b000001); 1771 INSN(fnegs, 0b000, 0b00, 0b000010); 1772 INSN(fsqrts, 0b000, 0b00, 0b000011); 1773 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision 1774 1775private: 1776 INSN(i_fmovd, 0b000, 0b01, 0b000000); 1777public: 1778 INSN(fabsd, 0b000, 0b01, 0b000001); 1779 INSN(fnegd, 0b000, 0b01, 0b000010); 1780 INSN(fsqrtd, 0b000, 0b01, 0b000011); 1781 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision 1782 1783 void fmovd(FloatRegister Vd, FloatRegister Vn) { 1784 assert(Vd != Vn, "should be"); 1785 i_fmovd(Vd, Vn); 1786 } 1787 1788 void fmovs(FloatRegister Vd, FloatRegister Vn) { 1789 assert(Vd != Vn, "should be"); 1790 i_fmovs(Vd, Vn); 1791 } 1792 1793#undef INSN 1794 1795 // Floating-point data-processing (2 source) 1796 void data_processing(unsigned op31, unsigned type, unsigned opcode, 1797 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { 1798 starti; 1799 f(op31, 31, 29); 1800 f(0b11110, 28, 24); 1801 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10); 1802 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1803 } 1804 1805#define INSN(NAME, op31, type, opcode) \ 1806 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \ 1807 data_processing(op31, type, opcode, Vd, Vn, Vm); \ 1808 } 1809 1810 INSN(fmuls, 0b000, 0b00, 0b0000); 1811 INSN(fdivs, 0b000, 0b00, 0b0001); 1812 INSN(fadds, 0b000, 0b00, 0b0010); 1813 INSN(fsubs, 0b000, 0b00, 0b0011); 1814 INSN(fnmuls, 0b000, 0b00, 0b1000); 1815 1816 INSN(fmuld, 0b000, 0b01, 0b0000); 1817 INSN(fdivd, 0b000, 0b01, 0b0001); 1818 INSN(faddd, 0b000, 0b01, 0b0010); 1819 INSN(fsubd, 0b000, 0b01, 0b0011); 1820 INSN(fnmuld, 0b000, 0b01, 0b1000); 1821 1822#undef INSN 1823 1824 // Floating-point data-processing (3 source) 1825 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0, 1826 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, 1827 FloatRegister Va) { 1828 starti; 1829 f(op31, 31, 29); 1830 f(0b11111, 28, 24); 1831 f(type, 23, 22), f(o1, 21), f(o0, 15); 1832 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0); 1833 } 1834 1835#define INSN(NAME, op31, type, o1, o0) \ 1836 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \ 1837 FloatRegister Va) { \ 1838 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \ 1839 } 1840 1841 INSN(fmadds, 0b000, 0b00, 0, 0); 1842 INSN(fmsubs, 0b000, 0b00, 0, 1); 1843 INSN(fnmadds, 0b000, 0b00, 1, 0); 1844 INSN(fnmsubs, 0b000, 0b00, 1, 1); 1845 1846 INSN(fmaddd, 0b000, 0b01, 0, 0); 1847 INSN(fmsubd, 0b000, 0b01, 0, 1); 1848 INSN(fnmaddd, 0b000, 0b01, 1, 0); 1849 INSN(fnmsub, 0b000, 0b01, 1, 1); 1850 1851#undef INSN 1852 1853 // Floating-point conditional select 1854 void fp_conditional_select(unsigned op31, unsigned type, 1855 unsigned op1, unsigned op2, 1856 Condition cond, FloatRegister Vd, 1857 FloatRegister Vn, FloatRegister Vm) { 1858 starti; 1859 f(op31, 31, 29); 1860 f(0b11110, 28, 24); 1861 f(type, 23, 22); 1862 f(op1, 21, 21); 1863 f(op2, 11, 10); 1864 f(cond, 15, 12); 1865 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); 1866 } 1867 1868#define INSN(NAME, op31, type, op1, op2) \ 1869 void NAME(FloatRegister Vd, FloatRegister Vn, \ 1870 FloatRegister Vm, Condition cond) { \ 1871 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \ 1872 } 1873 1874 INSN(fcsels, 0b000, 0b00, 0b1, 0b11); 1875 INSN(fcseld, 0b000, 0b01, 0b1, 0b11); 1876 1877#undef INSN 1878 1879 // Floating-point<->integer conversions 1880 void float_int_convert(unsigned op31, unsigned type, 1881 unsigned rmode, unsigned opcode, 1882 Register Rd, Register Rn) { 1883 starti; 1884 f(op31, 31, 29); 1885 f(0b11110, 28, 24); 1886 f(type, 23, 22), f(1, 21), f(rmode, 20, 19); 1887 f(opcode, 18, 16), f(0b000000, 15, 10); 1888 zrf(Rn, 5), zrf(Rd, 0); 1889 } 1890 1891#define INSN(NAME, op31, type, rmode, opcode) \ 1892 void NAME(Register Rd, FloatRegister Vn) { \ 1893 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \ 1894 } 1895 1896 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000); 1897 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000); 1898 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000); 1899 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000); 1900 1901 INSN(fmovs, 0b000, 0b00, 0b00, 0b110); 1902 INSN(fmovd, 0b100, 0b01, 0b00, 0b110); 1903 1904 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110); 1905 1906#undef INSN 1907 1908#define INSN(NAME, op31, type, rmode, opcode) \ 1909 void NAME(FloatRegister Vd, Register Rn) { \ 1910 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \ 1911 } 1912 1913 INSN(fmovs, 0b000, 0b00, 0b00, 0b111); 1914 INSN(fmovd, 0b100, 0b01, 0b00, 0b111); 1915 1916 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010); 1917 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010); 1918 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010); 1919 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010); 1920 1921 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111); 1922 1923#undef INSN 1924 1925 // Floating-point compare 1926 void float_compare(unsigned op31, unsigned type, 1927 unsigned op, unsigned op2, 1928 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) { 1929 starti; 1930 f(op31, 31, 29); 1931 f(0b11110, 28, 24); 1932 f(type, 23, 22), f(1, 21); 1933 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0); 1934 rf(Vn, 5), rf(Vm, 16); 1935 } 1936 1937 1938#define INSN(NAME, op31, type, op, op2) \ 1939 void NAME(FloatRegister Vn, FloatRegister Vm) { \ 1940 float_compare(op31, type, op, op2, Vn, Vm); \ 1941 } 1942 1943#define INSN1(NAME, op31, type, op, op2) \ 1944 void NAME(FloatRegister Vn, double d) { \ 1945 assert_cond(d == 0.0); \ 1946 float_compare(op31, type, op, op2, Vn); \ 1947 } 1948 1949 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000); 1950 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000); 1951 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000); 1952 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000); 1953 1954 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000); 1955 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000); 1956 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000); 1957 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000); 1958 1959#undef INSN 1960#undef INSN1 1961 1962 // Floating-point Move (immediate) 1963private: 1964 unsigned pack(double value); 1965 1966 void fmov_imm(FloatRegister Vn, double value, unsigned size) { 1967 starti; 1968 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21); 1969 f(pack(value), 20, 13), f(0b10000000, 12, 5); 1970 rf(Vn, 0); 1971 } 1972 1973public: 1974 1975 void fmovs(FloatRegister Vn, double value) { 1976 if (value) 1977 fmov_imm(Vn, value, 0b00); 1978 else 1979 fmovs(Vn, zr); 1980 } 1981 void fmovd(FloatRegister Vn, double value) { 1982 if (value) 1983 fmov_imm(Vn, value, 0b01); 1984 else 1985 fmovd(Vn, zr); 1986 } 1987 1988/* SIMD extensions 1989 * 1990 * We just use FloatRegister in the following. They are exactly the same 1991 * as SIMD registers. 1992 */ 1993 public: 1994 1995 enum SIMD_Arrangement { 1996 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q 1997 }; 1998 1999 enum SIMD_RegVariant { 2000 B, H, S, D, Q 2001 }; 2002 2003#define INSN(NAME, op) \ 2004 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \ 2005 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \ 2006 } \ 2007 2008 INSN(ldr, 1); 2009 INSN(str, 0); 2010 2011#undef INSN 2012 2013 private: 2014 2015 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) { 2016 starti; 2017 f(0,31), f((int)T & 1, 30); 2018 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12); 2019 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 2020 } 2021 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 2022 int imm, int op1, int op2) { 2023 starti; 2024 f(0,31), f((int)T & 1, 30); 2025 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12); 2026 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 2027 } 2028 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, 2029 Register Xm, int op1, int op2) { 2030 starti; 2031 f(0,31), f((int)T & 1, 30); 2032 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12); 2033 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0); 2034 } 2035 2036 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) { 2037 switch (a.getMode()) { 2038 case Address::base_plus_offset: 2039 guarantee(a.offset() == 0, "no offset allowed here"); 2040 ld_st(Vt, T, a.base(), op1, op2); 2041 break; 2042 case Address::post: 2043 ld_st(Vt, T, a.base(), a.offset(), op1, op2); 2044 break; 2045 case Address::base_plus_offset_reg: 2046 ld_st(Vt, T, a.base(), a.index(), op1, op2); 2047 break; 2048 default: 2049 ShouldNotReachHere(); 2050 } 2051 } 2052 2053 public: 2054 2055#define INSN1(NAME, op1, op2) \ 2056 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \ 2057 ld_st(Vt, T, a, op1, op2); \ 2058 } 2059 2060#define INSN2(NAME, op1, op2) \ 2061 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \ 2062 assert(Vt->successor() == Vt2, "Registers must be ordered"); \ 2063 ld_st(Vt, T, a, op1, op2); \ 2064 } 2065 2066#define INSN3(NAME, op1, op2) \ 2067 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 2068 SIMD_Arrangement T, const Address &a) { \ 2069 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \ 2070 "Registers must be ordered"); \ 2071 ld_st(Vt, T, a, op1, op2); \ 2072 } 2073 2074#define INSN4(NAME, op1, op2) \ 2075 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \ 2076 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \ 2077 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \ 2078 Vt3->successor() == Vt4, "Registers must be ordered"); \ 2079 ld_st(Vt, T, a, op1, op2); \ 2080 } 2081 2082 INSN1(ld1, 0b001100010, 0b0111); 2083 INSN2(ld1, 0b001100010, 0b1010); 2084 INSN3(ld1, 0b001100010, 0b0110); 2085 INSN4(ld1, 0b001100010, 0b0010); 2086 2087 INSN2(ld2, 0b001100010, 0b1000); 2088 INSN3(ld3, 0b001100010, 0b0100); 2089 INSN4(ld4, 0b001100010, 0b0000); 2090 2091 INSN1(st1, 0b001100000, 0b0111); 2092 INSN2(st1, 0b001100000, 0b1010); 2093 INSN3(st1, 0b001100000, 0b0110); 2094 INSN4(st1, 0b001100000, 0b0010); 2095 2096 INSN2(st2, 0b001100000, 0b1000); 2097 INSN3(st3, 0b001100000, 0b0100); 2098 INSN4(st4, 0b001100000, 0b0000); 2099 2100 INSN1(ld1r, 0b001101010, 0b1100); 2101 INSN2(ld2r, 0b001101011, 0b1100); 2102 INSN3(ld3r, 0b001101010, 0b1110); 2103 INSN4(ld4r, 0b001101011, 0b1110); 2104 2105#undef INSN1 2106#undef INSN2 2107#undef INSN3 2108#undef INSN4 2109 2110#define INSN(NAME, opc) \ 2111 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2112 starti; \ 2113 assert(T == T8B || T == T16B, "must be T8B or T16B"); \ 2114 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \ 2115 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2116 } 2117 2118 INSN(eor, 0b101110001); 2119 INSN(orr, 0b001110101); 2120 INSN(andr, 0b001110001); 2121 INSN(bic, 0b001110011); 2122 INSN(bif, 0b101110111); 2123 INSN(bit, 0b101110101); 2124 INSN(bsl, 0b101110011); 2125 INSN(orn, 0b001110111); 2126 2127#undef INSN 2128 2129#define INSN(NAME, opc, opc2) \ 2130 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2131 starti; \ 2132 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2133 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \ 2134 rf(Vn, 5), rf(Vd, 0); \ 2135 } 2136 2137 INSN(addv, 0, 0b100001); 2138 INSN(subv, 1, 0b100001); 2139 INSN(mulv, 0, 0b100111); 2140 INSN(mlav, 0, 0b100101); 2141 INSN(mlsv, 1, 0b100101); 2142 INSN(sshl, 0, 0b010001); 2143 INSN(ushl, 1, 0b010001); 2144 2145#undef INSN 2146 2147#define INSN(NAME, opc, opc2) \ 2148 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2149 starti; \ 2150 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \ 2151 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \ 2152 rf(Vn, 5), rf(Vd, 0); \ 2153 } 2154 2155 INSN(absr, 0, 0b100000101110); 2156 INSN(negr, 1, 0b100000101110); 2157 INSN(notr, 1, 0b100000010110); 2158 INSN(addv, 0, 0b110001101110); 2159 INSN(cls, 0, 0b100000010010); 2160 INSN(clz, 1, 0b100000010010); 2161 INSN(cnt, 0, 0b100000010110); 2162 2163#undef INSN 2164 2165#define INSN(NAME, op0, cmode0) \ 2166 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \ 2167 unsigned cmode = cmode0; \ 2168 unsigned op = op0; \ 2169 starti; \ 2170 assert(lsl == 0 || \ 2171 ((T == T4H || T == T8H) && lsl == 8) || \ 2172 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \ 2173 cmode |= lsl >> 2; \ 2174 if (T == T4H || T == T8H) cmode |= 0b1000; \ 2175 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \ 2176 assert(op == 0 && cmode0 == 0, "must be MOVI"); \ 2177 cmode = 0b1110; \ 2178 if (T == T1D || T == T2D) op = 1; \ 2179 } \ 2180 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \ 2181 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \ 2182 rf(Vd, 0); \ 2183 } 2184 2185 INSN(movi, 0, 0); 2186 INSN(orri, 0, 1); 2187 INSN(mvni, 1, 0); 2188 INSN(bici, 1, 1); 2189 2190#undef INSN 2191 2192#define INSN(NAME, op1, op2, op3) \ 2193 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2194 starti; \ 2195 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \ 2196 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \ 2197 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2198 } 2199 2200 INSN(fadd, 0, 0, 0b110101); 2201 INSN(fdiv, 1, 0, 0b111111); 2202 INSN(fmul, 1, 0, 0b110111); 2203 INSN(fsub, 0, 1, 0b110101); 2204 2205#undef INSN 2206 2207#define INSN(NAME, opc) \ 2208 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2209 starti; \ 2210 assert(T == T4S, "arrangement must be T4S"); \ 2211 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2212 } 2213 2214 INSN(sha1c, 0b000000); 2215 INSN(sha1m, 0b001000); 2216 INSN(sha1p, 0b000100); 2217 INSN(sha1su0, 0b001100); 2218 INSN(sha256h2, 0b010100); 2219 INSN(sha256h, 0b010000); 2220 INSN(sha256su1, 0b011000); 2221 2222#undef INSN 2223 2224#define INSN(NAME, opc) \ 2225 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2226 starti; \ 2227 assert(T == T4S, "arrangement must be T4S"); \ 2228 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2229 } 2230 2231 INSN(sha1h, 0b000010); 2232 INSN(sha1su1, 0b000110); 2233 INSN(sha256su0, 0b001010); 2234 2235#undef INSN 2236 2237#define INSN(NAME, opc) \ 2238 void NAME(FloatRegister Vd, FloatRegister Vn) { \ 2239 starti; \ 2240 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \ 2241 } 2242 2243 INSN(aese, 0b0100111000101000010010); 2244 INSN(aesd, 0b0100111000101000010110); 2245 INSN(aesmc, 0b0100111000101000011010); 2246 INSN(aesimc, 0b0100111000101000011110); 2247 2248#undef INSN 2249 2250 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) { 2251 starti; 2252 assert(T != Q, "invalid register variant"); 2253 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15); 2254 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0); 2255 } 2256 2257 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) { 2258 starti; 2259 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21); 2260 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10); 2261 rf(Vn, 5), rf(Rd, 0); 2262 } 2263 2264#define INSN(NAME, opc, opc2) \ 2265 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \ 2266 starti; \ 2267 /* The encodings for the immh:immb fields (bits 22:16) are \ 2268 * 0001 xxx 8B/16B, shift = xxx \ 2269 * 001x xxx 4H/8H, shift = xxxx \ 2270 * 01xx xxx 2S/4S, shift = xxxxx \ 2271 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \ 2272 */ \ 2273 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \ 2274 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \ 2275 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \ 2276 } 2277 2278 INSN(shl, 0, 0b010101); 2279 INSN(sshr, 0, 0b000001); 2280 INSN(ushr, 1, 0b000001); 2281 2282#undef INSN 2283 2284 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2285 starti; 2286 /* The encodings for the immh:immb fields (bits 22:16) are 2287 * 0001 xxx 8H, 8B/16b shift = xxx 2288 * 001x xxx 4S, 4H/8H shift = xxxx 2289 * 01xx xxx 2D, 2S/4S shift = xxxxx 2290 * 1xxx xxx RESERVED 2291 */ 2292 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement"); 2293 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value"); 2294 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16); 2295 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2296 } 2297 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) { 2298 ushll(Vd, Ta, Vn, Tb, shift); 2299 } 2300 2301 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){ 2302 starti; 2303 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21); 2304 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0); 2305 } 2306 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){ 2307 uzp1(Vd, Vn, Vm, T, 1); 2308 } 2309 2310 // Move from general purpose register 2311 // mov Vd.T[index], Rn 2312 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) { 2313 starti; 2314 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2315 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0); 2316 } 2317 2318 // Move to general purpose register 2319 // mov Rd, Vn.T[index] 2320 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) { 2321 starti; 2322 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21); 2323 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2324 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0); 2325 } 2326 2327 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2328 starti; 2329 assert((Ta == T1Q && (Tb == T1D || Tb == T2D)) || 2330 (Ta == T8H && (Tb == T8B || Tb == T16B)), "Invalid Size specifier"); 2331 int size = (Ta == T1Q) ? 0b11 : 0b00; 2332 f(0, 31), f(Tb & 1, 30), f(0b001110, 29, 24), f(size, 23, 22); 2333 f(1, 21), rf(Vm, 16), f(0b111000, 15, 10), rf(Vn, 5), rf(Vd, 0); 2334 } 2335 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) { 2336 assert(Tb == T2D || Tb == T16B, "pmull2 assumes T2D or T16B as the second size specifier"); 2337 pmull(Vd, Ta, Vn, Vm, Tb); 2338 } 2339 2340 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) { 2341 starti; 2342 int size_b = (int)Tb >> 1; 2343 int size_a = (int)Ta >> 1; 2344 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier"); 2345 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22); 2346 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0); 2347 } 2348 2349 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs) 2350 { 2351 starti; 2352 assert(T != T1D, "reserved encoding"); 2353 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2354 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0); 2355 } 2356 2357 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0) 2358 { 2359 starti; 2360 assert(T != T1D, "reserved encoding"); 2361 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21); 2362 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16); 2363 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0); 2364 } 2365 2366 // AdvSIMD ZIP/UZP/TRN 2367#define INSN(NAME, opcode) \ 2368 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \ 2369 starti; \ 2370 f(0, 31), f(0b001110, 29, 24), f(0, 21), f(0b001110, 15, 10); \ 2371 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0); \ 2372 f(T & 1, 30), f(T >> 1, 23, 22); \ 2373 } 2374 2375 INSN(uzp1, 0b001); 2376 INSN(trn1, 0b010); 2377 INSN(zip1, 0b011); 2378 INSN(uzp2, 0b101); 2379 INSN(trn2, 0b110); 2380 INSN(zip2, 0b111); 2381 2382#undef INSN 2383 2384 // CRC32 instructions 2385#define INSN(NAME, c, sf, sz) \ 2386 void NAME(Register Rd, Register Rn, Register Rm) { \ 2387 starti; \ 2388 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \ 2389 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \ 2390 } 2391 2392 INSN(crc32b, 0, 0, 0b00); 2393 INSN(crc32h, 0, 0, 0b01); 2394 INSN(crc32w, 0, 0, 0b10); 2395 INSN(crc32x, 0, 1, 0b11); 2396 INSN(crc32cb, 1, 0, 0b00); 2397 INSN(crc32ch, 1, 0, 0b01); 2398 INSN(crc32cw, 1, 0, 0b10); 2399 INSN(crc32cx, 1, 1, 0b11); 2400 2401#undef INSN 2402 2403 // Table vector lookup 2404#define INSN(NAME, op) \ 2405 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, unsigned registers, FloatRegister Vm) { \ 2406 starti; \ 2407 assert(T == T8B || T == T16B, "invalid arrangement"); \ 2408 assert(0 < registers && registers <= 4, "invalid number of registers"); \ 2409 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21), rf(Vm, 16), f(0, 15); \ 2410 f(registers - 1, 14, 13), f(op, 12),f(0b00, 11, 10), rf(Vn, 5), rf(Vd, 0); \ 2411 } 2412 2413 INSN(tbl, 0); 2414 INSN(tbx, 1); 2415 2416#undef INSN 2417 2418 // AdvSIMD two-reg misc 2419#define INSN(NAME, U, opcode) \ 2420 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \ 2421 starti; \ 2422 assert((ASSERTION), MSG); \ 2423 f(0, 31), f((int)T & 1, 30), f(U, 29), f(0b01110, 28, 24); \ 2424 f((int)(T >> 1), 23, 22), f(0b10000, 21, 17), f(opcode, 16, 12); \ 2425 f(0b10, 11, 10), rf(Vn, 5), rf(Vd, 0); \ 2426 } 2427 2428#define MSG "invalid arrangement" 2429 2430#define ASSERTION (T == T2S || T == T4S || T == T2D) 2431 INSN(fsqrt, 1, 0b11111); 2432 INSN(fabs, 0, 0b01111); 2433 INSN(fneg, 1, 0b01111); 2434#undef ASSERTION 2435 2436#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H || T == T2S || T == T4S) 2437 INSN(rev64, 0, 0b00000); 2438#undef ASSERTION 2439 2440#define ASSERTION (T == T8B || T == T16B || T == T4H || T == T8H) 2441 INSN(rev32, 1, 0b00000); 2442private: 2443 INSN(_rbit, 1, 0b00101); 2444public: 2445 2446#undef ASSERTION 2447 2448#define ASSERTION (T == T8B || T == T16B) 2449 INSN(rev16, 0, 0b00001); 2450 // RBIT only allows T8B and T16B but encodes them oddly. Argh... 2451 void rbit(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { 2452 assert((ASSERTION), MSG); 2453 _rbit(Vd, SIMD_Arrangement(T & 1 | 0b010), Vn); 2454 } 2455#undef ASSERTION 2456 2457#undef MSG 2458 2459#undef INSN 2460 2461void ext(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm, int index) 2462 { 2463 starti; 2464 assert(T == T8B || T == T16B, "invalid arrangement"); 2465 assert((T == T8B && index <= 0b0111) || (T == T16B && index <= 0b1111), "Invalid index value"); 2466 f(0, 31), f((int)T & 1, 30), f(0b101110000, 29, 21); 2467 rf(Vm, 16), f(0, 15), f(index, 14, 11); 2468 f(0, 10), rf(Vn, 5), rf(Vd, 0); 2469 } 2470 2471/* Simulator extensions to the ISA 2472 2473 haltsim 2474 2475 takes no arguments, causes the sim to enter a debug break and then 2476 return from the simulator run() call with STATUS_HALT? The linking 2477 code will call fatal() when it sees STATUS_HALT. 2478 2479 blrt Xn, Wm 2480 blrt Xn, #gpargs, #fpargs, #type 2481 Xn holds the 64 bit x86 branch_address 2482 call format is encoded either as immediate data in the call 2483 or in register Wm. In the latter case 2484 Wm[13..6] = #gpargs, 2485 Wm[5..2] = #fpargs, 2486 Wm[1,0] = #type 2487 2488 calls the x86 code address 'branch_address' supplied in Xn passing 2489 arguments taken from the general and floating point registers according 2490 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0 2491 or v0 according to the the return type #type' where 2492 2493 address branch_address; 2494 uimm4 gpargs; 2495 uimm4 fpargs; 2496 enum ReturnType type; 2497 2498 enum ReturnType 2499 { 2500 void_ret = 0, 2501 int_ret = 1, 2502 long_ret = 1, 2503 obj_ret = 1, // i.e. same as long 2504 float_ret = 2, 2505 double_ret = 3 2506 } 2507 2508 notify 2509 2510 notifies the simulator of a transfer of control. instr[14:0] 2511 identifies the type of change of control. 2512 2513 0 ==> initial entry to a method. 2514 2515 1 ==> return into a method from a submethod call. 2516 2517 2 ==> exit out of Java method code. 2518 2519 3 ==> start execution for a new bytecode. 2520 2521 in cases 1 and 2 the simulator is expected to use a JVM callback to 2522 identify the name of the specific method being executed. in case 4 2523 the simulator is expected to use a JVM callback to identify the 2524 bytecode index. 2525 2526 Instruction encodings 2527 --------------------- 2528 2529 These are encoded in the space with instr[28:25] = 00 which is 2530 unallocated. Encodings are 2531 2532 10987654321098765432109876543210 2533 PSEUDO_HALT = 0x11100000000000000000000000000000 2534 PSEUDO_BLRT = 0x11000000000000000_______________ 2535 PSEUDO_BLRTR = 0x1100000000000000100000__________ 2536 PSEUDO_NOTIFY = 0x10100000000000000_______________ 2537 2538 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY 2539 2540 for BLRT 2541 instr[14,11] = #gpargs, instr[10,7] = #fpargs 2542 instr[6,5] = #type, instr[4,0] = Rn 2543 for BLRTR 2544 instr[9,5] = Rm, instr[4,0] = Rn 2545 for NOTIFY 2546 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart 2547*/ 2548 2549 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start }; 2550 2551 virtual void notify(int type) { 2552 if (UseBuiltinSim) { 2553 starti; 2554 // 109 2555 f(0b101, 31, 29); 2556 // 87654321098765 2557 f(0b00000000000000, 28, 15); 2558 f(type, 14, 0); 2559 } 2560 } 2561 2562 void blrt(Register Rn, int gpargs, int fpargs, int type) { 2563 if (UseBuiltinSim) { 2564 starti; 2565 f(0b110, 31 ,29); 2566 f(0b00, 28, 25); 2567 // 4321098765 2568 f(0b0000000000, 24, 15); 2569 f(gpargs, 14, 11); 2570 f(fpargs, 10, 7); 2571 f(type, 6, 5); 2572 rf(Rn, 0); 2573 } else { 2574 blr(Rn); 2575 } 2576 } 2577 2578 void blrt(Register Rn, Register Rm) { 2579 if (UseBuiltinSim) { 2580 starti; 2581 f(0b110, 31 ,29); 2582 f(0b00, 28, 25); 2583 // 4321098765 2584 f(0b0000000001, 24, 15); 2585 // 43210 2586 f(0b00000, 14, 10); 2587 rf(Rm, 5); 2588 rf(Rn, 0); 2589 } else { 2590 blr(Rn); 2591 } 2592 } 2593 2594 void haltsim() { 2595 starti; 2596 f(0b111, 31 ,29); 2597 f(0b00, 28, 27); 2598 // 654321098765432109876543210 2599 f(0b000000000000000000000000000, 26, 0); 2600 } 2601 2602 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2603 } 2604 2605 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr, 2606 Register tmp, 2607 int offset) { 2608 ShouldNotCallThis(); 2609 return RegisterOrConstant(); 2610 } 2611 2612 // Stack overflow checking 2613 virtual void bang_stack_with_offset(int offset); 2614 2615 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm); 2616 static bool operand_valid_for_add_sub_immediate(long imm); 2617 static bool operand_valid_for_float_immediate(double imm); 2618 2619 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 2620 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 2621}; 2622 2623inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a, 2624 Assembler::Membar_mask_bits b) { 2625 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b)); 2626} 2627 2628Instruction_aarch64::~Instruction_aarch64() { 2629 assem->emit(); 2630} 2631 2632#undef starti 2633 2634// Invert a condition 2635inline const Assembler::Condition operator~(const Assembler::Condition cond) { 2636 return Assembler::Condition(int(cond) ^ 1); 2637} 2638 2639class BiasedLockingCounters; 2640 2641extern "C" void das(uint64_t start, int len); 2642 2643#endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP 2644