matcher.hpp revision 196:d1605aabd0a1
1/* 2 * Copyright 1997-2008 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25class Compile; 26class Node; 27class MachNode; 28class MachTypeNode; 29class MachOper; 30 31//---------------------------Matcher------------------------------------------- 32class Matcher : public PhaseTransform { 33 friend class VMStructs; 34 // Private arena of State objects 35 ResourceArea _states_arena; 36 37 VectorSet _visited; // Visit bits 38 39 // Used to control the Label pass 40 VectorSet _shared; // Shared Ideal Node 41 VectorSet _dontcare; // Nothing the matcher cares about 42 43 // Private methods which perform the actual matching and reduction 44 // Walks the label tree, generating machine nodes 45 MachNode *ReduceInst( State *s, int rule, Node *&mem); 46 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); 47 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); 48 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); 49 50 // If this node already matched using "rule", return the MachNode for it. 51 MachNode* find_shared_node(Node* n, uint rule); 52 53 // Convert a dense opcode number to an expanded rule number 54 const int *_reduceOp; 55 const int *_leftOp; 56 const int *_rightOp; 57 58 // Map dense opcode number to info on when rule is swallowed constant. 59 const bool *_swallowed; 60 61 // Map dense rule number to determine if this is an instruction chain rule 62 const uint _begin_inst_chain_rule; 63 const uint _end_inst_chain_rule; 64 65 // We want to clone constants and possible CmpI-variants. 66 // If we do not clone CmpI, then we can have many instances of 67 // condition codes alive at once. This is OK on some chips and 68 // bad on others. Hence the machine-dependent table lookup. 69 const char *_must_clone; 70 71 // Find shared Nodes, or Nodes that otherwise are Matcher roots 72 void find_shared( Node *n ); 73 74 // Debug and profile information for nodes in old space: 75 GrowableArray<Node_Notes*>* _old_node_note_array; 76 77 // Node labeling iterator for instruction selection 78 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); 79 80 Node *transform( Node *dummy ); 81 82 Node_List &_proj_list; // For Machine nodes killing many values 83 84 Node_Array _shared_nodes; 85 86 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots 87 88 // Accessors for the inherited field PhaseTransform::_nodes: 89 void grow_new_node_array(uint idx_limit) { 90 _nodes.map(idx_limit-1, NULL); 91 } 92 bool has_new_node(const Node* n) const { 93 return _nodes.at(n->_idx) != NULL; 94 } 95 Node* new_node(const Node* n) const { 96 assert(has_new_node(n), "set before get"); 97 return _nodes.at(n->_idx); 98 } 99 void set_new_node(const Node* n, Node *nn) { 100 assert(!has_new_node(n), "set only once"); 101 _nodes.map(n->_idx, nn); 102 } 103 104#ifdef ASSERT 105 // Make sure only new nodes are reachable from this node 106 void verify_new_nodes_only(Node* root); 107#endif 108 109public: 110 int LabelRootDepth; 111 static const int base2reg[]; // Map Types to machine register types 112 // Convert ideal machine register to a register mask for spill-loads 113 static const RegMask *idealreg2regmask[]; 114 RegMask *idealreg2spillmask[_last_machine_leaf]; 115 RegMask *idealreg2debugmask[_last_machine_leaf]; 116 void init_spill_mask( Node *ret ); 117 // Convert machine register number to register mask 118 static uint mreg2regmask_max; 119 static RegMask mreg2regmask[]; 120 static RegMask STACK_ONLY_mask; 121 122 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } 123 void set_shared( Node *n ) { _shared.set(n->_idx); } 124 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } 125 void set_visited( Node *n ) { _visited.set(n->_idx); } 126 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } 127 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } 128 129 // Mode bit to tell DFA and expand rules whether we are running after 130 // (or during) register selection. Usually, the matcher runs before, 131 // but it will also get called to generate post-allocation spill code. 132 // In this situation, it is a deadly error to attempt to allocate more 133 // temporary registers. 134 bool _allocation_started; 135 136 // Machine register names 137 static const char *regName[]; 138 // Machine register encodings 139 static const unsigned char _regEncode[]; 140 // Machine Node names 141 const char **_ruleName; 142 // Rules that are cheaper to rematerialize than to spill 143 static const uint _begin_rematerialize; 144 static const uint _end_rematerialize; 145 146 // An array of chars, from 0 to _last_Mach_Reg. 147 // No Save = 'N' (for register windows) 148 // Save on Entry = 'E' 149 // Save on Call = 'C' 150 // Always Save = 'A' (same as SOE + SOC) 151 const char *_register_save_policy; 152 const char *_c_reg_save_policy; 153 // Convert a machine register to a machine register type, so-as to 154 // properly match spill code. 155 const int *_register_save_type; 156 // Maps from machine register to boolean; true if machine register can 157 // be holding a call argument in some signature. 158 static bool can_be_java_arg( int reg ); 159 // Maps from machine register to boolean; true if machine register holds 160 // a spillable argument. 161 static bool is_spillable_arg( int reg ); 162 163 // List of IfFalse or IfTrue Nodes that indicate a taken null test. 164 // List is valid in the post-matching space. 165 Node_List _null_check_tests; 166 void collect_null_checks( Node *proj ); 167 void validate_null_checks( ); 168 169 Matcher( Node_List &proj_list ); 170 171 // Select instructions for entire method 172 void match( ); 173 // Helper for match 174 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); 175 176 // Transform, then walk. Does implicit DCE while walking. 177 // Name changed from "transform" to avoid it being virtual. 178 Node *xform( Node *old_space_node, int Nodes ); 179 180 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 181 MachNode *match_tree( const Node *n ); 182 MachNode *match_sfpt( SafePointNode *sfpt ); 183 // Helper for match_sfpt 184 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); 185 186 // Initialize first stack mask and related masks. 187 void init_first_stack_mask(); 188 189 // If we should save-on-entry this register 190 bool is_save_on_entry( int reg ); 191 192 // Fixup the save-on-entry registers 193 void Fixup_Save_On_Entry( ); 194 195 // --- Frame handling --- 196 197 // Register number of the stack slot corresponding to the incoming SP. 198 // Per the Big Picture in the AD file, it is: 199 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 200 OptoReg::Name _old_SP; 201 202 // Register number of the stack slot corresponding to the highest incoming 203 // argument on the stack. Per the Big Picture in the AD file, it is: 204 // _old_SP + out_preserve_stack_slots + incoming argument size. 205 OptoReg::Name _in_arg_limit; 206 207 // Register number of the stack slot corresponding to the new SP. 208 // Per the Big Picture in the AD file, it is: 209 // _in_arg_limit + pad0 210 OptoReg::Name _new_SP; 211 212 // Register number of the stack slot corresponding to the highest outgoing 213 // argument on the stack. Per the Big Picture in the AD file, it is: 214 // _new_SP + max outgoing arguments of all calls 215 OptoReg::Name _out_arg_limit; 216 217 OptoRegPair *_parm_regs; // Array of machine registers per argument 218 RegMask *_calling_convention_mask; // Array of RegMasks per argument 219 220 // Does matcher support this ideal node? 221 static const bool has_match_rule(int opcode); 222 static const bool _hasMatchRule[_last_opcode]; 223 224 // Used to determine if we have fast l2f conversion 225 // USII has it, USIII doesn't 226 static const bool convL2FSupported(void); 227 228 // Vector width in bytes 229 static const uint vector_width_in_bytes(void); 230 231 // Vector ideal reg 232 static const uint vector_ideal_reg(void); 233 234 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) 235 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). 236 // Depends on the details of 64-bit constant generation on the CPU. 237 static const bool isSimpleConstant64(jlong con); 238 239 // These calls are all generated by the ADLC 240 241 // TRUE - grows up, FALSE - grows down (Intel) 242 virtual bool stack_direction() const; 243 244 // Java-Java calling convention 245 // (what you use when Java calls Java) 246 247 // Alignment of stack in bytes, standard Intel word alignment is 4. 248 // Sparc probably wants at least double-word (8). 249 static uint stack_alignment_in_bytes(); 250 // Alignment of stack, measured in stack slots. 251 // The size of stack slots is defined by VMRegImpl::stack_slot_size. 252 static uint stack_alignment_in_slots() { 253 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); 254 } 255 256 // Array mapping arguments to registers. Argument 0 is usually the 'this' 257 // pointer. Registers can include stack-slots and regular registers. 258 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); 259 260 // Convert a sig into a calling convention register layout 261 // and find interesting things about it. 262 static OptoReg::Name find_receiver( bool is_outgoing ); 263 // Return address register. On Intel it is a stack-slot. On PowerPC 264 // it is the Link register. On Sparc it is r31? 265 virtual OptoReg::Name return_addr() const; 266 RegMask _return_addr_mask; 267 // Return value register. On Intel it is EAX. On Sparc i0/o0. 268 static OptoRegPair return_value(int ideal_reg, bool is_outgoing); 269 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing); 270 RegMask _return_value_mask; 271 // Inline Cache Register 272 static OptoReg::Name inline_cache_reg(); 273 static const RegMask &inline_cache_reg_mask(); 274 static int inline_cache_reg_encode(); 275 276 // Register for DIVI projection of divmodI 277 static RegMask divI_proj_mask(); 278 // Register for MODI projection of divmodI 279 static RegMask modI_proj_mask(); 280 281 // Register for DIVL projection of divmodL 282 static RegMask divL_proj_mask(); 283 // Register for MODL projection of divmodL 284 static RegMask modL_proj_mask(); 285 286 // Java-Interpreter calling convention 287 // (what you use when calling between compiled-Java and Interpreted-Java 288 289 // Number of callee-save + always-save registers 290 // Ignores frame pointer and "special" registers 291 static int number_of_saved_registers(); 292 293 // The Method-klass-holder may be passed in the inline_cache_reg 294 // and then expanded into the inline_cache_reg and a method_oop register 295 296 static OptoReg::Name interpreter_method_oop_reg(); 297 static const RegMask &interpreter_method_oop_reg_mask(); 298 static int interpreter_method_oop_reg_encode(); 299 300 static OptoReg::Name compiler_method_oop_reg(); 301 static const RegMask &compiler_method_oop_reg_mask(); 302 static int compiler_method_oop_reg_encode(); 303 304 // Interpreter's Frame Pointer Register 305 static OptoReg::Name interpreter_frame_pointer_reg(); 306 static const RegMask &interpreter_frame_pointer_reg_mask(); 307 308 // Java-Native calling convention 309 // (what you use when intercalling between Java and C++ code) 310 311 // Array mapping arguments to registers. Argument 0 is usually the 'this' 312 // pointer. Registers can include stack-slots and regular registers. 313 static void c_calling_convention( BasicType*, VMRegPair *, uint ); 314 // Frame pointer. The frame pointer is kept at the base of the stack 315 // and so is probably the stack pointer for most machines. On Intel 316 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 317 OptoReg::Name c_frame_pointer() const; 318 static RegMask c_frame_ptr_mask; 319 320 // !!!!! Special stuff for building ScopeDescs 321 virtual int regnum_to_fpu_offset(int regnum); 322 323 // Is this branch offset small enough to be addressed by a short branch? 324 bool is_short_branch_offset(int offset); 325 326 // Optional scaling for the parameter to the ClearArray/CopyArray node. 327 static const bool init_array_count_is_in_bytes; 328 329 // Threshold small size (in bytes) for a ClearArray/CopyArray node. 330 // Anything this size or smaller may get converted to discrete scalar stores. 331 static const int init_array_short_size; 332 333 // Should the Matcher clone shifts on addressing modes, expecting them to 334 // be subsumed into complex addressing expressions or compute them into 335 // registers? True for Intel but false for most RISCs 336 static const bool clone_shift_expressions; 337 338 // Is it better to copy float constants, or load them directly from memory? 339 // Intel can load a float constant from a direct address, requiring no 340 // extra registers. Most RISCs will have to materialize an address into a 341 // register first, so they may as well materialize the constant immediately. 342 static const bool rematerialize_float_constants; 343 344 // If CPU can load and store mis-aligned doubles directly then no fixup is 345 // needed. Else we split the double into 2 integer pieces and move it 346 // piece-by-piece. Only happens when passing doubles into C code or when 347 // calling i2c adapters as the Java calling convention forces doubles to be 348 // aligned. 349 static const bool misaligned_doubles_ok; 350 351 // Perform a platform dependent implicit null fixup. This is needed 352 // on windows95 to take care of some unusual register constraints. 353 void pd_implicit_null_fixup(MachNode *load, uint idx); 354 355 // Advertise here if the CPU requires explicit rounding operations 356 // to implement the UseStrictFP mode. 357 static const bool strict_fp_requires_explicit_rounding; 358 359 // Do floats take an entire double register or just half? 360 static const bool float_in_double; 361 // Do ints take an entire long register or just half? 362 static const bool int_in_long; 363 364 // This routine is run whenever a graph fails to match. 365 // If it returns, the compiler should bailout to interpreter without error. 366 // In non-product mode, SoftMatchFailure is false to detect non-canonical 367 // graphs. Print a message and exit. 368 static void soft_match_failure() { 369 if( SoftMatchFailure ) return; 370 else { fatal("SoftMatchFailure is not allowed except in product"); } 371 } 372 373 // Used by the DFA in dfa_sparc.cpp. Check for a prior FastLock 374 // acting as an Acquire and thus we don't need an Acquire here. We 375 // retain the Node to act as a compiler ordering barrier. 376 static bool prior_fast_lock( const Node *acq ); 377 378 // Used by the DFA in dfa_sparc.cpp. Check for a following 379 // FastUnLock acting as a Release and thus we don't need a Release 380 // here. We retain the Node to act as a compiler ordering barrier. 381 static bool post_fast_unlock( const Node *rel ); 382 383 // Check for a following volatile memory barrier without an 384 // intervening load and thus we don't need a barrier here. We 385 // retain the Node to act as a compiler ordering barrier. 386 static bool post_store_load_barrier(const Node* mb); 387 388 389#ifdef ASSERT 390 void dump_old2new_map(); // machine-independent to machine-dependent 391#endif 392}; 393