1/* 2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#ifndef SHARE_VM_OPTO_MATCHER_HPP 26#define SHARE_VM_OPTO_MATCHER_HPP 27 28#include "libadt/vectset.hpp" 29#include "memory/resourceArea.hpp" 30#include "opto/node.hpp" 31#include "opto/phaseX.hpp" 32#include "opto/regmask.hpp" 33 34class Compile; 35class Node; 36class MachNode; 37class MachTypeNode; 38class MachOper; 39 40//---------------------------Matcher------------------------------------------- 41class Matcher : public PhaseTransform { 42 friend class VMStructs; 43 44public: 45 46 // State and MStack class used in xform() and find_shared() iterative methods. 47 enum Node_State { Pre_Visit, // node has to be pre-visited 48 Visit, // visit node 49 Post_Visit, // post-visit node 50 Alt_Post_Visit // alternative post-visit path 51 }; 52 53 class MStack: public Node_Stack { 54 public: 55 MStack(int size) : Node_Stack(size) { } 56 57 void push(Node *n, Node_State ns) { 58 Node_Stack::push(n, (uint)ns); 59 } 60 void push(Node *n, Node_State ns, Node *parent, int indx) { 61 ++_inode_top; 62 if ((_inode_top + 1) >= _inode_max) grow(); 63 _inode_top->node = parent; 64 _inode_top->indx = (uint)indx; 65 ++_inode_top; 66 _inode_top->node = n; 67 _inode_top->indx = (uint)ns; 68 } 69 Node *parent() { 70 pop(); 71 return node(); 72 } 73 Node_State state() const { 74 return (Node_State)index(); 75 } 76 void set_state(Node_State ns) { 77 set_index((uint)ns); 78 } 79 }; 80 81private: 82 // Private arena of State objects 83 ResourceArea _states_arena; 84 85 VectorSet _visited; // Visit bits 86 87 // Used to control the Label pass 88 VectorSet _shared; // Shared Ideal Node 89 VectorSet _dontcare; // Nothing the matcher cares about 90 91 // Private methods which perform the actual matching and reduction 92 // Walks the label tree, generating machine nodes 93 MachNode *ReduceInst( State *s, int rule, Node *&mem); 94 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); 95 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); 96 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); 97 98 // If this node already matched using "rule", return the MachNode for it. 99 MachNode* find_shared_node(Node* n, uint rule); 100 101 // Convert a dense opcode number to an expanded rule number 102 const int *_reduceOp; 103 const int *_leftOp; 104 const int *_rightOp; 105 106 // Map dense opcode number to info on when rule is swallowed constant. 107 const bool *_swallowed; 108 109 // Map dense rule number to determine if this is an instruction chain rule 110 const uint _begin_inst_chain_rule; 111 const uint _end_inst_chain_rule; 112 113 // We want to clone constants and possible CmpI-variants. 114 // If we do not clone CmpI, then we can have many instances of 115 // condition codes alive at once. This is OK on some chips and 116 // bad on others. Hence the machine-dependent table lookup. 117 const char *_must_clone; 118 119 // Find shared Nodes, or Nodes that otherwise are Matcher roots 120 void find_shared( Node *n ); 121#ifdef X86 122 bool is_bmi_pattern(Node *n, Node *m); 123#endif 124 125 // Debug and profile information for nodes in old space: 126 GrowableArray<Node_Notes*>* _old_node_note_array; 127 128 // Node labeling iterator for instruction selection 129 Node *Label_Root( const Node *n, State *svec, Node *control, const Node *mem ); 130 131 Node *transform( Node *dummy ); 132 133 Node_List _projection_list; // For Machine nodes killing many values 134 135 Node_Array _shared_nodes; 136 137 debug_only(Node_Array _old2new_map;) // Map roots of ideal-trees to machine-roots 138 debug_only(Node_Array _new2old_map;) // Maps machine nodes back to ideal 139 140 // Accessors for the inherited field PhaseTransform::_nodes: 141 void grow_new_node_array(uint idx_limit) { 142 _nodes.map(idx_limit-1, NULL); 143 } 144 bool has_new_node(const Node* n) const { 145 return _nodes.at(n->_idx) != NULL; 146 } 147 Node* new_node(const Node* n) const { 148 assert(has_new_node(n), "set before get"); 149 return _nodes.at(n->_idx); 150 } 151 void set_new_node(const Node* n, Node *nn) { 152 assert(!has_new_node(n), "set only once"); 153 _nodes.map(n->_idx, nn); 154 } 155 156#ifdef ASSERT 157 // Make sure only new nodes are reachable from this node 158 void verify_new_nodes_only(Node* root); 159 160 Node* _mem_node; // Ideal memory node consumed by mach node 161#endif 162 163 // Mach node for ConP #NULL 164 MachNode* _mach_null; 165 166 void handle_precedence_edges(Node* n, MachNode *mach); 167 168public: 169 int LabelRootDepth; 170 // Convert ideal machine register to a register mask for spill-loads 171 static const RegMask *idealreg2regmask[]; 172 RegMask *idealreg2spillmask [_last_machine_leaf]; 173 RegMask *idealreg2debugmask [_last_machine_leaf]; 174 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; 175 void init_spill_mask( Node *ret ); 176 // Convert machine register number to register mask 177 static uint mreg2regmask_max; 178 static RegMask mreg2regmask[]; 179 static RegMask STACK_ONLY_mask; 180 181 MachNode* mach_null() const { return _mach_null; } 182 183 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } 184 void set_shared( Node *n ) { _shared.set(n->_idx); } 185 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } 186 void set_visited( Node *n ) { _visited.set(n->_idx); } 187 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } 188 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } 189 190 // Mode bit to tell DFA and expand rules whether we are running after 191 // (or during) register selection. Usually, the matcher runs before, 192 // but it will also get called to generate post-allocation spill code. 193 // In this situation, it is a deadly error to attempt to allocate more 194 // temporary registers. 195 bool _allocation_started; 196 197 // Machine register names 198 static const char *regName[]; 199 // Machine register encodings 200 static const unsigned char _regEncode[]; 201 // Machine Node names 202 const char **_ruleName; 203 // Rules that are cheaper to rematerialize than to spill 204 static const uint _begin_rematerialize; 205 static const uint _end_rematerialize; 206 207 // An array of chars, from 0 to _last_Mach_Reg. 208 // No Save = 'N' (for register windows) 209 // Save on Entry = 'E' 210 // Save on Call = 'C' 211 // Always Save = 'A' (same as SOE + SOC) 212 const char *_register_save_policy; 213 const char *_c_reg_save_policy; 214 // Convert a machine register to a machine register type, so-as to 215 // properly match spill code. 216 const int *_register_save_type; 217 // Maps from machine register to boolean; true if machine register can 218 // be holding a call argument in some signature. 219 static bool can_be_java_arg( int reg ); 220 // Maps from machine register to boolean; true if machine register holds 221 // a spillable argument. 222 static bool is_spillable_arg( int reg ); 223 224 // List of IfFalse or IfTrue Nodes that indicate a taken null test. 225 // List is valid in the post-matching space. 226 Node_List _null_check_tests; 227 void collect_null_checks( Node *proj, Node *orig_proj ); 228 void validate_null_checks( ); 229 230 Matcher(); 231 232 // Get a projection node at position pos 233 Node* get_projection(uint pos) { 234 return _projection_list[pos]; 235 } 236 237 // Push a projection node onto the projection list 238 void push_projection(Node* node) { 239 _projection_list.push(node); 240 } 241 242 Node* pop_projection() { 243 return _projection_list.pop(); 244 } 245 246 // Number of nodes in the projection list 247 uint number_of_projections() const { 248 return _projection_list.size(); 249 } 250 251 // Select instructions for entire method 252 void match(); 253 254 // Helper for match 255 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); 256 257 // Transform, then walk. Does implicit DCE while walking. 258 // Name changed from "transform" to avoid it being virtual. 259 Node *xform( Node *old_space_node, int Nodes ); 260 261 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 262 MachNode *match_tree( const Node *n ); 263 MachNode *match_sfpt( SafePointNode *sfpt ); 264 // Helper for match_sfpt 265 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); 266 267 // Initialize first stack mask and related masks. 268 void init_first_stack_mask(); 269 270 // If we should save-on-entry this register 271 bool is_save_on_entry( int reg ); 272 273 // Fixup the save-on-entry registers 274 void Fixup_Save_On_Entry( ); 275 276 // --- Frame handling --- 277 278 // Register number of the stack slot corresponding to the incoming SP. 279 // Per the Big Picture in the AD file, it is: 280 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 281 OptoReg::Name _old_SP; 282 283 // Register number of the stack slot corresponding to the highest incoming 284 // argument on the stack. Per the Big Picture in the AD file, it is: 285 // _old_SP + out_preserve_stack_slots + incoming argument size. 286 OptoReg::Name _in_arg_limit; 287 288 // Register number of the stack slot corresponding to the new SP. 289 // Per the Big Picture in the AD file, it is: 290 // _in_arg_limit + pad0 291 OptoReg::Name _new_SP; 292 293 // Register number of the stack slot corresponding to the highest outgoing 294 // argument on the stack. Per the Big Picture in the AD file, it is: 295 // _new_SP + max outgoing arguments of all calls 296 OptoReg::Name _out_arg_limit; 297 298 OptoRegPair *_parm_regs; // Array of machine registers per argument 299 RegMask *_calling_convention_mask; // Array of RegMasks per argument 300 301 // Does matcher have a match rule for this ideal node? 302 static const bool has_match_rule(int opcode); 303 static const bool _hasMatchRule[_last_opcode]; 304 305 // Does matcher have a match rule for this ideal node and is the 306 // predicate (if there is one) true? 307 // NOTE: If this function is used more commonly in the future, ADLC 308 // should generate this one. 309 static const bool match_rule_supported(int opcode); 310 311 // identify extra cases that we might want to provide match rules for 312 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 313 static const bool match_rule_supported_vector(int opcode, int vlen); 314 315 // Some microarchitectures have mask registers used on vectors 316 static const bool has_predicated_vectors(void); 317 318 // Some uarchs have different sized float register resources 319 static const int float_pressure(int default_pressure_threshold); 320 321 // Used to determine if we have fast l2f conversion 322 // USII has it, USIII doesn't 323 static const bool convL2FSupported(void); 324 325 // Vector width in bytes 326 static const int vector_width_in_bytes(BasicType bt); 327 328 // Limits on vector size (number of elements). 329 static const int max_vector_size(const BasicType bt); 330 static const int min_vector_size(const BasicType bt); 331 static const bool vector_size_supported(const BasicType bt, int size) { 332 return (Matcher::max_vector_size(bt) >= size && 333 Matcher::min_vector_size(bt) <= size); 334 } 335 336 // Vector ideal reg 337 static const uint vector_ideal_reg(int len); 338 static const uint vector_shift_count_ideal_reg(int len); 339 340 // CPU supports misaligned vectors store/load. 341 static const bool misaligned_vectors_ok(); 342 343 // Should original key array reference be passed to AES stubs 344 static const bool pass_original_key_for_aes(); 345 346 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.) 347 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI). 348 // Depends on the details of 64-bit constant generation on the CPU. 349 static const bool isSimpleConstant64(jlong con); 350 351 // These calls are all generated by the ADLC 352 353 // TRUE - grows up, FALSE - grows down (Intel) 354 virtual bool stack_direction() const; 355 356 // Java-Java calling convention 357 // (what you use when Java calls Java) 358 359 // Alignment of stack in bytes, standard Intel word alignment is 4. 360 // Sparc probably wants at least double-word (8). 361 static uint stack_alignment_in_bytes(); 362 // Alignment of stack, measured in stack slots. 363 // The size of stack slots is defined by VMRegImpl::stack_slot_size. 364 static uint stack_alignment_in_slots() { 365 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); 366 } 367 368 // Array mapping arguments to registers. Argument 0 is usually the 'this' 369 // pointer. Registers can include stack-slots and regular registers. 370 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing ); 371 372 // Convert a sig into a calling convention register layout 373 // and find interesting things about it. 374 static OptoReg::Name find_receiver( bool is_outgoing ); 375 // Return address register. On Intel it is a stack-slot. On PowerPC 376 // it is the Link register. On Sparc it is r31? 377 virtual OptoReg::Name return_addr() const; 378 RegMask _return_addr_mask; 379 // Return value register. On Intel it is EAX. On Sparc i0/o0. 380 static OptoRegPair return_value(uint ideal_reg, bool is_outgoing); 381 static OptoRegPair c_return_value(uint ideal_reg, bool is_outgoing); 382 RegMask _return_value_mask; 383 // Inline Cache Register 384 static OptoReg::Name inline_cache_reg(); 385 static int inline_cache_reg_encode(); 386 387 // Register for DIVI projection of divmodI 388 static RegMask divI_proj_mask(); 389 // Register for MODI projection of divmodI 390 static RegMask modI_proj_mask(); 391 392 // Register for DIVL projection of divmodL 393 static RegMask divL_proj_mask(); 394 // Register for MODL projection of divmodL 395 static RegMask modL_proj_mask(); 396 397 // Use hardware DIV instruction when it is faster than 398 // a code which use multiply for division by constant. 399 static bool use_asm_for_ldiv_by_con( jlong divisor ); 400 401 static const RegMask method_handle_invoke_SP_save_mask(); 402 403 // Java-Interpreter calling convention 404 // (what you use when calling between compiled-Java and Interpreted-Java 405 406 // Number of callee-save + always-save registers 407 // Ignores frame pointer and "special" registers 408 static int number_of_saved_registers(); 409 410 // The Method-klass-holder may be passed in the inline_cache_reg 411 // and then expanded into the inline_cache_reg and a method_oop register 412 413 static OptoReg::Name interpreter_method_oop_reg(); 414 static int interpreter_method_oop_reg_encode(); 415 416 static OptoReg::Name compiler_method_oop_reg(); 417 static const RegMask &compiler_method_oop_reg_mask(); 418 static int compiler_method_oop_reg_encode(); 419 420 // Interpreter's Frame Pointer Register 421 static OptoReg::Name interpreter_frame_pointer_reg(); 422 423 // Java-Native calling convention 424 // (what you use when intercalling between Java and C++ code) 425 426 // Array mapping arguments to registers. Argument 0 is usually the 'this' 427 // pointer. Registers can include stack-slots and regular registers. 428 static void c_calling_convention( BasicType*, VMRegPair *, uint ); 429 // Frame pointer. The frame pointer is kept at the base of the stack 430 // and so is probably the stack pointer for most machines. On Intel 431 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 432 OptoReg::Name c_frame_pointer() const; 433 static RegMask c_frame_ptr_mask; 434 435 // !!!!! Special stuff for building ScopeDescs 436 virtual int regnum_to_fpu_offset(int regnum); 437 438 // Is this branch offset small enough to be addressed by a short branch? 439 bool is_short_branch_offset(int rule, int br_size, int offset); 440 441 // Optional scaling for the parameter to the ClearArray/CopyArray node. 442 static const bool init_array_count_is_in_bytes; 443 444 // Some hardware needs 2 CMOV's for longs. 445 static const int long_cmove_cost(); 446 447 // Some hardware have expensive CMOV for float and double. 448 static const int float_cmove_cost(); 449 450 // Should the Matcher clone shifts on addressing modes, expecting them to 451 // be subsumed into complex addressing expressions or compute them into 452 // registers? True for Intel but false for most RISCs 453 bool clone_address_expressions(AddPNode* m, MStack& mstack, VectorSet& address_visited); 454 // Clone base + offset address expression 455 bool clone_base_plus_offset_address(AddPNode* m, MStack& mstack, VectorSet& address_visited); 456 457 static bool narrow_oop_use_complex_address(); 458 static bool narrow_klass_use_complex_address(); 459 460 static bool const_oop_prefer_decode(); 461 static bool const_klass_prefer_decode(); 462 463 // Generate implicit null check for narrow oops if it can fold 464 // into address expression (x64). 465 // 466 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression 467 // NullCheck narrow_oop_reg 468 // 469 // When narrow oops can't fold into address expression (Sparc) and 470 // base is not null use decode_not_null and normal implicit null check. 471 // Note, decode_not_null node can be used here since it is referenced 472 // only on non null path but it requires special handling, see 473 // collect_null_checks(): 474 // 475 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' 476 // [oop_reg + offset] 477 // NullCheck oop_reg 478 // 479 // With Zero base and when narrow oops can not fold into address 480 // expression use normal implicit null check since only shift 481 // is needed to decode narrow oop. 482 // 483 // decode narrow_oop_reg, oop_reg // only 'shift' 484 // [oop_reg + offset] 485 // NullCheck oop_reg 486 // 487 inline static bool gen_narrow_oop_implicit_null_checks() { 488 // Advice matcher to perform null checks on the narrow oop side. 489 // Implicit checks are not possible on the uncompressed oop side anyway 490 // (at least not for read accesses). 491 // Performs significantly better (especially on Power 6). 492 if (!os::zero_page_read_protected()) { 493 return true; 494 } 495 return Universe::narrow_oop_use_implicit_null_checks() && 496 (narrow_oop_use_complex_address() || 497 Universe::narrow_oop_base() != NULL); 498 } 499 500 // Is it better to copy float constants, or load them directly from memory? 501 // Intel can load a float constant from a direct address, requiring no 502 // extra registers. Most RISCs will have to materialize an address into a 503 // register first, so they may as well materialize the constant immediately. 504 static const bool rematerialize_float_constants; 505 506 // If CPU can load and store mis-aligned doubles directly then no fixup is 507 // needed. Else we split the double into 2 integer pieces and move it 508 // piece-by-piece. Only happens when passing doubles into C code or when 509 // calling i2c adapters as the Java calling convention forces doubles to be 510 // aligned. 511 static const bool misaligned_doubles_ok; 512 513 // Does the CPU require postalloc expand (see block.cpp for description of 514 // postalloc expand)? 515 static const bool require_postalloc_expand; 516 517 // Perform a platform dependent implicit null fixup. This is needed 518 // on windows95 to take care of some unusual register constraints. 519 void pd_implicit_null_fixup(MachNode *load, uint idx); 520 521 // Advertise here if the CPU requires explicit rounding operations 522 // to implement the UseStrictFP mode. 523 static const bool strict_fp_requires_explicit_rounding; 524 525 // Are floats conerted to double when stored to stack during deoptimization? 526 static bool float_in_double(); 527 // Do ints take an entire long register or just half? 528 static const bool int_in_long; 529 530 // Do the processor's shift instructions only use the low 5/6 bits 531 // of the count for 32/64 bit ints? If not we need to do the masking 532 // ourselves. 533 static const bool need_masked_shift_count; 534 535 // Whether code generation need accurate ConvI2L types. 536 static const bool convi2l_type_required; 537 538 // This routine is run whenever a graph fails to match. 539 // If it returns, the compiler should bailout to interpreter without error. 540 // In non-product mode, SoftMatchFailure is false to detect non-canonical 541 // graphs. Print a message and exit. 542 static void soft_match_failure() { 543 if( SoftMatchFailure ) return; 544 else { fatal("SoftMatchFailure is not allowed except in product"); } 545 } 546 547 // Check for a following volatile memory barrier without an 548 // intervening load and thus we don't need a barrier here. We 549 // retain the Node to act as a compiler ordering barrier. 550 static bool post_store_load_barrier(const Node* mb); 551 552 // Does n lead to an uncommon trap that can cause deoptimization? 553 static bool branches_to_uncommon_trap(const Node *n); 554 555#ifdef ASSERT 556 void dump_old2new_map(); // machine-independent to machine-dependent 557 558 Node* find_old_node(Node* new_node) { 559 return _new2old_map[new_node->_idx]; 560 } 561#endif 562}; 563 564#endif // SHARE_VM_OPTO_MATCHER_HPP 565