1/* 2 * Copyright (c) 2003, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#ifndef OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP 26#define OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP 27 28#include <intrin.h> 29#include "runtime/atomic.hpp" 30#include "runtime/orderAccess.hpp" 31#include "runtime/os.hpp" 32 33// Compiler version last used for testing: Microsoft Visual Studio 2010 34// Please update this information when this file changes 35 36// Implementation of class OrderAccess. 37 38// A compiler barrier, forcing the C++ compiler to invalidate all memory assumptions 39inline void compiler_barrier() { 40 _ReadWriteBarrier(); 41} 42 43// Note that in MSVC, volatile memory accesses are explicitly 44// guaranteed to have acquire release semantics (w.r.t. compiler 45// reordering) and therefore does not even need a compiler barrier 46// for normal acquire release accesses. And all generalized 47// bound calls like release_store go through OrderAccess::load 48// and OrderAccess::store which do volatile memory accesses. 49template<> inline void ScopedFence<X_ACQUIRE>::postfix() { } 50template<> inline void ScopedFence<RELEASE_X>::prefix() { } 51template<> inline void ScopedFence<RELEASE_X_FENCE>::prefix() { } 52template<> inline void ScopedFence<RELEASE_X_FENCE>::postfix() { OrderAccess::fence(); } 53 54inline void OrderAccess::loadload() { compiler_barrier(); } 55inline void OrderAccess::storestore() { compiler_barrier(); } 56inline void OrderAccess::loadstore() { compiler_barrier(); } 57inline void OrderAccess::storeload() { fence(); } 58 59inline void OrderAccess::acquire() { compiler_barrier(); } 60inline void OrderAccess::release() { compiler_barrier(); } 61 62inline void OrderAccess::fence() { 63#ifdef AMD64 64 StubRoutines_fence(); 65#else 66 if (os::is_MP()) { 67 __asm { 68 lock add dword ptr [esp], 0; 69 } 70 } 71#endif // AMD64 72 compiler_barrier(); 73} 74 75#ifndef AMD64 76template<> 77inline void OrderAccess::specialized_release_store_fence<jbyte> (volatile jbyte* p, jbyte v) { 78 __asm { 79 mov edx, p; 80 mov al, v; 81 xchg al, byte ptr [edx]; 82 } 83} 84 85template<> 86inline void OrderAccess::specialized_release_store_fence<jshort>(volatile jshort* p, jshort v) { 87 __asm { 88 mov edx, p; 89 mov ax, v; 90 xchg ax, word ptr [edx]; 91 } 92} 93 94template<> 95inline void OrderAccess::specialized_release_store_fence<jint> (volatile jint* p, jint v) { 96 __asm { 97 mov edx, p; 98 mov eax, v; 99 xchg eax, dword ptr [edx]; 100 } 101} 102#endif // AMD64 103 104template<> 105inline void OrderAccess::specialized_release_store_fence<jfloat>(volatile jfloat* p, jfloat v) { 106 release_store_fence((volatile jint*)p, jint_cast(v)); 107} 108template<> 109inline void OrderAccess::specialized_release_store_fence<jdouble>(volatile jdouble* p, jdouble v) { 110 release_store_fence((volatile jlong*)p, jlong_cast(v)); 111} 112 113#define VM_HAS_GENERALIZED_ORDER_ACCESS 1 114 115#endif // OS_CPU_WINDOWS_X86_VM_ORDERACCESS_WINDOWS_X86_INLINE_HPP 116