vm_version_x86.hpp revision 6178:8867fec28aa1
1/* 2 * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#ifndef CPU_X86_VM_VM_VERSION_X86_HPP 26#define CPU_X86_VM_VM_VERSION_X86_HPP 27 28#include "runtime/globals_extension.hpp" 29#include "runtime/vm_version.hpp" 30 31class VM_Version : public Abstract_VM_Version { 32public: 33 // cpuid result register layouts. These are all unions of a uint32_t 34 // (in case anyone wants access to the register as a whole) and a bitfield. 35 36 union StdCpuid1Eax { 37 uint32_t value; 38 struct { 39 uint32_t stepping : 4, 40 model : 4, 41 family : 4, 42 proc_type : 2, 43 : 2, 44 ext_model : 4, 45 ext_family : 8, 46 : 4; 47 } bits; 48 }; 49 50 union StdCpuid1Ebx { // example, unused 51 uint32_t value; 52 struct { 53 uint32_t brand_id : 8, 54 clflush_size : 8, 55 threads_per_cpu : 8, 56 apic_id : 8; 57 } bits; 58 }; 59 60 union StdCpuid1Ecx { 61 uint32_t value; 62 struct { 63 uint32_t sse3 : 1, 64 clmul : 1, 65 : 1, 66 monitor : 1, 67 : 1, 68 vmx : 1, 69 : 1, 70 est : 1, 71 : 1, 72 ssse3 : 1, 73 cid : 1, 74 : 2, 75 cmpxchg16: 1, 76 : 4, 77 dca : 1, 78 sse4_1 : 1, 79 sse4_2 : 1, 80 : 2, 81 popcnt : 1, 82 : 1, 83 aes : 1, 84 : 1, 85 osxsave : 1, 86 avx : 1, 87 : 3; 88 } bits; 89 }; 90 91 union StdCpuid1Edx { 92 uint32_t value; 93 struct { 94 uint32_t : 4, 95 tsc : 1, 96 : 3, 97 cmpxchg8 : 1, 98 : 6, 99 cmov : 1, 100 : 3, 101 clflush : 1, 102 : 3, 103 mmx : 1, 104 fxsr : 1, 105 sse : 1, 106 sse2 : 1, 107 : 1, 108 ht : 1, 109 : 3; 110 } bits; 111 }; 112 113 union DcpCpuid4Eax { 114 uint32_t value; 115 struct { 116 uint32_t cache_type : 5, 117 : 21, 118 cores_per_cpu : 6; 119 } bits; 120 }; 121 122 union DcpCpuid4Ebx { 123 uint32_t value; 124 struct { 125 uint32_t L1_line_size : 12, 126 partitions : 10, 127 associativity : 10; 128 } bits; 129 }; 130 131 union TplCpuidBEbx { 132 uint32_t value; 133 struct { 134 uint32_t logical_cpus : 16, 135 : 16; 136 } bits; 137 }; 138 139 union ExtCpuid1Ecx { 140 uint32_t value; 141 struct { 142 uint32_t LahfSahf : 1, 143 CmpLegacy : 1, 144 : 3, 145 lzcnt_intel : 1, 146 lzcnt : 1, 147 sse4a : 1, 148 misalignsse : 1, 149 prefetchw : 1, 150 : 22; 151 } bits; 152 }; 153 154 union ExtCpuid1Edx { 155 uint32_t value; 156 struct { 157 uint32_t : 22, 158 mmx_amd : 1, 159 mmx : 1, 160 fxsr : 1, 161 : 4, 162 long_mode : 1, 163 tdnow2 : 1, 164 tdnow : 1; 165 } bits; 166 }; 167 168 union ExtCpuid5Ex { 169 uint32_t value; 170 struct { 171 uint32_t L1_line_size : 8, 172 L1_tag_lines : 8, 173 L1_assoc : 8, 174 L1_size : 8; 175 } bits; 176 }; 177 178 union ExtCpuid7Edx { 179 uint32_t value; 180 struct { 181 uint32_t : 8, 182 tsc_invariance : 1, 183 : 23; 184 } bits; 185 }; 186 187 union ExtCpuid8Ecx { 188 uint32_t value; 189 struct { 190 uint32_t cores_per_cpu : 8, 191 : 24; 192 } bits; 193 }; 194 195 union SefCpuid7Eax { 196 uint32_t value; 197 }; 198 199 union SefCpuid7Ebx { 200 uint32_t value; 201 struct { 202 uint32_t fsgsbase : 1, 203 : 2, 204 bmi1 : 1, 205 : 1, 206 avx2 : 1, 207 : 2, 208 bmi2 : 1, 209 erms : 1, 210 : 22; 211 } bits; 212 }; 213 214 union XemXcr0Eax { 215 uint32_t value; 216 struct { 217 uint32_t x87 : 1, 218 sse : 1, 219 ymm : 1, 220 : 29; 221 } bits; 222 }; 223 224protected: 225 static int _cpu; 226 static int _model; 227 static int _stepping; 228 static int _cpuFeatures; // features returned by the "cpuid" instruction 229 // 0 if this instruction is not available 230 static const char* _features_str; 231 232 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 233 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 234 235 enum { 236 CPU_CX8 = (1 << 0), // next bits are from cpuid 1 (EDX) 237 CPU_CMOV = (1 << 1), 238 CPU_FXSR = (1 << 2), 239 CPU_HT = (1 << 3), 240 CPU_MMX = (1 << 4), 241 CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions 242 // may not necessarily support other 3dnow instructions 243 CPU_SSE = (1 << 6), 244 CPU_SSE2 = (1 << 7), 245 CPU_SSE3 = (1 << 8), // SSE3 comes from cpuid 1 (ECX) 246 CPU_SSSE3 = (1 << 9), 247 CPU_SSE4A = (1 << 10), 248 CPU_SSE4_1 = (1 << 11), 249 CPU_SSE4_2 = (1 << 12), 250 CPU_POPCNT = (1 << 13), 251 CPU_LZCNT = (1 << 14), 252 CPU_TSC = (1 << 15), 253 CPU_TSCINV = (1 << 16), 254 CPU_AVX = (1 << 17), 255 CPU_AVX2 = (1 << 18), 256 CPU_AES = (1 << 19), 257 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions 258 CPU_CLMUL = (1 << 21), // carryless multiply for CRC 259 CPU_BMI1 = (1 << 22), 260 CPU_BMI2 = (1 << 23) 261 } cpuFeatureFlags; 262 263 enum { 264 // AMD 265 CPU_FAMILY_AMD_11H = 0x11, 266 // Intel 267 CPU_FAMILY_INTEL_CORE = 6, 268 CPU_MODEL_NEHALEM = 0x1e, 269 CPU_MODEL_NEHALEM_EP = 0x1a, 270 CPU_MODEL_NEHALEM_EX = 0x2e, 271 CPU_MODEL_WESTMERE = 0x25, 272 CPU_MODEL_WESTMERE_EP = 0x2c, 273 CPU_MODEL_WESTMERE_EX = 0x2f, 274 CPU_MODEL_SANDYBRIDGE = 0x2a, 275 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 276 CPU_MODEL_IVYBRIDGE_EP = 0x3a 277 } cpuExtendedFamily; 278 279 // cpuid information block. All info derived from executing cpuid with 280 // various function numbers is stored here. Intel and AMD info is 281 // merged in this block: accessor methods disentangle it. 282 // 283 // The info block is laid out in subblocks of 4 dwords corresponding to 284 // eax, ebx, ecx and edx, whether or not they contain anything useful. 285 struct CpuidInfo { 286 // cpuid function 0 287 uint32_t std_max_function; 288 uint32_t std_vendor_name_0; 289 uint32_t std_vendor_name_1; 290 uint32_t std_vendor_name_2; 291 292 // cpuid function 1 293 StdCpuid1Eax std_cpuid1_eax; 294 StdCpuid1Ebx std_cpuid1_ebx; 295 StdCpuid1Ecx std_cpuid1_ecx; 296 StdCpuid1Edx std_cpuid1_edx; 297 298 // cpuid function 4 (deterministic cache parameters) 299 DcpCpuid4Eax dcp_cpuid4_eax; 300 DcpCpuid4Ebx dcp_cpuid4_ebx; 301 uint32_t dcp_cpuid4_ecx; // unused currently 302 uint32_t dcp_cpuid4_edx; // unused currently 303 304 // cpuid function 7 (structured extended features) 305 SefCpuid7Eax sef_cpuid7_eax; 306 SefCpuid7Ebx sef_cpuid7_ebx; 307 uint32_t sef_cpuid7_ecx; // unused currently 308 uint32_t sef_cpuid7_edx; // unused currently 309 310 // cpuid function 0xB (processor topology) 311 // ecx = 0 312 uint32_t tpl_cpuidB0_eax; 313 TplCpuidBEbx tpl_cpuidB0_ebx; 314 uint32_t tpl_cpuidB0_ecx; // unused currently 315 uint32_t tpl_cpuidB0_edx; // unused currently 316 317 // ecx = 1 318 uint32_t tpl_cpuidB1_eax; 319 TplCpuidBEbx tpl_cpuidB1_ebx; 320 uint32_t tpl_cpuidB1_ecx; // unused currently 321 uint32_t tpl_cpuidB1_edx; // unused currently 322 323 // ecx = 2 324 uint32_t tpl_cpuidB2_eax; 325 TplCpuidBEbx tpl_cpuidB2_ebx; 326 uint32_t tpl_cpuidB2_ecx; // unused currently 327 uint32_t tpl_cpuidB2_edx; // unused currently 328 329 // cpuid function 0x80000000 // example, unused 330 uint32_t ext_max_function; 331 uint32_t ext_vendor_name_0; 332 uint32_t ext_vendor_name_1; 333 uint32_t ext_vendor_name_2; 334 335 // cpuid function 0x80000001 336 uint32_t ext_cpuid1_eax; // reserved 337 uint32_t ext_cpuid1_ebx; // reserved 338 ExtCpuid1Ecx ext_cpuid1_ecx; 339 ExtCpuid1Edx ext_cpuid1_edx; 340 341 // cpuid functions 0x80000002 thru 0x80000004: example, unused 342 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 343 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 344 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 345 346 // cpuid function 0x80000005 // AMD L1, Intel reserved 347 uint32_t ext_cpuid5_eax; // unused currently 348 uint32_t ext_cpuid5_ebx; // reserved 349 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 350 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 351 352 // cpuid function 0x80000007 353 uint32_t ext_cpuid7_eax; // reserved 354 uint32_t ext_cpuid7_ebx; // reserved 355 uint32_t ext_cpuid7_ecx; // reserved 356 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 357 358 // cpuid function 0x80000008 359 uint32_t ext_cpuid8_eax; // unused currently 360 uint32_t ext_cpuid8_ebx; // reserved 361 ExtCpuid8Ecx ext_cpuid8_ecx; 362 uint32_t ext_cpuid8_edx; // reserved 363 364 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 365 XemXcr0Eax xem_xcr0_eax; 366 uint32_t xem_xcr0_edx; // reserved 367 368 // Space to save ymm registers after signal handle 369 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 370 }; 371 372 // The actual cpuid info block 373 static CpuidInfo _cpuid_info; 374 375 // Extractors and predicates 376 static uint32_t extended_cpu_family() { 377 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family; 378 result += _cpuid_info.std_cpuid1_eax.bits.ext_family; 379 return result; 380 } 381 382 static uint32_t extended_cpu_model() { 383 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model; 384 result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4; 385 return result; 386 } 387 388 static uint32_t cpu_stepping() { 389 uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping; 390 return result; 391 } 392 393 static uint logical_processor_count() { 394 uint result = threads_per_core(); 395 return result; 396 } 397 398 static uint32_t feature_flags() { 399 uint32_t result = 0; 400 if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0) 401 result |= CPU_CX8; 402 if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0) 403 result |= CPU_CMOV; 404 if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() && 405 _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0)) 406 result |= CPU_FXSR; 407 // HT flag is set for multi-core processors also. 408 if (threads_per_core() > 1) 409 result |= CPU_HT; 410 if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() && 411 _cpuid_info.ext_cpuid1_edx.bits.mmx != 0)) 412 result |= CPU_MMX; 413 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0) 414 result |= CPU_SSE; 415 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0) 416 result |= CPU_SSE2; 417 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0) 418 result |= CPU_SSE3; 419 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0) 420 result |= CPU_SSSE3; 421 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0) 422 result |= CPU_SSE4_1; 423 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0) 424 result |= CPU_SSE4_2; 425 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0) 426 result |= CPU_POPCNT; 427 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 && 428 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 && 429 _cpuid_info.xem_xcr0_eax.bits.sse != 0 && 430 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) { 431 result |= CPU_AVX; 432 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0) 433 result |= CPU_AVX2; 434 } 435 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0) 436 result |= CPU_BMI1; 437 if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0) 438 result |= CPU_TSC; 439 if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0) 440 result |= CPU_TSCINV; 441 if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0) 442 result |= CPU_AES; 443 if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0) 444 result |= CPU_ERMS; 445 if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0) 446 result |= CPU_CLMUL; 447 448 // AMD features. 449 if (is_amd()) { 450 if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) || 451 (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0)) 452 result |= CPU_3DNOW_PREFETCH; 453 if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0) 454 result |= CPU_LZCNT; 455 if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0) 456 result |= CPU_SSE4A; 457 } 458 // Intel features. 459 if(is_intel()) { 460 if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0) 461 result |= CPU_BMI2; 462 if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0) 463 result |= CPU_LZCNT; 464 } 465 466 return result; 467 } 468 469 static bool os_supports_avx_vectors() { 470 if (!supports_avx()) { 471 return false; 472 } 473 // Verify that OS save/restore all bits of AVX registers 474 // during signal processing. 475 int nreg = 2 LP64_ONLY(+2); 476 for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register 477 if (_cpuid_info.ymm_save[i] != ymm_test_value()) { 478 return false; 479 } 480 } 481 return true; 482 } 483 484 static void get_processor_features(); 485 486public: 487 // Offsets for cpuid asm stub 488 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 489 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 490 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 491 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 492 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 493 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 494 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 495 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 496 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 497 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 498 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 499 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 500 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 501 502 // The value used to check ymm register after signal handle 503 static int ymm_test_value() { return 0xCAFEBABE; } 504 505 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 506 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 507 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 508 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 509 510 static void clean_cpuFeatures() { _cpuFeatures = 0; } 511 static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); } 512 513 514 // Initialization 515 static void initialize(); 516 517 // Asserts 518 static void assert_is_initialized() { 519 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 520 } 521 522 // 523 // Processor family: 524 // 3 - 386 525 // 4 - 486 526 // 5 - Pentium 527 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 528 // Pentium M, Core Solo, Core Duo, Core2 Duo 529 // family 6 model: 9, 13, 14, 15 530 // 0x0f - Pentium 4, Opteron 531 // 532 // Note: The cpu family should be used to select between 533 // instruction sequences which are valid on all Intel 534 // processors. Use the feature test functions below to 535 // determine whether a particular instruction is supported. 536 // 537 static int cpu_family() { return _cpu;} 538 static bool is_P6() { return cpu_family() >= 6; } 539 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 540 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 541 542 static bool supports_processor_topology() { 543 return (_cpuid_info.std_max_function >= 0xB) && 544 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 545 // Some cpus have max cpuid >= 0xB but do not support processor topology. 546 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 547 } 548 549 static uint cores_per_cpu() { 550 uint result = 1; 551 if (is_intel()) { 552 if (supports_processor_topology()) { 553 result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus / 554 _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 555 } else { 556 result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1); 557 } 558 } else if (is_amd()) { 559 result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1); 560 } 561 return result; 562 } 563 564 static uint threads_per_core() { 565 uint result = 1; 566 if (is_intel() && supports_processor_topology()) { 567 result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus; 568 } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) { 569 result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu / 570 cores_per_cpu(); 571 } 572 return result; 573 } 574 575 static intx prefetch_data_size() { 576 intx result = 0; 577 if (is_intel()) { 578 result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1); 579 } else if (is_amd()) { 580 result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size; 581 } 582 if (result < 32) // not defined ? 583 result = 32; // 32 bytes by default on x86 and other x64 584 return result; 585 } 586 587 // 588 // Feature identification 589 // 590 static bool supports_cpuid() { return _cpuFeatures != 0; } 591 static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; } 592 static bool supports_cmov() { return (_cpuFeatures & CPU_CMOV) != 0; } 593 static bool supports_fxsr() { return (_cpuFeatures & CPU_FXSR) != 0; } 594 static bool supports_ht() { return (_cpuFeatures & CPU_HT) != 0; } 595 static bool supports_mmx() { return (_cpuFeatures & CPU_MMX) != 0; } 596 static bool supports_sse() { return (_cpuFeatures & CPU_SSE) != 0; } 597 static bool supports_sse2() { return (_cpuFeatures & CPU_SSE2) != 0; } 598 static bool supports_sse3() { return (_cpuFeatures & CPU_SSE3) != 0; } 599 static bool supports_ssse3() { return (_cpuFeatures & CPU_SSSE3)!= 0; } 600 static bool supports_sse4_1() { return (_cpuFeatures & CPU_SSE4_1) != 0; } 601 static bool supports_sse4_2() { return (_cpuFeatures & CPU_SSE4_2) != 0; } 602 static bool supports_popcnt() { return (_cpuFeatures & CPU_POPCNT) != 0; } 603 static bool supports_avx() { return (_cpuFeatures & CPU_AVX) != 0; } 604 static bool supports_avx2() { return (_cpuFeatures & CPU_AVX2) != 0; } 605 static bool supports_tsc() { return (_cpuFeatures & CPU_TSC) != 0; } 606 static bool supports_aes() { return (_cpuFeatures & CPU_AES) != 0; } 607 static bool supports_erms() { return (_cpuFeatures & CPU_ERMS) != 0; } 608 static bool supports_clmul() { return (_cpuFeatures & CPU_CLMUL) != 0; } 609 static bool supports_bmi1() { return (_cpuFeatures & CPU_BMI1) != 0; } 610 static bool supports_bmi2() { return (_cpuFeatures & CPU_BMI2) != 0; } 611 // Intel features 612 static bool is_intel_family_core() { return is_intel() && 613 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 614 615 static bool is_intel_tsc_synched_at_init() { 616 if (is_intel_family_core()) { 617 uint32_t ext_model = extended_cpu_model(); 618 if (ext_model == CPU_MODEL_NEHALEM_EP || 619 ext_model == CPU_MODEL_WESTMERE_EP || 620 ext_model == CPU_MODEL_SANDYBRIDGE_EP || 621 ext_model == CPU_MODEL_IVYBRIDGE_EP) { 622 // <= 2-socket invariant tsc support. EX versions are usually used 623 // in > 2-socket systems and likely don't synchronize tscs at 624 // initialization. 625 // Code that uses tsc values must be prepared for them to arbitrarily 626 // jump forward or backward. 627 return true; 628 } 629 } 630 return false; 631 } 632 633 // AMD features 634 static bool supports_3dnow_prefetch() { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; } 635 static bool supports_mmx_ext() { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; } 636 static bool supports_lzcnt() { return (_cpuFeatures & CPU_LZCNT) != 0; } 637 static bool supports_sse4a() { return (_cpuFeatures & CPU_SSE4A) != 0; } 638 639 static bool is_amd_Barcelona() { return is_amd() && 640 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 641 642 // Intel and AMD newer cores support fast timestamps well 643 static bool supports_tscinv_bit() { 644 return (_cpuFeatures & CPU_TSCINV) != 0; 645 } 646 static bool supports_tscinv() { 647 return supports_tscinv_bit() && 648 ( (is_amd() && !is_amd_Barcelona()) || 649 is_intel_tsc_synched_at_init() ); 650 } 651 652 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 653 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 654 supports_sse3() && _model != 0x1C; } 655 656 static bool supports_compare_and_exchange() { return true; } 657 658 static const char* cpu_features() { return _features_str; } 659 660 static intx allocate_prefetch_distance() { 661 // This method should be called before allocate_prefetch_style(). 662 // 663 // Hardware prefetching (distance/size in bytes): 664 // Pentium 3 - 64 / 32 665 // Pentium 4 - 256 / 128 666 // Athlon - 64 / 32 ???? 667 // Opteron - 128 / 64 only when 2 sequential cache lines accessed 668 // Core - 128 / 64 669 // 670 // Software prefetching (distance in bytes / instruction with best score): 671 // Pentium 3 - 128 / prefetchnta 672 // Pentium 4 - 512 / prefetchnta 673 // Athlon - 128 / prefetchnta 674 // Opteron - 256 / prefetchnta 675 // Core - 256 / prefetchnta 676 // It will be used only when AllocatePrefetchStyle > 0 677 678 intx count = AllocatePrefetchDistance; 679 if (count < 0) { // default ? 680 if (is_amd()) { // AMD 681 if (supports_sse2()) 682 count = 256; // Opteron 683 else 684 count = 128; // Athlon 685 } else { // Intel 686 if (supports_sse2()) 687 if (cpu_family() == 6) { 688 count = 256; // Pentium M, Core, Core2 689 } else { 690 count = 512; // Pentium 4 691 } 692 else 693 count = 128; // Pentium 3 (and all other old CPUs) 694 } 695 } 696 return count; 697 } 698 static intx allocate_prefetch_style() { 699 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 700 // Return 0 if AllocatePrefetchDistance was not defined. 701 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0; 702 } 703 704 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from 705 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap. 706 // Tested intervals from 128 to 2048 in increments of 64 == one cache line. 707 // 256 bytes (4 dcache lines) was the nearest runner-up to 576. 708 709 // gc copy/scan is disabled if prefetchw isn't supported, because 710 // Prefetch::write emits an inlined prefetchw on Linux. 711 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t. 712 // The used prefetcht0 instruction works for both amd64 and em64t. 713 static intx prefetch_copy_interval_in_bytes() { 714 intx interval = PrefetchCopyIntervalInBytes; 715 return interval >= 0 ? interval : 576; 716 } 717 static intx prefetch_scan_interval_in_bytes() { 718 intx interval = PrefetchScanIntervalInBytes; 719 return interval >= 0 ? interval : 576; 720 } 721 static intx prefetch_fields_ahead() { 722 intx count = PrefetchFieldsAhead; 723 return count >= 0 ? count : 1; 724 } 725}; 726 727#endif // CPU_X86_VM_VM_VERSION_X86_HPP 728