sparc.ad revision 2614:95134e034042
1// 2// Copyright (c) 1998, 2011, Oracle and/or its affiliates. All rights reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20// or visit www.oracle.com if you need additional information or have any 21// questions. 22// 23// 24 25// SPARC Architecture Description File 26 27//----------REGISTER DEFINITION BLOCK------------------------------------------ 28// This information is used by the matcher and the register allocator to 29// describe individual registers and classes of registers within the target 30// archtecture. 31register %{ 32//----------Architecture Description Register Definitions---------------------- 33// General Registers 34// "reg_def" name ( register save type, C convention save type, 35// ideal register type, encoding, vm name ); 36// Register Save Types: 37// 38// NS = No-Save: The register allocator assumes that these registers 39// can be used without saving upon entry to the method, & 40// that they do not need to be saved at call sites. 41// 42// SOC = Save-On-Call: The register allocator assumes that these registers 43// can be used without saving upon entry to the method, 44// but that they must be saved at call sites. 45// 46// SOE = Save-On-Entry: The register allocator assumes that these registers 47// must be saved before using them upon entry to the 48// method, but they do not need to be saved at call 49// sites. 50// 51// AS = Always-Save: The register allocator assumes that these registers 52// must be saved before using them upon entry to the 53// method, & that they must be saved at call sites. 54// 55// Ideal Register Type is used to determine how to save & restore a 56// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58// 59// The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62// ---------------------------- 63// Integer/Long Registers 64// ---------------------------- 65 66// Need to expose the hi/lo aspect of 64-bit registers 67// This register set is used for both the 64-bit build and 68// the 32-bit build with 1-register longs. 69 70// Global Registers 0-7 71reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88// Output Registers 0-7 89reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106// Local Registers 0-7 107reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124// Input Registers 0-7 125reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142// ---------------------------- 143// Float/Double Registers 144// ---------------------------- 145 146// Float Registers 147reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180// Double Registers 181// The rules of ADL require that double registers be defined in pairs. 182// Each pair must be two 32-bit values, but not necessarily a pair of 183// single float registers. In each pair, ADLC-assigned register numbers 184// must be adjacent, with the lower number even. Finally, when the 185// CPU stores such a register pair to memory, the word associated with 186// the lower ADLC-assigned number must be stored to the lower address. 187 188// These definitions specify the actual bit encodings of the sparc 189// double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190// wants 0-63, so we have to convert every time we want to use fp regs 191// with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192// 255 is a flag meaning "don't go here". 193// I believe we can't handle callee-save doubles D32 and up until 194// the place in the sparc stack crawler that asserts on the 255 is 195// fixed up. 196reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230// ---------------------------- 231// Special Registers 232// Condition Codes Flag Registers 233// I tried to break out ICC and XCC but it's not very pretty. 234// Every Sparc instruction which defs/kills one also kills the other. 235// Hence every compare instruction which defs one kind of flags ends 236// up needing a kill of the other. 237reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244// ---------------------------- 245// Specify the enum values for the registers. These enums are only used by the 246// OptoReg "class". We can convert these enum values at will to VMReg when needed 247// for visibility to the rest of the vm. The order of this enum influences the 248// register allocator so having the freedom to set this order and not be stuck 249// with the order that is natural for the rest of the vm is worth it. 250alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256// Note that a register is not allocatable unless it is also mentioned 257// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277//----------Architecture Description Register Classes-------------------------- 278// Several register classes are automatically defined based upon information in 279// this architecture description. 280// 1) reg_class inline_cache_reg ( as defined in frame section ) 281// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283// 284 285// G0 is not included in integer class since it has special meaning. 286reg_class g0_reg(R_G0); 287 288// ---------------------------- 289// Integer Register Classes 290// ---------------------------- 291// Exclusions from i_reg: 292// R_G0: hardwired zero 293// R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294// R_G6: reserved by Solaris ABI to tools 295// R_G7: reserved by Solaris ABI to libthread 296// R_O7: Used as a temp in many encodings 297reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299// Class for all integer registers, except the G registers. This is used for 300// encodings which use G registers as temps. The regular inputs to such 301// instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302// will not put an input into a temp register. 303reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305reg_class g1_regI(R_G1); 306reg_class g3_regI(R_G3); 307reg_class g4_regI(R_G4); 308reg_class o0_regI(R_O0); 309reg_class o7_regI(R_O7); 310 311// ---------------------------- 312// Pointer Register Classes 313// ---------------------------- 314#ifdef _LP64 315// 64-bit build means 64-bit pointers means hi/lo pairs 316reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 320// Lock encodings use G3 and G4 internally 321reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 325// Special class for storeP instructions, which can store SP or RPC to TLS. 326// It is also used for memory addressing, allowing direct TLS addressing. 327reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 331// R_L7 is the lowest-priority callee-save (i.e., NS) register 332// We use it to save R_G2 across calls out of Java. 333reg_class l7_regP(R_L7H,R_L7); 334 335// Other special pointer regs 336reg_class g1_regP(R_G1H,R_G1); 337reg_class g2_regP(R_G2H,R_G2); 338reg_class g3_regP(R_G3H,R_G3); 339reg_class g4_regP(R_G4H,R_G4); 340reg_class g5_regP(R_G5H,R_G5); 341reg_class i0_regP(R_I0H,R_I0); 342reg_class o0_regP(R_O0H,R_O0); 343reg_class o1_regP(R_O1H,R_O1); 344reg_class o2_regP(R_O2H,R_O2); 345reg_class o7_regP(R_O7H,R_O7); 346 347#else // _LP64 348// 32-bit build means 32-bit pointers means 1 register. 349reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 353// Lock encodings use G3 and G4 internally 354reg_class lock_ptr_reg(R_G1, R_G5, 355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 358// Special class for storeP instructions, which can store SP or RPC to TLS. 359// It is also used for memory addressing, allowing direct TLS addressing. 360reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 364// R_L7 is the lowest-priority callee-save (i.e., NS) register 365// We use it to save R_G2 across calls out of Java. 366reg_class l7_regP(R_L7); 367 368// Other special pointer regs 369reg_class g1_regP(R_G1); 370reg_class g2_regP(R_G2); 371reg_class g3_regP(R_G3); 372reg_class g4_regP(R_G4); 373reg_class g5_regP(R_G5); 374reg_class i0_regP(R_I0); 375reg_class o0_regP(R_O0); 376reg_class o1_regP(R_O1); 377reg_class o2_regP(R_O2); 378reg_class o7_regP(R_O7); 379#endif // _LP64 380 381 382// ---------------------------- 383// Long Register Classes 384// ---------------------------- 385// Longs in 1 register. Aligned adjacent hi/lo pairs. 386// Note: O7 is never in this class; it is sometimes used as an encoding temp. 387reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 389#ifdef _LP64 390// 64-bit, longs in 1 register: use all 64-bit integer registers 391// 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 394#endif // _LP64 395 ); 396 397reg_class g1_regL(R_G1H,R_G1); 398reg_class g3_regL(R_G3H,R_G3); 399reg_class o2_regL(R_O2H,R_O2); 400reg_class o7_regL(R_O7H,R_O7); 401 402// ---------------------------- 403// Special Class for Condition Code Flags Register 404reg_class int_flags(CCR); 405reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 406reg_class float_flag0(FCC0); 407 408 409// ---------------------------- 410// Float Point Register Classes 411// ---------------------------- 412// Skip F30/F31, they are reserved for mem-mem copies 413reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 414 415// Paired floating point registers--they show up in the same order as the floats, 416// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 417reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 419 /* Use extra V9 double registers; this AD file does not support V8 */ 420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 422 ); 423 424// Paired floating point registers--they show up in the same order as the floats, 425// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 426// This class is usable for mis-aligned loads as happen in I2C adapters. 427reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 429%} 430 431//----------DEFINITION BLOCK--------------------------------------------------- 432// Define name --> value mappings to inform the ADLC of an integer valued name 433// Current support includes integer values in the range [0, 0x7FFFFFFF] 434// Format: 435// int_def <name> ( <int_value>, <expression>); 436// Generated Code in ad_<arch>.hpp 437// #define <name> (<expression>) 438// // value == <int_value> 439// Generated code in ad_<arch>.cpp adlc_verification() 440// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 441// 442definitions %{ 443// The default cost (of an ALU instruction). 444 int_def DEFAULT_COST ( 100, 100); 445 int_def HUGE_COST (1000000, 1000000); 446 447// Memory refs are twice as expensive as run-of-the-mill. 448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 449 450// Branches are even more expensive. 451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 452 int_def CALL_COST ( 300, DEFAULT_COST * 3); 453%} 454 455 456//----------SOURCE BLOCK------------------------------------------------------- 457// This is a block of C++ code which provides values, functions, and 458// definitions necessary in the rest of the architecture description 459source_hpp %{ 460// Must be visible to the DFA in dfa_sparc.cpp 461extern bool can_branch_register( Node *bol, Node *cmp ); 462 463// Macros to extract hi & lo halves from a long pair. 464// G0 is not part of any long pair, so assert on that. 465// Prevents accidentally using G1 instead of G0. 466#define LONG_HI_REG(x) (x) 467#define LONG_LO_REG(x) (x) 468 469%} 470 471source %{ 472#define __ _masm. 473 474// Block initializing store 475#define ASI_BLK_INIT_QUAD_LDD_P 0xE2 476 477// tertiary op of a LoadP or StoreP encoding 478#define REGP_OP true 479 480static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 481static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 482static Register reg_to_register_object(int register_encoding); 483 484// Used by the DFA in dfa_sparc.cpp. 485// Check for being able to use a V9 branch-on-register. Requires a 486// compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 487// extended. Doesn't work following an integer ADD, for example, because of 488// overflow (-1 incremented yields 0 plus a carry in the high-order word). On 489// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 490// replace them with zero, which could become sign-extension in a different OS 491// release. There's no obvious reason why an interrupt will ever fill these 492// bits with non-zero junk (the registers are reloaded with standard LD 493// instructions which either zero-fill or sign-fill). 494bool can_branch_register( Node *bol, Node *cmp ) { 495 if( !BranchOnRegister ) return false; 496#ifdef _LP64 497 if( cmp->Opcode() == Op_CmpP ) 498 return true; // No problems with pointer compares 499#endif 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525} 526 527// **************************************************************************** 528 529// REQUIRED FUNCTIONALITY 530 531// !!!!! Special hack to get all type of calls to specify the byte offset 532// from the start of the call to the point where the return address 533// will point. 534// The "return address" is the address of the call instruction, plus 8. 535 536int MachCallStaticJavaNode::ret_addr_offset() { 537 int offset = NativeCall::instruction_size; // call; delay slot 538 if (_method_handle_invoke) 539 offset += 4; // restore SP 540 return offset; 541} 542 543int MachCallDynamicJavaNode::ret_addr_offset() { 544 int vtable_index = this->_vtable_index; 545 if (vtable_index < 0) { 546 // must be invalid_vtable_index, not nonvirtual_vtable_index 547 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 548 return (NativeMovConstReg::instruction_size + 549 NativeCall::instruction_size); // sethi; setlo; call; delay slot 550 } else { 551 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 552 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 553 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 554 int klass_load_size; 555 if (UseCompressedOops) { 556 assert(Universe::heap() != NULL, "java heap should be initialized"); 557 if (Universe::narrow_oop_base() == NULL) 558 klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 559 else 560 klass_load_size = 3*BytesPerInstWord; 561 } else { 562 klass_load_size = 1*BytesPerInstWord; 563 } 564 if( Assembler::is_simm13(v_off) ) { 565 return klass_load_size + 566 (2*BytesPerInstWord + // ld_ptr, ld_ptr 567 NativeCall::instruction_size); // call; delay slot 568 } else { 569 return klass_load_size + 570 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 571 NativeCall::instruction_size); // call; delay slot 572 } 573 } 574} 575 576int MachCallRuntimeNode::ret_addr_offset() { 577#ifdef _LP64 578 if (MacroAssembler::is_far_target(entry_point())) { 579 return NativeFarCall::instruction_size; 580 } else { 581 return NativeCall::instruction_size; 582 } 583#else 584 return NativeCall::instruction_size; // call; delay slot 585#endif 586} 587 588// Indicate if the safepoint node needs the polling page as an input. 589// Since Sparc does not have absolute addressing, it does. 590bool SafePointNode::needs_polling_address_input() { 591 return true; 592} 593 594// emit an interrupt that is caught by the debugger (for debugging compiler) 595void emit_break(CodeBuffer &cbuf) { 596 MacroAssembler _masm(&cbuf); 597 __ breakpoint_trap(); 598} 599 600#ifndef PRODUCT 601void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 602 st->print("TA"); 603} 604#endif 605 606void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 607 emit_break(cbuf); 608} 609 610uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 611 return MachNode::size(ra_); 612} 613 614// Traceable jump 615void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 616 MacroAssembler _masm(&cbuf); 617 Register rdest = reg_to_register_object(jump_target); 618 __ JMP(rdest, 0); 619 __ delayed()->nop(); 620} 621 622// Traceable jump and set exception pc 623void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 624 MacroAssembler _masm(&cbuf); 625 Register rdest = reg_to_register_object(jump_target); 626 __ JMP(rdest, 0); 627 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 628} 629 630void emit_nop(CodeBuffer &cbuf) { 631 MacroAssembler _masm(&cbuf); 632 __ nop(); 633} 634 635void emit_illtrap(CodeBuffer &cbuf) { 636 MacroAssembler _masm(&cbuf); 637 __ illtrap(0); 638} 639 640 641intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 642 assert(n->rule() != loadUB_rule, ""); 643 644 intptr_t offset = 0; 645 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 646 const Node* addr = n->get_base_and_disp(offset, adr_type); 647 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 648 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 649 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 650 atype = atype->add_offset(offset); 651 assert(disp32 == offset, "wrong disp32"); 652 return atype->_offset; 653} 654 655 656intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 657 assert(n->rule() != loadUB_rule, ""); 658 659 intptr_t offset = 0; 660 Node* addr = n->in(2); 661 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 662 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 663 Node* a = addr->in(2/*AddPNode::Address*/); 664 Node* o = addr->in(3/*AddPNode::Offset*/); 665 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 666 atype = a->bottom_type()->is_ptr()->add_offset(offset); 667 assert(atype->isa_oop_ptr(), "still an oop"); 668 } 669 offset = atype->is_ptr()->_offset; 670 if (offset != Type::OffsetBot) offset += disp32; 671 return offset; 672} 673 674static inline jdouble replicate_immI(int con, int count, int width) { 675 // Load a constant replicated "count" times with width "width" 676 int bit_width = width * 8; 677 jlong elt_val = con; 678 elt_val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 679 jlong val = elt_val; 680 for (int i = 0; i < count - 1; i++) { 681 val <<= bit_width; 682 val |= elt_val; 683 } 684 jdouble dval = *((jdouble*) &val); // coerce to double type 685 return dval; 686} 687 688// Standard Sparc opcode form2 field breakdown 689static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 690 f0 &= (1<<19)-1; // Mask displacement to 19 bits 691 int op = (f30 << 30) | 692 (f29 << 29) | 693 (f25 << 25) | 694 (f22 << 22) | 695 (f20 << 20) | 696 (f19 << 19) | 697 (f0 << 0); 698 cbuf.insts()->emit_int32(op); 699} 700 701// Standard Sparc opcode form2 field breakdown 702static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 703 f0 >>= 10; // Drop 10 bits 704 f0 &= (1<<22)-1; // Mask displacement to 22 bits 705 int op = (f30 << 30) | 706 (f25 << 25) | 707 (f22 << 22) | 708 (f0 << 0); 709 cbuf.insts()->emit_int32(op); 710} 711 712// Standard Sparc opcode form3 field breakdown 713static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 714 int op = (f30 << 30) | 715 (f25 << 25) | 716 (f19 << 19) | 717 (f14 << 14) | 718 (f5 << 5) | 719 (f0 << 0); 720 cbuf.insts()->emit_int32(op); 721} 722 723// Standard Sparc opcode form3 field breakdown 724static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 725 simm13 &= (1<<13)-1; // Mask to 13 bits 726 int op = (f30 << 30) | 727 (f25 << 25) | 728 (f19 << 19) | 729 (f14 << 14) | 730 (1 << 13) | // bit to indicate immediate-mode 731 (simm13<<0); 732 cbuf.insts()->emit_int32(op); 733} 734 735static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 736 simm10 &= (1<<10)-1; // Mask to 10 bits 737 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 738} 739 740#ifdef ASSERT 741// Helper function for VerifyOops in emit_form3_mem_reg 742void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 743 warning("VerifyOops encountered unexpected instruction:"); 744 n->dump(2); 745 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 746} 747#endif 748 749 750void emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 751 int src1_enc, int disp32, int src2_enc, int dst_enc) { 752 753#ifdef ASSERT 754 // The following code implements the +VerifyOops feature. 755 // It verifies oop values which are loaded into or stored out of 756 // the current method activation. +VerifyOops complements techniques 757 // like ScavengeALot, because it eagerly inspects oops in transit, 758 // as they enter or leave the stack, as opposed to ScavengeALot, 759 // which inspects oops "at rest", in the stack or heap, at safepoints. 760 // For this reason, +VerifyOops can sometimes detect bugs very close 761 // to their point of creation. It can also serve as a cross-check 762 // on the validity of oop maps, when used toegether with ScavengeALot. 763 764 // It would be good to verify oops at other points, especially 765 // when an oop is used as a base pointer for a load or store. 766 // This is presently difficult, because it is hard to know when 767 // a base address is biased or not. (If we had such information, 768 // it would be easy and useful to make a two-argument version of 769 // verify_oop which unbiases the base, and performs verification.) 770 771 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 772 bool is_verified_oop_base = false; 773 bool is_verified_oop_load = false; 774 bool is_verified_oop_store = false; 775 int tmp_enc = -1; 776 if (VerifyOops && src1_enc != R_SP_enc) { 777 // classify the op, mainly for an assert check 778 int st_op = 0, ld_op = 0; 779 switch (primary) { 780 case Assembler::stb_op3: st_op = Op_StoreB; break; 781 case Assembler::sth_op3: st_op = Op_StoreC; break; 782 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 783 case Assembler::stw_op3: st_op = Op_StoreI; break; 784 case Assembler::std_op3: st_op = Op_StoreL; break; 785 case Assembler::stf_op3: st_op = Op_StoreF; break; 786 case Assembler::stdf_op3: st_op = Op_StoreD; break; 787 788 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 789 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 790 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 791 case Assembler::ldx_op3: // may become LoadP or stay LoadI 792 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 793 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 794 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 795 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 796 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 797 case Assembler::ldub_op3: ld_op = Op_LoadB; break; 798 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 799 800 default: ShouldNotReachHere(); 801 } 802 if (tertiary == REGP_OP) { 803 if (st_op == Op_StoreI) st_op = Op_StoreP; 804 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 805 else ShouldNotReachHere(); 806 if (st_op) { 807 // a store 808 // inputs are (0:control, 1:memory, 2:address, 3:value) 809 Node* n2 = n->in(3); 810 if (n2 != NULL) { 811 const Type* t = n2->bottom_type(); 812 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 813 } 814 } else { 815 // a load 816 const Type* t = n->bottom_type(); 817 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 818 } 819 } 820 821 if (ld_op) { 822 // a Load 823 // inputs are (0:control, 1:memory, 2:address) 824 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 825 !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 826 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 827 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 828 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 829 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 830 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 831 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 832 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 834 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 835 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 836 !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 837 !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 838 !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && 839 !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && 840 !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && 841 !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && 842 !(n->rule() == loadUB_rule)) { 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 844 } 845 } else if (st_op) { 846 // a Store 847 // inputs are (0:control, 1:memory, 2:address, 3:value) 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 853 !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && 854 !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && 855 !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && 856 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 857 verify_oops_warning(n, n->ideal_Opcode(), st_op); 858 } 859 } 860 861 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 862 Node* addr = n->in(2); 863 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 864 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 865 if (atype != NULL) { 866 intptr_t offset = get_offset_from_base(n, atype, disp32); 867 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 868 if (offset != offset_2) { 869 get_offset_from_base(n, atype, disp32); 870 get_offset_from_base_2(n, atype, disp32); 871 } 872 assert(offset == offset_2, "different offsets"); 873 if (offset == disp32) { 874 // we now know that src1 is a true oop pointer 875 is_verified_oop_base = true; 876 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 877 if( primary == Assembler::ldd_op3 ) { 878 is_verified_oop_base = false; // Cannot 'ldd' into O7 879 } else { 880 tmp_enc = dst_enc; 881 dst_enc = R_O7_enc; // Load into O7; preserve source oop 882 assert(src1_enc != dst_enc, ""); 883 } 884 } 885 } 886 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 887 || offset == oopDesc::mark_offset_in_bytes())) { 888 // loading the mark should not be allowed either, but 889 // we don't check this since it conflicts with InlineObjectHash 890 // usage of LoadINode to get the mark. We could keep the 891 // check if we create a new LoadMarkNode 892 // but do not verify the object before its header is initialized 893 ShouldNotReachHere(); 894 } 895 } 896 } 897 } 898 } 899#endif 900 901 uint instr; 902 instr = (Assembler::ldst_op << 30) 903 | (dst_enc << 25) 904 | (primary << 19) 905 | (src1_enc << 14); 906 907 uint index = src2_enc; 908 int disp = disp32; 909 910 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 911 disp += STACK_BIAS; 912 913 // We should have a compiler bailout here rather than a guarantee. 914 // Better yet would be some mechanism to handle variable-size matches correctly. 915 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 916 917 if( disp == 0 ) { 918 // use reg-reg form 919 // bit 13 is already zero 920 instr |= index; 921 } else { 922 // use reg-imm form 923 instr |= 0x00002000; // set bit 13 to one 924 instr |= disp & 0x1FFF; 925 } 926 927 cbuf.insts()->emit_int32(instr); 928 929#ifdef ASSERT 930 { 931 MacroAssembler _masm(&cbuf); 932 if (is_verified_oop_base) { 933 __ verify_oop(reg_to_register_object(src1_enc)); 934 } 935 if (is_verified_oop_store) { 936 __ verify_oop(reg_to_register_object(dst_enc)); 937 } 938 if (tmp_enc != -1) { 939 __ mov(O7, reg_to_register_object(tmp_enc)); 940 } 941 if (is_verified_oop_load) { 942 __ verify_oop(reg_to_register_object(dst_enc)); 943 } 944 } 945#endif 946} 947 948void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) { 949 // The method which records debug information at every safepoint 950 // expects the call to be the first instruction in the snippet as 951 // it creates a PcDesc structure which tracks the offset of a call 952 // from the start of the codeBlob. This offset is computed as 953 // code_end() - code_begin() of the code which has been emitted 954 // so far. 955 // In this particular case we have skirted around the problem by 956 // putting the "mov" instruction in the delay slot but the problem 957 // may bite us again at some other point and a cleaner/generic 958 // solution using relocations would be needed. 959 MacroAssembler _masm(&cbuf); 960 __ set_inst_mark(); 961 962 // We flush the current window just so that there is a valid stack copy 963 // the fact that the current window becomes active again instantly is 964 // not a problem there is nothing live in it. 965 966#ifdef ASSERT 967 int startpos = __ offset(); 968#endif /* ASSERT */ 969 970 __ call((address)entry_point, rtype); 971 972 if (preserve_g2) __ delayed()->mov(G2, L7); 973 else __ delayed()->nop(); 974 975 if (preserve_g2) __ mov(L7, G2); 976 977#ifdef ASSERT 978 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 979#ifdef _LP64 980 // Trash argument dump slots. 981 __ set(0xb0b8ac0db0b8ac0d, G1); 982 __ mov(G1, G5); 983 __ stx(G1, SP, STACK_BIAS + 0x80); 984 __ stx(G1, SP, STACK_BIAS + 0x88); 985 __ stx(G1, SP, STACK_BIAS + 0x90); 986 __ stx(G1, SP, STACK_BIAS + 0x98); 987 __ stx(G1, SP, STACK_BIAS + 0xA0); 988 __ stx(G1, SP, STACK_BIAS + 0xA8); 989#else // _LP64 990 // this is also a native call, so smash the first 7 stack locations, 991 // and the various registers 992 993 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 994 // while [SP+0x44..0x58] are the argument dump slots. 995 __ set((intptr_t)0xbaadf00d, G1); 996 __ mov(G1, G5); 997 __ sllx(G1, 32, G1); 998 __ or3(G1, G5, G1); 999 __ mov(G1, G5); 1000 __ stx(G1, SP, 0x40); 1001 __ stx(G1, SP, 0x48); 1002 __ stx(G1, SP, 0x50); 1003 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 1004#endif // _LP64 1005 } 1006#endif /*ASSERT*/ 1007} 1008 1009//============================================================================= 1010// REQUIRED FUNCTIONALITY for encoding 1011void emit_lo(CodeBuffer &cbuf, int val) { } 1012void emit_hi(CodeBuffer &cbuf, int val) { } 1013 1014 1015//============================================================================= 1016const bool Matcher::constant_table_absolute_addressing = false; 1017const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask; 1018 1019void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1020 Compile* C = ra_->C; 1021 Compile::ConstantTable& constant_table = C->constant_table(); 1022 MacroAssembler _masm(&cbuf); 1023 1024 Register r = as_Register(ra_->get_encode(this)); 1025 CodeSection* cs = __ code()->consts(); 1026 int consts_size = cs->align_at_start(cs->size()); 1027 1028 if (UseRDPCForConstantTableBase) { 1029 // For the following RDPC logic to work correctly the consts 1030 // section must be allocated right before the insts section. This 1031 // assert checks for that. The layout and the SECT_* constants 1032 // are defined in src/share/vm/asm/codeBuffer.hpp. 1033 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1034 int offset = __ offset(); 1035 int disp; 1036 1037 // If the displacement from the current PC to the constant table 1038 // base fits into simm13 we set the constant table base to the 1039 // current PC. 1040 if (__ is_simm13(-(consts_size + offset))) { 1041 constant_table.set_table_base_offset(-(consts_size + offset)); 1042 disp = 0; 1043 } else { 1044 // If the offset of the top constant (last entry in the table) 1045 // fits into simm13 we set the constant table base to the actual 1046 // table base. 1047 if (__ is_simm13(constant_table.top_offset())) { 1048 constant_table.set_table_base_offset(0); 1049 disp = consts_size + offset; 1050 } else { 1051 // Otherwise we set the constant table base in the middle of the 1052 // constant table. 1053 int half_consts_size = consts_size / 2; 1054 assert(half_consts_size * 2 == consts_size, "sanity"); 1055 constant_table.set_table_base_offset(-half_consts_size); // table base offset gets added to the load displacement. 1056 disp = half_consts_size + offset; 1057 } 1058 } 1059 1060 __ rdpc(r); 1061 1062 if (disp != 0) { 1063 assert(r != O7, "need temporary"); 1064 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1065 } 1066 } 1067 else { 1068 // Materialize the constant table base. 1069 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size)); 1070 address baseaddr = cs->start() + -(constant_table.table_base_offset()); 1071 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1072 AddressLiteral base(baseaddr, rspec); 1073 __ set(base, r); 1074 } 1075} 1076 1077uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1078 if (UseRDPCForConstantTableBase) { 1079 // This is really the worst case but generally it's only 1 instruction. 1080 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1081 } else { 1082 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1083 } 1084} 1085 1086#ifndef PRODUCT 1087void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1088 char reg[128]; 1089 ra_->dump_register(this, reg); 1090 if (UseRDPCForConstantTableBase) { 1091 st->print("RDPC %s\t! constant table base", reg); 1092 } else { 1093 st->print("SET &constanttable,%s\t! constant table base", reg); 1094 } 1095} 1096#endif 1097 1098 1099//============================================================================= 1100 1101#ifndef PRODUCT 1102void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1103 Compile* C = ra_->C; 1104 1105 for (int i = 0; i < OptoPrologueNops; i++) { 1106 st->print_cr("NOP"); st->print("\t"); 1107 } 1108 1109 if( VerifyThread ) { 1110 st->print_cr("Verify_Thread"); st->print("\t"); 1111 } 1112 1113 size_t framesize = C->frame_slots() << LogBytesPerInt; 1114 1115 // Calls to C2R adapters often do not accept exceptional returns. 1116 // We require that their callers must bang for them. But be careful, because 1117 // some VM calls (such as call site linkage) can use several kilobytes of 1118 // stack. But the stack safety zone should account for that. 1119 // See bugs 4446381, 4468289, 4497237. 1120 if (C->need_stack_bang(framesize)) { 1121 st->print_cr("! stack bang"); st->print("\t"); 1122 } 1123 1124 if (Assembler::is_simm13(-framesize)) { 1125 st->print ("SAVE R_SP,-%d,R_SP",framesize); 1126 } else { 1127 st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 1128 st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 1129 st->print ("SAVE R_SP,R_G3,R_SP"); 1130 } 1131 1132} 1133#endif 1134 1135void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1136 Compile* C = ra_->C; 1137 MacroAssembler _masm(&cbuf); 1138 1139 for (int i = 0; i < OptoPrologueNops; i++) { 1140 __ nop(); 1141 } 1142 1143 __ verify_thread(); 1144 1145 size_t framesize = C->frame_slots() << LogBytesPerInt; 1146 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1147 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1148 1149 // Calls to C2R adapters often do not accept exceptional returns. 1150 // We require that their callers must bang for them. But be careful, because 1151 // some VM calls (such as call site linkage) can use several kilobytes of 1152 // stack. But the stack safety zone should account for that. 1153 // See bugs 4446381, 4468289, 4497237. 1154 if (C->need_stack_bang(framesize)) { 1155 __ generate_stack_overflow_check(framesize); 1156 } 1157 1158 if (Assembler::is_simm13(-framesize)) { 1159 __ save(SP, -framesize, SP); 1160 } else { 1161 __ sethi(-framesize & ~0x3ff, G3); 1162 __ add(G3, -framesize & 0x3ff, G3); 1163 __ save(SP, G3, SP); 1164 } 1165 C->set_frame_complete( __ offset() ); 1166} 1167 1168uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1169 return MachNode::size(ra_); 1170} 1171 1172int MachPrologNode::reloc() const { 1173 return 10; // a large enough number 1174} 1175 1176//============================================================================= 1177#ifndef PRODUCT 1178void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1179 Compile* C = ra_->C; 1180 1181 if( do_polling() && ra_->C->is_method_compilation() ) { 1182 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1183#ifdef _LP64 1184 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1185#else 1186 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 1187#endif 1188 } 1189 1190 if( do_polling() ) 1191 st->print("RET\n\t"); 1192 1193 st->print("RESTORE"); 1194} 1195#endif 1196 1197void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1198 MacroAssembler _masm(&cbuf); 1199 Compile* C = ra_->C; 1200 1201 __ verify_thread(); 1202 1203 // If this does safepoint polling, then do it here 1204 if( do_polling() && ra_->C->is_method_compilation() ) { 1205 AddressLiteral polling_page(os::get_polling_page()); 1206 __ sethi(polling_page, L0); 1207 __ relocate(relocInfo::poll_return_type); 1208 __ ld_ptr( L0, 0, G0 ); 1209 } 1210 1211 // If this is a return, then stuff the restore in the delay slot 1212 if( do_polling() ) { 1213 __ ret(); 1214 __ delayed()->restore(); 1215 } else { 1216 __ restore(); 1217 } 1218} 1219 1220uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1221 return MachNode::size(ra_); 1222} 1223 1224int MachEpilogNode::reloc() const { 1225 return 16; // a large enough number 1226} 1227 1228const Pipeline * MachEpilogNode::pipeline() const { 1229 return MachNode::pipeline_class(); 1230} 1231 1232int MachEpilogNode::safepoint_offset() const { 1233 assert( do_polling(), "no return for this epilog node"); 1234 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1235} 1236 1237//============================================================================= 1238 1239// Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1240enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1241static enum RC rc_class( OptoReg::Name reg ) { 1242 if( !OptoReg::is_valid(reg) ) return rc_bad; 1243 if (OptoReg::is_stack(reg)) return rc_stack; 1244 VMReg r = OptoReg::as_VMReg(reg); 1245 if (r->is_Register()) return rc_int; 1246 assert(r->is_FloatRegister(), "must be"); 1247 return rc_float; 1248} 1249 1250static int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 1251 if( cbuf ) { 1252 // Better yet would be some mechanism to handle variable-size matches correctly 1253 if (!Assembler::is_simm13(offset + STACK_BIAS)) { 1254 ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 1255 } else { 1256 emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1257 } 1258 } 1259#ifndef PRODUCT 1260 else if( !do_size ) { 1261 if( size != 0 ) st->print("\n\t"); 1262 if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 1263 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 1264 } 1265#endif 1266 return size+4; 1267} 1268 1269static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 1270 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 1271#ifndef PRODUCT 1272 else if( !do_size ) { 1273 if( size != 0 ) st->print("\n\t"); 1274 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 1275 } 1276#endif 1277 return size+4; 1278} 1279 1280uint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 1281 PhaseRegAlloc *ra_, 1282 bool do_size, 1283 outputStream* st ) const { 1284 // Get registers to move 1285 OptoReg::Name src_second = ra_->get_reg_second(in(1)); 1286 OptoReg::Name src_first = ra_->get_reg_first(in(1)); 1287 OptoReg::Name dst_second = ra_->get_reg_second(this ); 1288 OptoReg::Name dst_first = ra_->get_reg_first(this ); 1289 1290 enum RC src_second_rc = rc_class(src_second); 1291 enum RC src_first_rc = rc_class(src_first); 1292 enum RC dst_second_rc = rc_class(dst_second); 1293 enum RC dst_first_rc = rc_class(dst_first); 1294 1295 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 1296 1297 // Generate spill code! 1298 int size = 0; 1299 1300 if( src_first == dst_first && src_second == dst_second ) 1301 return size; // Self copy, no move 1302 1303 // -------------------------------------- 1304 // Check for mem-mem move. Load into unused float registers and fall into 1305 // the float-store case. 1306 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 1307 int offset = ra_->reg2offset(src_first); 1308 // Further check for aligned-adjacent pair, so we can use a double load 1309 if( (src_first&1)==0 && src_first+1 == src_second ) { 1310 src_second = OptoReg::Name(R_F31_num); 1311 src_second_rc = rc_float; 1312 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 1313 } else { 1314 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 1315 } 1316 src_first = OptoReg::Name(R_F30_num); 1317 src_first_rc = rc_float; 1318 } 1319 1320 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1321 int offset = ra_->reg2offset(src_second); 1322 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 1323 src_second = OptoReg::Name(R_F31_num); 1324 src_second_rc = rc_float; 1325 } 1326 1327 // -------------------------------------- 1328 // Check for float->int copy; requires a trip through memory 1329 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1330 int offset = frame::register_save_words*wordSize; 1331 if (cbuf) { 1332 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 1333 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1334 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1335 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 1336 } 1337#ifndef PRODUCT 1338 else if (!do_size) { 1339 if (size != 0) st->print("\n\t"); 1340 st->print( "SUB R_SP,16,R_SP\n"); 1341 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1342 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1343 st->print("\tADD R_SP,16,R_SP\n"); 1344 } 1345#endif 1346 size += 16; 1347 } 1348 1349 // Check for float->int copy on T4 1350 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1351 // Further check for aligned-adjacent pair, so we can use a double move 1352 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1353 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st); 1354 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st); 1355 } 1356 // Check for int->float copy on T4 1357 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1358 // Further check for aligned-adjacent pair, so we can use a double move 1359 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second) 1360 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st); 1361 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st); 1362 } 1363 1364 // -------------------------------------- 1365 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1366 // In such cases, I have to do the big-endian swap. For aligned targets, the 1367 // hardware does the flop for me. Doubles are always aligned, so no problem 1368 // there. Misaligned sources only come from native-long-returns (handled 1369 // special below). 1370#ifndef _LP64 1371 if( src_first_rc == rc_int && // source is already big-endian 1372 src_second_rc != rc_bad && // 64-bit move 1373 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 1374 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 1375 // Do the big-endian flop. 1376 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 1377 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 1378 } 1379#endif 1380 1381 // -------------------------------------- 1382 // Check for integer reg-reg copy 1383 if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 1384#ifndef _LP64 1385 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 1386 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1387 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1388 // operand contains the least significant word of the 64-bit value and vice versa. 1389 OptoReg::Name tmp = OptoReg::Name(R_O7_num); 1390 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 1391 // Shift O0 left in-place, zero-extend O1, then OR them into the dst 1392 if( cbuf ) { 1393 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 1394 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 1395 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 1396#ifndef PRODUCT 1397 } else if( !do_size ) { 1398 if( size != 0 ) st->print("\n\t"); 1399 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 1400 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 1401 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 1402#endif 1403 } 1404 return size+12; 1405 } 1406 else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 1407 // returning a long value in I0/I1 1408 // a SpillCopy must be able to target a return instruction's reg_class 1409 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 1410 // as stored in memory. On a big-endian machine like SPARC, this means that the _second 1411 // operand contains the least significant word of the 64-bit value and vice versa. 1412 OptoReg::Name tdest = dst_first; 1413 1414 if (src_first == dst_first) { 1415 tdest = OptoReg::Name(R_O7_num); 1416 size += 4; 1417 } 1418 1419 if( cbuf ) { 1420 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 1421 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 1422 // ShrL_reg_imm6 1423 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 1424 // ShrR_reg_imm6 src, 0, dst 1425 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 1426 if (tdest != dst_first) { 1427 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1428 } 1429 } 1430#ifndef PRODUCT 1431 else if( !do_size ) { 1432 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1433 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1434 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1435 if (tdest != dst_first) { 1436 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1437 } 1438 } 1439#endif // PRODUCT 1440 return size+8; 1441 } 1442#endif // !_LP64 1443 // Else normal reg-reg copy 1444 assert( src_second != dst_first, "smashed second before evacuating it" ); 1445 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1446 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1447 // This moves an aligned adjacent pair. 1448 // See if we are done. 1449 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1450 return size; 1451 } 1452 1453 // Check for integer store 1454 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1455 int offset = ra_->reg2offset(dst_first); 1456 // Further check for aligned-adjacent pair, so we can use a double store 1457 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1458 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1459 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1460 } 1461 1462 // Check for integer load 1463 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1464 int offset = ra_->reg2offset(src_first); 1465 // Further check for aligned-adjacent pair, so we can use a double load 1466 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1467 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1468 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1469 } 1470 1471 // Check for float reg-reg copy 1472 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1473 // Further check for aligned-adjacent pair, so we can use a double move 1474 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1475 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1476 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1477 } 1478 1479 // Check for float store 1480 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1481 int offset = ra_->reg2offset(dst_first); 1482 // Further check for aligned-adjacent pair, so we can use a double store 1483 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1484 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1485 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1486 } 1487 1488 // Check for float load 1489 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1490 int offset = ra_->reg2offset(src_first); 1491 // Further check for aligned-adjacent pair, so we can use a double load 1492 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1493 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1494 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1495 } 1496 1497 // -------------------------------------------------------------------- 1498 // Check for hi bits still needing moving. Only happens for misaligned 1499 // arguments to native calls. 1500 if( src_second == dst_second ) 1501 return size; // Self copy; no move 1502 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1503 1504#ifndef _LP64 1505 // In the LP64 build, all registers can be moved as aligned/adjacent 1506 // pairs, so there's never any need to move the high bits separately. 1507 // The 32-bit builds have to deal with the 32-bit ABI which can force 1508 // all sorts of silly alignment problems. 1509 1510 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1511 // 32-bits of a 64-bit register, but are needed in low bits of another 1512 // register (else it's a hi-bits-to-hi-bits copy which should have 1513 // happened already as part of a 64-bit move) 1514 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1515 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1516 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1517 // Shift src_second down to dst_second's low bits. 1518 if( cbuf ) { 1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1520#ifndef PRODUCT 1521 } else if( !do_size ) { 1522 if( size != 0 ) st->print("\n\t"); 1523 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1524#endif 1525 } 1526 return size+4; 1527 } 1528 1529 // Check for high word integer store. Must down-shift the hi bits 1530 // into a temp register, then fall into the case of storing int bits. 1531 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1532 // Shift src_second down to dst_second's low bits. 1533 if( cbuf ) { 1534 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1535#ifndef PRODUCT 1536 } else if( !do_size ) { 1537 if( size != 0 ) st->print("\n\t"); 1538 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1539#endif 1540 } 1541 size+=4; 1542 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1543 } 1544 1545 // Check for high word integer load 1546 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1547 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1548 1549 // Check for high word integer store 1550 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1551 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1552 1553 // Check for high word float store 1554 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1555 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1556 1557#endif // !_LP64 1558 1559 Unimplemented(); 1560} 1561 1562#ifndef PRODUCT 1563void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1564 implementation( NULL, ra_, false, st ); 1565} 1566#endif 1567 1568void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1569 implementation( &cbuf, ra_, false, NULL ); 1570} 1571 1572uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1573 return implementation( NULL, ra_, true, NULL ); 1574} 1575 1576//============================================================================= 1577#ifndef PRODUCT 1578void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1579 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1580} 1581#endif 1582 1583void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1584 MacroAssembler _masm(&cbuf); 1585 for(int i = 0; i < _count; i += 1) { 1586 __ nop(); 1587 } 1588} 1589 1590uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1591 return 4 * _count; 1592} 1593 1594 1595//============================================================================= 1596#ifndef PRODUCT 1597void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1598 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1599 int reg = ra_->get_reg_first(this); 1600 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1601} 1602#endif 1603 1604void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1605 MacroAssembler _masm(&cbuf); 1606 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1607 int reg = ra_->get_encode(this); 1608 1609 if (Assembler::is_simm13(offset)) { 1610 __ add(SP, offset, reg_to_register_object(reg)); 1611 } else { 1612 __ set(offset, O7); 1613 __ add(SP, O7, reg_to_register_object(reg)); 1614 } 1615} 1616 1617uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1618 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1619 assert(ra_ == ra_->C->regalloc(), "sanity"); 1620 return ra_->C->scratch_emit_size(this); 1621} 1622 1623//============================================================================= 1624 1625// emit call stub, compiled java to interpretor 1626void emit_java_to_interp(CodeBuffer &cbuf ) { 1627 1628 // Stub is fixed up when the corresponding call is converted from calling 1629 // compiled code to calling interpreted code. 1630 // set (empty), G5 1631 // jmp -1 1632 1633 address mark = cbuf.insts_mark(); // get mark within main instrs section 1634 1635 MacroAssembler _masm(&cbuf); 1636 1637 address base = 1638 __ start_a_stub(Compile::MAX_stubs_size); 1639 if (base == NULL) return; // CodeBuffer::expand failed 1640 1641 // static stub relocation stores the instruction address of the call 1642 __ relocate(static_stub_Relocation::spec(mark)); 1643 1644 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1645 1646 __ set_inst_mark(); 1647 AddressLiteral addrlit(-1); 1648 __ JUMP(addrlit, G3, 0); 1649 1650 __ delayed()->nop(); 1651 1652 // Update current stubs pointer and restore code_end. 1653 __ end_a_stub(); 1654} 1655 1656// size of call stub, compiled java to interpretor 1657uint size_java_to_interp() { 1658 // This doesn't need to be accurate but it must be larger or equal to 1659 // the real size of the stub. 1660 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1661 NativeJump::instruction_size + // sethi; jmp; nop 1662 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1663} 1664// relocation entries for call stub, compiled java to interpretor 1665uint reloc_java_to_interp() { 1666 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1667} 1668 1669 1670//============================================================================= 1671#ifndef PRODUCT 1672void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1673 st->print_cr("\nUEP:"); 1674#ifdef _LP64 1675 if (UseCompressedOops) { 1676 assert(Universe::heap() != NULL, "java heap should be initialized"); 1677 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1678 st->print_cr("\tSLL R_G5,3,R_G5"); 1679 if (Universe::narrow_oop_base() != NULL) 1680 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1681 } else { 1682 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1683 } 1684 st->print_cr("\tCMP R_G5,R_G3" ); 1685 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1686#else // _LP64 1687 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1688 st->print_cr("\tCMP R_G5,R_G3" ); 1689 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1690#endif // _LP64 1691} 1692#endif 1693 1694void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1695 MacroAssembler _masm(&cbuf); 1696 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1697 Register temp_reg = G3; 1698 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1699 1700 // Load klass from receiver 1701 __ load_klass(O0, temp_reg); 1702 // Compare against expected klass 1703 __ cmp(temp_reg, G5_ic_reg); 1704 // Branch to miss code, checks xcc or icc depending 1705 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1706} 1707 1708uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1709 return MachNode::size(ra_); 1710} 1711 1712 1713//============================================================================= 1714 1715uint size_exception_handler() { 1716 if (TraceJumps) { 1717 return (400); // just a guess 1718 } 1719 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1720} 1721 1722uint size_deopt_handler() { 1723 if (TraceJumps) { 1724 return (400); // just a guess 1725 } 1726 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1727} 1728 1729// Emit exception handler code. 1730int emit_exception_handler(CodeBuffer& cbuf) { 1731 Register temp_reg = G3; 1732 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1733 MacroAssembler _masm(&cbuf); 1734 1735 address base = 1736 __ start_a_stub(size_exception_handler()); 1737 if (base == NULL) return 0; // CodeBuffer::expand failed 1738 1739 int offset = __ offset(); 1740 1741 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1742 __ delayed()->nop(); 1743 1744 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1745 1746 __ end_a_stub(); 1747 1748 return offset; 1749} 1750 1751int emit_deopt_handler(CodeBuffer& cbuf) { 1752 // Can't use any of the current frame's registers as we may have deopted 1753 // at a poll and everything (including G3) can be live. 1754 Register temp_reg = L0; 1755 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1756 MacroAssembler _masm(&cbuf); 1757 1758 address base = 1759 __ start_a_stub(size_deopt_handler()); 1760 if (base == NULL) return 0; // CodeBuffer::expand failed 1761 1762 int offset = __ offset(); 1763 __ save_frame(0); 1764 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1765 __ delayed()->restore(); 1766 1767 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1768 1769 __ end_a_stub(); 1770 return offset; 1771 1772} 1773 1774// Given a register encoding, produce a Integer Register object 1775static Register reg_to_register_object(int register_encoding) { 1776 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1777 return as_Register(register_encoding); 1778} 1779 1780// Given a register encoding, produce a single-precision Float Register object 1781static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1782 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1783 return as_SingleFloatRegister(register_encoding); 1784} 1785 1786// Given a register encoding, produce a double-precision Float Register object 1787static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1788 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1789 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1790 return as_DoubleFloatRegister(register_encoding); 1791} 1792 1793const bool Matcher::match_rule_supported(int opcode) { 1794 if (!has_match_rule(opcode)) 1795 return false; 1796 1797 switch (opcode) { 1798 case Op_CountLeadingZerosI: 1799 case Op_CountLeadingZerosL: 1800 case Op_CountTrailingZerosI: 1801 case Op_CountTrailingZerosL: 1802 if (!UsePopCountInstruction) 1803 return false; 1804 break; 1805 } 1806 1807 return true; // Per default match rules are supported. 1808} 1809 1810int Matcher::regnum_to_fpu_offset(int regnum) { 1811 return regnum - 32; // The FP registers are in the second chunk 1812} 1813 1814#ifdef ASSERT 1815address last_rethrow = NULL; // debugging aid for Rethrow encoding 1816#endif 1817 1818// Vector width in bytes 1819const uint Matcher::vector_width_in_bytes(void) { 1820 return 8; 1821} 1822 1823// Vector ideal reg 1824const uint Matcher::vector_ideal_reg(void) { 1825 return Op_RegD; 1826} 1827 1828// USII supports fxtof through the whole range of number, USIII doesn't 1829const bool Matcher::convL2FSupported(void) { 1830 return VM_Version::has_fast_fxtof(); 1831} 1832 1833// Is this branch offset short enough that a short branch can be used? 1834// 1835// NOTE: If the platform does not provide any short branch variants, then 1836// this method should return false for offset 0. 1837bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1838 // The passed offset is relative to address of the branch. 1839 // Don't need to adjust the offset. 1840 return UseCBCond && Assembler::is_simm(offset, 12); 1841} 1842 1843const bool Matcher::isSimpleConstant64(jlong value) { 1844 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1845 // Depends on optimizations in MacroAssembler::setx. 1846 int hi = (int)(value >> 32); 1847 int lo = (int)(value & ~0); 1848 return (hi == 0) || (hi == -1) || (lo == 0); 1849} 1850 1851// No scaling for the parameter the ClearArray node. 1852const bool Matcher::init_array_count_is_in_bytes = true; 1853 1854// Threshold size for cleararray. 1855const int Matcher::init_array_short_size = 8 * BytesPerLong; 1856 1857// Should the Matcher clone shifts on addressing modes, expecting them to 1858// be subsumed into complex addressing expressions or compute them into 1859// registers? True for Intel but false for most RISCs 1860const bool Matcher::clone_shift_expressions = false; 1861 1862// Do we need to mask the count passed to shift instructions or does 1863// the cpu only look at the lower 5/6 bits anyway? 1864const bool Matcher::need_masked_shift_count = false; 1865 1866bool Matcher::narrow_oop_use_complex_address() { 1867 NOT_LP64(ShouldNotCallThis()); 1868 assert(UseCompressedOops, "only for compressed oops code"); 1869 return false; 1870} 1871 1872// Is it better to copy float constants, or load them directly from memory? 1873// Intel can load a float constant from a direct address, requiring no 1874// extra registers. Most RISCs will have to materialize an address into a 1875// register first, so they would do better to copy the constant from stack. 1876const bool Matcher::rematerialize_float_constants = false; 1877 1878// If CPU can load and store mis-aligned doubles directly then no fixup is 1879// needed. Else we split the double into 2 integer pieces and move it 1880// piece-by-piece. Only happens when passing doubles into C code as the 1881// Java calling convention forces doubles to be aligned. 1882#ifdef _LP64 1883const bool Matcher::misaligned_doubles_ok = true; 1884#else 1885const bool Matcher::misaligned_doubles_ok = false; 1886#endif 1887 1888// No-op on SPARC. 1889void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1890} 1891 1892// Advertise here if the CPU requires explicit rounding operations 1893// to implement the UseStrictFP mode. 1894const bool Matcher::strict_fp_requires_explicit_rounding = false; 1895 1896// Are floats conerted to double when stored to stack during deoptimization? 1897// Sparc does not handle callee-save floats. 1898bool Matcher::float_in_double() { return false; } 1899 1900// Do ints take an entire long register or just half? 1901// Note that we if-def off of _LP64. 1902// The relevant question is how the int is callee-saved. In _LP64 1903// the whole long is written but de-opt'ing will have to extract 1904// the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1905#ifdef _LP64 1906const bool Matcher::int_in_long = true; 1907#else 1908const bool Matcher::int_in_long = false; 1909#endif 1910 1911// Return whether or not this register is ever used as an argument. This 1912// function is used on startup to build the trampoline stubs in generateOptoStub. 1913// Registers not mentioned will be killed by the VM call in the trampoline, and 1914// arguments in those registers not be available to the callee. 1915bool Matcher::can_be_java_arg( int reg ) { 1916 // Standard sparc 6 args in registers 1917 if( reg == R_I0_num || 1918 reg == R_I1_num || 1919 reg == R_I2_num || 1920 reg == R_I3_num || 1921 reg == R_I4_num || 1922 reg == R_I5_num ) return true; 1923#ifdef _LP64 1924 // 64-bit builds can pass 64-bit pointers and longs in 1925 // the high I registers 1926 if( reg == R_I0H_num || 1927 reg == R_I1H_num || 1928 reg == R_I2H_num || 1929 reg == R_I3H_num || 1930 reg == R_I4H_num || 1931 reg == R_I5H_num ) return true; 1932 1933 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1934 return true; 1935 } 1936 1937#else 1938 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1939 // Longs cannot be passed in O regs, because O regs become I regs 1940 // after a 'save' and I regs get their high bits chopped off on 1941 // interrupt. 1942 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1943 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1944#endif 1945 // A few float args in registers 1946 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1947 1948 return false; 1949} 1950 1951bool Matcher::is_spillable_arg( int reg ) { 1952 return can_be_java_arg(reg); 1953} 1954 1955bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1956 // Use hardware SDIVX instruction when it is 1957 // faster than a code which use multiply. 1958 return VM_Version::has_fast_idiv(); 1959} 1960 1961// Register for DIVI projection of divmodI 1962RegMask Matcher::divI_proj_mask() { 1963 ShouldNotReachHere(); 1964 return RegMask(); 1965} 1966 1967// Register for MODI projection of divmodI 1968RegMask Matcher::modI_proj_mask() { 1969 ShouldNotReachHere(); 1970 return RegMask(); 1971} 1972 1973// Register for DIVL projection of divmodL 1974RegMask Matcher::divL_proj_mask() { 1975 ShouldNotReachHere(); 1976 return RegMask(); 1977} 1978 1979// Register for MODL projection of divmodL 1980RegMask Matcher::modL_proj_mask() { 1981 ShouldNotReachHere(); 1982 return RegMask(); 1983} 1984 1985const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1986 return L7_REGP_mask; 1987} 1988 1989%} 1990 1991 1992// The intptr_t operand types, defined by textual substitution. 1993// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1994#ifdef _LP64 1995#define immX immL 1996#define immX13 immL13 1997#define immX13m7 immL13m7 1998#define iRegX iRegL 1999#define g1RegX g1RegL 2000#else 2001#define immX immI 2002#define immX13 immI13 2003#define immX13m7 immI13m7 2004#define iRegX iRegI 2005#define g1RegX g1RegI 2006#endif 2007 2008//----------ENCODING BLOCK----------------------------------------------------- 2009// This block specifies the encoding classes used by the compiler to output 2010// byte streams. Encoding classes are parameterized macros used by 2011// Machine Instruction Nodes in order to generate the bit encoding of the 2012// instruction. Operands specify their base encoding interface with the 2013// interface keyword. There are currently supported four interfaces, 2014// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2015// operand to generate a function which returns its register number when 2016// queried. CONST_INTER causes an operand to generate a function which 2017// returns the value of the constant when queried. MEMORY_INTER causes an 2018// operand to generate four functions which return the Base Register, the 2019// Index Register, the Scale Value, and the Offset Value of the operand when 2020// queried. COND_INTER causes an operand to generate six functions which 2021// return the encoding code (ie - encoding bits for the instruction) 2022// associated with each basic boolean condition for a conditional instruction. 2023// 2024// Instructions specify two basic values for encoding. Again, a function 2025// is available to check if the constant displacement is an oop. They use the 2026// ins_encode keyword to specify their encoding classes (which must be 2027// a sequence of enc_class names, and their parameters, specified in 2028// the encoding block), and they use the 2029// opcode keyword to specify, in order, their primary, secondary, and 2030// tertiary opcode. Only the opcode sections which a particular instruction 2031// needs for encoding need to be specified. 2032encode %{ 2033 enc_class enc_untested %{ 2034#ifdef ASSERT 2035 MacroAssembler _masm(&cbuf); 2036 __ untested("encoding"); 2037#endif 2038 %} 2039 2040 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 2041 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 2042 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2043 %} 2044 2045 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 2046 emit_form3_mem_reg(cbuf, this, $primary, -1, 2047 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 2048 %} 2049 2050 enc_class form3_mem_prefetch_read( memory mem ) %{ 2051 emit_form3_mem_reg(cbuf, this, $primary, -1, 2052 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2053 %} 2054 2055 enc_class form3_mem_prefetch_write( memory mem ) %{ 2056 emit_form3_mem_reg(cbuf, this, $primary, -1, 2057 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2058 %} 2059 2060 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2061 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 2062 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 2063 guarantee($mem$$index == R_G0_enc, "double index?"); 2064 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2065 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2066 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2067 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2068 %} 2069 2070 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2071 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 2072 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 2073 guarantee($mem$$index == R_G0_enc, "double index?"); 2074 // Load long with 2 instructions 2075 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2076 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2077 %} 2078 2079 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2080 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2081 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2082 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2083 %} 2084 2085 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2086 // Encode a reg-reg copy. If it is useless, then empty encoding. 2087 if( $rs2$$reg != $rd$$reg ) 2088 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2089 %} 2090 2091 // Target lo half of long 2092 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2093 // Encode a reg-reg copy. If it is useless, then empty encoding. 2094 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2095 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2096 %} 2097 2098 // Source lo half of long 2099 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2100 // Encode a reg-reg copy. If it is useless, then empty encoding. 2101 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2102 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2103 %} 2104 2105 // Target hi half of long 2106 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2107 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2108 %} 2109 2110 // Source lo half of long, and leave it sign extended. 2111 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2112 // Sign extend low half 2113 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2114 %} 2115 2116 // Source hi half of long, and leave it sign extended. 2117 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2118 // Shift high half to low half 2119 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2120 %} 2121 2122 // Source hi half of long 2123 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2124 // Encode a reg-reg copy. If it is useless, then empty encoding. 2125 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2126 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2127 %} 2128 2129 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2130 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2131 %} 2132 2133 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2134 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2135 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2136 %} 2137 2138 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2139 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2140 // clear if nothing else is happening 2141 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2142 // blt,a,pn done 2143 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2144 // mov dst,-1 in delay slot 2145 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2146 %} 2147 2148 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2149 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2150 %} 2151 2152 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2153 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2154 %} 2155 2156 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2157 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2158 %} 2159 2160 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2161 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2162 %} 2163 2164 enc_class move_return_pc_to_o1() %{ 2165 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2166 %} 2167 2168#ifdef _LP64 2169 /* %%% merge with enc_to_bool */ 2170 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2171 MacroAssembler _masm(&cbuf); 2172 2173 Register src_reg = reg_to_register_object($src$$reg); 2174 Register dst_reg = reg_to_register_object($dst$$reg); 2175 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2176 %} 2177#endif 2178 2179 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2180 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2181 MacroAssembler _masm(&cbuf); 2182 2183 Register p_reg = reg_to_register_object($p$$reg); 2184 Register q_reg = reg_to_register_object($q$$reg); 2185 Register y_reg = reg_to_register_object($y$$reg); 2186 Register tmp_reg = reg_to_register_object($tmp$$reg); 2187 2188 __ subcc( p_reg, q_reg, p_reg ); 2189 __ add ( p_reg, y_reg, tmp_reg ); 2190 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2191 %} 2192 2193 enc_class form_d2i_helper(regD src, regF dst) %{ 2194 // fcmp %fcc0,$src,$src 2195 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2196 // branch %fcc0 not-nan, predict taken 2197 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2198 // fdtoi $src,$dst 2199 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2200 // fitos $dst,$dst (if nan) 2201 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2202 // clear $dst (if nan) 2203 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2204 // carry on here... 2205 %} 2206 2207 enc_class form_d2l_helper(regD src, regD dst) %{ 2208 // fcmp %fcc0,$src,$src check for NAN 2209 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2210 // branch %fcc0 not-nan, predict taken 2211 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2212 // fdtox $src,$dst convert in delay slot 2213 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2214 // fxtod $dst,$dst (if nan) 2215 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2216 // clear $dst (if nan) 2217 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2218 // carry on here... 2219 %} 2220 2221 enc_class form_f2i_helper(regF src, regF dst) %{ 2222 // fcmps %fcc0,$src,$src 2223 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2224 // branch %fcc0 not-nan, predict taken 2225 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2226 // fstoi $src,$dst 2227 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2228 // fitos $dst,$dst (if nan) 2229 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2230 // clear $dst (if nan) 2231 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2232 // carry on here... 2233 %} 2234 2235 enc_class form_f2l_helper(regF src, regD dst) %{ 2236 // fcmps %fcc0,$src,$src 2237 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2238 // branch %fcc0 not-nan, predict taken 2239 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2240 // fstox $src,$dst 2241 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2242 // fxtod $dst,$dst (if nan) 2243 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2244 // clear $dst (if nan) 2245 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2246 // carry on here... 2247 %} 2248 2249 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2250 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2251 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2252 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2253 2254 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2255 2256 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2257 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2258 2259 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2260 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2261 %} 2262 2263 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2264 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2265 %} 2266 2267 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2268 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2269 %} 2270 2271 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2272 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2273 %} 2274 2275 enc_class form3_convI2F(regF rs2, regF rd) %{ 2276 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2277 %} 2278 2279 // Encloding class for traceable jumps 2280 enc_class form_jmpl(g3RegP dest) %{ 2281 emit_jmpl(cbuf, $dest$$reg); 2282 %} 2283 2284 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2285 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2286 %} 2287 2288 enc_class form2_nop() %{ 2289 emit_nop(cbuf); 2290 %} 2291 2292 enc_class form2_illtrap() %{ 2293 emit_illtrap(cbuf); 2294 %} 2295 2296 2297 // Compare longs and convert into -1, 0, 1. 2298 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2299 // CMP $src1,$src2 2300 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2301 // blt,a,pn done 2302 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2303 // mov dst,-1 in delay slot 2304 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2305 // bgt,a,pn done 2306 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2307 // mov dst,1 in delay slot 2308 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2309 // CLR $dst 2310 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2311 %} 2312 2313 enc_class enc_PartialSubtypeCheck() %{ 2314 MacroAssembler _masm(&cbuf); 2315 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2316 __ delayed()->nop(); 2317 %} 2318 2319 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2320 MacroAssembler _masm(&cbuf); 2321 Label* L = $labl$$label; 2322 Assembler::Predict predict_taken = 2323 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2324 2325 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2326 __ delayed()->nop(); 2327 %} 2328 2329 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2330 MacroAssembler _masm(&cbuf); 2331 Label* L = $labl$$label; 2332 Assembler::Predict predict_taken = 2333 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2334 2335 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2336 __ delayed()->nop(); 2337 %} 2338 2339 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2340 int op = (Assembler::arith_op << 30) | 2341 ($dst$$reg << 25) | 2342 (Assembler::movcc_op3 << 19) | 2343 (1 << 18) | // cc2 bit for 'icc' 2344 ($cmp$$cmpcode << 14) | 2345 (0 << 13) | // select register move 2346 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2347 ($src$$reg << 0); 2348 cbuf.insts()->emit_int32(op); 2349 %} 2350 2351 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2352 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2353 int op = (Assembler::arith_op << 30) | 2354 ($dst$$reg << 25) | 2355 (Assembler::movcc_op3 << 19) | 2356 (1 << 18) | // cc2 bit for 'icc' 2357 ($cmp$$cmpcode << 14) | 2358 (1 << 13) | // select immediate move 2359 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2360 (simm11 << 0); 2361 cbuf.insts()->emit_int32(op); 2362 %} 2363 2364 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2365 int op = (Assembler::arith_op << 30) | 2366 ($dst$$reg << 25) | 2367 (Assembler::movcc_op3 << 19) | 2368 (0 << 18) | // cc2 bit for 'fccX' 2369 ($cmp$$cmpcode << 14) | 2370 (0 << 13) | // select register move 2371 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2372 ($src$$reg << 0); 2373 cbuf.insts()->emit_int32(op); 2374 %} 2375 2376 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2377 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2378 int op = (Assembler::arith_op << 30) | 2379 ($dst$$reg << 25) | 2380 (Assembler::movcc_op3 << 19) | 2381 (0 << 18) | // cc2 bit for 'fccX' 2382 ($cmp$$cmpcode << 14) | 2383 (1 << 13) | // select immediate move 2384 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2385 (simm11 << 0); 2386 cbuf.insts()->emit_int32(op); 2387 %} 2388 2389 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2390 int op = (Assembler::arith_op << 30) | 2391 ($dst$$reg << 25) | 2392 (Assembler::fpop2_op3 << 19) | 2393 (0 << 18) | 2394 ($cmp$$cmpcode << 14) | 2395 (1 << 13) | // select register move 2396 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2397 ($primary << 5) | // select single, double or quad 2398 ($src$$reg << 0); 2399 cbuf.insts()->emit_int32(op); 2400 %} 2401 2402 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2403 int op = (Assembler::arith_op << 30) | 2404 ($dst$$reg << 25) | 2405 (Assembler::fpop2_op3 << 19) | 2406 (0 << 18) | 2407 ($cmp$$cmpcode << 14) | 2408 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2409 ($primary << 5) | // select single, double or quad 2410 ($src$$reg << 0); 2411 cbuf.insts()->emit_int32(op); 2412 %} 2413 2414 // Used by the MIN/MAX encodings. Same as a CMOV, but 2415 // the condition comes from opcode-field instead of an argument. 2416 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2417 int op = (Assembler::arith_op << 30) | 2418 ($dst$$reg << 25) | 2419 (Assembler::movcc_op3 << 19) | 2420 (1 << 18) | // cc2 bit for 'icc' 2421 ($primary << 14) | 2422 (0 << 13) | // select register move 2423 (0 << 11) | // cc1, cc0 bits for 'icc' 2424 ($src$$reg << 0); 2425 cbuf.insts()->emit_int32(op); 2426 %} 2427 2428 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2429 int op = (Assembler::arith_op << 30) | 2430 ($dst$$reg << 25) | 2431 (Assembler::movcc_op3 << 19) | 2432 (6 << 16) | // cc2 bit for 'xcc' 2433 ($primary << 14) | 2434 (0 << 13) | // select register move 2435 (0 << 11) | // cc1, cc0 bits for 'icc' 2436 ($src$$reg << 0); 2437 cbuf.insts()->emit_int32(op); 2438 %} 2439 2440 enc_class Set13( immI13 src, iRegI rd ) %{ 2441 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2442 %} 2443 2444 enc_class SetHi22( immI src, iRegI rd ) %{ 2445 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2446 %} 2447 2448 enc_class Set32( immI src, iRegI rd ) %{ 2449 MacroAssembler _masm(&cbuf); 2450 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2451 %} 2452 2453 enc_class call_epilog %{ 2454 if( VerifyStackAtCalls ) { 2455 MacroAssembler _masm(&cbuf); 2456 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2457 Register temp_reg = G3; 2458 __ add(SP, framesize, temp_reg); 2459 __ cmp(temp_reg, FP); 2460 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2461 } 2462 %} 2463 2464 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2465 // to G1 so the register allocator will not have to deal with the misaligned register 2466 // pair. 2467 enc_class adjust_long_from_native_call %{ 2468#ifndef _LP64 2469 if (returns_long()) { 2470 // sllx O0,32,O0 2471 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2472 // srl O1,0,O1 2473 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2474 // or O0,O1,G1 2475 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2476 } 2477#endif 2478 %} 2479 2480 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2481 // CALL directly to the runtime 2482 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2483 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2484 /*preserve_g2=*/true); 2485 %} 2486 2487 enc_class preserve_SP %{ 2488 MacroAssembler _masm(&cbuf); 2489 __ mov(SP, L7_mh_SP_save); 2490 %} 2491 2492 enc_class restore_SP %{ 2493 MacroAssembler _masm(&cbuf); 2494 __ mov(L7_mh_SP_save, SP); 2495 %} 2496 2497 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2498 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2499 // who we intended to call. 2500 if ( !_method ) { 2501 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2502 } else if (_optimized_virtual) { 2503 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2504 } else { 2505 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2506 } 2507 if( _method ) { // Emit stub for static call 2508 emit_java_to_interp(cbuf); 2509 } 2510 %} 2511 2512 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2513 MacroAssembler _masm(&cbuf); 2514 __ set_inst_mark(); 2515 int vtable_index = this->_vtable_index; 2516 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2517 if (vtable_index < 0) { 2518 // must be invalid_vtable_index, not nonvirtual_vtable_index 2519 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2520 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2521 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2522 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2523 // !!!!! 2524 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2525 // emit_call_dynamic_prologue( cbuf ); 2526 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2527 2528 address virtual_call_oop_addr = __ inst_mark(); 2529 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2530 // who we intended to call. 2531 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2532 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2533 } else { 2534 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2535 // Just go thru the vtable 2536 // get receiver klass (receiver already checked for non-null) 2537 // If we end up going thru a c2i adapter interpreter expects method in G5 2538 int off = __ offset(); 2539 __ load_klass(O0, G3_scratch); 2540 int klass_load_size; 2541 if (UseCompressedOops) { 2542 assert(Universe::heap() != NULL, "java heap should be initialized"); 2543 if (Universe::narrow_oop_base() == NULL) 2544 klass_load_size = 2*BytesPerInstWord; 2545 else 2546 klass_load_size = 3*BytesPerInstWord; 2547 } else { 2548 klass_load_size = 1*BytesPerInstWord; 2549 } 2550 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2551 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2552 if( __ is_simm13(v_off) ) { 2553 __ ld_ptr(G3, v_off, G5_method); 2554 } else { 2555 // Generate 2 instructions 2556 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2557 __ or3(G5_method, v_off & 0x3ff, G5_method); 2558 // ld_ptr, set_hi, set 2559 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2560 "Unexpected instruction size(s)"); 2561 __ ld_ptr(G3, G5_method, G5_method); 2562 } 2563 // NOTE: for vtable dispatches, the vtable entry will never be null. 2564 // However it may very well end up in handle_wrong_method if the 2565 // method is abstract for the particular class. 2566 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2567 // jump to target (either compiled code or c2iadapter) 2568 __ jmpl(G3_scratch, G0, O7); 2569 __ delayed()->nop(); 2570 } 2571 %} 2572 2573 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2574 MacroAssembler _masm(&cbuf); 2575 2576 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2577 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2578 // we might be calling a C2I adapter which needs it. 2579 2580 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2581 // Load nmethod 2582 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2583 2584 // CALL to compiled java, indirect the contents of G3 2585 __ set_inst_mark(); 2586 __ callr(temp_reg, G0); 2587 __ delayed()->nop(); 2588 %} 2589 2590enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2591 MacroAssembler _masm(&cbuf); 2592 Register Rdividend = reg_to_register_object($src1$$reg); 2593 Register Rdivisor = reg_to_register_object($src2$$reg); 2594 Register Rresult = reg_to_register_object($dst$$reg); 2595 2596 __ sra(Rdivisor, 0, Rdivisor); 2597 __ sra(Rdividend, 0, Rdividend); 2598 __ sdivx(Rdividend, Rdivisor, Rresult); 2599%} 2600 2601enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2602 MacroAssembler _masm(&cbuf); 2603 2604 Register Rdividend = reg_to_register_object($src1$$reg); 2605 int divisor = $imm$$constant; 2606 Register Rresult = reg_to_register_object($dst$$reg); 2607 2608 __ sra(Rdividend, 0, Rdividend); 2609 __ sdivx(Rdividend, divisor, Rresult); 2610%} 2611 2612enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2613 MacroAssembler _masm(&cbuf); 2614 Register Rsrc1 = reg_to_register_object($src1$$reg); 2615 Register Rsrc2 = reg_to_register_object($src2$$reg); 2616 Register Rdst = reg_to_register_object($dst$$reg); 2617 2618 __ sra( Rsrc1, 0, Rsrc1 ); 2619 __ sra( Rsrc2, 0, Rsrc2 ); 2620 __ mulx( Rsrc1, Rsrc2, Rdst ); 2621 __ srlx( Rdst, 32, Rdst ); 2622%} 2623 2624enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2625 MacroAssembler _masm(&cbuf); 2626 Register Rdividend = reg_to_register_object($src1$$reg); 2627 Register Rdivisor = reg_to_register_object($src2$$reg); 2628 Register Rresult = reg_to_register_object($dst$$reg); 2629 Register Rscratch = reg_to_register_object($scratch$$reg); 2630 2631 assert(Rdividend != Rscratch, ""); 2632 assert(Rdivisor != Rscratch, ""); 2633 2634 __ sra(Rdividend, 0, Rdividend); 2635 __ sra(Rdivisor, 0, Rdivisor); 2636 __ sdivx(Rdividend, Rdivisor, Rscratch); 2637 __ mulx(Rscratch, Rdivisor, Rscratch); 2638 __ sub(Rdividend, Rscratch, Rresult); 2639%} 2640 2641enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2642 MacroAssembler _masm(&cbuf); 2643 2644 Register Rdividend = reg_to_register_object($src1$$reg); 2645 int divisor = $imm$$constant; 2646 Register Rresult = reg_to_register_object($dst$$reg); 2647 Register Rscratch = reg_to_register_object($scratch$$reg); 2648 2649 assert(Rdividend != Rscratch, ""); 2650 2651 __ sra(Rdividend, 0, Rdividend); 2652 __ sdivx(Rdividend, divisor, Rscratch); 2653 __ mulx(Rscratch, divisor, Rscratch); 2654 __ sub(Rdividend, Rscratch, Rresult); 2655%} 2656 2657enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2658 MacroAssembler _masm(&cbuf); 2659 2660 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2661 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2662 2663 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2664%} 2665 2666enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2667 MacroAssembler _masm(&cbuf); 2668 2669 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2670 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2671 2672 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2673%} 2674 2675enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2676 MacroAssembler _masm(&cbuf); 2677 2678 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2679 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2680 2681 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2682%} 2683 2684enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2685 MacroAssembler _masm(&cbuf); 2686 2687 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2688 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2689 2690 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2691%} 2692 2693enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2694 MacroAssembler _masm(&cbuf); 2695 2696 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2697 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2698 2699 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2700%} 2701 2702enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2703 MacroAssembler _masm(&cbuf); 2704 2705 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2706 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2707 2708 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2709%} 2710 2711enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2712 MacroAssembler _masm(&cbuf); 2713 2714 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2715 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2716 2717 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2718%} 2719 2720enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2721 MacroAssembler _masm(&cbuf); 2722 2723 Register Roop = reg_to_register_object($oop$$reg); 2724 Register Rbox = reg_to_register_object($box$$reg); 2725 Register Rscratch = reg_to_register_object($scratch$$reg); 2726 Register Rmark = reg_to_register_object($scratch2$$reg); 2727 2728 assert(Roop != Rscratch, ""); 2729 assert(Roop != Rmark, ""); 2730 assert(Rbox != Rscratch, ""); 2731 assert(Rbox != Rmark, ""); 2732 2733 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2734%} 2735 2736enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2737 MacroAssembler _masm(&cbuf); 2738 2739 Register Roop = reg_to_register_object($oop$$reg); 2740 Register Rbox = reg_to_register_object($box$$reg); 2741 Register Rscratch = reg_to_register_object($scratch$$reg); 2742 Register Rmark = reg_to_register_object($scratch2$$reg); 2743 2744 assert(Roop != Rscratch, ""); 2745 assert(Roop != Rmark, ""); 2746 assert(Rbox != Rscratch, ""); 2747 assert(Rbox != Rmark, ""); 2748 2749 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2750 %} 2751 2752 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2753 MacroAssembler _masm(&cbuf); 2754 Register Rmem = reg_to_register_object($mem$$reg); 2755 Register Rold = reg_to_register_object($old$$reg); 2756 Register Rnew = reg_to_register_object($new$$reg); 2757 2758 // casx_under_lock picks 1 of 3 encodings: 2759 // For 32-bit pointers you get a 32-bit CAS 2760 // For 64-bit pointers you get a 64-bit CASX 2761 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2762 __ cmp( Rold, Rnew ); 2763 %} 2764 2765 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2766 Register Rmem = reg_to_register_object($mem$$reg); 2767 Register Rold = reg_to_register_object($old$$reg); 2768 Register Rnew = reg_to_register_object($new$$reg); 2769 2770 MacroAssembler _masm(&cbuf); 2771 __ mov(Rnew, O7); 2772 __ casx(Rmem, Rold, O7); 2773 __ cmp( Rold, O7 ); 2774 %} 2775 2776 // raw int cas, used for compareAndSwap 2777 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2778 Register Rmem = reg_to_register_object($mem$$reg); 2779 Register Rold = reg_to_register_object($old$$reg); 2780 Register Rnew = reg_to_register_object($new$$reg); 2781 2782 MacroAssembler _masm(&cbuf); 2783 __ mov(Rnew, O7); 2784 __ cas(Rmem, Rold, O7); 2785 __ cmp( Rold, O7 ); 2786 %} 2787 2788 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2789 Register Rres = reg_to_register_object($res$$reg); 2790 2791 MacroAssembler _masm(&cbuf); 2792 __ mov(1, Rres); 2793 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2794 %} 2795 2796 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2797 Register Rres = reg_to_register_object($res$$reg); 2798 2799 MacroAssembler _masm(&cbuf); 2800 __ mov(1, Rres); 2801 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2802 %} 2803 2804 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2805 MacroAssembler _masm(&cbuf); 2806 Register Rdst = reg_to_register_object($dst$$reg); 2807 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2808 : reg_to_DoubleFloatRegister_object($src1$$reg); 2809 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2810 : reg_to_DoubleFloatRegister_object($src2$$reg); 2811 2812 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2813 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2814 %} 2815 2816 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2817 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2818 MacroAssembler _masm(&cbuf); 2819 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2820 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2821 Register base_pointer_arg = reg_to_register_object($base$$reg); 2822 2823 Label loop; 2824 __ mov(nof_bytes_arg, nof_bytes_tmp); 2825 2826 // Loop and clear, walking backwards through the array. 2827 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2828 __ bind(loop); 2829 __ deccc(nof_bytes_tmp, 8); 2830 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2831 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2832 // %%%% this mini-loop must not cross a cache boundary! 2833 %} 2834 2835 2836 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2837 Label Ldone, Lloop; 2838 MacroAssembler _masm(&cbuf); 2839 2840 Register str1_reg = reg_to_register_object($str1$$reg); 2841 Register str2_reg = reg_to_register_object($str2$$reg); 2842 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2843 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2844 Register result_reg = reg_to_register_object($result$$reg); 2845 2846 assert(result_reg != str1_reg && 2847 result_reg != str2_reg && 2848 result_reg != cnt1_reg && 2849 result_reg != cnt2_reg , 2850 "need different registers"); 2851 2852 // Compute the minimum of the string lengths(str1_reg) and the 2853 // difference of the string lengths (stack) 2854 2855 // See if the lengths are different, and calculate min in str1_reg. 2856 // Stash diff in O7 in case we need it for a tie-breaker. 2857 Label Lskip; 2858 __ subcc(cnt1_reg, cnt2_reg, O7); 2859 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2860 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2861 // cnt2 is shorter, so use its count: 2862 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2863 __ bind(Lskip); 2864 2865 // reallocate cnt1_reg, cnt2_reg, result_reg 2866 // Note: limit_reg holds the string length pre-scaled by 2 2867 Register limit_reg = cnt1_reg; 2868 Register chr2_reg = cnt2_reg; 2869 Register chr1_reg = result_reg; 2870 // str{12} are the base pointers 2871 2872 // Is the minimum length zero? 2873 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2874 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2875 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2876 2877 // Load first characters 2878 __ lduh(str1_reg, 0, chr1_reg); 2879 __ lduh(str2_reg, 0, chr2_reg); 2880 2881 // Compare first characters 2882 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2883 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2884 assert(chr1_reg == result_reg, "result must be pre-placed"); 2885 __ delayed()->nop(); 2886 2887 { 2888 // Check after comparing first character to see if strings are equivalent 2889 Label LSkip2; 2890 // Check if the strings start at same location 2891 __ cmp(str1_reg, str2_reg); 2892 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2893 __ delayed()->nop(); 2894 2895 // Check if the length difference is zero (in O7) 2896 __ cmp(G0, O7); 2897 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2898 __ delayed()->mov(G0, result_reg); // result is zero 2899 2900 // Strings might not be equal 2901 __ bind(LSkip2); 2902 } 2903 2904 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2905 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2906 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2907 2908 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2909 __ add(str1_reg, limit_reg, str1_reg); 2910 __ add(str2_reg, limit_reg, str2_reg); 2911 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2912 2913 // Compare the rest of the characters 2914 __ lduh(str1_reg, limit_reg, chr1_reg); 2915 __ bind(Lloop); 2916 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2917 __ lduh(str2_reg, limit_reg, chr2_reg); 2918 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2919 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2920 assert(chr1_reg == result_reg, "result must be pre-placed"); 2921 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2922 // annul LDUH if branch is not taken to prevent access past end of string 2923 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2924 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2925 2926 // If strings are equal up to min length, return the length difference. 2927 __ mov(O7, result_reg); 2928 2929 // Otherwise, return the difference between the first mismatched chars. 2930 __ bind(Ldone); 2931 %} 2932 2933enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2934 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2935 MacroAssembler _masm(&cbuf); 2936 2937 Register str1_reg = reg_to_register_object($str1$$reg); 2938 Register str2_reg = reg_to_register_object($str2$$reg); 2939 Register cnt_reg = reg_to_register_object($cnt$$reg); 2940 Register tmp1_reg = O7; 2941 Register result_reg = reg_to_register_object($result$$reg); 2942 2943 assert(result_reg != str1_reg && 2944 result_reg != str2_reg && 2945 result_reg != cnt_reg && 2946 result_reg != tmp1_reg , 2947 "need different registers"); 2948 2949 __ cmp(str1_reg, str2_reg); //same char[] ? 2950 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2951 __ delayed()->add(G0, 1, result_reg); 2952 2953 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn); 2954 __ delayed()->add(G0, 1, result_reg); // count == 0 2955 2956 //rename registers 2957 Register limit_reg = cnt_reg; 2958 Register chr1_reg = result_reg; 2959 Register chr2_reg = tmp1_reg; 2960 2961 //check for alignment and position the pointers to the ends 2962 __ or3(str1_reg, str2_reg, chr1_reg); 2963 __ andcc(chr1_reg, 0x3, chr1_reg); 2964 // notZero means at least one not 4-byte aligned. 2965 // We could optimize the case when both arrays are not aligned 2966 // but it is not frequent case and it requires additional checks. 2967 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 2968 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 2969 2970 // Compare char[] arrays aligned to 4 bytes. 2971 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 2972 chr1_reg, chr2_reg, Ldone); 2973 __ ba(Ldone); 2974 __ delayed()->add(G0, 1, result_reg); 2975 2976 // char by char compare 2977 __ bind(Lchar); 2978 __ add(str1_reg, limit_reg, str1_reg); 2979 __ add(str2_reg, limit_reg, str2_reg); 2980 __ neg(limit_reg); //negate count 2981 2982 __ lduh(str1_reg, limit_reg, chr1_reg); 2983 // Lchar_loop 2984 __ bind(Lchar_loop); 2985 __ lduh(str2_reg, limit_reg, chr2_reg); 2986 __ cmp(chr1_reg, chr2_reg); 2987 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 2988 __ delayed()->mov(G0, result_reg); //not equal 2989 __ inccc(limit_reg, sizeof(jchar)); 2990 // annul LDUH if branch is not taken to prevent access past end of string 2991 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 2992 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2993 2994 __ add(G0, 1, result_reg); //equal 2995 2996 __ bind(Ldone); 2997 %} 2998 2999enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 3000 Label Lvector, Ldone, Lloop; 3001 MacroAssembler _masm(&cbuf); 3002 3003 Register ary1_reg = reg_to_register_object($ary1$$reg); 3004 Register ary2_reg = reg_to_register_object($ary2$$reg); 3005 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 3006 Register tmp2_reg = O7; 3007 Register result_reg = reg_to_register_object($result$$reg); 3008 3009 int length_offset = arrayOopDesc::length_offset_in_bytes(); 3010 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 3011 3012 // return true if the same array 3013 __ cmp(ary1_reg, ary2_reg); 3014 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3015 __ delayed()->add(G0, 1, result_reg); // equal 3016 3017 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3018 __ delayed()->mov(G0, result_reg); // not equal 3019 3020 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3021 __ delayed()->mov(G0, result_reg); // not equal 3022 3023 //load the lengths of arrays 3024 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3025 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3026 3027 // return false if the two arrays are not equal length 3028 __ cmp(tmp1_reg, tmp2_reg); 3029 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3030 __ delayed()->mov(G0, result_reg); // not equal 3031 3032 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn); 3033 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3034 3035 // load array addresses 3036 __ add(ary1_reg, base_offset, ary1_reg); 3037 __ add(ary2_reg, base_offset, ary2_reg); 3038 3039 // renaming registers 3040 Register chr1_reg = result_reg; // for characters in ary1 3041 Register chr2_reg = tmp2_reg; // for characters in ary2 3042 Register limit_reg = tmp1_reg; // length 3043 3044 // set byte count 3045 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3046 3047 // Compare char[] arrays aligned to 4 bytes. 3048 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3049 chr1_reg, chr2_reg, Ldone); 3050 __ add(G0, 1, result_reg); // equals 3051 3052 __ bind(Ldone); 3053 %} 3054 3055 enc_class enc_rethrow() %{ 3056 cbuf.set_insts_mark(); 3057 Register temp_reg = G3; 3058 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3059 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3060 MacroAssembler _masm(&cbuf); 3061#ifdef ASSERT 3062 __ save_frame(0); 3063 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3064 __ sethi(last_rethrow_addrlit, L1); 3065 Address addr(L1, last_rethrow_addrlit.low10()); 3066 __ get_pc(L2); 3067 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3068 __ st_ptr(L2, addr); 3069 __ restore(); 3070#endif 3071 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3072 __ delayed()->nop(); 3073 %} 3074 3075 enc_class emit_mem_nop() %{ 3076 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3077 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3078 %} 3079 3080 enc_class emit_fadd_nop() %{ 3081 // Generates the instruction FMOVS f31,f31 3082 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3083 %} 3084 3085 enc_class emit_br_nop() %{ 3086 // Generates the instruction BPN,PN . 3087 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3088 %} 3089 3090 enc_class enc_membar_acquire %{ 3091 MacroAssembler _masm(&cbuf); 3092 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3093 %} 3094 3095 enc_class enc_membar_release %{ 3096 MacroAssembler _masm(&cbuf); 3097 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3098 %} 3099 3100 enc_class enc_membar_volatile %{ 3101 MacroAssembler _masm(&cbuf); 3102 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3103 %} 3104 3105 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3106 MacroAssembler _masm(&cbuf); 3107 Register src_reg = reg_to_register_object($src$$reg); 3108 Register dst_reg = reg_to_register_object($dst$$reg); 3109 __ sllx(src_reg, 56, dst_reg); 3110 __ srlx(dst_reg, 8, O7); 3111 __ or3 (dst_reg, O7, dst_reg); 3112 __ srlx(dst_reg, 16, O7); 3113 __ or3 (dst_reg, O7, dst_reg); 3114 __ srlx(dst_reg, 32, O7); 3115 __ or3 (dst_reg, O7, dst_reg); 3116 %} 3117 3118 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3119 MacroAssembler _masm(&cbuf); 3120 Register src_reg = reg_to_register_object($src$$reg); 3121 Register dst_reg = reg_to_register_object($dst$$reg); 3122 __ sll(src_reg, 24, dst_reg); 3123 __ srl(dst_reg, 8, O7); 3124 __ or3(dst_reg, O7, dst_reg); 3125 __ srl(dst_reg, 16, O7); 3126 __ or3(dst_reg, O7, dst_reg); 3127 %} 3128 3129 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3130 MacroAssembler _masm(&cbuf); 3131 Register src_reg = reg_to_register_object($src$$reg); 3132 Register dst_reg = reg_to_register_object($dst$$reg); 3133 __ sllx(src_reg, 48, dst_reg); 3134 __ srlx(dst_reg, 16, O7); 3135 __ or3 (dst_reg, O7, dst_reg); 3136 __ srlx(dst_reg, 32, O7); 3137 __ or3 (dst_reg, O7, dst_reg); 3138 %} 3139 3140 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3141 MacroAssembler _masm(&cbuf); 3142 Register src_reg = reg_to_register_object($src$$reg); 3143 Register dst_reg = reg_to_register_object($dst$$reg); 3144 __ sllx(src_reg, 32, dst_reg); 3145 __ srlx(dst_reg, 32, O7); 3146 __ or3 (dst_reg, O7, dst_reg); 3147 %} 3148 3149%} 3150 3151//----------FRAME-------------------------------------------------------------- 3152// Definition of frame structure and management information. 3153// 3154// S T A C K L A Y O U T Allocators stack-slot number 3155// | (to get allocators register number 3156// G Owned by | | v add VMRegImpl::stack0) 3157// r CALLER | | 3158// o | +--------+ pad to even-align allocators stack-slot 3159// w V | pad0 | numbers; owned by CALLER 3160// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3161// h ^ | in | 5 3162// | | args | 4 Holes in incoming args owned by SELF 3163// | | | | 3 3164// | | +--------+ 3165// V | | old out| Empty on Intel, window on Sparc 3166// | old |preserve| Must be even aligned. 3167// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3168// | | in | 3 area for Intel ret address 3169// Owned by |preserve| Empty on Sparc. 3170// SELF +--------+ 3171// | | pad2 | 2 pad to align old SP 3172// | +--------+ 1 3173// | | locks | 0 3174// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3175// | | pad1 | 11 pad to align new SP 3176// | +--------+ 3177// | | | 10 3178// | | spills | 9 spills 3179// V | | 8 (pad0 slot for callee) 3180// -----------+--------+----> Matcher::_out_arg_limit, unaligned 3181// ^ | out | 7 3182// | | args | 6 Holes in outgoing args owned by CALLEE 3183// Owned by +--------+ 3184// CALLEE | new out| 6 Empty on Intel, window on Sparc 3185// | new |preserve| Must be even-aligned. 3186// | SP-+--------+----> Matcher::_new_SP, even aligned 3187// | | | 3188// 3189// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3190// known from SELF's arguments and the Java calling convention. 3191// Region 6-7 is determined per call site. 3192// Note 2: If the calling convention leaves holes in the incoming argument 3193// area, those holes are owned by SELF. Holes in the outgoing area 3194// are owned by the CALLEE. Holes should not be nessecary in the 3195// incoming area, as the Java calling convention is completely under 3196// the control of the AD file. Doubles can be sorted and packed to 3197// avoid holes. Holes in the outgoing arguments may be nessecary for 3198// varargs C calling conventions. 3199// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3200// even aligned with pad0 as needed. 3201// Region 6 is even aligned. Region 6-7 is NOT even aligned; 3202// region 6-11 is even aligned; it may be padded out more so that 3203// the region from SP to FP meets the minimum stack alignment. 3204 3205frame %{ 3206 // What direction does stack grow in (assumed to be same for native & Java) 3207 stack_direction(TOWARDS_LOW); 3208 3209 // These two registers define part of the calling convention 3210 // between compiled code and the interpreter. 3211 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3212 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3213 3214 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3215 cisc_spilling_operand_name(indOffset); 3216 3217 // Number of stack slots consumed by a Monitor enter 3218#ifdef _LP64 3219 sync_stack_slots(2); 3220#else 3221 sync_stack_slots(1); 3222#endif 3223 3224 // Compiled code's Frame Pointer 3225 frame_pointer(R_SP); 3226 3227 // Stack alignment requirement 3228 stack_alignment(StackAlignmentInBytes); 3229 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3230 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3231 3232 // Number of stack slots between incoming argument block and the start of 3233 // a new frame. The PROLOG must add this many slots to the stack. The 3234 // EPILOG must remove this many slots. 3235 in_preserve_stack_slots(0); 3236 3237 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3238 // for calls to C. Supports the var-args backing area for register parms. 3239 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3240#ifdef _LP64 3241 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3242 varargs_C_out_slots_killed(12); 3243#else 3244 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3245 varargs_C_out_slots_killed( 7); 3246#endif 3247 3248 // The after-PROLOG location of the return address. Location of 3249 // return address specifies a type (REG or STACK) and a number 3250 // representing the register number (i.e. - use a register name) or 3251 // stack slot. 3252 return_addr(REG R_I7); // Ret Addr is in register I7 3253 3254 // Body of function which returns an OptoRegs array locating 3255 // arguments either in registers or in stack slots for calling 3256 // java 3257 calling_convention %{ 3258 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3259 3260 %} 3261 3262 // Body of function which returns an OptoRegs array locating 3263 // arguments either in registers or in stack slots for callin 3264 // C. 3265 c_calling_convention %{ 3266 // This is obviously always outgoing 3267 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3268 %} 3269 3270 // Location of native (C/C++) and interpreter return values. This is specified to 3271 // be the same as Java. In the 32-bit VM, long values are actually returned from 3272 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3273 // to and from the register pairs is done by the appropriate call and epilog 3274 // opcodes. This simplifies the register allocator. 3275 c_return_value %{ 3276 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3277#ifdef _LP64 3278 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3279 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3280 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3281 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3282#else // !_LP64 3283 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3284 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3285 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3286 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3287#endif 3288 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3289 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3290 %} 3291 3292 // Location of compiled Java return values. Same as C 3293 return_value %{ 3294 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3295#ifdef _LP64 3296 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3297 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3298 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3299 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3300#else // !_LP64 3301 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3302 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3303 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3304 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3305#endif 3306 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3307 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3308 %} 3309 3310%} 3311 3312 3313//----------ATTRIBUTES--------------------------------------------------------- 3314//----------Operand Attributes------------------------------------------------- 3315op_attrib op_cost(1); // Required cost attribute 3316 3317//----------Instruction Attributes--------------------------------------------- 3318ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3319ins_attrib ins_size(32); // Required size attribute (in bits) 3320ins_attrib ins_avoid_back_to_back(0); // instruction should not be generated back to back 3321ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3322 // non-matching short branch variant of some 3323 // long branch? 3324 3325//----------OPERANDS----------------------------------------------------------- 3326// Operand definitions must precede instruction definitions for correct parsing 3327// in the ADLC because operands constitute user defined types which are used in 3328// instruction definitions. 3329 3330//----------Simple Operands---------------------------------------------------- 3331// Immediate Operands 3332// Integer Immediate: 32-bit 3333operand immI() %{ 3334 match(ConI); 3335 3336 op_cost(0); 3337 // formats are generated automatically for constants and base registers 3338 format %{ %} 3339 interface(CONST_INTER); 3340%} 3341 3342// Integer Immediate: 8-bit 3343operand immI8() %{ 3344 predicate(Assembler::is_simm(n->get_int(), 8)); 3345 match(ConI); 3346 op_cost(0); 3347 format %{ %} 3348 interface(CONST_INTER); 3349%} 3350 3351// Integer Immediate: 13-bit 3352operand immI13() %{ 3353 predicate(Assembler::is_simm13(n->get_int())); 3354 match(ConI); 3355 op_cost(0); 3356 3357 format %{ %} 3358 interface(CONST_INTER); 3359%} 3360 3361// Integer Immediate: 13-bit minus 7 3362operand immI13m7() %{ 3363 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3364 match(ConI); 3365 op_cost(0); 3366 3367 format %{ %} 3368 interface(CONST_INTER); 3369%} 3370 3371// Integer Immediate: 16-bit 3372operand immI16() %{ 3373 predicate(Assembler::is_simm(n->get_int(), 16)); 3374 match(ConI); 3375 op_cost(0); 3376 format %{ %} 3377 interface(CONST_INTER); 3378%} 3379 3380// Unsigned (positive) Integer Immediate: 13-bit 3381operand immU13() %{ 3382 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3383 match(ConI); 3384 op_cost(0); 3385 3386 format %{ %} 3387 interface(CONST_INTER); 3388%} 3389 3390// Integer Immediate: 6-bit 3391operand immU6() %{ 3392 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3393 match(ConI); 3394 op_cost(0); 3395 format %{ %} 3396 interface(CONST_INTER); 3397%} 3398 3399// Integer Immediate: 11-bit 3400operand immI11() %{ 3401 predicate(Assembler::is_simm(n->get_int(),11)); 3402 match(ConI); 3403 op_cost(0); 3404 format %{ %} 3405 interface(CONST_INTER); 3406%} 3407 3408// Integer Immediate: 5-bit 3409operand immI5() %{ 3410 predicate(Assembler::is_simm(n->get_int(), 5)); 3411 match(ConI); 3412 op_cost(0); 3413 format %{ %} 3414 interface(CONST_INTER); 3415%} 3416 3417// Integer Immediate: 0-bit 3418operand immI0() %{ 3419 predicate(n->get_int() == 0); 3420 match(ConI); 3421 op_cost(0); 3422 3423 format %{ %} 3424 interface(CONST_INTER); 3425%} 3426 3427// Integer Immediate: the value 10 3428operand immI10() %{ 3429 predicate(n->get_int() == 10); 3430 match(ConI); 3431 op_cost(0); 3432 3433 format %{ %} 3434 interface(CONST_INTER); 3435%} 3436 3437// Integer Immediate: the values 0-31 3438operand immU5() %{ 3439 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3440 match(ConI); 3441 op_cost(0); 3442 3443 format %{ %} 3444 interface(CONST_INTER); 3445%} 3446 3447// Integer Immediate: the values 1-31 3448operand immI_1_31() %{ 3449 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3450 match(ConI); 3451 op_cost(0); 3452 3453 format %{ %} 3454 interface(CONST_INTER); 3455%} 3456 3457// Integer Immediate: the values 32-63 3458operand immI_32_63() %{ 3459 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3460 match(ConI); 3461 op_cost(0); 3462 3463 format %{ %} 3464 interface(CONST_INTER); 3465%} 3466 3467// Immediates for special shifts (sign extend) 3468 3469// Integer Immediate: the value 16 3470operand immI_16() %{ 3471 predicate(n->get_int() == 16); 3472 match(ConI); 3473 op_cost(0); 3474 3475 format %{ %} 3476 interface(CONST_INTER); 3477%} 3478 3479// Integer Immediate: the value 24 3480operand immI_24() %{ 3481 predicate(n->get_int() == 24); 3482 match(ConI); 3483 op_cost(0); 3484 3485 format %{ %} 3486 interface(CONST_INTER); 3487%} 3488 3489// Integer Immediate: the value 255 3490operand immI_255() %{ 3491 predicate( n->get_int() == 255 ); 3492 match(ConI); 3493 op_cost(0); 3494 3495 format %{ %} 3496 interface(CONST_INTER); 3497%} 3498 3499// Integer Immediate: the value 65535 3500operand immI_65535() %{ 3501 predicate(n->get_int() == 65535); 3502 match(ConI); 3503 op_cost(0); 3504 3505 format %{ %} 3506 interface(CONST_INTER); 3507%} 3508 3509// Long Immediate: the value FF 3510operand immL_FF() %{ 3511 predicate( n->get_long() == 0xFFL ); 3512 match(ConL); 3513 op_cost(0); 3514 3515 format %{ %} 3516 interface(CONST_INTER); 3517%} 3518 3519// Long Immediate: the value FFFF 3520operand immL_FFFF() %{ 3521 predicate( n->get_long() == 0xFFFFL ); 3522 match(ConL); 3523 op_cost(0); 3524 3525 format %{ %} 3526 interface(CONST_INTER); 3527%} 3528 3529// Pointer Immediate: 32 or 64-bit 3530operand immP() %{ 3531 match(ConP); 3532 3533 op_cost(5); 3534 // formats are generated automatically for constants and base registers 3535 format %{ %} 3536 interface(CONST_INTER); 3537%} 3538 3539#ifdef _LP64 3540// Pointer Immediate: 64-bit 3541operand immP_set() %{ 3542 predicate(!VM_Version::is_niagara_plus()); 3543 match(ConP); 3544 3545 op_cost(5); 3546 // formats are generated automatically for constants and base registers 3547 format %{ %} 3548 interface(CONST_INTER); 3549%} 3550 3551// Pointer Immediate: 64-bit 3552// From Niagara2 processors on a load should be better than materializing. 3553operand immP_load() %{ 3554 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3555 match(ConP); 3556 3557 op_cost(5); 3558 // formats are generated automatically for constants and base registers 3559 format %{ %} 3560 interface(CONST_INTER); 3561%} 3562 3563// Pointer Immediate: 64-bit 3564operand immP_no_oop_cheap() %{ 3565 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3566 match(ConP); 3567 3568 op_cost(5); 3569 // formats are generated automatically for constants and base registers 3570 format %{ %} 3571 interface(CONST_INTER); 3572%} 3573#endif 3574 3575operand immP13() %{ 3576 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3577 match(ConP); 3578 op_cost(0); 3579 3580 format %{ %} 3581 interface(CONST_INTER); 3582%} 3583 3584operand immP0() %{ 3585 predicate(n->get_ptr() == 0); 3586 match(ConP); 3587 op_cost(0); 3588 3589 format %{ %} 3590 interface(CONST_INTER); 3591%} 3592 3593operand immP_poll() %{ 3594 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3595 match(ConP); 3596 3597 // formats are generated automatically for constants and base registers 3598 format %{ %} 3599 interface(CONST_INTER); 3600%} 3601 3602// Pointer Immediate 3603operand immN() 3604%{ 3605 match(ConN); 3606 3607 op_cost(10); 3608 format %{ %} 3609 interface(CONST_INTER); 3610%} 3611 3612// NULL Pointer Immediate 3613operand immN0() 3614%{ 3615 predicate(n->get_narrowcon() == 0); 3616 match(ConN); 3617 3618 op_cost(0); 3619 format %{ %} 3620 interface(CONST_INTER); 3621%} 3622 3623operand immL() %{ 3624 match(ConL); 3625 op_cost(40); 3626 // formats are generated automatically for constants and base registers 3627 format %{ %} 3628 interface(CONST_INTER); 3629%} 3630 3631operand immL0() %{ 3632 predicate(n->get_long() == 0L); 3633 match(ConL); 3634 op_cost(0); 3635 // formats are generated automatically for constants and base registers 3636 format %{ %} 3637 interface(CONST_INTER); 3638%} 3639 3640// Integer Immediate: 5-bit 3641operand immL5() %{ 3642 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm((int)n->get_long(), 5)); 3643 match(ConL); 3644 op_cost(0); 3645 format %{ %} 3646 interface(CONST_INTER); 3647%} 3648 3649// Long Immediate: 13-bit 3650operand immL13() %{ 3651 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3652 match(ConL); 3653 op_cost(0); 3654 3655 format %{ %} 3656 interface(CONST_INTER); 3657%} 3658 3659// Long Immediate: 13-bit minus 7 3660operand immL13m7() %{ 3661 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3662 match(ConL); 3663 op_cost(0); 3664 3665 format %{ %} 3666 interface(CONST_INTER); 3667%} 3668 3669// Long Immediate: low 32-bit mask 3670operand immL_32bits() %{ 3671 predicate(n->get_long() == 0xFFFFFFFFL); 3672 match(ConL); 3673 op_cost(0); 3674 3675 format %{ %} 3676 interface(CONST_INTER); 3677%} 3678 3679// Long Immediate: cheap (materialize in <= 3 instructions) 3680operand immL_cheap() %{ 3681 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3682 match(ConL); 3683 op_cost(0); 3684 3685 format %{ %} 3686 interface(CONST_INTER); 3687%} 3688 3689// Long Immediate: expensive (materialize in > 3 instructions) 3690operand immL_expensive() %{ 3691 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3692 match(ConL); 3693 op_cost(0); 3694 3695 format %{ %} 3696 interface(CONST_INTER); 3697%} 3698 3699// Double Immediate 3700operand immD() %{ 3701 match(ConD); 3702 3703 op_cost(40); 3704 format %{ %} 3705 interface(CONST_INTER); 3706%} 3707 3708operand immD0() %{ 3709#ifdef _LP64 3710 // on 64-bit architectures this comparision is faster 3711 predicate(jlong_cast(n->getd()) == 0); 3712#else 3713 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3714#endif 3715 match(ConD); 3716 3717 op_cost(0); 3718 format %{ %} 3719 interface(CONST_INTER); 3720%} 3721 3722// Float Immediate 3723operand immF() %{ 3724 match(ConF); 3725 3726 op_cost(20); 3727 format %{ %} 3728 interface(CONST_INTER); 3729%} 3730 3731// Float Immediate: 0 3732operand immF0() %{ 3733 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3734 match(ConF); 3735 3736 op_cost(0); 3737 format %{ %} 3738 interface(CONST_INTER); 3739%} 3740 3741// Integer Register Operands 3742// Integer Register 3743operand iRegI() %{ 3744 constraint(ALLOC_IN_RC(int_reg)); 3745 match(RegI); 3746 3747 match(notemp_iRegI); 3748 match(g1RegI); 3749 match(o0RegI); 3750 match(iRegIsafe); 3751 3752 format %{ %} 3753 interface(REG_INTER); 3754%} 3755 3756operand notemp_iRegI() %{ 3757 constraint(ALLOC_IN_RC(notemp_int_reg)); 3758 match(RegI); 3759 3760 match(o0RegI); 3761 3762 format %{ %} 3763 interface(REG_INTER); 3764%} 3765 3766operand o0RegI() %{ 3767 constraint(ALLOC_IN_RC(o0_regI)); 3768 match(iRegI); 3769 3770 format %{ %} 3771 interface(REG_INTER); 3772%} 3773 3774// Pointer Register 3775operand iRegP() %{ 3776 constraint(ALLOC_IN_RC(ptr_reg)); 3777 match(RegP); 3778 3779 match(lock_ptr_RegP); 3780 match(g1RegP); 3781 match(g2RegP); 3782 match(g3RegP); 3783 match(g4RegP); 3784 match(i0RegP); 3785 match(o0RegP); 3786 match(o1RegP); 3787 match(l7RegP); 3788 3789 format %{ %} 3790 interface(REG_INTER); 3791%} 3792 3793operand sp_ptr_RegP() %{ 3794 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3795 match(RegP); 3796 match(iRegP); 3797 3798 format %{ %} 3799 interface(REG_INTER); 3800%} 3801 3802operand lock_ptr_RegP() %{ 3803 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3804 match(RegP); 3805 match(i0RegP); 3806 match(o0RegP); 3807 match(o1RegP); 3808 match(l7RegP); 3809 3810 format %{ %} 3811 interface(REG_INTER); 3812%} 3813 3814operand g1RegP() %{ 3815 constraint(ALLOC_IN_RC(g1_regP)); 3816 match(iRegP); 3817 3818 format %{ %} 3819 interface(REG_INTER); 3820%} 3821 3822operand g2RegP() %{ 3823 constraint(ALLOC_IN_RC(g2_regP)); 3824 match(iRegP); 3825 3826 format %{ %} 3827 interface(REG_INTER); 3828%} 3829 3830operand g3RegP() %{ 3831 constraint(ALLOC_IN_RC(g3_regP)); 3832 match(iRegP); 3833 3834 format %{ %} 3835 interface(REG_INTER); 3836%} 3837 3838operand g1RegI() %{ 3839 constraint(ALLOC_IN_RC(g1_regI)); 3840 match(iRegI); 3841 3842 format %{ %} 3843 interface(REG_INTER); 3844%} 3845 3846operand g3RegI() %{ 3847 constraint(ALLOC_IN_RC(g3_regI)); 3848 match(iRegI); 3849 3850 format %{ %} 3851 interface(REG_INTER); 3852%} 3853 3854operand g4RegI() %{ 3855 constraint(ALLOC_IN_RC(g4_regI)); 3856 match(iRegI); 3857 3858 format %{ %} 3859 interface(REG_INTER); 3860%} 3861 3862operand g4RegP() %{ 3863 constraint(ALLOC_IN_RC(g4_regP)); 3864 match(iRegP); 3865 3866 format %{ %} 3867 interface(REG_INTER); 3868%} 3869 3870operand i0RegP() %{ 3871 constraint(ALLOC_IN_RC(i0_regP)); 3872 match(iRegP); 3873 3874 format %{ %} 3875 interface(REG_INTER); 3876%} 3877 3878operand o0RegP() %{ 3879 constraint(ALLOC_IN_RC(o0_regP)); 3880 match(iRegP); 3881 3882 format %{ %} 3883 interface(REG_INTER); 3884%} 3885 3886operand o1RegP() %{ 3887 constraint(ALLOC_IN_RC(o1_regP)); 3888 match(iRegP); 3889 3890 format %{ %} 3891 interface(REG_INTER); 3892%} 3893 3894operand o2RegP() %{ 3895 constraint(ALLOC_IN_RC(o2_regP)); 3896 match(iRegP); 3897 3898 format %{ %} 3899 interface(REG_INTER); 3900%} 3901 3902operand o7RegP() %{ 3903 constraint(ALLOC_IN_RC(o7_regP)); 3904 match(iRegP); 3905 3906 format %{ %} 3907 interface(REG_INTER); 3908%} 3909 3910operand l7RegP() %{ 3911 constraint(ALLOC_IN_RC(l7_regP)); 3912 match(iRegP); 3913 3914 format %{ %} 3915 interface(REG_INTER); 3916%} 3917 3918operand o7RegI() %{ 3919 constraint(ALLOC_IN_RC(o7_regI)); 3920 match(iRegI); 3921 3922 format %{ %} 3923 interface(REG_INTER); 3924%} 3925 3926operand iRegN() %{ 3927 constraint(ALLOC_IN_RC(int_reg)); 3928 match(RegN); 3929 3930 format %{ %} 3931 interface(REG_INTER); 3932%} 3933 3934// Long Register 3935operand iRegL() %{ 3936 constraint(ALLOC_IN_RC(long_reg)); 3937 match(RegL); 3938 3939 format %{ %} 3940 interface(REG_INTER); 3941%} 3942 3943operand o2RegL() %{ 3944 constraint(ALLOC_IN_RC(o2_regL)); 3945 match(iRegL); 3946 3947 format %{ %} 3948 interface(REG_INTER); 3949%} 3950 3951operand o7RegL() %{ 3952 constraint(ALLOC_IN_RC(o7_regL)); 3953 match(iRegL); 3954 3955 format %{ %} 3956 interface(REG_INTER); 3957%} 3958 3959operand g1RegL() %{ 3960 constraint(ALLOC_IN_RC(g1_regL)); 3961 match(iRegL); 3962 3963 format %{ %} 3964 interface(REG_INTER); 3965%} 3966 3967operand g3RegL() %{ 3968 constraint(ALLOC_IN_RC(g3_regL)); 3969 match(iRegL); 3970 3971 format %{ %} 3972 interface(REG_INTER); 3973%} 3974 3975// Int Register safe 3976// This is 64bit safe 3977operand iRegIsafe() %{ 3978 constraint(ALLOC_IN_RC(long_reg)); 3979 3980 match(iRegI); 3981 3982 format %{ %} 3983 interface(REG_INTER); 3984%} 3985 3986// Condition Code Flag Register 3987operand flagsReg() %{ 3988 constraint(ALLOC_IN_RC(int_flags)); 3989 match(RegFlags); 3990 3991 format %{ "ccr" %} // both ICC and XCC 3992 interface(REG_INTER); 3993%} 3994 3995// Condition Code Register, unsigned comparisons. 3996operand flagsRegU() %{ 3997 constraint(ALLOC_IN_RC(int_flags)); 3998 match(RegFlags); 3999 4000 format %{ "icc_U" %} 4001 interface(REG_INTER); 4002%} 4003 4004// Condition Code Register, pointer comparisons. 4005operand flagsRegP() %{ 4006 constraint(ALLOC_IN_RC(int_flags)); 4007 match(RegFlags); 4008 4009#ifdef _LP64 4010 format %{ "xcc_P" %} 4011#else 4012 format %{ "icc_P" %} 4013#endif 4014 interface(REG_INTER); 4015%} 4016 4017// Condition Code Register, long comparisons. 4018operand flagsRegL() %{ 4019 constraint(ALLOC_IN_RC(int_flags)); 4020 match(RegFlags); 4021 4022 format %{ "xcc_L" %} 4023 interface(REG_INTER); 4024%} 4025 4026// Condition Code Register, floating comparisons, unordered same as "less". 4027operand flagsRegF() %{ 4028 constraint(ALLOC_IN_RC(float_flags)); 4029 match(RegFlags); 4030 match(flagsRegF0); 4031 4032 format %{ %} 4033 interface(REG_INTER); 4034%} 4035 4036operand flagsRegF0() %{ 4037 constraint(ALLOC_IN_RC(float_flag0)); 4038 match(RegFlags); 4039 4040 format %{ %} 4041 interface(REG_INTER); 4042%} 4043 4044 4045// Condition Code Flag Register used by long compare 4046operand flagsReg_long_LTGE() %{ 4047 constraint(ALLOC_IN_RC(int_flags)); 4048 match(RegFlags); 4049 format %{ "icc_LTGE" %} 4050 interface(REG_INTER); 4051%} 4052operand flagsReg_long_EQNE() %{ 4053 constraint(ALLOC_IN_RC(int_flags)); 4054 match(RegFlags); 4055 format %{ "icc_EQNE" %} 4056 interface(REG_INTER); 4057%} 4058operand flagsReg_long_LEGT() %{ 4059 constraint(ALLOC_IN_RC(int_flags)); 4060 match(RegFlags); 4061 format %{ "icc_LEGT" %} 4062 interface(REG_INTER); 4063%} 4064 4065 4066operand regD() %{ 4067 constraint(ALLOC_IN_RC(dflt_reg)); 4068 match(RegD); 4069 4070 match(regD_low); 4071 4072 format %{ %} 4073 interface(REG_INTER); 4074%} 4075 4076operand regF() %{ 4077 constraint(ALLOC_IN_RC(sflt_reg)); 4078 match(RegF); 4079 4080 format %{ %} 4081 interface(REG_INTER); 4082%} 4083 4084operand regD_low() %{ 4085 constraint(ALLOC_IN_RC(dflt_low_reg)); 4086 match(regD); 4087 4088 format %{ %} 4089 interface(REG_INTER); 4090%} 4091 4092// Special Registers 4093 4094// Method Register 4095operand inline_cache_regP(iRegP reg) %{ 4096 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4097 match(reg); 4098 format %{ %} 4099 interface(REG_INTER); 4100%} 4101 4102operand interpreter_method_oop_regP(iRegP reg) %{ 4103 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4104 match(reg); 4105 format %{ %} 4106 interface(REG_INTER); 4107%} 4108 4109 4110//----------Complex Operands--------------------------------------------------- 4111// Indirect Memory Reference 4112operand indirect(sp_ptr_RegP reg) %{ 4113 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4114 match(reg); 4115 4116 op_cost(100); 4117 format %{ "[$reg]" %} 4118 interface(MEMORY_INTER) %{ 4119 base($reg); 4120 index(0x0); 4121 scale(0x0); 4122 disp(0x0); 4123 %} 4124%} 4125 4126// Indirect with simm13 Offset 4127operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4128 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4129 match(AddP reg offset); 4130 4131 op_cost(100); 4132 format %{ "[$reg + $offset]" %} 4133 interface(MEMORY_INTER) %{ 4134 base($reg); 4135 index(0x0); 4136 scale(0x0); 4137 disp($offset); 4138 %} 4139%} 4140 4141// Indirect with simm13 Offset minus 7 4142operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4143 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4144 match(AddP reg offset); 4145 4146 op_cost(100); 4147 format %{ "[$reg + $offset]" %} 4148 interface(MEMORY_INTER) %{ 4149 base($reg); 4150 index(0x0); 4151 scale(0x0); 4152 disp($offset); 4153 %} 4154%} 4155 4156// Note: Intel has a swapped version also, like this: 4157//operand indOffsetX(iRegI reg, immP offset) %{ 4158// constraint(ALLOC_IN_RC(int_reg)); 4159// match(AddP offset reg); 4160// 4161// op_cost(100); 4162// format %{ "[$reg + $offset]" %} 4163// interface(MEMORY_INTER) %{ 4164// base($reg); 4165// index(0x0); 4166// scale(0x0); 4167// disp($offset); 4168// %} 4169//%} 4170//// However, it doesn't make sense for SPARC, since 4171// we have no particularly good way to embed oops in 4172// single instructions. 4173 4174// Indirect with Register Index 4175operand indIndex(iRegP addr, iRegX index) %{ 4176 constraint(ALLOC_IN_RC(ptr_reg)); 4177 match(AddP addr index); 4178 4179 op_cost(100); 4180 format %{ "[$addr + $index]" %} 4181 interface(MEMORY_INTER) %{ 4182 base($addr); 4183 index($index); 4184 scale(0x0); 4185 disp(0x0); 4186 %} 4187%} 4188 4189//----------Special Memory Operands-------------------------------------------- 4190// Stack Slot Operand - This operand is used for loading and storing temporary 4191// values on the stack where a match requires a value to 4192// flow through memory. 4193operand stackSlotI(sRegI reg) %{ 4194 constraint(ALLOC_IN_RC(stack_slots)); 4195 op_cost(100); 4196 //match(RegI); 4197 format %{ "[$reg]" %} 4198 interface(MEMORY_INTER) %{ 4199 base(0xE); // R_SP 4200 index(0x0); 4201 scale(0x0); 4202 disp($reg); // Stack Offset 4203 %} 4204%} 4205 4206operand stackSlotP(sRegP reg) %{ 4207 constraint(ALLOC_IN_RC(stack_slots)); 4208 op_cost(100); 4209 //match(RegP); 4210 format %{ "[$reg]" %} 4211 interface(MEMORY_INTER) %{ 4212 base(0xE); // R_SP 4213 index(0x0); 4214 scale(0x0); 4215 disp($reg); // Stack Offset 4216 %} 4217%} 4218 4219operand stackSlotF(sRegF reg) %{ 4220 constraint(ALLOC_IN_RC(stack_slots)); 4221 op_cost(100); 4222 //match(RegF); 4223 format %{ "[$reg]" %} 4224 interface(MEMORY_INTER) %{ 4225 base(0xE); // R_SP 4226 index(0x0); 4227 scale(0x0); 4228 disp($reg); // Stack Offset 4229 %} 4230%} 4231operand stackSlotD(sRegD reg) %{ 4232 constraint(ALLOC_IN_RC(stack_slots)); 4233 op_cost(100); 4234 //match(RegD); 4235 format %{ "[$reg]" %} 4236 interface(MEMORY_INTER) %{ 4237 base(0xE); // R_SP 4238 index(0x0); 4239 scale(0x0); 4240 disp($reg); // Stack Offset 4241 %} 4242%} 4243operand stackSlotL(sRegL reg) %{ 4244 constraint(ALLOC_IN_RC(stack_slots)); 4245 op_cost(100); 4246 //match(RegL); 4247 format %{ "[$reg]" %} 4248 interface(MEMORY_INTER) %{ 4249 base(0xE); // R_SP 4250 index(0x0); 4251 scale(0x0); 4252 disp($reg); // Stack Offset 4253 %} 4254%} 4255 4256// Operands for expressing Control Flow 4257// NOTE: Label is a predefined operand which should not be redefined in 4258// the AD file. It is generically handled within the ADLC. 4259 4260//----------Conditional Branch Operands---------------------------------------- 4261// Comparison Op - This is the operation of the comparison, and is limited to 4262// the following set of codes: 4263// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4264// 4265// Other attributes of the comparison, such as unsignedness, are specified 4266// by the comparison instruction that sets a condition code flags register. 4267// That result is represented by a flags operand whose subtype is appropriate 4268// to the unsignedness (etc.) of the comparison. 4269// 4270// Later, the instruction which matches both the Comparison Op (a Bool) and 4271// the flags (produced by the Cmp) specifies the coding of the comparison op 4272// by matching a specific subtype of Bool operand below, such as cmpOpU. 4273 4274operand cmpOp() %{ 4275 match(Bool); 4276 4277 format %{ "" %} 4278 interface(COND_INTER) %{ 4279 equal(0x1); 4280 not_equal(0x9); 4281 less(0x3); 4282 greater_equal(0xB); 4283 less_equal(0x2); 4284 greater(0xA); 4285 %} 4286%} 4287 4288// Comparison Op, unsigned 4289operand cmpOpU() %{ 4290 match(Bool); 4291 4292 format %{ "u" %} 4293 interface(COND_INTER) %{ 4294 equal(0x1); 4295 not_equal(0x9); 4296 less(0x5); 4297 greater_equal(0xD); 4298 less_equal(0x4); 4299 greater(0xC); 4300 %} 4301%} 4302 4303// Comparison Op, pointer (same as unsigned) 4304operand cmpOpP() %{ 4305 match(Bool); 4306 4307 format %{ "p" %} 4308 interface(COND_INTER) %{ 4309 equal(0x1); 4310 not_equal(0x9); 4311 less(0x5); 4312 greater_equal(0xD); 4313 less_equal(0x4); 4314 greater(0xC); 4315 %} 4316%} 4317 4318// Comparison Op, branch-register encoding 4319operand cmpOp_reg() %{ 4320 match(Bool); 4321 4322 format %{ "" %} 4323 interface(COND_INTER) %{ 4324 equal (0x1); 4325 not_equal (0x5); 4326 less (0x3); 4327 greater_equal(0x7); 4328 less_equal (0x2); 4329 greater (0x6); 4330 %} 4331%} 4332 4333// Comparison Code, floating, unordered same as less 4334operand cmpOpF() %{ 4335 match(Bool); 4336 4337 format %{ "fl" %} 4338 interface(COND_INTER) %{ 4339 equal(0x9); 4340 not_equal(0x1); 4341 less(0x3); 4342 greater_equal(0xB); 4343 less_equal(0xE); 4344 greater(0x6); 4345 %} 4346%} 4347 4348// Used by long compare 4349operand cmpOp_commute() %{ 4350 match(Bool); 4351 4352 format %{ "" %} 4353 interface(COND_INTER) %{ 4354 equal(0x1); 4355 not_equal(0x9); 4356 less(0xA); 4357 greater_equal(0x2); 4358 less_equal(0xB); 4359 greater(0x3); 4360 %} 4361%} 4362 4363//----------OPERAND CLASSES---------------------------------------------------- 4364// Operand Classes are groups of operands that are used to simplify 4365// instruction definitions by not requiring the AD writer to specify separate 4366// instructions for every form of operand when the instruction accepts 4367// multiple operand types with the same basic encoding and format. The classic 4368// case of this is memory operands. 4369opclass memory( indirect, indOffset13, indIndex ); 4370opclass indIndexMemory( indIndex ); 4371 4372//----------PIPELINE----------------------------------------------------------- 4373pipeline %{ 4374 4375//----------ATTRIBUTES--------------------------------------------------------- 4376attributes %{ 4377 fixed_size_instructions; // Fixed size instructions 4378 branch_has_delay_slot; // Branch has delay slot following 4379 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4380 instruction_unit_size = 4; // An instruction is 4 bytes long 4381 instruction_fetch_unit_size = 16; // The processor fetches one line 4382 instruction_fetch_units = 1; // of 16 bytes 4383 4384 // List of nop instructions 4385 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4386%} 4387 4388//----------RESOURCES---------------------------------------------------------- 4389// Resources are the functional units available to the machine 4390resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4391 4392//----------PIPELINE DESCRIPTION----------------------------------------------- 4393// Pipeline Description specifies the stages in the machine's pipeline 4394 4395pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4396 4397//----------PIPELINE CLASSES--------------------------------------------------- 4398// Pipeline Classes describe the stages in which input and output are 4399// referenced by the hardware pipeline. 4400 4401// Integer ALU reg-reg operation 4402pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4403 single_instruction; 4404 dst : E(write); 4405 src1 : R(read); 4406 src2 : R(read); 4407 IALU : R; 4408%} 4409 4410// Integer ALU reg-reg long operation 4411pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4412 instruction_count(2); 4413 dst : E(write); 4414 src1 : R(read); 4415 src2 : R(read); 4416 IALU : R; 4417 IALU : R; 4418%} 4419 4420// Integer ALU reg-reg long dependent operation 4421pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4422 instruction_count(1); multiple_bundles; 4423 dst : E(write); 4424 src1 : R(read); 4425 src2 : R(read); 4426 cr : E(write); 4427 IALU : R(2); 4428%} 4429 4430// Integer ALU reg-imm operaion 4431pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4432 single_instruction; 4433 dst : E(write); 4434 src1 : R(read); 4435 IALU : R; 4436%} 4437 4438// Integer ALU reg-reg operation with condition code 4439pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4440 single_instruction; 4441 dst : E(write); 4442 cr : E(write); 4443 src1 : R(read); 4444 src2 : R(read); 4445 IALU : R; 4446%} 4447 4448// Integer ALU reg-imm operation with condition code 4449pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4450 single_instruction; 4451 dst : E(write); 4452 cr : E(write); 4453 src1 : R(read); 4454 IALU : R; 4455%} 4456 4457// Integer ALU zero-reg operation 4458pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4459 single_instruction; 4460 dst : E(write); 4461 src2 : R(read); 4462 IALU : R; 4463%} 4464 4465// Integer ALU zero-reg operation with condition code only 4466pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4467 single_instruction; 4468 cr : E(write); 4469 src : R(read); 4470 IALU : R; 4471%} 4472 4473// Integer ALU reg-reg operation with condition code only 4474pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4475 single_instruction; 4476 cr : E(write); 4477 src1 : R(read); 4478 src2 : R(read); 4479 IALU : R; 4480%} 4481 4482// Integer ALU reg-imm operation with condition code only 4483pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4484 single_instruction; 4485 cr : E(write); 4486 src1 : R(read); 4487 IALU : R; 4488%} 4489 4490// Integer ALU reg-reg-zero operation with condition code only 4491pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4492 single_instruction; 4493 cr : E(write); 4494 src1 : R(read); 4495 src2 : R(read); 4496 IALU : R; 4497%} 4498 4499// Integer ALU reg-imm-zero operation with condition code only 4500pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4501 single_instruction; 4502 cr : E(write); 4503 src1 : R(read); 4504 IALU : R; 4505%} 4506 4507// Integer ALU reg-reg operation with condition code, src1 modified 4508pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4509 single_instruction; 4510 cr : E(write); 4511 src1 : E(write); 4512 src1 : R(read); 4513 src2 : R(read); 4514 IALU : R; 4515%} 4516 4517// Integer ALU reg-imm operation with condition code, src1 modified 4518pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4519 single_instruction; 4520 cr : E(write); 4521 src1 : E(write); 4522 src1 : R(read); 4523 IALU : R; 4524%} 4525 4526pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4527 multiple_bundles; 4528 dst : E(write)+4; 4529 cr : E(write); 4530 src1 : R(read); 4531 src2 : R(read); 4532 IALU : R(3); 4533 BR : R(2); 4534%} 4535 4536// Integer ALU operation 4537pipe_class ialu_none(iRegI dst) %{ 4538 single_instruction; 4539 dst : E(write); 4540 IALU : R; 4541%} 4542 4543// Integer ALU reg operation 4544pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4545 single_instruction; may_have_no_code; 4546 dst : E(write); 4547 src : R(read); 4548 IALU : R; 4549%} 4550 4551// Integer ALU reg conditional operation 4552// This instruction has a 1 cycle stall, and cannot execute 4553// in the same cycle as the instruction setting the condition 4554// code. We kludge this by pretending to read the condition code 4555// 1 cycle earlier, and by marking the functional units as busy 4556// for 2 cycles with the result available 1 cycle later than 4557// is really the case. 4558pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4559 single_instruction; 4560 op2_out : C(write); 4561 op1 : R(read); 4562 cr : R(read); // This is really E, with a 1 cycle stall 4563 BR : R(2); 4564 MS : R(2); 4565%} 4566 4567#ifdef _LP64 4568pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4569 instruction_count(1); multiple_bundles; 4570 dst : C(write)+1; 4571 src : R(read)+1; 4572 IALU : R(1); 4573 BR : E(2); 4574 MS : E(2); 4575%} 4576#endif 4577 4578// Integer ALU reg operation 4579pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4580 single_instruction; may_have_no_code; 4581 dst : E(write); 4582 src : R(read); 4583 IALU : R; 4584%} 4585pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4586 single_instruction; may_have_no_code; 4587 dst : E(write); 4588 src : R(read); 4589 IALU : R; 4590%} 4591 4592// Two integer ALU reg operations 4593pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4594 instruction_count(2); 4595 dst : E(write); 4596 src : R(read); 4597 A0 : R; 4598 A1 : R; 4599%} 4600 4601// Two integer ALU reg operations 4602pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4603 instruction_count(2); may_have_no_code; 4604 dst : E(write); 4605 src : R(read); 4606 A0 : R; 4607 A1 : R; 4608%} 4609 4610// Integer ALU imm operation 4611pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4612 single_instruction; 4613 dst : E(write); 4614 IALU : R; 4615%} 4616 4617// Integer ALU reg-reg with carry operation 4618pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4619 single_instruction; 4620 dst : E(write); 4621 src1 : R(read); 4622 src2 : R(read); 4623 IALU : R; 4624%} 4625 4626// Integer ALU cc operation 4627pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4628 single_instruction; 4629 dst : E(write); 4630 cc : R(read); 4631 IALU : R; 4632%} 4633 4634// Integer ALU cc / second IALU operation 4635pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4636 instruction_count(1); multiple_bundles; 4637 dst : E(write)+1; 4638 src : R(read); 4639 IALU : R; 4640%} 4641 4642// Integer ALU cc / second IALU operation 4643pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4644 instruction_count(1); multiple_bundles; 4645 dst : E(write)+1; 4646 p : R(read); 4647 q : R(read); 4648 IALU : R; 4649%} 4650 4651// Integer ALU hi-lo-reg operation 4652pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4653 instruction_count(1); multiple_bundles; 4654 dst : E(write)+1; 4655 IALU : R(2); 4656%} 4657 4658// Float ALU hi-lo-reg operation (with temp) 4659pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4660 instruction_count(1); multiple_bundles; 4661 dst : E(write)+1; 4662 IALU : R(2); 4663%} 4664 4665// Long Constant 4666pipe_class loadConL( iRegL dst, immL src ) %{ 4667 instruction_count(2); multiple_bundles; 4668 dst : E(write)+1; 4669 IALU : R(2); 4670 IALU : R(2); 4671%} 4672 4673// Pointer Constant 4674pipe_class loadConP( iRegP dst, immP src ) %{ 4675 instruction_count(0); multiple_bundles; 4676 fixed_latency(6); 4677%} 4678 4679// Polling Address 4680pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4681#ifdef _LP64 4682 instruction_count(0); multiple_bundles; 4683 fixed_latency(6); 4684#else 4685 dst : E(write); 4686 IALU : R; 4687#endif 4688%} 4689 4690// Long Constant small 4691pipe_class loadConLlo( iRegL dst, immL src ) %{ 4692 instruction_count(2); 4693 dst : E(write); 4694 IALU : R; 4695 IALU : R; 4696%} 4697 4698// [PHH] This is wrong for 64-bit. See LdImmF/D. 4699pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4700 instruction_count(1); multiple_bundles; 4701 src : R(read); 4702 dst : M(write)+1; 4703 IALU : R; 4704 MS : E; 4705%} 4706 4707// Integer ALU nop operation 4708pipe_class ialu_nop() %{ 4709 single_instruction; 4710 IALU : R; 4711%} 4712 4713// Integer ALU nop operation 4714pipe_class ialu_nop_A0() %{ 4715 single_instruction; 4716 A0 : R; 4717%} 4718 4719// Integer ALU nop operation 4720pipe_class ialu_nop_A1() %{ 4721 single_instruction; 4722 A1 : R; 4723%} 4724 4725// Integer Multiply reg-reg operation 4726pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4727 single_instruction; 4728 dst : E(write); 4729 src1 : R(read); 4730 src2 : R(read); 4731 MS : R(5); 4732%} 4733 4734// Integer Multiply reg-imm operation 4735pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4736 single_instruction; 4737 dst : E(write); 4738 src1 : R(read); 4739 MS : R(5); 4740%} 4741 4742pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4743 single_instruction; 4744 dst : E(write)+4; 4745 src1 : R(read); 4746 src2 : R(read); 4747 MS : R(6); 4748%} 4749 4750pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4751 single_instruction; 4752 dst : E(write)+4; 4753 src1 : R(read); 4754 MS : R(6); 4755%} 4756 4757// Integer Divide reg-reg 4758pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4759 instruction_count(1); multiple_bundles; 4760 dst : E(write); 4761 temp : E(write); 4762 src1 : R(read); 4763 src2 : R(read); 4764 temp : R(read); 4765 MS : R(38); 4766%} 4767 4768// Integer Divide reg-imm 4769pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4770 instruction_count(1); multiple_bundles; 4771 dst : E(write); 4772 temp : E(write); 4773 src1 : R(read); 4774 temp : R(read); 4775 MS : R(38); 4776%} 4777 4778// Long Divide 4779pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4780 dst : E(write)+71; 4781 src1 : R(read); 4782 src2 : R(read)+1; 4783 MS : R(70); 4784%} 4785 4786pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4787 dst : E(write)+71; 4788 src1 : R(read); 4789 MS : R(70); 4790%} 4791 4792// Floating Point Add Float 4793pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4794 single_instruction; 4795 dst : X(write); 4796 src1 : E(read); 4797 src2 : E(read); 4798 FA : R; 4799%} 4800 4801// Floating Point Add Double 4802pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4803 single_instruction; 4804 dst : X(write); 4805 src1 : E(read); 4806 src2 : E(read); 4807 FA : R; 4808%} 4809 4810// Floating Point Conditional Move based on integer flags 4811pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4812 single_instruction; 4813 dst : X(write); 4814 src : E(read); 4815 cr : R(read); 4816 FA : R(2); 4817 BR : R(2); 4818%} 4819 4820// Floating Point Conditional Move based on integer flags 4821pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4822 single_instruction; 4823 dst : X(write); 4824 src : E(read); 4825 cr : R(read); 4826 FA : R(2); 4827 BR : R(2); 4828%} 4829 4830// Floating Point Multiply Float 4831pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4832 single_instruction; 4833 dst : X(write); 4834 src1 : E(read); 4835 src2 : E(read); 4836 FM : R; 4837%} 4838 4839// Floating Point Multiply Double 4840pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4841 single_instruction; 4842 dst : X(write); 4843 src1 : E(read); 4844 src2 : E(read); 4845 FM : R; 4846%} 4847 4848// Floating Point Divide Float 4849pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4850 single_instruction; 4851 dst : X(write); 4852 src1 : E(read); 4853 src2 : E(read); 4854 FM : R; 4855 FDIV : C(14); 4856%} 4857 4858// Floating Point Divide Double 4859pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4860 single_instruction; 4861 dst : X(write); 4862 src1 : E(read); 4863 src2 : E(read); 4864 FM : R; 4865 FDIV : C(17); 4866%} 4867 4868// Floating Point Move/Negate/Abs Float 4869pipe_class faddF_reg(regF dst, regF src) %{ 4870 single_instruction; 4871 dst : W(write); 4872 src : E(read); 4873 FA : R(1); 4874%} 4875 4876// Floating Point Move/Negate/Abs Double 4877pipe_class faddD_reg(regD dst, regD src) %{ 4878 single_instruction; 4879 dst : W(write); 4880 src : E(read); 4881 FA : R; 4882%} 4883 4884// Floating Point Convert F->D 4885pipe_class fcvtF2D(regD dst, regF src) %{ 4886 single_instruction; 4887 dst : X(write); 4888 src : E(read); 4889 FA : R; 4890%} 4891 4892// Floating Point Convert I->D 4893pipe_class fcvtI2D(regD dst, regF src) %{ 4894 single_instruction; 4895 dst : X(write); 4896 src : E(read); 4897 FA : R; 4898%} 4899 4900// Floating Point Convert LHi->D 4901pipe_class fcvtLHi2D(regD dst, regD src) %{ 4902 single_instruction; 4903 dst : X(write); 4904 src : E(read); 4905 FA : R; 4906%} 4907 4908// Floating Point Convert L->D 4909pipe_class fcvtL2D(regD dst, regF src) %{ 4910 single_instruction; 4911 dst : X(write); 4912 src : E(read); 4913 FA : R; 4914%} 4915 4916// Floating Point Convert L->F 4917pipe_class fcvtL2F(regD dst, regF src) %{ 4918 single_instruction; 4919 dst : X(write); 4920 src : E(read); 4921 FA : R; 4922%} 4923 4924// Floating Point Convert D->F 4925pipe_class fcvtD2F(regD dst, regF src) %{ 4926 single_instruction; 4927 dst : X(write); 4928 src : E(read); 4929 FA : R; 4930%} 4931 4932// Floating Point Convert I->L 4933pipe_class fcvtI2L(regD dst, regF src) %{ 4934 single_instruction; 4935 dst : X(write); 4936 src : E(read); 4937 FA : R; 4938%} 4939 4940// Floating Point Convert D->F 4941pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4942 instruction_count(1); multiple_bundles; 4943 dst : X(write)+6; 4944 src : E(read); 4945 FA : R; 4946%} 4947 4948// Floating Point Convert D->L 4949pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4950 instruction_count(1); multiple_bundles; 4951 dst : X(write)+6; 4952 src : E(read); 4953 FA : R; 4954%} 4955 4956// Floating Point Convert F->I 4957pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4958 instruction_count(1); multiple_bundles; 4959 dst : X(write)+6; 4960 src : E(read); 4961 FA : R; 4962%} 4963 4964// Floating Point Convert F->L 4965pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4966 instruction_count(1); multiple_bundles; 4967 dst : X(write)+6; 4968 src : E(read); 4969 FA : R; 4970%} 4971 4972// Floating Point Convert I->F 4973pipe_class fcvtI2F(regF dst, regF src) %{ 4974 single_instruction; 4975 dst : X(write); 4976 src : E(read); 4977 FA : R; 4978%} 4979 4980// Floating Point Compare 4981pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4982 single_instruction; 4983 cr : X(write); 4984 src1 : E(read); 4985 src2 : E(read); 4986 FA : R; 4987%} 4988 4989// Floating Point Compare 4990pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4991 single_instruction; 4992 cr : X(write); 4993 src1 : E(read); 4994 src2 : E(read); 4995 FA : R; 4996%} 4997 4998// Floating Add Nop 4999pipe_class fadd_nop() %{ 5000 single_instruction; 5001 FA : R; 5002%} 5003 5004// Integer Store to Memory 5005pipe_class istore_mem_reg(memory mem, iRegI src) %{ 5006 single_instruction; 5007 mem : R(read); 5008 src : C(read); 5009 MS : R; 5010%} 5011 5012// Integer Store to Memory 5013pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 5014 single_instruction; 5015 mem : R(read); 5016 src : C(read); 5017 MS : R; 5018%} 5019 5020// Integer Store Zero to Memory 5021pipe_class istore_mem_zero(memory mem, immI0 src) %{ 5022 single_instruction; 5023 mem : R(read); 5024 MS : R; 5025%} 5026 5027// Special Stack Slot Store 5028pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 5029 single_instruction; 5030 stkSlot : R(read); 5031 src : C(read); 5032 MS : R; 5033%} 5034 5035// Special Stack Slot Store 5036pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 5037 instruction_count(2); multiple_bundles; 5038 stkSlot : R(read); 5039 src : C(read); 5040 MS : R(2); 5041%} 5042 5043// Float Store 5044pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 5045 single_instruction; 5046 mem : R(read); 5047 src : C(read); 5048 MS : R; 5049%} 5050 5051// Float Store 5052pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 5053 single_instruction; 5054 mem : R(read); 5055 MS : R; 5056%} 5057 5058// Double Store 5059pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 5060 instruction_count(1); 5061 mem : R(read); 5062 src : C(read); 5063 MS : R; 5064%} 5065 5066// Double Store 5067pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 5068 single_instruction; 5069 mem : R(read); 5070 MS : R; 5071%} 5072 5073// Special Stack Slot Float Store 5074pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 5075 single_instruction; 5076 stkSlot : R(read); 5077 src : C(read); 5078 MS : R; 5079%} 5080 5081// Special Stack Slot Double Store 5082pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 5083 single_instruction; 5084 stkSlot : R(read); 5085 src : C(read); 5086 MS : R; 5087%} 5088 5089// Integer Load (when sign bit propagation not needed) 5090pipe_class iload_mem(iRegI dst, memory mem) %{ 5091 single_instruction; 5092 mem : R(read); 5093 dst : C(write); 5094 MS : R; 5095%} 5096 5097// Integer Load from stack operand 5098pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5099 single_instruction; 5100 mem : R(read); 5101 dst : C(write); 5102 MS : R; 5103%} 5104 5105// Integer Load (when sign bit propagation or masking is needed) 5106pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5107 single_instruction; 5108 mem : R(read); 5109 dst : M(write); 5110 MS : R; 5111%} 5112 5113// Float Load 5114pipe_class floadF_mem(regF dst, memory mem) %{ 5115 single_instruction; 5116 mem : R(read); 5117 dst : M(write); 5118 MS : R; 5119%} 5120 5121// Float Load 5122pipe_class floadD_mem(regD dst, memory mem) %{ 5123 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5124 mem : R(read); 5125 dst : M(write); 5126 MS : R; 5127%} 5128 5129// Float Load 5130pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5131 single_instruction; 5132 stkSlot : R(read); 5133 dst : M(write); 5134 MS : R; 5135%} 5136 5137// Float Load 5138pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5139 single_instruction; 5140 stkSlot : R(read); 5141 dst : M(write); 5142 MS : R; 5143%} 5144 5145// Memory Nop 5146pipe_class mem_nop() %{ 5147 single_instruction; 5148 MS : R; 5149%} 5150 5151pipe_class sethi(iRegP dst, immI src) %{ 5152 single_instruction; 5153 dst : E(write); 5154 IALU : R; 5155%} 5156 5157pipe_class loadPollP(iRegP poll) %{ 5158 single_instruction; 5159 poll : R(read); 5160 MS : R; 5161%} 5162 5163pipe_class br(Universe br, label labl) %{ 5164 single_instruction_with_delay_slot; 5165 BR : R; 5166%} 5167 5168pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5169 single_instruction_with_delay_slot; 5170 cr : E(read); 5171 BR : R; 5172%} 5173 5174pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5175 single_instruction_with_delay_slot; 5176 op1 : E(read); 5177 BR : R; 5178 MS : R; 5179%} 5180 5181// Compare and branch 5182pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 5183 instruction_count(2); has_delay_slot; 5184 cr : E(write); 5185 src1 : R(read); 5186 src2 : R(read); 5187 IALU : R; 5188 BR : R; 5189%} 5190 5191// Compare and branch 5192pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 5193 instruction_count(2); has_delay_slot; 5194 cr : E(write); 5195 src1 : R(read); 5196 IALU : R; 5197 BR : R; 5198%} 5199 5200// Compare and branch using cbcond 5201pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 5202 single_instruction; 5203 src1 : E(read); 5204 src2 : E(read); 5205 IALU : R; 5206 BR : R; 5207%} 5208 5209// Compare and branch using cbcond 5210pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 5211 single_instruction; 5212 src1 : E(read); 5213 IALU : R; 5214 BR : R; 5215%} 5216 5217pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5218 single_instruction_with_delay_slot; 5219 cr : E(read); 5220 BR : R; 5221%} 5222 5223pipe_class br_nop() %{ 5224 single_instruction; 5225 BR : R; 5226%} 5227 5228pipe_class simple_call(method meth) %{ 5229 instruction_count(2); multiple_bundles; force_serialization; 5230 fixed_latency(100); 5231 BR : R(1); 5232 MS : R(1); 5233 A0 : R(1); 5234%} 5235 5236pipe_class compiled_call(method meth) %{ 5237 instruction_count(1); multiple_bundles; force_serialization; 5238 fixed_latency(100); 5239 MS : R(1); 5240%} 5241 5242pipe_class call(method meth) %{ 5243 instruction_count(0); multiple_bundles; force_serialization; 5244 fixed_latency(100); 5245%} 5246 5247pipe_class tail_call(Universe ignore, label labl) %{ 5248 single_instruction; has_delay_slot; 5249 fixed_latency(100); 5250 BR : R(1); 5251 MS : R(1); 5252%} 5253 5254pipe_class ret(Universe ignore) %{ 5255 single_instruction; has_delay_slot; 5256 BR : R(1); 5257 MS : R(1); 5258%} 5259 5260pipe_class ret_poll(g3RegP poll) %{ 5261 instruction_count(3); has_delay_slot; 5262 poll : E(read); 5263 MS : R; 5264%} 5265 5266// The real do-nothing guy 5267pipe_class empty( ) %{ 5268 instruction_count(0); 5269%} 5270 5271pipe_class long_memory_op() %{ 5272 instruction_count(0); multiple_bundles; force_serialization; 5273 fixed_latency(25); 5274 MS : R(1); 5275%} 5276 5277// Check-cast 5278pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5279 array : R(read); 5280 match : R(read); 5281 IALU : R(2); 5282 BR : R(2); 5283 MS : R; 5284%} 5285 5286// Convert FPU flags into +1,0,-1 5287pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5288 src1 : E(read); 5289 src2 : E(read); 5290 dst : E(write); 5291 FA : R; 5292 MS : R(2); 5293 BR : R(2); 5294%} 5295 5296// Compare for p < q, and conditionally add y 5297pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5298 p : E(read); 5299 q : E(read); 5300 y : E(read); 5301 IALU : R(3) 5302%} 5303 5304// Perform a compare, then move conditionally in a branch delay slot. 5305pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5306 src2 : E(read); 5307 srcdst : E(read); 5308 IALU : R; 5309 BR : R; 5310%} 5311 5312// Define the class for the Nop node 5313define %{ 5314 MachNop = ialu_nop; 5315%} 5316 5317%} 5318 5319//----------INSTRUCTIONS------------------------------------------------------- 5320 5321//------------Special Stack Slot instructions - no match rules----------------- 5322instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5323 // No match rule to avoid chain rule match. 5324 effect(DEF dst, USE src); 5325 ins_cost(MEMORY_REF_COST); 5326 size(4); 5327 format %{ "LDF $src,$dst\t! stkI to regF" %} 5328 opcode(Assembler::ldf_op3); 5329 ins_encode(simple_form3_mem_reg(src, dst)); 5330 ins_pipe(floadF_stk); 5331%} 5332 5333instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5334 // No match rule to avoid chain rule match. 5335 effect(DEF dst, USE src); 5336 ins_cost(MEMORY_REF_COST); 5337 size(4); 5338 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5339 opcode(Assembler::lddf_op3); 5340 ins_encode(simple_form3_mem_reg(src, dst)); 5341 ins_pipe(floadD_stk); 5342%} 5343 5344instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5345 // No match rule to avoid chain rule match. 5346 effect(DEF dst, USE src); 5347 ins_cost(MEMORY_REF_COST); 5348 size(4); 5349 format %{ "STF $src,$dst\t! regF to stkI" %} 5350 opcode(Assembler::stf_op3); 5351 ins_encode(simple_form3_mem_reg(dst, src)); 5352 ins_pipe(fstoreF_stk_reg); 5353%} 5354 5355instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5356 // No match rule to avoid chain rule match. 5357 effect(DEF dst, USE src); 5358 ins_cost(MEMORY_REF_COST); 5359 size(4); 5360 format %{ "STDF $src,$dst\t! regD to stkL" %} 5361 opcode(Assembler::stdf_op3); 5362 ins_encode(simple_form3_mem_reg(dst, src)); 5363 ins_pipe(fstoreD_stk_reg); 5364%} 5365 5366instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5367 effect(DEF dst, USE src); 5368 ins_cost(MEMORY_REF_COST*2); 5369 size(8); 5370 format %{ "STW $src,$dst.hi\t! long\n\t" 5371 "STW R_G0,$dst.lo" %} 5372 opcode(Assembler::stw_op3); 5373 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5374 ins_pipe(lstoreI_stk_reg); 5375%} 5376 5377instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5378 // No match rule to avoid chain rule match. 5379 effect(DEF dst, USE src); 5380 ins_cost(MEMORY_REF_COST); 5381 size(4); 5382 format %{ "STX $src,$dst\t! regL to stkD" %} 5383 opcode(Assembler::stx_op3); 5384 ins_encode(simple_form3_mem_reg( dst, src ) ); 5385 ins_pipe(istore_stk_reg); 5386%} 5387 5388//---------- Chain stack slots between similar types -------- 5389 5390// Load integer from stack slot 5391instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5392 match(Set dst src); 5393 ins_cost(MEMORY_REF_COST); 5394 5395 size(4); 5396 format %{ "LDUW $src,$dst\t!stk" %} 5397 opcode(Assembler::lduw_op3); 5398 ins_encode(simple_form3_mem_reg( src, dst ) ); 5399 ins_pipe(iload_mem); 5400%} 5401 5402// Store integer to stack slot 5403instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5404 match(Set dst src); 5405 ins_cost(MEMORY_REF_COST); 5406 5407 size(4); 5408 format %{ "STW $src,$dst\t!stk" %} 5409 opcode(Assembler::stw_op3); 5410 ins_encode(simple_form3_mem_reg( dst, src ) ); 5411 ins_pipe(istore_mem_reg); 5412%} 5413 5414// Load long from stack slot 5415instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5416 match(Set dst src); 5417 5418 ins_cost(MEMORY_REF_COST); 5419 size(4); 5420 format %{ "LDX $src,$dst\t! long" %} 5421 opcode(Assembler::ldx_op3); 5422 ins_encode(simple_form3_mem_reg( src, dst ) ); 5423 ins_pipe(iload_mem); 5424%} 5425 5426// Store long to stack slot 5427instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5428 match(Set dst src); 5429 5430 ins_cost(MEMORY_REF_COST); 5431 size(4); 5432 format %{ "STX $src,$dst\t! long" %} 5433 opcode(Assembler::stx_op3); 5434 ins_encode(simple_form3_mem_reg( dst, src ) ); 5435 ins_pipe(istore_mem_reg); 5436%} 5437 5438#ifdef _LP64 5439// Load pointer from stack slot, 64-bit encoding 5440instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5441 match(Set dst src); 5442 ins_cost(MEMORY_REF_COST); 5443 size(4); 5444 format %{ "LDX $src,$dst\t!ptr" %} 5445 opcode(Assembler::ldx_op3); 5446 ins_encode(simple_form3_mem_reg( src, dst ) ); 5447 ins_pipe(iload_mem); 5448%} 5449 5450// Store pointer to stack slot 5451instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5452 match(Set dst src); 5453 ins_cost(MEMORY_REF_COST); 5454 size(4); 5455 format %{ "STX $src,$dst\t!ptr" %} 5456 opcode(Assembler::stx_op3); 5457 ins_encode(simple_form3_mem_reg( dst, src ) ); 5458 ins_pipe(istore_mem_reg); 5459%} 5460#else // _LP64 5461// Load pointer from stack slot, 32-bit encoding 5462instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5463 match(Set dst src); 5464 ins_cost(MEMORY_REF_COST); 5465 format %{ "LDUW $src,$dst\t!ptr" %} 5466 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5467 ins_encode(simple_form3_mem_reg( src, dst ) ); 5468 ins_pipe(iload_mem); 5469%} 5470 5471// Store pointer to stack slot 5472instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5473 match(Set dst src); 5474 ins_cost(MEMORY_REF_COST); 5475 format %{ "STW $src,$dst\t!ptr" %} 5476 opcode(Assembler::stw_op3, Assembler::ldst_op); 5477 ins_encode(simple_form3_mem_reg( dst, src ) ); 5478 ins_pipe(istore_mem_reg); 5479%} 5480#endif // _LP64 5481 5482//------------Special Nop instructions for bundling - no match rules----------- 5483// Nop using the A0 functional unit 5484instruct Nop_A0() %{ 5485 ins_cost(0); 5486 5487 format %{ "NOP ! Alu Pipeline" %} 5488 opcode(Assembler::or_op3, Assembler::arith_op); 5489 ins_encode( form2_nop() ); 5490 ins_pipe(ialu_nop_A0); 5491%} 5492 5493// Nop using the A1 functional unit 5494instruct Nop_A1( ) %{ 5495 ins_cost(0); 5496 5497 format %{ "NOP ! Alu Pipeline" %} 5498 opcode(Assembler::or_op3, Assembler::arith_op); 5499 ins_encode( form2_nop() ); 5500 ins_pipe(ialu_nop_A1); 5501%} 5502 5503// Nop using the memory functional unit 5504instruct Nop_MS( ) %{ 5505 ins_cost(0); 5506 5507 format %{ "NOP ! Memory Pipeline" %} 5508 ins_encode( emit_mem_nop ); 5509 ins_pipe(mem_nop); 5510%} 5511 5512// Nop using the floating add functional unit 5513instruct Nop_FA( ) %{ 5514 ins_cost(0); 5515 5516 format %{ "NOP ! Floating Add Pipeline" %} 5517 ins_encode( emit_fadd_nop ); 5518 ins_pipe(fadd_nop); 5519%} 5520 5521// Nop using the branch functional unit 5522instruct Nop_BR( ) %{ 5523 ins_cost(0); 5524 5525 format %{ "NOP ! Branch Pipeline" %} 5526 ins_encode( emit_br_nop ); 5527 ins_pipe(br_nop); 5528%} 5529 5530//----------Load/Store/Move Instructions--------------------------------------- 5531//----------Load Instructions-------------------------------------------------- 5532// Load Byte (8bit signed) 5533instruct loadB(iRegI dst, memory mem) %{ 5534 match(Set dst (LoadB mem)); 5535 ins_cost(MEMORY_REF_COST); 5536 5537 size(4); 5538 format %{ "LDSB $mem,$dst\t! byte" %} 5539 ins_encode %{ 5540 __ ldsb($mem$$Address, $dst$$Register); 5541 %} 5542 ins_pipe(iload_mask_mem); 5543%} 5544 5545// Load Byte (8bit signed) into a Long Register 5546instruct loadB2L(iRegL dst, memory mem) %{ 5547 match(Set dst (ConvI2L (LoadB mem))); 5548 ins_cost(MEMORY_REF_COST); 5549 5550 size(4); 5551 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5552 ins_encode %{ 5553 __ ldsb($mem$$Address, $dst$$Register); 5554 %} 5555 ins_pipe(iload_mask_mem); 5556%} 5557 5558// Load Unsigned Byte (8bit UNsigned) into an int reg 5559instruct loadUB(iRegI dst, memory mem) %{ 5560 match(Set dst (LoadUB mem)); 5561 ins_cost(MEMORY_REF_COST); 5562 5563 size(4); 5564 format %{ "LDUB $mem,$dst\t! ubyte" %} 5565 ins_encode %{ 5566 __ ldub($mem$$Address, $dst$$Register); 5567 %} 5568 ins_pipe(iload_mem); 5569%} 5570 5571// Load Unsigned Byte (8bit UNsigned) into a Long Register 5572instruct loadUB2L(iRegL dst, memory mem) %{ 5573 match(Set dst (ConvI2L (LoadUB mem))); 5574 ins_cost(MEMORY_REF_COST); 5575 5576 size(4); 5577 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5578 ins_encode %{ 5579 __ ldub($mem$$Address, $dst$$Register); 5580 %} 5581 ins_pipe(iload_mem); 5582%} 5583 5584// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5585instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5586 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5587 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5588 5589 size(2*4); 5590 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5591 "AND $dst,$mask,$dst" %} 5592 ins_encode %{ 5593 __ ldub($mem$$Address, $dst$$Register); 5594 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5595 %} 5596 ins_pipe(iload_mem); 5597%} 5598 5599// Load Short (16bit signed) 5600instruct loadS(iRegI dst, memory mem) %{ 5601 match(Set dst (LoadS mem)); 5602 ins_cost(MEMORY_REF_COST); 5603 5604 size(4); 5605 format %{ "LDSH $mem,$dst\t! short" %} 5606 ins_encode %{ 5607 __ ldsh($mem$$Address, $dst$$Register); 5608 %} 5609 ins_pipe(iload_mask_mem); 5610%} 5611 5612// Load Short (16 bit signed) to Byte (8 bit signed) 5613instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5614 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5615 ins_cost(MEMORY_REF_COST); 5616 5617 size(4); 5618 5619 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5620 ins_encode %{ 5621 __ ldsb($mem$$Address, $dst$$Register, 1); 5622 %} 5623 ins_pipe(iload_mask_mem); 5624%} 5625 5626// Load Short (16bit signed) into a Long Register 5627instruct loadS2L(iRegL dst, memory mem) %{ 5628 match(Set dst (ConvI2L (LoadS mem))); 5629 ins_cost(MEMORY_REF_COST); 5630 5631 size(4); 5632 format %{ "LDSH $mem,$dst\t! short -> long" %} 5633 ins_encode %{ 5634 __ ldsh($mem$$Address, $dst$$Register); 5635 %} 5636 ins_pipe(iload_mask_mem); 5637%} 5638 5639// Load Unsigned Short/Char (16bit UNsigned) 5640instruct loadUS(iRegI dst, memory mem) %{ 5641 match(Set dst (LoadUS mem)); 5642 ins_cost(MEMORY_REF_COST); 5643 5644 size(4); 5645 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5646 ins_encode %{ 5647 __ lduh($mem$$Address, $dst$$Register); 5648 %} 5649 ins_pipe(iload_mem); 5650%} 5651 5652// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5653instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5654 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5655 ins_cost(MEMORY_REF_COST); 5656 5657 size(4); 5658 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5659 ins_encode %{ 5660 __ ldsb($mem$$Address, $dst$$Register, 1); 5661 %} 5662 ins_pipe(iload_mask_mem); 5663%} 5664 5665// Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5666instruct loadUS2L(iRegL dst, memory mem) %{ 5667 match(Set dst (ConvI2L (LoadUS mem))); 5668 ins_cost(MEMORY_REF_COST); 5669 5670 size(4); 5671 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5672 ins_encode %{ 5673 __ lduh($mem$$Address, $dst$$Register); 5674 %} 5675 ins_pipe(iload_mem); 5676%} 5677 5678// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5679instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5680 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5681 ins_cost(MEMORY_REF_COST); 5682 5683 size(4); 5684 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5685 ins_encode %{ 5686 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5687 %} 5688 ins_pipe(iload_mem); 5689%} 5690 5691// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5692instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5693 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5694 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5695 5696 size(2*4); 5697 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5698 "AND $dst,$mask,$dst" %} 5699 ins_encode %{ 5700 Register Rdst = $dst$$Register; 5701 __ lduh($mem$$Address, Rdst); 5702 __ and3(Rdst, $mask$$constant, Rdst); 5703 %} 5704 ins_pipe(iload_mem); 5705%} 5706 5707// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5708instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5709 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5710 effect(TEMP dst, TEMP tmp); 5711 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5712 5713 size((3+1)*4); // set may use two instructions. 5714 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5715 "SET $mask,$tmp\n\t" 5716 "AND $dst,$tmp,$dst" %} 5717 ins_encode %{ 5718 Register Rdst = $dst$$Register; 5719 Register Rtmp = $tmp$$Register; 5720 __ lduh($mem$$Address, Rdst); 5721 __ set($mask$$constant, Rtmp); 5722 __ and3(Rdst, Rtmp, Rdst); 5723 %} 5724 ins_pipe(iload_mem); 5725%} 5726 5727// Load Integer 5728instruct loadI(iRegI dst, memory mem) %{ 5729 match(Set dst (LoadI mem)); 5730 ins_cost(MEMORY_REF_COST); 5731 5732 size(4); 5733 format %{ "LDUW $mem,$dst\t! int" %} 5734 ins_encode %{ 5735 __ lduw($mem$$Address, $dst$$Register); 5736 %} 5737 ins_pipe(iload_mem); 5738%} 5739 5740// Load Integer to Byte (8 bit signed) 5741instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5742 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5743 ins_cost(MEMORY_REF_COST); 5744 5745 size(4); 5746 5747 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5748 ins_encode %{ 5749 __ ldsb($mem$$Address, $dst$$Register, 3); 5750 %} 5751 ins_pipe(iload_mask_mem); 5752%} 5753 5754// Load Integer to Unsigned Byte (8 bit UNsigned) 5755instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5756 match(Set dst (AndI (LoadI mem) mask)); 5757 ins_cost(MEMORY_REF_COST); 5758 5759 size(4); 5760 5761 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5762 ins_encode %{ 5763 __ ldub($mem$$Address, $dst$$Register, 3); 5764 %} 5765 ins_pipe(iload_mask_mem); 5766%} 5767 5768// Load Integer to Short (16 bit signed) 5769instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5770 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5771 ins_cost(MEMORY_REF_COST); 5772 5773 size(4); 5774 5775 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5776 ins_encode %{ 5777 __ ldsh($mem$$Address, $dst$$Register, 2); 5778 %} 5779 ins_pipe(iload_mask_mem); 5780%} 5781 5782// Load Integer to Unsigned Short (16 bit UNsigned) 5783instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5784 match(Set dst (AndI (LoadI mem) mask)); 5785 ins_cost(MEMORY_REF_COST); 5786 5787 size(4); 5788 5789 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5790 ins_encode %{ 5791 __ lduh($mem$$Address, $dst$$Register, 2); 5792 %} 5793 ins_pipe(iload_mask_mem); 5794%} 5795 5796// Load Integer into a Long Register 5797instruct loadI2L(iRegL dst, memory mem) %{ 5798 match(Set dst (ConvI2L (LoadI mem))); 5799 ins_cost(MEMORY_REF_COST); 5800 5801 size(4); 5802 format %{ "LDSW $mem,$dst\t! int -> long" %} 5803 ins_encode %{ 5804 __ ldsw($mem$$Address, $dst$$Register); 5805 %} 5806 ins_pipe(iload_mask_mem); 5807%} 5808 5809// Load Integer with mask 0xFF into a Long Register 5810instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5811 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5812 ins_cost(MEMORY_REF_COST); 5813 5814 size(4); 5815 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5816 ins_encode %{ 5817 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5818 %} 5819 ins_pipe(iload_mem); 5820%} 5821 5822// Load Integer with mask 0xFFFF into a Long Register 5823instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5824 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5825 ins_cost(MEMORY_REF_COST); 5826 5827 size(4); 5828 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5829 ins_encode %{ 5830 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5831 %} 5832 ins_pipe(iload_mem); 5833%} 5834 5835// Load Integer with a 13-bit mask into a Long Register 5836instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5837 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5838 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5839 5840 size(2*4); 5841 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5842 "AND $dst,$mask,$dst" %} 5843 ins_encode %{ 5844 Register Rdst = $dst$$Register; 5845 __ lduw($mem$$Address, Rdst); 5846 __ and3(Rdst, $mask$$constant, Rdst); 5847 %} 5848 ins_pipe(iload_mem); 5849%} 5850 5851// Load Integer with a 32-bit mask into a Long Register 5852instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5853 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5854 effect(TEMP dst, TEMP tmp); 5855 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5856 5857 size((3+1)*4); // set may use two instructions. 5858 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5859 "SET $mask,$tmp\n\t" 5860 "AND $dst,$tmp,$dst" %} 5861 ins_encode %{ 5862 Register Rdst = $dst$$Register; 5863 Register Rtmp = $tmp$$Register; 5864 __ lduw($mem$$Address, Rdst); 5865 __ set($mask$$constant, Rtmp); 5866 __ and3(Rdst, Rtmp, Rdst); 5867 %} 5868 ins_pipe(iload_mem); 5869%} 5870 5871// Load Unsigned Integer into a Long Register 5872instruct loadUI2L(iRegL dst, memory mem) %{ 5873 match(Set dst (LoadUI2L mem)); 5874 ins_cost(MEMORY_REF_COST); 5875 5876 size(4); 5877 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5878 ins_encode %{ 5879 __ lduw($mem$$Address, $dst$$Register); 5880 %} 5881 ins_pipe(iload_mem); 5882%} 5883 5884// Load Long - aligned 5885instruct loadL(iRegL dst, memory mem ) %{ 5886 match(Set dst (LoadL mem)); 5887 ins_cost(MEMORY_REF_COST); 5888 5889 size(4); 5890 format %{ "LDX $mem,$dst\t! long" %} 5891 ins_encode %{ 5892 __ ldx($mem$$Address, $dst$$Register); 5893 %} 5894 ins_pipe(iload_mem); 5895%} 5896 5897// Load Long - UNaligned 5898instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5899 match(Set dst (LoadL_unaligned mem)); 5900 effect(KILL tmp); 5901 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5902 size(16); 5903 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5904 "\tLDUW $mem ,$dst\n" 5905 "\tSLLX #32, $dst, $dst\n" 5906 "\tOR $dst, R_O7, $dst" %} 5907 opcode(Assembler::lduw_op3); 5908 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5909 ins_pipe(iload_mem); 5910%} 5911 5912// Load Aligned Packed Byte into a Double Register 5913instruct loadA8B(regD dst, memory mem) %{ 5914 match(Set dst (Load8B mem)); 5915 ins_cost(MEMORY_REF_COST); 5916 size(4); 5917 format %{ "LDDF $mem,$dst\t! packed8B" %} 5918 opcode(Assembler::lddf_op3); 5919 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5920 ins_pipe(floadD_mem); 5921%} 5922 5923// Load Aligned Packed Char into a Double Register 5924instruct loadA4C(regD dst, memory mem) %{ 5925 match(Set dst (Load4C mem)); 5926 ins_cost(MEMORY_REF_COST); 5927 size(4); 5928 format %{ "LDDF $mem,$dst\t! packed4C" %} 5929 opcode(Assembler::lddf_op3); 5930 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5931 ins_pipe(floadD_mem); 5932%} 5933 5934// Load Aligned Packed Short into a Double Register 5935instruct loadA4S(regD dst, memory mem) %{ 5936 match(Set dst (Load4S mem)); 5937 ins_cost(MEMORY_REF_COST); 5938 size(4); 5939 format %{ "LDDF $mem,$dst\t! packed4S" %} 5940 opcode(Assembler::lddf_op3); 5941 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5942 ins_pipe(floadD_mem); 5943%} 5944 5945// Load Aligned Packed Int into a Double Register 5946instruct loadA2I(regD dst, memory mem) %{ 5947 match(Set dst (Load2I mem)); 5948 ins_cost(MEMORY_REF_COST); 5949 size(4); 5950 format %{ "LDDF $mem,$dst\t! packed2I" %} 5951 opcode(Assembler::lddf_op3); 5952 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5953 ins_pipe(floadD_mem); 5954%} 5955 5956// Load Range 5957instruct loadRange(iRegI dst, memory mem) %{ 5958 match(Set dst (LoadRange mem)); 5959 ins_cost(MEMORY_REF_COST); 5960 5961 size(4); 5962 format %{ "LDUW $mem,$dst\t! range" %} 5963 opcode(Assembler::lduw_op3); 5964 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5965 ins_pipe(iload_mem); 5966%} 5967 5968// Load Integer into %f register (for fitos/fitod) 5969instruct loadI_freg(regF dst, memory mem) %{ 5970 match(Set dst (LoadI mem)); 5971 ins_cost(MEMORY_REF_COST); 5972 size(4); 5973 5974 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5975 opcode(Assembler::ldf_op3); 5976 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5977 ins_pipe(floadF_mem); 5978%} 5979 5980// Load Pointer 5981instruct loadP(iRegP dst, memory mem) %{ 5982 match(Set dst (LoadP mem)); 5983 ins_cost(MEMORY_REF_COST); 5984 size(4); 5985 5986#ifndef _LP64 5987 format %{ "LDUW $mem,$dst\t! ptr" %} 5988 ins_encode %{ 5989 __ lduw($mem$$Address, $dst$$Register); 5990 %} 5991#else 5992 format %{ "LDX $mem,$dst\t! ptr" %} 5993 ins_encode %{ 5994 __ ldx($mem$$Address, $dst$$Register); 5995 %} 5996#endif 5997 ins_pipe(iload_mem); 5998%} 5999 6000// Load Compressed Pointer 6001instruct loadN(iRegN dst, memory mem) %{ 6002 match(Set dst (LoadN mem)); 6003 ins_cost(MEMORY_REF_COST); 6004 size(4); 6005 6006 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 6007 ins_encode %{ 6008 __ lduw($mem$$Address, $dst$$Register); 6009 %} 6010 ins_pipe(iload_mem); 6011%} 6012 6013// Load Klass Pointer 6014instruct loadKlass(iRegP dst, memory mem) %{ 6015 match(Set dst (LoadKlass mem)); 6016 ins_cost(MEMORY_REF_COST); 6017 size(4); 6018 6019#ifndef _LP64 6020 format %{ "LDUW $mem,$dst\t! klass ptr" %} 6021 ins_encode %{ 6022 __ lduw($mem$$Address, $dst$$Register); 6023 %} 6024#else 6025 format %{ "LDX $mem,$dst\t! klass ptr" %} 6026 ins_encode %{ 6027 __ ldx($mem$$Address, $dst$$Register); 6028 %} 6029#endif 6030 ins_pipe(iload_mem); 6031%} 6032 6033// Load narrow Klass Pointer 6034instruct loadNKlass(iRegN dst, memory mem) %{ 6035 match(Set dst (LoadNKlass mem)); 6036 ins_cost(MEMORY_REF_COST); 6037 size(4); 6038 6039 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 6040 ins_encode %{ 6041 __ lduw($mem$$Address, $dst$$Register); 6042 %} 6043 ins_pipe(iload_mem); 6044%} 6045 6046// Load Double 6047instruct loadD(regD dst, memory mem) %{ 6048 match(Set dst (LoadD mem)); 6049 ins_cost(MEMORY_REF_COST); 6050 6051 size(4); 6052 format %{ "LDDF $mem,$dst" %} 6053 opcode(Assembler::lddf_op3); 6054 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6055 ins_pipe(floadD_mem); 6056%} 6057 6058// Load Double - UNaligned 6059instruct loadD_unaligned(regD_low dst, memory mem ) %{ 6060 match(Set dst (LoadD_unaligned mem)); 6061 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 6062 size(8); 6063 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 6064 "\tLDF $mem+4,$dst.lo\t!" %} 6065 opcode(Assembler::ldf_op3); 6066 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 6067 ins_pipe(iload_mem); 6068%} 6069 6070// Load Float 6071instruct loadF(regF dst, memory mem) %{ 6072 match(Set dst (LoadF mem)); 6073 ins_cost(MEMORY_REF_COST); 6074 6075 size(4); 6076 format %{ "LDF $mem,$dst" %} 6077 opcode(Assembler::ldf_op3); 6078 ins_encode(simple_form3_mem_reg( mem, dst ) ); 6079 ins_pipe(floadF_mem); 6080%} 6081 6082// Load Constant 6083instruct loadConI( iRegI dst, immI src ) %{ 6084 match(Set dst src); 6085 ins_cost(DEFAULT_COST * 3/2); 6086 format %{ "SET $src,$dst" %} 6087 ins_encode( Set32(src, dst) ); 6088 ins_pipe(ialu_hi_lo_reg); 6089%} 6090 6091instruct loadConI13( iRegI dst, immI13 src ) %{ 6092 match(Set dst src); 6093 6094 size(4); 6095 format %{ "MOV $src,$dst" %} 6096 ins_encode( Set13( src, dst ) ); 6097 ins_pipe(ialu_imm); 6098%} 6099 6100#ifndef _LP64 6101instruct loadConP(iRegP dst, immP con) %{ 6102 match(Set dst con); 6103 ins_cost(DEFAULT_COST * 3/2); 6104 format %{ "SET $con,$dst\t!ptr" %} 6105 ins_encode %{ 6106 // [RGV] This next line should be generated from ADLC 6107 if (_opnds[1]->constant_is_oop()) { 6108 intptr_t val = $con$$constant; 6109 __ set_oop_constant((jobject) val, $dst$$Register); 6110 } else { // non-oop pointers, e.g. card mark base, heap top 6111 __ set($con$$constant, $dst$$Register); 6112 } 6113 %} 6114 ins_pipe(loadConP); 6115%} 6116#else 6117instruct loadConP_set(iRegP dst, immP_set con) %{ 6118 match(Set dst con); 6119 ins_cost(DEFAULT_COST * 3/2); 6120 format %{ "SET $con,$dst\t! ptr" %} 6121 ins_encode %{ 6122 // [RGV] This next line should be generated from ADLC 6123 if (_opnds[1]->constant_is_oop()) { 6124 intptr_t val = $con$$constant; 6125 __ set_oop_constant((jobject) val, $dst$$Register); 6126 } else { // non-oop pointers, e.g. card mark base, heap top 6127 __ set($con$$constant, $dst$$Register); 6128 } 6129 %} 6130 ins_pipe(loadConP); 6131%} 6132 6133instruct loadConP_load(iRegP dst, immP_load con) %{ 6134 match(Set dst con); 6135 ins_cost(MEMORY_REF_COST); 6136 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 6137 ins_encode %{ 6138 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6139 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 6140 %} 6141 ins_pipe(loadConP); 6142%} 6143 6144instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 6145 match(Set dst con); 6146 ins_cost(DEFAULT_COST * 3/2); 6147 format %{ "SET $con,$dst\t! non-oop ptr" %} 6148 ins_encode %{ 6149 __ set($con$$constant, $dst$$Register); 6150 %} 6151 ins_pipe(loadConP); 6152%} 6153#endif // _LP64 6154 6155instruct loadConP0(iRegP dst, immP0 src) %{ 6156 match(Set dst src); 6157 6158 size(4); 6159 format %{ "CLR $dst\t!ptr" %} 6160 ins_encode %{ 6161 __ clr($dst$$Register); 6162 %} 6163 ins_pipe(ialu_imm); 6164%} 6165 6166instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6167 match(Set dst src); 6168 ins_cost(DEFAULT_COST); 6169 format %{ "SET $src,$dst\t!ptr" %} 6170 ins_encode %{ 6171 AddressLiteral polling_page(os::get_polling_page()); 6172 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6173 %} 6174 ins_pipe(loadConP_poll); 6175%} 6176 6177instruct loadConN0(iRegN dst, immN0 src) %{ 6178 match(Set dst src); 6179 6180 size(4); 6181 format %{ "CLR $dst\t! compressed NULL ptr" %} 6182 ins_encode %{ 6183 __ clr($dst$$Register); 6184 %} 6185 ins_pipe(ialu_imm); 6186%} 6187 6188instruct loadConN(iRegN dst, immN src) %{ 6189 match(Set dst src); 6190 ins_cost(DEFAULT_COST * 3/2); 6191 format %{ "SET $src,$dst\t! compressed ptr" %} 6192 ins_encode %{ 6193 Register dst = $dst$$Register; 6194 __ set_narrow_oop((jobject)$src$$constant, dst); 6195 %} 6196 ins_pipe(ialu_hi_lo_reg); 6197%} 6198 6199// Materialize long value (predicated by immL_cheap). 6200instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 6201 match(Set dst con); 6202 effect(KILL tmp); 6203 ins_cost(DEFAULT_COST * 3); 6204 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 6205 ins_encode %{ 6206 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 6207 %} 6208 ins_pipe(loadConL); 6209%} 6210 6211// Load long value from constant table (predicated by immL_expensive). 6212instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 6213 match(Set dst con); 6214 ins_cost(MEMORY_REF_COST); 6215 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 6216 ins_encode %{ 6217 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 6218 __ ldx($constanttablebase, con_offset, $dst$$Register); 6219 %} 6220 ins_pipe(loadConL); 6221%} 6222 6223instruct loadConL0( iRegL dst, immL0 src ) %{ 6224 match(Set dst src); 6225 ins_cost(DEFAULT_COST); 6226 size(4); 6227 format %{ "CLR $dst\t! long" %} 6228 ins_encode( Set13( src, dst ) ); 6229 ins_pipe(ialu_imm); 6230%} 6231 6232instruct loadConL13( iRegL dst, immL13 src ) %{ 6233 match(Set dst src); 6234 ins_cost(DEFAULT_COST * 2); 6235 6236 size(4); 6237 format %{ "MOV $src,$dst\t! long" %} 6238 ins_encode( Set13( src, dst ) ); 6239 ins_pipe(ialu_imm); 6240%} 6241 6242instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 6243 match(Set dst con); 6244 effect(KILL tmp); 6245 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 6246 ins_encode %{ 6247 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6248 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 6249 %} 6250 ins_pipe(loadConFD); 6251%} 6252 6253instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 6254 match(Set dst con); 6255 effect(KILL tmp); 6256 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 6257 ins_encode %{ 6258 // XXX This is a quick fix for 6833573. 6259 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 6260 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 6261 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 6262 %} 6263 ins_pipe(loadConFD); 6264%} 6265 6266// Prefetch instructions. 6267// Must be safe to execute with invalid address (cannot fault). 6268 6269instruct prefetchr( memory mem ) %{ 6270 match( PrefetchRead mem ); 6271 ins_cost(MEMORY_REF_COST); 6272 6273 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6274 opcode(Assembler::prefetch_op3); 6275 ins_encode( form3_mem_prefetch_read( mem ) ); 6276 ins_pipe(iload_mem); 6277%} 6278 6279instruct prefetchw( memory mem ) %{ 6280 predicate(AllocatePrefetchStyle != 3 ); 6281 match( PrefetchWrite mem ); 6282 ins_cost(MEMORY_REF_COST); 6283 6284 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6285 opcode(Assembler::prefetch_op3); 6286 ins_encode( form3_mem_prefetch_write( mem ) ); 6287 ins_pipe(iload_mem); 6288%} 6289 6290// Use BIS instruction to prefetch. 6291instruct prefetchw_bis( memory mem ) %{ 6292 predicate(AllocatePrefetchStyle == 3); 6293 match( PrefetchWrite mem ); 6294 ins_cost(MEMORY_REF_COST); 6295 6296 format %{ "STXA G0,$mem\t! // Block initializing store" %} 6297 ins_encode %{ 6298 Register base = as_Register($mem$$base); 6299 int disp = $mem$$disp; 6300 if (disp != 0) { 6301 __ add(base, AllocatePrefetchStepSize, base); 6302 } 6303 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 6304 %} 6305 ins_pipe(istore_mem_reg); 6306%} 6307 6308//----------Store Instructions------------------------------------------------- 6309// Store Byte 6310instruct storeB(memory mem, iRegI src) %{ 6311 match(Set mem (StoreB mem src)); 6312 ins_cost(MEMORY_REF_COST); 6313 6314 size(4); 6315 format %{ "STB $src,$mem\t! byte" %} 6316 opcode(Assembler::stb_op3); 6317 ins_encode(simple_form3_mem_reg( mem, src ) ); 6318 ins_pipe(istore_mem_reg); 6319%} 6320 6321instruct storeB0(memory mem, immI0 src) %{ 6322 match(Set mem (StoreB mem src)); 6323 ins_cost(MEMORY_REF_COST); 6324 6325 size(4); 6326 format %{ "STB $src,$mem\t! byte" %} 6327 opcode(Assembler::stb_op3); 6328 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6329 ins_pipe(istore_mem_zero); 6330%} 6331 6332instruct storeCM0(memory mem, immI0 src) %{ 6333 match(Set mem (StoreCM mem src)); 6334 ins_cost(MEMORY_REF_COST); 6335 6336 size(4); 6337 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6338 opcode(Assembler::stb_op3); 6339 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6340 ins_pipe(istore_mem_zero); 6341%} 6342 6343// Store Char/Short 6344instruct storeC(memory mem, iRegI src) %{ 6345 match(Set mem (StoreC mem src)); 6346 ins_cost(MEMORY_REF_COST); 6347 6348 size(4); 6349 format %{ "STH $src,$mem\t! short" %} 6350 opcode(Assembler::sth_op3); 6351 ins_encode(simple_form3_mem_reg( mem, src ) ); 6352 ins_pipe(istore_mem_reg); 6353%} 6354 6355instruct storeC0(memory mem, immI0 src) %{ 6356 match(Set mem (StoreC mem src)); 6357 ins_cost(MEMORY_REF_COST); 6358 6359 size(4); 6360 format %{ "STH $src,$mem\t! short" %} 6361 opcode(Assembler::sth_op3); 6362 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6363 ins_pipe(istore_mem_zero); 6364%} 6365 6366// Store Integer 6367instruct storeI(memory mem, iRegI src) %{ 6368 match(Set mem (StoreI mem src)); 6369 ins_cost(MEMORY_REF_COST); 6370 6371 size(4); 6372 format %{ "STW $src,$mem" %} 6373 opcode(Assembler::stw_op3); 6374 ins_encode(simple_form3_mem_reg( mem, src ) ); 6375 ins_pipe(istore_mem_reg); 6376%} 6377 6378// Store Long 6379instruct storeL(memory mem, iRegL src) %{ 6380 match(Set mem (StoreL mem src)); 6381 ins_cost(MEMORY_REF_COST); 6382 size(4); 6383 format %{ "STX $src,$mem\t! long" %} 6384 opcode(Assembler::stx_op3); 6385 ins_encode(simple_form3_mem_reg( mem, src ) ); 6386 ins_pipe(istore_mem_reg); 6387%} 6388 6389instruct storeI0(memory mem, immI0 src) %{ 6390 match(Set mem (StoreI mem src)); 6391 ins_cost(MEMORY_REF_COST); 6392 6393 size(4); 6394 format %{ "STW $src,$mem" %} 6395 opcode(Assembler::stw_op3); 6396 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6397 ins_pipe(istore_mem_zero); 6398%} 6399 6400instruct storeL0(memory mem, immL0 src) %{ 6401 match(Set mem (StoreL mem src)); 6402 ins_cost(MEMORY_REF_COST); 6403 6404 size(4); 6405 format %{ "STX $src,$mem" %} 6406 opcode(Assembler::stx_op3); 6407 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6408 ins_pipe(istore_mem_zero); 6409%} 6410 6411// Store Integer from float register (used after fstoi) 6412instruct storeI_Freg(memory mem, regF src) %{ 6413 match(Set mem (StoreI mem src)); 6414 ins_cost(MEMORY_REF_COST); 6415 6416 size(4); 6417 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6418 opcode(Assembler::stf_op3); 6419 ins_encode(simple_form3_mem_reg( mem, src ) ); 6420 ins_pipe(fstoreF_mem_reg); 6421%} 6422 6423// Store Pointer 6424instruct storeP(memory dst, sp_ptr_RegP src) %{ 6425 match(Set dst (StoreP dst src)); 6426 ins_cost(MEMORY_REF_COST); 6427 size(4); 6428 6429#ifndef _LP64 6430 format %{ "STW $src,$dst\t! ptr" %} 6431 opcode(Assembler::stw_op3, 0, REGP_OP); 6432#else 6433 format %{ "STX $src,$dst\t! ptr" %} 6434 opcode(Assembler::stx_op3, 0, REGP_OP); 6435#endif 6436 ins_encode( form3_mem_reg( dst, src ) ); 6437 ins_pipe(istore_mem_spORreg); 6438%} 6439 6440instruct storeP0(memory dst, immP0 src) %{ 6441 match(Set dst (StoreP dst src)); 6442 ins_cost(MEMORY_REF_COST); 6443 size(4); 6444 6445#ifndef _LP64 6446 format %{ "STW $src,$dst\t! ptr" %} 6447 opcode(Assembler::stw_op3, 0, REGP_OP); 6448#else 6449 format %{ "STX $src,$dst\t! ptr" %} 6450 opcode(Assembler::stx_op3, 0, REGP_OP); 6451#endif 6452 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6453 ins_pipe(istore_mem_zero); 6454%} 6455 6456// Store Compressed Pointer 6457instruct storeN(memory dst, iRegN src) %{ 6458 match(Set dst (StoreN dst src)); 6459 ins_cost(MEMORY_REF_COST); 6460 size(4); 6461 6462 format %{ "STW $src,$dst\t! compressed ptr" %} 6463 ins_encode %{ 6464 Register base = as_Register($dst$$base); 6465 Register index = as_Register($dst$$index); 6466 Register src = $src$$Register; 6467 if (index != G0) { 6468 __ stw(src, base, index); 6469 } else { 6470 __ stw(src, base, $dst$$disp); 6471 } 6472 %} 6473 ins_pipe(istore_mem_spORreg); 6474%} 6475 6476instruct storeN0(memory dst, immN0 src) %{ 6477 match(Set dst (StoreN dst src)); 6478 ins_cost(MEMORY_REF_COST); 6479 size(4); 6480 6481 format %{ "STW $src,$dst\t! compressed ptr" %} 6482 ins_encode %{ 6483 Register base = as_Register($dst$$base); 6484 Register index = as_Register($dst$$index); 6485 if (index != G0) { 6486 __ stw(0, base, index); 6487 } else { 6488 __ stw(0, base, $dst$$disp); 6489 } 6490 %} 6491 ins_pipe(istore_mem_zero); 6492%} 6493 6494// Store Double 6495instruct storeD( memory mem, regD src) %{ 6496 match(Set mem (StoreD mem src)); 6497 ins_cost(MEMORY_REF_COST); 6498 6499 size(4); 6500 format %{ "STDF $src,$mem" %} 6501 opcode(Assembler::stdf_op3); 6502 ins_encode(simple_form3_mem_reg( mem, src ) ); 6503 ins_pipe(fstoreD_mem_reg); 6504%} 6505 6506instruct storeD0( memory mem, immD0 src) %{ 6507 match(Set mem (StoreD mem src)); 6508 ins_cost(MEMORY_REF_COST); 6509 6510 size(4); 6511 format %{ "STX $src,$mem" %} 6512 opcode(Assembler::stx_op3); 6513 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6514 ins_pipe(fstoreD_mem_zero); 6515%} 6516 6517// Store Float 6518instruct storeF( memory mem, regF src) %{ 6519 match(Set mem (StoreF mem src)); 6520 ins_cost(MEMORY_REF_COST); 6521 6522 size(4); 6523 format %{ "STF $src,$mem" %} 6524 opcode(Assembler::stf_op3); 6525 ins_encode(simple_form3_mem_reg( mem, src ) ); 6526 ins_pipe(fstoreF_mem_reg); 6527%} 6528 6529instruct storeF0( memory mem, immF0 src) %{ 6530 match(Set mem (StoreF mem src)); 6531 ins_cost(MEMORY_REF_COST); 6532 6533 size(4); 6534 format %{ "STW $src,$mem\t! storeF0" %} 6535 opcode(Assembler::stw_op3); 6536 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6537 ins_pipe(fstoreF_mem_zero); 6538%} 6539 6540// Store Aligned Packed Bytes in Double register to memory 6541instruct storeA8B(memory mem, regD src) %{ 6542 match(Set mem (Store8B mem src)); 6543 ins_cost(MEMORY_REF_COST); 6544 size(4); 6545 format %{ "STDF $src,$mem\t! packed8B" %} 6546 opcode(Assembler::stdf_op3); 6547 ins_encode(simple_form3_mem_reg( mem, src ) ); 6548 ins_pipe(fstoreD_mem_reg); 6549%} 6550 6551// Convert oop pointer into compressed form 6552instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6553 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6554 match(Set dst (EncodeP src)); 6555 format %{ "encode_heap_oop $src, $dst" %} 6556 ins_encode %{ 6557 __ encode_heap_oop($src$$Register, $dst$$Register); 6558 %} 6559 ins_pipe(ialu_reg); 6560%} 6561 6562instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6563 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6564 match(Set dst (EncodeP src)); 6565 format %{ "encode_heap_oop_not_null $src, $dst" %} 6566 ins_encode %{ 6567 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6568 %} 6569 ins_pipe(ialu_reg); 6570%} 6571 6572instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6573 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6574 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6575 match(Set dst (DecodeN src)); 6576 format %{ "decode_heap_oop $src, $dst" %} 6577 ins_encode %{ 6578 __ decode_heap_oop($src$$Register, $dst$$Register); 6579 %} 6580 ins_pipe(ialu_reg); 6581%} 6582 6583instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6584 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6585 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6586 match(Set dst (DecodeN src)); 6587 format %{ "decode_heap_oop_not_null $src, $dst" %} 6588 ins_encode %{ 6589 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6590 %} 6591 ins_pipe(ialu_reg); 6592%} 6593 6594 6595// Store Zero into Aligned Packed Bytes 6596instruct storeA8B0(memory mem, immI0 zero) %{ 6597 match(Set mem (Store8B mem zero)); 6598 ins_cost(MEMORY_REF_COST); 6599 size(4); 6600 format %{ "STX $zero,$mem\t! packed8B" %} 6601 opcode(Assembler::stx_op3); 6602 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6603 ins_pipe(fstoreD_mem_zero); 6604%} 6605 6606// Store Aligned Packed Chars/Shorts in Double register to memory 6607instruct storeA4C(memory mem, regD src) %{ 6608 match(Set mem (Store4C mem src)); 6609 ins_cost(MEMORY_REF_COST); 6610 size(4); 6611 format %{ "STDF $src,$mem\t! packed4C" %} 6612 opcode(Assembler::stdf_op3); 6613 ins_encode(simple_form3_mem_reg( mem, src ) ); 6614 ins_pipe(fstoreD_mem_reg); 6615%} 6616 6617// Store Zero into Aligned Packed Chars/Shorts 6618instruct storeA4C0(memory mem, immI0 zero) %{ 6619 match(Set mem (Store4C mem (Replicate4C zero))); 6620 ins_cost(MEMORY_REF_COST); 6621 size(4); 6622 format %{ "STX $zero,$mem\t! packed4C" %} 6623 opcode(Assembler::stx_op3); 6624 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6625 ins_pipe(fstoreD_mem_zero); 6626%} 6627 6628// Store Aligned Packed Ints in Double register to memory 6629instruct storeA2I(memory mem, regD src) %{ 6630 match(Set mem (Store2I mem src)); 6631 ins_cost(MEMORY_REF_COST); 6632 size(4); 6633 format %{ "STDF $src,$mem\t! packed2I" %} 6634 opcode(Assembler::stdf_op3); 6635 ins_encode(simple_form3_mem_reg( mem, src ) ); 6636 ins_pipe(fstoreD_mem_reg); 6637%} 6638 6639// Store Zero into Aligned Packed Ints 6640instruct storeA2I0(memory mem, immI0 zero) %{ 6641 match(Set mem (Store2I mem zero)); 6642 ins_cost(MEMORY_REF_COST); 6643 size(4); 6644 format %{ "STX $zero,$mem\t! packed2I" %} 6645 opcode(Assembler::stx_op3); 6646 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6647 ins_pipe(fstoreD_mem_zero); 6648%} 6649 6650 6651//----------MemBar Instructions----------------------------------------------- 6652// Memory barrier flavors 6653 6654instruct membar_acquire() %{ 6655 match(MemBarAcquire); 6656 ins_cost(4*MEMORY_REF_COST); 6657 6658 size(0); 6659 format %{ "MEMBAR-acquire" %} 6660 ins_encode( enc_membar_acquire ); 6661 ins_pipe(long_memory_op); 6662%} 6663 6664instruct membar_acquire_lock() %{ 6665 match(MemBarAcquireLock); 6666 ins_cost(0); 6667 6668 size(0); 6669 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6670 ins_encode( ); 6671 ins_pipe(empty); 6672%} 6673 6674instruct membar_release() %{ 6675 match(MemBarRelease); 6676 ins_cost(4*MEMORY_REF_COST); 6677 6678 size(0); 6679 format %{ "MEMBAR-release" %} 6680 ins_encode( enc_membar_release ); 6681 ins_pipe(long_memory_op); 6682%} 6683 6684instruct membar_release_lock() %{ 6685 match(MemBarReleaseLock); 6686 ins_cost(0); 6687 6688 size(0); 6689 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6690 ins_encode( ); 6691 ins_pipe(empty); 6692%} 6693 6694instruct membar_volatile() %{ 6695 match(MemBarVolatile); 6696 ins_cost(4*MEMORY_REF_COST); 6697 6698 size(4); 6699 format %{ "MEMBAR-volatile" %} 6700 ins_encode( enc_membar_volatile ); 6701 ins_pipe(long_memory_op); 6702%} 6703 6704instruct unnecessary_membar_volatile() %{ 6705 match(MemBarVolatile); 6706 predicate(Matcher::post_store_load_barrier(n)); 6707 ins_cost(0); 6708 6709 size(0); 6710 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6711 ins_encode( ); 6712 ins_pipe(empty); 6713%} 6714 6715//----------Register Move Instructions----------------------------------------- 6716instruct roundDouble_nop(regD dst) %{ 6717 match(Set dst (RoundDouble dst)); 6718 ins_cost(0); 6719 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6720 ins_encode( ); 6721 ins_pipe(empty); 6722%} 6723 6724 6725instruct roundFloat_nop(regF dst) %{ 6726 match(Set dst (RoundFloat dst)); 6727 ins_cost(0); 6728 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6729 ins_encode( ); 6730 ins_pipe(empty); 6731%} 6732 6733 6734// Cast Index to Pointer for unsafe natives 6735instruct castX2P(iRegX src, iRegP dst) %{ 6736 match(Set dst (CastX2P src)); 6737 6738 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6739 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6740 ins_pipe(ialu_reg); 6741%} 6742 6743// Cast Pointer to Index for unsafe natives 6744instruct castP2X(iRegP src, iRegX dst) %{ 6745 match(Set dst (CastP2X src)); 6746 6747 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6748 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6749 ins_pipe(ialu_reg); 6750%} 6751 6752instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6753 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6754 match(Set stkSlot src); // chain rule 6755 ins_cost(MEMORY_REF_COST); 6756 format %{ "STDF $src,$stkSlot\t!stk" %} 6757 opcode(Assembler::stdf_op3); 6758 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6759 ins_pipe(fstoreD_stk_reg); 6760%} 6761 6762instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6763 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6764 match(Set dst stkSlot); // chain rule 6765 ins_cost(MEMORY_REF_COST); 6766 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6767 opcode(Assembler::lddf_op3); 6768 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6769 ins_pipe(floadD_stk); 6770%} 6771 6772instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6773 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6774 match(Set stkSlot src); // chain rule 6775 ins_cost(MEMORY_REF_COST); 6776 format %{ "STF $src,$stkSlot\t!stk" %} 6777 opcode(Assembler::stf_op3); 6778 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6779 ins_pipe(fstoreF_stk_reg); 6780%} 6781 6782//----------Conditional Move--------------------------------------------------- 6783// Conditional move 6784instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6785 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6786 ins_cost(150); 6787 format %{ "MOV$cmp $pcc,$src,$dst" %} 6788 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6789 ins_pipe(ialu_reg); 6790%} 6791 6792instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6793 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6794 ins_cost(140); 6795 format %{ "MOV$cmp $pcc,$src,$dst" %} 6796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6797 ins_pipe(ialu_imm); 6798%} 6799 6800instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6801 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6802 ins_cost(150); 6803 size(4); 6804 format %{ "MOV$cmp $icc,$src,$dst" %} 6805 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6806 ins_pipe(ialu_reg); 6807%} 6808 6809instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6810 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6811 ins_cost(140); 6812 size(4); 6813 format %{ "MOV$cmp $icc,$src,$dst" %} 6814 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6815 ins_pipe(ialu_imm); 6816%} 6817 6818instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6819 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6820 ins_cost(150); 6821 size(4); 6822 format %{ "MOV$cmp $icc,$src,$dst" %} 6823 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6824 ins_pipe(ialu_reg); 6825%} 6826 6827instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6828 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6829 ins_cost(140); 6830 size(4); 6831 format %{ "MOV$cmp $icc,$src,$dst" %} 6832 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6833 ins_pipe(ialu_imm); 6834%} 6835 6836instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6837 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6838 ins_cost(150); 6839 size(4); 6840 format %{ "MOV$cmp $fcc,$src,$dst" %} 6841 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6842 ins_pipe(ialu_reg); 6843%} 6844 6845instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6846 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6847 ins_cost(140); 6848 size(4); 6849 format %{ "MOV$cmp $fcc,$src,$dst" %} 6850 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6851 ins_pipe(ialu_imm); 6852%} 6853 6854// Conditional move for RegN. Only cmov(reg,reg). 6855instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6856 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6857 ins_cost(150); 6858 format %{ "MOV$cmp $pcc,$src,$dst" %} 6859 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6860 ins_pipe(ialu_reg); 6861%} 6862 6863// This instruction also works with CmpN so we don't need cmovNN_reg. 6864instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6865 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6866 ins_cost(150); 6867 size(4); 6868 format %{ "MOV$cmp $icc,$src,$dst" %} 6869 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6870 ins_pipe(ialu_reg); 6871%} 6872 6873// This instruction also works with CmpN so we don't need cmovNN_reg. 6874instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6875 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6876 ins_cost(150); 6877 size(4); 6878 format %{ "MOV$cmp $icc,$src,$dst" %} 6879 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6880 ins_pipe(ialu_reg); 6881%} 6882 6883instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6884 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6885 ins_cost(150); 6886 size(4); 6887 format %{ "MOV$cmp $fcc,$src,$dst" %} 6888 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6889 ins_pipe(ialu_reg); 6890%} 6891 6892// Conditional move 6893instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6894 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6895 ins_cost(150); 6896 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6897 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6898 ins_pipe(ialu_reg); 6899%} 6900 6901instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6902 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6903 ins_cost(140); 6904 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6905 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6906 ins_pipe(ialu_imm); 6907%} 6908 6909// This instruction also works with CmpN so we don't need cmovPN_reg. 6910instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6911 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6912 ins_cost(150); 6913 6914 size(4); 6915 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6916 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6917 ins_pipe(ialu_reg); 6918%} 6919 6920instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6921 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6922 ins_cost(150); 6923 6924 size(4); 6925 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6926 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6927 ins_pipe(ialu_reg); 6928%} 6929 6930instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6931 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6932 ins_cost(140); 6933 6934 size(4); 6935 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6936 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6937 ins_pipe(ialu_imm); 6938%} 6939 6940instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6941 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6942 ins_cost(140); 6943 6944 size(4); 6945 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6946 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6947 ins_pipe(ialu_imm); 6948%} 6949 6950instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6951 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6952 ins_cost(150); 6953 size(4); 6954 format %{ "MOV$cmp $fcc,$src,$dst" %} 6955 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6956 ins_pipe(ialu_imm); 6957%} 6958 6959instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6960 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6961 ins_cost(140); 6962 size(4); 6963 format %{ "MOV$cmp $fcc,$src,$dst" %} 6964 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6965 ins_pipe(ialu_imm); 6966%} 6967 6968// Conditional move 6969instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6970 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6971 ins_cost(150); 6972 opcode(0x101); 6973 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6974 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6975 ins_pipe(int_conditional_float_move); 6976%} 6977 6978instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6979 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6980 ins_cost(150); 6981 6982 size(4); 6983 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6984 opcode(0x101); 6985 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6986 ins_pipe(int_conditional_float_move); 6987%} 6988 6989instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6990 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6991 ins_cost(150); 6992 6993 size(4); 6994 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6995 opcode(0x101); 6996 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6997 ins_pipe(int_conditional_float_move); 6998%} 6999 7000// Conditional move, 7001instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 7002 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 7003 ins_cost(150); 7004 size(4); 7005 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 7006 opcode(0x1); 7007 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7008 ins_pipe(int_conditional_double_move); 7009%} 7010 7011// Conditional move 7012instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 7013 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 7014 ins_cost(150); 7015 size(4); 7016 opcode(0x102); 7017 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 7018 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7019 ins_pipe(int_conditional_double_move); 7020%} 7021 7022instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 7023 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7024 ins_cost(150); 7025 7026 size(4); 7027 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7028 opcode(0x102); 7029 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7030 ins_pipe(int_conditional_double_move); 7031%} 7032 7033instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 7034 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 7035 ins_cost(150); 7036 7037 size(4); 7038 format %{ "FMOVD$cmp $icc,$src,$dst" %} 7039 opcode(0x102); 7040 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 7041 ins_pipe(int_conditional_double_move); 7042%} 7043 7044// Conditional move, 7045instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 7046 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 7047 ins_cost(150); 7048 size(4); 7049 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 7050 opcode(0x2); 7051 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 7052 ins_pipe(int_conditional_double_move); 7053%} 7054 7055// Conditional move 7056instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 7057 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7058 ins_cost(150); 7059 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7060 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 7061 ins_pipe(ialu_reg); 7062%} 7063 7064instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 7065 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 7066 ins_cost(140); 7067 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 7068 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 7069 ins_pipe(ialu_imm); 7070%} 7071 7072instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 7073 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7074 ins_cost(150); 7075 7076 size(4); 7077 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7078 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7079 ins_pipe(ialu_reg); 7080%} 7081 7082 7083instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 7084 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 7085 ins_cost(150); 7086 7087 size(4); 7088 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 7089 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 7090 ins_pipe(ialu_reg); 7091%} 7092 7093 7094instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 7095 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 7096 ins_cost(150); 7097 7098 size(4); 7099 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 7100 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 7101 ins_pipe(ialu_reg); 7102%} 7103 7104 7105 7106//----------OS and Locking Instructions---------------------------------------- 7107 7108// This name is KNOWN by the ADLC and cannot be changed. 7109// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 7110// for this guy. 7111instruct tlsLoadP(g2RegP dst) %{ 7112 match(Set dst (ThreadLocal)); 7113 7114 size(0); 7115 ins_cost(0); 7116 format %{ "# TLS is in G2" %} 7117 ins_encode( /*empty encoding*/ ); 7118 ins_pipe(ialu_none); 7119%} 7120 7121instruct checkCastPP( iRegP dst ) %{ 7122 match(Set dst (CheckCastPP dst)); 7123 7124 size(0); 7125 format %{ "# checkcastPP of $dst" %} 7126 ins_encode( /*empty encoding*/ ); 7127 ins_pipe(empty); 7128%} 7129 7130 7131instruct castPP( iRegP dst ) %{ 7132 match(Set dst (CastPP dst)); 7133 format %{ "# castPP of $dst" %} 7134 ins_encode( /*empty encoding*/ ); 7135 ins_pipe(empty); 7136%} 7137 7138instruct castII( iRegI dst ) %{ 7139 match(Set dst (CastII dst)); 7140 format %{ "# castII of $dst" %} 7141 ins_encode( /*empty encoding*/ ); 7142 ins_cost(0); 7143 ins_pipe(empty); 7144%} 7145 7146//----------Arithmetic Instructions-------------------------------------------- 7147// Addition Instructions 7148// Register Addition 7149instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7150 match(Set dst (AddI src1 src2)); 7151 7152 size(4); 7153 format %{ "ADD $src1,$src2,$dst" %} 7154 ins_encode %{ 7155 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7156 %} 7157 ins_pipe(ialu_reg_reg); 7158%} 7159 7160// Immediate Addition 7161instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7162 match(Set dst (AddI src1 src2)); 7163 7164 size(4); 7165 format %{ "ADD $src1,$src2,$dst" %} 7166 opcode(Assembler::add_op3, Assembler::arith_op); 7167 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7168 ins_pipe(ialu_reg_imm); 7169%} 7170 7171// Pointer Register Addition 7172instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7173 match(Set dst (AddP src1 src2)); 7174 7175 size(4); 7176 format %{ "ADD $src1,$src2,$dst" %} 7177 opcode(Assembler::add_op3, Assembler::arith_op); 7178 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7179 ins_pipe(ialu_reg_reg); 7180%} 7181 7182// Pointer Immediate Addition 7183instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7184 match(Set dst (AddP src1 src2)); 7185 7186 size(4); 7187 format %{ "ADD $src1,$src2,$dst" %} 7188 opcode(Assembler::add_op3, Assembler::arith_op); 7189 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7190 ins_pipe(ialu_reg_imm); 7191%} 7192 7193// Long Addition 7194instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7195 match(Set dst (AddL src1 src2)); 7196 7197 size(4); 7198 format %{ "ADD $src1,$src2,$dst\t! long" %} 7199 opcode(Assembler::add_op3, Assembler::arith_op); 7200 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7201 ins_pipe(ialu_reg_reg); 7202%} 7203 7204instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7205 match(Set dst (AddL src1 con)); 7206 7207 size(4); 7208 format %{ "ADD $src1,$con,$dst" %} 7209 opcode(Assembler::add_op3, Assembler::arith_op); 7210 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7211 ins_pipe(ialu_reg_imm); 7212%} 7213 7214//----------Conditional_store-------------------------------------------------- 7215// Conditional-store of the updated heap-top. 7216// Used during allocation of the shared heap. 7217// Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7218 7219// LoadP-locked. Same as a regular pointer load when used with a compare-swap 7220instruct loadPLocked(iRegP dst, memory mem) %{ 7221 match(Set dst (LoadPLocked mem)); 7222 ins_cost(MEMORY_REF_COST); 7223 7224#ifndef _LP64 7225 size(4); 7226 format %{ "LDUW $mem,$dst\t! ptr" %} 7227 opcode(Assembler::lduw_op3, 0, REGP_OP); 7228#else 7229 format %{ "LDX $mem,$dst\t! ptr" %} 7230 opcode(Assembler::ldx_op3, 0, REGP_OP); 7231#endif 7232 ins_encode( form3_mem_reg( mem, dst ) ); 7233 ins_pipe(iload_mem); 7234%} 7235 7236// LoadL-locked. Same as a regular long load when used with a compare-swap 7237instruct loadLLocked(iRegL dst, memory mem) %{ 7238 match(Set dst (LoadLLocked mem)); 7239 ins_cost(MEMORY_REF_COST); 7240 size(4); 7241 format %{ "LDX $mem,$dst\t! long" %} 7242 opcode(Assembler::ldx_op3); 7243 ins_encode(simple_form3_mem_reg( mem, dst ) ); 7244 ins_pipe(iload_mem); 7245%} 7246 7247instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7248 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7249 effect( KILL newval ); 7250 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7251 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7252 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7253 ins_pipe( long_memory_op ); 7254%} 7255 7256// Conditional-store of an int value. 7257instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7258 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7259 effect( KILL newval ); 7260 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7261 "CMP $oldval,$newval\t\t! See if we made progress" %} 7262 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7263 ins_pipe( long_memory_op ); 7264%} 7265 7266// Conditional-store of a long value. 7267instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7268 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7269 effect( KILL newval ); 7270 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7271 "CMP $oldval,$newval\t\t! See if we made progress" %} 7272 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7273 ins_pipe( long_memory_op ); 7274%} 7275 7276// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7277 7278instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7279 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7280 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7281 format %{ 7282 "MOV $newval,O7\n\t" 7283 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7284 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7285 "MOV 1,$res\n\t" 7286 "MOVne xcc,R_G0,$res" 7287 %} 7288 ins_encode( enc_casx(mem_ptr, oldval, newval), 7289 enc_lflags_ne_to_boolean(res) ); 7290 ins_pipe( long_memory_op ); 7291%} 7292 7293 7294instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7295 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7296 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7297 format %{ 7298 "MOV $newval,O7\n\t" 7299 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7300 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7301 "MOV 1,$res\n\t" 7302 "MOVne icc,R_G0,$res" 7303 %} 7304 ins_encode( enc_casi(mem_ptr, oldval, newval), 7305 enc_iflags_ne_to_boolean(res) ); 7306 ins_pipe( long_memory_op ); 7307%} 7308 7309instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7310 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7311 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7312 format %{ 7313 "MOV $newval,O7\n\t" 7314 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7315 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7316 "MOV 1,$res\n\t" 7317 "MOVne xcc,R_G0,$res" 7318 %} 7319#ifdef _LP64 7320 ins_encode( enc_casx(mem_ptr, oldval, newval), 7321 enc_lflags_ne_to_boolean(res) ); 7322#else 7323 ins_encode( enc_casi(mem_ptr, oldval, newval), 7324 enc_iflags_ne_to_boolean(res) ); 7325#endif 7326 ins_pipe( long_memory_op ); 7327%} 7328 7329instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7330 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7331 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7332 format %{ 7333 "MOV $newval,O7\n\t" 7334 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7335 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7336 "MOV 1,$res\n\t" 7337 "MOVne icc,R_G0,$res" 7338 %} 7339 ins_encode( enc_casi(mem_ptr, oldval, newval), 7340 enc_iflags_ne_to_boolean(res) ); 7341 ins_pipe( long_memory_op ); 7342%} 7343 7344//--------------------- 7345// Subtraction Instructions 7346// Register Subtraction 7347instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7348 match(Set dst (SubI src1 src2)); 7349 7350 size(4); 7351 format %{ "SUB $src1,$src2,$dst" %} 7352 opcode(Assembler::sub_op3, Assembler::arith_op); 7353 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7354 ins_pipe(ialu_reg_reg); 7355%} 7356 7357// Immediate Subtraction 7358instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7359 match(Set dst (SubI src1 src2)); 7360 7361 size(4); 7362 format %{ "SUB $src1,$src2,$dst" %} 7363 opcode(Assembler::sub_op3, Assembler::arith_op); 7364 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7365 ins_pipe(ialu_reg_imm); 7366%} 7367 7368instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7369 match(Set dst (SubI zero src2)); 7370 7371 size(4); 7372 format %{ "NEG $src2,$dst" %} 7373 opcode(Assembler::sub_op3, Assembler::arith_op); 7374 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7375 ins_pipe(ialu_zero_reg); 7376%} 7377 7378// Long subtraction 7379instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7380 match(Set dst (SubL src1 src2)); 7381 7382 size(4); 7383 format %{ "SUB $src1,$src2,$dst\t! long" %} 7384 opcode(Assembler::sub_op3, Assembler::arith_op); 7385 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7386 ins_pipe(ialu_reg_reg); 7387%} 7388 7389// Immediate Subtraction 7390instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7391 match(Set dst (SubL src1 con)); 7392 7393 size(4); 7394 format %{ "SUB $src1,$con,$dst\t! long" %} 7395 opcode(Assembler::sub_op3, Assembler::arith_op); 7396 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7397 ins_pipe(ialu_reg_imm); 7398%} 7399 7400// Long negation 7401instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7402 match(Set dst (SubL zero src2)); 7403 7404 size(4); 7405 format %{ "NEG $src2,$dst\t! long" %} 7406 opcode(Assembler::sub_op3, Assembler::arith_op); 7407 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7408 ins_pipe(ialu_zero_reg); 7409%} 7410 7411// Multiplication Instructions 7412// Integer Multiplication 7413// Register Multiplication 7414instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7415 match(Set dst (MulI src1 src2)); 7416 7417 size(4); 7418 format %{ "MULX $src1,$src2,$dst" %} 7419 opcode(Assembler::mulx_op3, Assembler::arith_op); 7420 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7421 ins_pipe(imul_reg_reg); 7422%} 7423 7424// Immediate Multiplication 7425instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7426 match(Set dst (MulI src1 src2)); 7427 7428 size(4); 7429 format %{ "MULX $src1,$src2,$dst" %} 7430 opcode(Assembler::mulx_op3, Assembler::arith_op); 7431 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7432 ins_pipe(imul_reg_imm); 7433%} 7434 7435instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7436 match(Set dst (MulL src1 src2)); 7437 ins_cost(DEFAULT_COST * 5); 7438 size(4); 7439 format %{ "MULX $src1,$src2,$dst\t! long" %} 7440 opcode(Assembler::mulx_op3, Assembler::arith_op); 7441 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7442 ins_pipe(mulL_reg_reg); 7443%} 7444 7445// Immediate Multiplication 7446instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7447 match(Set dst (MulL src1 src2)); 7448 ins_cost(DEFAULT_COST * 5); 7449 size(4); 7450 format %{ "MULX $src1,$src2,$dst" %} 7451 opcode(Assembler::mulx_op3, Assembler::arith_op); 7452 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7453 ins_pipe(mulL_reg_imm); 7454%} 7455 7456// Integer Division 7457// Register Division 7458instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7459 match(Set dst (DivI src1 src2)); 7460 ins_cost((2+71)*DEFAULT_COST); 7461 7462 format %{ "SRA $src2,0,$src2\n\t" 7463 "SRA $src1,0,$src1\n\t" 7464 "SDIVX $src1,$src2,$dst" %} 7465 ins_encode( idiv_reg( src1, src2, dst ) ); 7466 ins_pipe(sdiv_reg_reg); 7467%} 7468 7469// Immediate Division 7470instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7471 match(Set dst (DivI src1 src2)); 7472 ins_cost((2+71)*DEFAULT_COST); 7473 7474 format %{ "SRA $src1,0,$src1\n\t" 7475 "SDIVX $src1,$src2,$dst" %} 7476 ins_encode( idiv_imm( src1, src2, dst ) ); 7477 ins_pipe(sdiv_reg_imm); 7478%} 7479 7480//----------Div-By-10-Expansion------------------------------------------------ 7481// Extract hi bits of a 32x32->64 bit multiply. 7482// Expand rule only, not matched 7483instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7484 effect( DEF dst, USE src1, USE src2 ); 7485 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7486 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7487 ins_encode( enc_mul_hi(dst,src1,src2)); 7488 ins_pipe(sdiv_reg_reg); 7489%} 7490 7491// Magic constant, reciprocal of 10 7492instruct loadConI_x66666667(iRegIsafe dst) %{ 7493 effect( DEF dst ); 7494 7495 size(8); 7496 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7497 ins_encode( Set32(0x66666667, dst) ); 7498 ins_pipe(ialu_hi_lo_reg); 7499%} 7500 7501// Register Shift Right Arithmetic Long by 32-63 7502instruct sra_31( iRegI dst, iRegI src ) %{ 7503 effect( DEF dst, USE src ); 7504 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7505 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7506 ins_pipe(ialu_reg_reg); 7507%} 7508 7509// Arithmetic Shift Right by 8-bit immediate 7510instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7511 effect( DEF dst, USE src ); 7512 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7513 opcode(Assembler::sra_op3, Assembler::arith_op); 7514 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7515 ins_pipe(ialu_reg_imm); 7516%} 7517 7518// Integer DIV with 10 7519instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7520 match(Set dst (DivI src div)); 7521 ins_cost((6+6)*DEFAULT_COST); 7522 expand %{ 7523 iRegIsafe tmp1; // Killed temps; 7524 iRegIsafe tmp2; // Killed temps; 7525 iRegI tmp3; // Killed temps; 7526 iRegI tmp4; // Killed temps; 7527 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7528 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7529 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7530 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7531 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7532 %} 7533%} 7534 7535// Register Long Division 7536instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7537 match(Set dst (DivL src1 src2)); 7538 ins_cost(DEFAULT_COST*71); 7539 size(4); 7540 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7541 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7542 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7543 ins_pipe(divL_reg_reg); 7544%} 7545 7546// Register Long Division 7547instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7548 match(Set dst (DivL src1 src2)); 7549 ins_cost(DEFAULT_COST*71); 7550 size(4); 7551 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7552 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7553 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7554 ins_pipe(divL_reg_imm); 7555%} 7556 7557// Integer Remainder 7558// Register Remainder 7559instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7560 match(Set dst (ModI src1 src2)); 7561 effect( KILL ccr, KILL temp); 7562 7563 format %{ "SREM $src1,$src2,$dst" %} 7564 ins_encode( irem_reg(src1, src2, dst, temp) ); 7565 ins_pipe(sdiv_reg_reg); 7566%} 7567 7568// Immediate Remainder 7569instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7570 match(Set dst (ModI src1 src2)); 7571 effect( KILL ccr, KILL temp); 7572 7573 format %{ "SREM $src1,$src2,$dst" %} 7574 ins_encode( irem_imm(src1, src2, dst, temp) ); 7575 ins_pipe(sdiv_reg_imm); 7576%} 7577 7578// Register Long Remainder 7579instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7580 effect(DEF dst, USE src1, USE src2); 7581 size(4); 7582 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7583 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7584 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7585 ins_pipe(divL_reg_reg); 7586%} 7587 7588// Register Long Division 7589instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7590 effect(DEF dst, USE src1, USE src2); 7591 size(4); 7592 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7593 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7594 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7595 ins_pipe(divL_reg_imm); 7596%} 7597 7598instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7599 effect(DEF dst, USE src1, USE src2); 7600 size(4); 7601 format %{ "MULX $src1,$src2,$dst\t! long" %} 7602 opcode(Assembler::mulx_op3, Assembler::arith_op); 7603 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7604 ins_pipe(mulL_reg_reg); 7605%} 7606 7607// Immediate Multiplication 7608instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7609 effect(DEF dst, USE src1, USE src2); 7610 size(4); 7611 format %{ "MULX $src1,$src2,$dst" %} 7612 opcode(Assembler::mulx_op3, Assembler::arith_op); 7613 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7614 ins_pipe(mulL_reg_imm); 7615%} 7616 7617instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7618 effect(DEF dst, USE src1, USE src2); 7619 size(4); 7620 format %{ "SUB $src1,$src2,$dst\t! long" %} 7621 opcode(Assembler::sub_op3, Assembler::arith_op); 7622 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7623 ins_pipe(ialu_reg_reg); 7624%} 7625 7626instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7627 effect(DEF dst, USE src1, USE src2); 7628 size(4); 7629 format %{ "SUB $src1,$src2,$dst\t! long" %} 7630 opcode(Assembler::sub_op3, Assembler::arith_op); 7631 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7632 ins_pipe(ialu_reg_reg); 7633%} 7634 7635// Register Long Remainder 7636instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7637 match(Set dst (ModL src1 src2)); 7638 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7639 expand %{ 7640 iRegL tmp1; 7641 iRegL tmp2; 7642 divL_reg_reg_1(tmp1, src1, src2); 7643 mulL_reg_reg_1(tmp2, tmp1, src2); 7644 subL_reg_reg_1(dst, src1, tmp2); 7645 %} 7646%} 7647 7648// Register Long Remainder 7649instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7650 match(Set dst (ModL src1 src2)); 7651 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7652 expand %{ 7653 iRegL tmp1; 7654 iRegL tmp2; 7655 divL_reg_imm13_1(tmp1, src1, src2); 7656 mulL_reg_imm13_1(tmp2, tmp1, src2); 7657 subL_reg_reg_2 (dst, src1, tmp2); 7658 %} 7659%} 7660 7661// Integer Shift Instructions 7662// Register Shift Left 7663instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7664 match(Set dst (LShiftI src1 src2)); 7665 7666 size(4); 7667 format %{ "SLL $src1,$src2,$dst" %} 7668 opcode(Assembler::sll_op3, Assembler::arith_op); 7669 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7670 ins_pipe(ialu_reg_reg); 7671%} 7672 7673// Register Shift Left Immediate 7674instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7675 match(Set dst (LShiftI src1 src2)); 7676 7677 size(4); 7678 format %{ "SLL $src1,$src2,$dst" %} 7679 opcode(Assembler::sll_op3, Assembler::arith_op); 7680 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7681 ins_pipe(ialu_reg_imm); 7682%} 7683 7684// Register Shift Left 7685instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7686 match(Set dst (LShiftL src1 src2)); 7687 7688 size(4); 7689 format %{ "SLLX $src1,$src2,$dst" %} 7690 opcode(Assembler::sllx_op3, Assembler::arith_op); 7691 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7692 ins_pipe(ialu_reg_reg); 7693%} 7694 7695// Register Shift Left Immediate 7696instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7697 match(Set dst (LShiftL src1 src2)); 7698 7699 size(4); 7700 format %{ "SLLX $src1,$src2,$dst" %} 7701 opcode(Assembler::sllx_op3, Assembler::arith_op); 7702 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7703 ins_pipe(ialu_reg_imm); 7704%} 7705 7706// Register Arithmetic Shift Right 7707instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7708 match(Set dst (RShiftI src1 src2)); 7709 size(4); 7710 format %{ "SRA $src1,$src2,$dst" %} 7711 opcode(Assembler::sra_op3, Assembler::arith_op); 7712 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7713 ins_pipe(ialu_reg_reg); 7714%} 7715 7716// Register Arithmetic Shift Right Immediate 7717instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7718 match(Set dst (RShiftI src1 src2)); 7719 7720 size(4); 7721 format %{ "SRA $src1,$src2,$dst" %} 7722 opcode(Assembler::sra_op3, Assembler::arith_op); 7723 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7724 ins_pipe(ialu_reg_imm); 7725%} 7726 7727// Register Shift Right Arithmatic Long 7728instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7729 match(Set dst (RShiftL src1 src2)); 7730 7731 size(4); 7732 format %{ "SRAX $src1,$src2,$dst" %} 7733 opcode(Assembler::srax_op3, Assembler::arith_op); 7734 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7735 ins_pipe(ialu_reg_reg); 7736%} 7737 7738// Register Shift Left Immediate 7739instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7740 match(Set dst (RShiftL src1 src2)); 7741 7742 size(4); 7743 format %{ "SRAX $src1,$src2,$dst" %} 7744 opcode(Assembler::srax_op3, Assembler::arith_op); 7745 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7746 ins_pipe(ialu_reg_imm); 7747%} 7748 7749// Register Shift Right 7750instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7751 match(Set dst (URShiftI src1 src2)); 7752 7753 size(4); 7754 format %{ "SRL $src1,$src2,$dst" %} 7755 opcode(Assembler::srl_op3, Assembler::arith_op); 7756 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7757 ins_pipe(ialu_reg_reg); 7758%} 7759 7760// Register Shift Right Immediate 7761instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7762 match(Set dst (URShiftI src1 src2)); 7763 7764 size(4); 7765 format %{ "SRL $src1,$src2,$dst" %} 7766 opcode(Assembler::srl_op3, Assembler::arith_op); 7767 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7768 ins_pipe(ialu_reg_imm); 7769%} 7770 7771// Register Shift Right 7772instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7773 match(Set dst (URShiftL src1 src2)); 7774 7775 size(4); 7776 format %{ "SRLX $src1,$src2,$dst" %} 7777 opcode(Assembler::srlx_op3, Assembler::arith_op); 7778 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7779 ins_pipe(ialu_reg_reg); 7780%} 7781 7782// Register Shift Right Immediate 7783instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7784 match(Set dst (URShiftL src1 src2)); 7785 7786 size(4); 7787 format %{ "SRLX $src1,$src2,$dst" %} 7788 opcode(Assembler::srlx_op3, Assembler::arith_op); 7789 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7790 ins_pipe(ialu_reg_imm); 7791%} 7792 7793// Register Shift Right Immediate with a CastP2X 7794#ifdef _LP64 7795instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7796 match(Set dst (URShiftL (CastP2X src1) src2)); 7797 size(4); 7798 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7799 opcode(Assembler::srlx_op3, Assembler::arith_op); 7800 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7801 ins_pipe(ialu_reg_imm); 7802%} 7803#else 7804instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7805 match(Set dst (URShiftI (CastP2X src1) src2)); 7806 size(4); 7807 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7808 opcode(Assembler::srl_op3, Assembler::arith_op); 7809 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7810 ins_pipe(ialu_reg_imm); 7811%} 7812#endif 7813 7814 7815//----------Floating Point Arithmetic Instructions----------------------------- 7816 7817// Add float single precision 7818instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7819 match(Set dst (AddF src1 src2)); 7820 7821 size(4); 7822 format %{ "FADDS $src1,$src2,$dst" %} 7823 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7824 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7825 ins_pipe(faddF_reg_reg); 7826%} 7827 7828// Add float double precision 7829instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7830 match(Set dst (AddD src1 src2)); 7831 7832 size(4); 7833 format %{ "FADDD $src1,$src2,$dst" %} 7834 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7835 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7836 ins_pipe(faddD_reg_reg); 7837%} 7838 7839// Sub float single precision 7840instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7841 match(Set dst (SubF src1 src2)); 7842 7843 size(4); 7844 format %{ "FSUBS $src1,$src2,$dst" %} 7845 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7846 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7847 ins_pipe(faddF_reg_reg); 7848%} 7849 7850// Sub float double precision 7851instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7852 match(Set dst (SubD src1 src2)); 7853 7854 size(4); 7855 format %{ "FSUBD $src1,$src2,$dst" %} 7856 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7857 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7858 ins_pipe(faddD_reg_reg); 7859%} 7860 7861// Mul float single precision 7862instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7863 match(Set dst (MulF src1 src2)); 7864 7865 size(4); 7866 format %{ "FMULS $src1,$src2,$dst" %} 7867 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7868 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7869 ins_pipe(fmulF_reg_reg); 7870%} 7871 7872// Mul float double precision 7873instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7874 match(Set dst (MulD src1 src2)); 7875 7876 size(4); 7877 format %{ "FMULD $src1,$src2,$dst" %} 7878 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7879 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7880 ins_pipe(fmulD_reg_reg); 7881%} 7882 7883// Div float single precision 7884instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7885 match(Set dst (DivF src1 src2)); 7886 7887 size(4); 7888 format %{ "FDIVS $src1,$src2,$dst" %} 7889 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7890 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7891 ins_pipe(fdivF_reg_reg); 7892%} 7893 7894// Div float double precision 7895instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7896 match(Set dst (DivD src1 src2)); 7897 7898 size(4); 7899 format %{ "FDIVD $src1,$src2,$dst" %} 7900 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7901 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7902 ins_pipe(fdivD_reg_reg); 7903%} 7904 7905// Absolute float double precision 7906instruct absD_reg(regD dst, regD src) %{ 7907 match(Set dst (AbsD src)); 7908 7909 format %{ "FABSd $src,$dst" %} 7910 ins_encode(fabsd(dst, src)); 7911 ins_pipe(faddD_reg); 7912%} 7913 7914// Absolute float single precision 7915instruct absF_reg(regF dst, regF src) %{ 7916 match(Set dst (AbsF src)); 7917 7918 format %{ "FABSs $src,$dst" %} 7919 ins_encode(fabss(dst, src)); 7920 ins_pipe(faddF_reg); 7921%} 7922 7923instruct negF_reg(regF dst, regF src) %{ 7924 match(Set dst (NegF src)); 7925 7926 size(4); 7927 format %{ "FNEGs $src,$dst" %} 7928 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7929 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7930 ins_pipe(faddF_reg); 7931%} 7932 7933instruct negD_reg(regD dst, regD src) %{ 7934 match(Set dst (NegD src)); 7935 7936 format %{ "FNEGd $src,$dst" %} 7937 ins_encode(fnegd(dst, src)); 7938 ins_pipe(faddD_reg); 7939%} 7940 7941// Sqrt float double precision 7942instruct sqrtF_reg_reg(regF dst, regF src) %{ 7943 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7944 7945 size(4); 7946 format %{ "FSQRTS $src,$dst" %} 7947 ins_encode(fsqrts(dst, src)); 7948 ins_pipe(fdivF_reg_reg); 7949%} 7950 7951// Sqrt float double precision 7952instruct sqrtD_reg_reg(regD dst, regD src) %{ 7953 match(Set dst (SqrtD src)); 7954 7955 size(4); 7956 format %{ "FSQRTD $src,$dst" %} 7957 ins_encode(fsqrtd(dst, src)); 7958 ins_pipe(fdivD_reg_reg); 7959%} 7960 7961//----------Logical Instructions----------------------------------------------- 7962// And Instructions 7963// Register And 7964instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7965 match(Set dst (AndI src1 src2)); 7966 7967 size(4); 7968 format %{ "AND $src1,$src2,$dst" %} 7969 opcode(Assembler::and_op3, Assembler::arith_op); 7970 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7971 ins_pipe(ialu_reg_reg); 7972%} 7973 7974// Immediate And 7975instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7976 match(Set dst (AndI src1 src2)); 7977 7978 size(4); 7979 format %{ "AND $src1,$src2,$dst" %} 7980 opcode(Assembler::and_op3, Assembler::arith_op); 7981 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7982 ins_pipe(ialu_reg_imm); 7983%} 7984 7985// Register And Long 7986instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7987 match(Set dst (AndL src1 src2)); 7988 7989 ins_cost(DEFAULT_COST); 7990 size(4); 7991 format %{ "AND $src1,$src2,$dst\t! long" %} 7992 opcode(Assembler::and_op3, Assembler::arith_op); 7993 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7994 ins_pipe(ialu_reg_reg); 7995%} 7996 7997instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7998 match(Set dst (AndL src1 con)); 7999 8000 ins_cost(DEFAULT_COST); 8001 size(4); 8002 format %{ "AND $src1,$con,$dst\t! long" %} 8003 opcode(Assembler::and_op3, Assembler::arith_op); 8004 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8005 ins_pipe(ialu_reg_imm); 8006%} 8007 8008// Or Instructions 8009// Register Or 8010instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8011 match(Set dst (OrI src1 src2)); 8012 8013 size(4); 8014 format %{ "OR $src1,$src2,$dst" %} 8015 opcode(Assembler::or_op3, Assembler::arith_op); 8016 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8017 ins_pipe(ialu_reg_reg); 8018%} 8019 8020// Immediate Or 8021instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8022 match(Set dst (OrI src1 src2)); 8023 8024 size(4); 8025 format %{ "OR $src1,$src2,$dst" %} 8026 opcode(Assembler::or_op3, Assembler::arith_op); 8027 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8028 ins_pipe(ialu_reg_imm); 8029%} 8030 8031// Register Or Long 8032instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8033 match(Set dst (OrL src1 src2)); 8034 8035 ins_cost(DEFAULT_COST); 8036 size(4); 8037 format %{ "OR $src1,$src2,$dst\t! long" %} 8038 opcode(Assembler::or_op3, Assembler::arith_op); 8039 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8040 ins_pipe(ialu_reg_reg); 8041%} 8042 8043instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8044 match(Set dst (OrL src1 con)); 8045 ins_cost(DEFAULT_COST*2); 8046 8047 ins_cost(DEFAULT_COST); 8048 size(4); 8049 format %{ "OR $src1,$con,$dst\t! long" %} 8050 opcode(Assembler::or_op3, Assembler::arith_op); 8051 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8052 ins_pipe(ialu_reg_imm); 8053%} 8054 8055#ifndef _LP64 8056 8057// Use sp_ptr_RegP to match G2 (TLS register) without spilling. 8058instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 8059 match(Set dst (OrI src1 (CastP2X src2))); 8060 8061 size(4); 8062 format %{ "OR $src1,$src2,$dst" %} 8063 opcode(Assembler::or_op3, Assembler::arith_op); 8064 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8065 ins_pipe(ialu_reg_reg); 8066%} 8067 8068#else 8069 8070instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 8071 match(Set dst (OrL src1 (CastP2X src2))); 8072 8073 ins_cost(DEFAULT_COST); 8074 size(4); 8075 format %{ "OR $src1,$src2,$dst\t! long" %} 8076 opcode(Assembler::or_op3, Assembler::arith_op); 8077 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8078 ins_pipe(ialu_reg_reg); 8079%} 8080 8081#endif 8082 8083// Xor Instructions 8084// Register Xor 8085instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 8086 match(Set dst (XorI src1 src2)); 8087 8088 size(4); 8089 format %{ "XOR $src1,$src2,$dst" %} 8090 opcode(Assembler::xor_op3, Assembler::arith_op); 8091 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8092 ins_pipe(ialu_reg_reg); 8093%} 8094 8095// Immediate Xor 8096instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 8097 match(Set dst (XorI src1 src2)); 8098 8099 size(4); 8100 format %{ "XOR $src1,$src2,$dst" %} 8101 opcode(Assembler::xor_op3, Assembler::arith_op); 8102 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 8103 ins_pipe(ialu_reg_imm); 8104%} 8105 8106// Register Xor Long 8107instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 8108 match(Set dst (XorL src1 src2)); 8109 8110 ins_cost(DEFAULT_COST); 8111 size(4); 8112 format %{ "XOR $src1,$src2,$dst\t! long" %} 8113 opcode(Assembler::xor_op3, Assembler::arith_op); 8114 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 8115 ins_pipe(ialu_reg_reg); 8116%} 8117 8118instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 8119 match(Set dst (XorL src1 con)); 8120 8121 ins_cost(DEFAULT_COST); 8122 size(4); 8123 format %{ "XOR $src1,$con,$dst\t! long" %} 8124 opcode(Assembler::xor_op3, Assembler::arith_op); 8125 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 8126 ins_pipe(ialu_reg_imm); 8127%} 8128 8129//----------Convert to Boolean------------------------------------------------- 8130// Nice hack for 32-bit tests but doesn't work for 8131// 64-bit pointers. 8132instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 8133 match(Set dst (Conv2B src)); 8134 effect( KILL ccr ); 8135 ins_cost(DEFAULT_COST*2); 8136 format %{ "CMP R_G0,$src\n\t" 8137 "ADDX R_G0,0,$dst" %} 8138 ins_encode( enc_to_bool( src, dst ) ); 8139 ins_pipe(ialu_reg_ialu); 8140%} 8141 8142#ifndef _LP64 8143instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 8144 match(Set dst (Conv2B src)); 8145 effect( KILL ccr ); 8146 ins_cost(DEFAULT_COST*2); 8147 format %{ "CMP R_G0,$src\n\t" 8148 "ADDX R_G0,0,$dst" %} 8149 ins_encode( enc_to_bool( src, dst ) ); 8150 ins_pipe(ialu_reg_ialu); 8151%} 8152#else 8153instruct convP2B( iRegI dst, iRegP src ) %{ 8154 match(Set dst (Conv2B src)); 8155 ins_cost(DEFAULT_COST*2); 8156 format %{ "MOV $src,$dst\n\t" 8157 "MOVRNZ $src,1,$dst" %} 8158 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8159 ins_pipe(ialu_clr_and_mover); 8160%} 8161#endif 8162 8163instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 8164 match(Set dst (CmpLTMask src zero)); 8165 effect(KILL ccr); 8166 size(4); 8167 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 8168 ins_encode %{ 8169 __ sra($src$$Register, 31, $dst$$Register); 8170 %} 8171 ins_pipe(ialu_reg_imm); 8172%} 8173 8174instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8175 match(Set dst (CmpLTMask p q)); 8176 effect( KILL ccr ); 8177 ins_cost(DEFAULT_COST*4); 8178 format %{ "CMP $p,$q\n\t" 8179 "MOV #0,$dst\n\t" 8180 "BLT,a .+8\n\t" 8181 "MOV #-1,$dst" %} 8182 ins_encode( enc_ltmask(p,q,dst) ); 8183 ins_pipe(ialu_reg_reg_ialu); 8184%} 8185 8186instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8187 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8188 effect(KILL ccr, TEMP tmp); 8189 ins_cost(DEFAULT_COST*3); 8190 8191 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8192 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8193 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8194 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8195 ins_pipe( cadd_cmpltmask ); 8196%} 8197 8198 8199//----------------------------------------------------------------- 8200// Direct raw moves between float and general registers using VIS3. 8201 8202// ins_pipe(faddF_reg); 8203instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 8204 predicate(UseVIS >= 3); 8205 match(Set dst (MoveF2I src)); 8206 8207 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 8208 ins_encode %{ 8209 __ movstouw($src$$FloatRegister, $dst$$Register); 8210 %} 8211 ins_pipe(ialu_reg_reg); 8212%} 8213 8214instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 8215 predicate(UseVIS >= 3); 8216 match(Set dst (MoveI2F src)); 8217 8218 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 8219 ins_encode %{ 8220 __ movwtos($src$$Register, $dst$$FloatRegister); 8221 %} 8222 ins_pipe(ialu_reg_reg); 8223%} 8224 8225instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 8226 predicate(UseVIS >= 3); 8227 match(Set dst (MoveD2L src)); 8228 8229 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 8230 ins_encode %{ 8231 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 8232 %} 8233 ins_pipe(ialu_reg_reg); 8234%} 8235 8236instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 8237 predicate(UseVIS >= 3); 8238 match(Set dst (MoveL2D src)); 8239 8240 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 8241 ins_encode %{ 8242 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 8243 %} 8244 ins_pipe(ialu_reg_reg); 8245%} 8246 8247 8248// Raw moves between float and general registers using stack. 8249 8250instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8251 match(Set dst (MoveF2I src)); 8252 effect(DEF dst, USE src); 8253 ins_cost(MEMORY_REF_COST); 8254 8255 size(4); 8256 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8257 opcode(Assembler::lduw_op3); 8258 ins_encode(simple_form3_mem_reg( src, dst ) ); 8259 ins_pipe(iload_mem); 8260%} 8261 8262instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8263 match(Set dst (MoveI2F src)); 8264 effect(DEF dst, USE src); 8265 ins_cost(MEMORY_REF_COST); 8266 8267 size(4); 8268 format %{ "LDF $src,$dst\t! MoveI2F" %} 8269 opcode(Assembler::ldf_op3); 8270 ins_encode(simple_form3_mem_reg(src, dst)); 8271 ins_pipe(floadF_stk); 8272%} 8273 8274instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8275 match(Set dst (MoveD2L src)); 8276 effect(DEF dst, USE src); 8277 ins_cost(MEMORY_REF_COST); 8278 8279 size(4); 8280 format %{ "LDX $src,$dst\t! MoveD2L" %} 8281 opcode(Assembler::ldx_op3); 8282 ins_encode(simple_form3_mem_reg( src, dst ) ); 8283 ins_pipe(iload_mem); 8284%} 8285 8286instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8287 match(Set dst (MoveL2D src)); 8288 effect(DEF dst, USE src); 8289 ins_cost(MEMORY_REF_COST); 8290 8291 size(4); 8292 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8293 opcode(Assembler::lddf_op3); 8294 ins_encode(simple_form3_mem_reg(src, dst)); 8295 ins_pipe(floadD_stk); 8296%} 8297 8298instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8299 match(Set dst (MoveF2I src)); 8300 effect(DEF dst, USE src); 8301 ins_cost(MEMORY_REF_COST); 8302 8303 size(4); 8304 format %{ "STF $src,$dst\t! MoveF2I" %} 8305 opcode(Assembler::stf_op3); 8306 ins_encode(simple_form3_mem_reg(dst, src)); 8307 ins_pipe(fstoreF_stk_reg); 8308%} 8309 8310instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8311 match(Set dst (MoveI2F src)); 8312 effect(DEF dst, USE src); 8313 ins_cost(MEMORY_REF_COST); 8314 8315 size(4); 8316 format %{ "STW $src,$dst\t! MoveI2F" %} 8317 opcode(Assembler::stw_op3); 8318 ins_encode(simple_form3_mem_reg( dst, src ) ); 8319 ins_pipe(istore_mem_reg); 8320%} 8321 8322instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8323 match(Set dst (MoveD2L src)); 8324 effect(DEF dst, USE src); 8325 ins_cost(MEMORY_REF_COST); 8326 8327 size(4); 8328 format %{ "STDF $src,$dst\t! MoveD2L" %} 8329 opcode(Assembler::stdf_op3); 8330 ins_encode(simple_form3_mem_reg(dst, src)); 8331 ins_pipe(fstoreD_stk_reg); 8332%} 8333 8334instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8335 match(Set dst (MoveL2D src)); 8336 effect(DEF dst, USE src); 8337 ins_cost(MEMORY_REF_COST); 8338 8339 size(4); 8340 format %{ "STX $src,$dst\t! MoveL2D" %} 8341 opcode(Assembler::stx_op3); 8342 ins_encode(simple_form3_mem_reg( dst, src ) ); 8343 ins_pipe(istore_mem_reg); 8344%} 8345 8346 8347//----------Arithmetic Conversion Instructions--------------------------------- 8348// The conversions operations are all Alpha sorted. Please keep it that way! 8349 8350instruct convD2F_reg(regF dst, regD src) %{ 8351 match(Set dst (ConvD2F src)); 8352 size(4); 8353 format %{ "FDTOS $src,$dst" %} 8354 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8355 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8356 ins_pipe(fcvtD2F); 8357%} 8358 8359 8360// Convert a double to an int in a float register. 8361// If the double is a NAN, stuff a zero in instead. 8362instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8363 effect(DEF dst, USE src, KILL fcc0); 8364 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8365 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8366 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8367 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8368 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8369 "skip:" %} 8370 ins_encode(form_d2i_helper(src,dst)); 8371 ins_pipe(fcvtD2I); 8372%} 8373 8374instruct convD2I_stk(stackSlotI dst, regD src) %{ 8375 match(Set dst (ConvD2I src)); 8376 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8377 expand %{ 8378 regF tmp; 8379 convD2I_helper(tmp, src); 8380 regF_to_stkI(dst, tmp); 8381 %} 8382%} 8383 8384instruct convD2I_reg(iRegI dst, regD src) %{ 8385 predicate(UseVIS >= 3); 8386 match(Set dst (ConvD2I src)); 8387 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8388 expand %{ 8389 regF tmp; 8390 convD2I_helper(tmp, src); 8391 MoveF2I_reg_reg(dst, tmp); 8392 %} 8393%} 8394 8395 8396// Convert a double to a long in a double register. 8397// If the double is a NAN, stuff a zero in instead. 8398instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8399 effect(DEF dst, USE src, KILL fcc0); 8400 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8401 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8402 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8403 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8404 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8405 "skip:" %} 8406 ins_encode(form_d2l_helper(src,dst)); 8407 ins_pipe(fcvtD2L); 8408%} 8409 8410instruct convD2L_stk(stackSlotL dst, regD src) %{ 8411 match(Set dst (ConvD2L src)); 8412 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8413 expand %{ 8414 regD tmp; 8415 convD2L_helper(tmp, src); 8416 regD_to_stkL(dst, tmp); 8417 %} 8418%} 8419 8420instruct convD2L_reg(iRegL dst, regD src) %{ 8421 predicate(UseVIS >= 3); 8422 match(Set dst (ConvD2L src)); 8423 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8424 expand %{ 8425 regD tmp; 8426 convD2L_helper(tmp, src); 8427 MoveD2L_reg_reg(dst, tmp); 8428 %} 8429%} 8430 8431 8432instruct convF2D_reg(regD dst, regF src) %{ 8433 match(Set dst (ConvF2D src)); 8434 format %{ "FSTOD $src,$dst" %} 8435 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8436 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8437 ins_pipe(fcvtF2D); 8438%} 8439 8440 8441// Convert a float to an int in a float register. 8442// If the float is a NAN, stuff a zero in instead. 8443instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8444 effect(DEF dst, USE src, KILL fcc0); 8445 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8446 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8447 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8448 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8449 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8450 "skip:" %} 8451 ins_encode(form_f2i_helper(src,dst)); 8452 ins_pipe(fcvtF2I); 8453%} 8454 8455instruct convF2I_stk(stackSlotI dst, regF src) %{ 8456 match(Set dst (ConvF2I src)); 8457 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8458 expand %{ 8459 regF tmp; 8460 convF2I_helper(tmp, src); 8461 regF_to_stkI(dst, tmp); 8462 %} 8463%} 8464 8465instruct convF2I_reg(iRegI dst, regF src) %{ 8466 predicate(UseVIS >= 3); 8467 match(Set dst (ConvF2I src)); 8468 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8469 expand %{ 8470 regF tmp; 8471 convF2I_helper(tmp, src); 8472 MoveF2I_reg_reg(dst, tmp); 8473 %} 8474%} 8475 8476 8477// Convert a float to a long in a float register. 8478// If the float is a NAN, stuff a zero in instead. 8479instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8480 effect(DEF dst, USE src, KILL fcc0); 8481 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8482 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8483 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8484 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8485 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8486 "skip:" %} 8487 ins_encode(form_f2l_helper(src,dst)); 8488 ins_pipe(fcvtF2L); 8489%} 8490 8491instruct convF2L_stk(stackSlotL dst, regF src) %{ 8492 match(Set dst (ConvF2L src)); 8493 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8494 expand %{ 8495 regD tmp; 8496 convF2L_helper(tmp, src); 8497 regD_to_stkL(dst, tmp); 8498 %} 8499%} 8500 8501instruct convF2L_reg(iRegL dst, regF src) %{ 8502 predicate(UseVIS >= 3); 8503 match(Set dst (ConvF2L src)); 8504 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8505 expand %{ 8506 regD tmp; 8507 convF2L_helper(tmp, src); 8508 MoveD2L_reg_reg(dst, tmp); 8509 %} 8510%} 8511 8512 8513instruct convI2D_helper(regD dst, regF tmp) %{ 8514 effect(USE tmp, DEF dst); 8515 format %{ "FITOD $tmp,$dst" %} 8516 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8517 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8518 ins_pipe(fcvtI2D); 8519%} 8520 8521instruct convI2D_stk(stackSlotI src, regD dst) %{ 8522 match(Set dst (ConvI2D src)); 8523 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8524 expand %{ 8525 regF tmp; 8526 stkI_to_regF(tmp, src); 8527 convI2D_helper(dst, tmp); 8528 %} 8529%} 8530 8531instruct convI2D_reg(regD_low dst, iRegI src) %{ 8532 predicate(UseVIS >= 3); 8533 match(Set dst (ConvI2D src)); 8534 expand %{ 8535 regF tmp; 8536 MoveI2F_reg_reg(tmp, src); 8537 convI2D_helper(dst, tmp); 8538 %} 8539%} 8540 8541instruct convI2D_mem(regD_low dst, memory mem) %{ 8542 match(Set dst (ConvI2D (LoadI mem))); 8543 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8544 size(8); 8545 format %{ "LDF $mem,$dst\n\t" 8546 "FITOD $dst,$dst" %} 8547 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8548 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8549 ins_pipe(floadF_mem); 8550%} 8551 8552 8553instruct convI2F_helper(regF dst, regF tmp) %{ 8554 effect(DEF dst, USE tmp); 8555 format %{ "FITOS $tmp,$dst" %} 8556 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8557 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8558 ins_pipe(fcvtI2F); 8559%} 8560 8561instruct convI2F_stk(regF dst, stackSlotI src) %{ 8562 match(Set dst (ConvI2F src)); 8563 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8564 expand %{ 8565 regF tmp; 8566 stkI_to_regF(tmp,src); 8567 convI2F_helper(dst, tmp); 8568 %} 8569%} 8570 8571instruct convI2F_reg(regF dst, iRegI src) %{ 8572 predicate(UseVIS >= 3); 8573 match(Set dst (ConvI2F src)); 8574 ins_cost(DEFAULT_COST); 8575 expand %{ 8576 regF tmp; 8577 MoveI2F_reg_reg(tmp, src); 8578 convI2F_helper(dst, tmp); 8579 %} 8580%} 8581 8582instruct convI2F_mem( regF dst, memory mem ) %{ 8583 match(Set dst (ConvI2F (LoadI mem))); 8584 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8585 size(8); 8586 format %{ "LDF $mem,$dst\n\t" 8587 "FITOS $dst,$dst" %} 8588 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8589 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8590 ins_pipe(floadF_mem); 8591%} 8592 8593 8594instruct convI2L_reg(iRegL dst, iRegI src) %{ 8595 match(Set dst (ConvI2L src)); 8596 size(4); 8597 format %{ "SRA $src,0,$dst\t! int->long" %} 8598 opcode(Assembler::sra_op3, Assembler::arith_op); 8599 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8600 ins_pipe(ialu_reg_reg); 8601%} 8602 8603// Zero-extend convert int to long 8604instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8605 match(Set dst (AndL (ConvI2L src) mask) ); 8606 size(4); 8607 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8608 opcode(Assembler::srl_op3, Assembler::arith_op); 8609 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8610 ins_pipe(ialu_reg_reg); 8611%} 8612 8613// Zero-extend long 8614instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8615 match(Set dst (AndL src mask) ); 8616 size(4); 8617 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8618 opcode(Assembler::srl_op3, Assembler::arith_op); 8619 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8620 ins_pipe(ialu_reg_reg); 8621%} 8622 8623 8624//----------- 8625// Long to Double conversion using V8 opcodes. 8626// Still useful because cheetah traps and becomes 8627// amazingly slow for some common numbers. 8628 8629// Magic constant, 0x43300000 8630instruct loadConI_x43300000(iRegI dst) %{ 8631 effect(DEF dst); 8632 size(4); 8633 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8634 ins_encode(SetHi22(0x43300000, dst)); 8635 ins_pipe(ialu_none); 8636%} 8637 8638// Magic constant, 0x41f00000 8639instruct loadConI_x41f00000(iRegI dst) %{ 8640 effect(DEF dst); 8641 size(4); 8642 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8643 ins_encode(SetHi22(0x41f00000, dst)); 8644 ins_pipe(ialu_none); 8645%} 8646 8647// Construct a double from two float halves 8648instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8649 effect(DEF dst, USE src1, USE src2); 8650 size(8); 8651 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8652 "FMOVS $src2.lo,$dst.lo" %} 8653 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8654 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8655 ins_pipe(faddD_reg_reg); 8656%} 8657 8658// Convert integer in high half of a double register (in the lower half of 8659// the double register file) to double 8660instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8661 effect(DEF dst, USE src); 8662 size(4); 8663 format %{ "FITOD $src,$dst" %} 8664 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8665 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8666 ins_pipe(fcvtLHi2D); 8667%} 8668 8669// Add float double precision 8670instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8671 effect(DEF dst, USE src1, USE src2); 8672 size(4); 8673 format %{ "FADDD $src1,$src2,$dst" %} 8674 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8675 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8676 ins_pipe(faddD_reg_reg); 8677%} 8678 8679// Sub float double precision 8680instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8681 effect(DEF dst, USE src1, USE src2); 8682 size(4); 8683 format %{ "FSUBD $src1,$src2,$dst" %} 8684 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8685 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8686 ins_pipe(faddD_reg_reg); 8687%} 8688 8689// Mul float double precision 8690instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8691 effect(DEF dst, USE src1, USE src2); 8692 size(4); 8693 format %{ "FMULD $src1,$src2,$dst" %} 8694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8695 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8696 ins_pipe(fmulD_reg_reg); 8697%} 8698 8699instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8700 match(Set dst (ConvL2D src)); 8701 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8702 8703 expand %{ 8704 regD_low tmpsrc; 8705 iRegI ix43300000; 8706 iRegI ix41f00000; 8707 stackSlotL lx43300000; 8708 stackSlotL lx41f00000; 8709 regD_low dx43300000; 8710 regD dx41f00000; 8711 regD tmp1; 8712 regD_low tmp2; 8713 regD tmp3; 8714 regD tmp4; 8715 8716 stkL_to_regD(tmpsrc, src); 8717 8718 loadConI_x43300000(ix43300000); 8719 loadConI_x41f00000(ix41f00000); 8720 regI_to_stkLHi(lx43300000, ix43300000); 8721 regI_to_stkLHi(lx41f00000, ix41f00000); 8722 stkL_to_regD(dx43300000, lx43300000); 8723 stkL_to_regD(dx41f00000, lx41f00000); 8724 8725 convI2D_regDHi_regD(tmp1, tmpsrc); 8726 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8727 subD_regD_regD(tmp3, tmp2, dx43300000); 8728 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8729 addD_regD_regD(dst, tmp3, tmp4); 8730 %} 8731%} 8732 8733// Long to Double conversion using fast fxtof 8734instruct convL2D_helper(regD dst, regD tmp) %{ 8735 effect(DEF dst, USE tmp); 8736 size(4); 8737 format %{ "FXTOD $tmp,$dst" %} 8738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8739 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8740 ins_pipe(fcvtL2D); 8741%} 8742 8743instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8744 predicate(VM_Version::has_fast_fxtof()); 8745 match(Set dst (ConvL2D src)); 8746 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8747 expand %{ 8748 regD tmp; 8749 stkL_to_regD(tmp, src); 8750 convL2D_helper(dst, tmp); 8751 %} 8752%} 8753 8754instruct convL2D_reg(regD dst, iRegL src) %{ 8755 predicate(UseVIS >= 3); 8756 match(Set dst (ConvL2D src)); 8757 expand %{ 8758 regD tmp; 8759 MoveL2D_reg_reg(tmp, src); 8760 convL2D_helper(dst, tmp); 8761 %} 8762%} 8763 8764// Long to Float conversion using fast fxtof 8765instruct convL2F_helper(regF dst, regD tmp) %{ 8766 effect(DEF dst, USE tmp); 8767 size(4); 8768 format %{ "FXTOS $tmp,$dst" %} 8769 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8770 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8771 ins_pipe(fcvtL2F); 8772%} 8773 8774instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8775 match(Set dst (ConvL2F src)); 8776 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8777 expand %{ 8778 regD tmp; 8779 stkL_to_regD(tmp, src); 8780 convL2F_helper(dst, tmp); 8781 %} 8782%} 8783 8784instruct convL2F_reg(regF dst, iRegL src) %{ 8785 predicate(UseVIS >= 3); 8786 match(Set dst (ConvL2F src)); 8787 ins_cost(DEFAULT_COST); 8788 expand %{ 8789 regD tmp; 8790 MoveL2D_reg_reg(tmp, src); 8791 convL2F_helper(dst, tmp); 8792 %} 8793%} 8794 8795//----------- 8796 8797instruct convL2I_reg(iRegI dst, iRegL src) %{ 8798 match(Set dst (ConvL2I src)); 8799#ifndef _LP64 8800 format %{ "MOV $src.lo,$dst\t! long->int" %} 8801 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8802 ins_pipe(ialu_move_reg_I_to_L); 8803#else 8804 size(4); 8805 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8806 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8807 ins_pipe(ialu_reg); 8808#endif 8809%} 8810 8811// Register Shift Right Immediate 8812instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8813 match(Set dst (ConvL2I (RShiftL src cnt))); 8814 8815 size(4); 8816 format %{ "SRAX $src,$cnt,$dst" %} 8817 opcode(Assembler::srax_op3, Assembler::arith_op); 8818 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8819 ins_pipe(ialu_reg_imm); 8820%} 8821 8822// Replicate scalar to packed byte values in Double register 8823instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8824 effect(DEF dst, USE src); 8825 format %{ "SLLX $src,56,$dst\n\t" 8826 "SRLX $dst, 8,O7\n\t" 8827 "OR $dst,O7,$dst\n\t" 8828 "SRLX $dst,16,O7\n\t" 8829 "OR $dst,O7,$dst\n\t" 8830 "SRLX $dst,32,O7\n\t" 8831 "OR $dst,O7,$dst\t! replicate8B" %} 8832 ins_encode( enc_repl8b(src, dst)); 8833 ins_pipe(ialu_reg); 8834%} 8835 8836// Replicate scalar to packed byte values in Double register 8837instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8838 match(Set dst (Replicate8B src)); 8839 expand %{ 8840 iRegL tmp; 8841 Repl8B_reg_helper(tmp, src); 8842 regL_to_stkD(dst, tmp); 8843 %} 8844%} 8845 8846// Replicate scalar constant to packed byte values in Double register 8847instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 8848 match(Set dst (Replicate8B con)); 8849 effect(KILL tmp); 8850 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 8851 ins_encode %{ 8852 // XXX This is a quick fix for 6833573. 8853 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 8854 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 8855 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 8856 %} 8857 ins_pipe(loadConFD); 8858%} 8859 8860// Replicate scalar to packed char values into stack slot 8861instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8862 effect(DEF dst, USE src); 8863 format %{ "SLLX $src,48,$dst\n\t" 8864 "SRLX $dst,16,O7\n\t" 8865 "OR $dst,O7,$dst\n\t" 8866 "SRLX $dst,32,O7\n\t" 8867 "OR $dst,O7,$dst\t! replicate4C" %} 8868 ins_encode( enc_repl4s(src, dst) ); 8869 ins_pipe(ialu_reg); 8870%} 8871 8872// Replicate scalar to packed char values into stack slot 8873instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8874 match(Set dst (Replicate4C src)); 8875 expand %{ 8876 iRegL tmp; 8877 Repl4C_reg_helper(tmp, src); 8878 regL_to_stkD(dst, tmp); 8879 %} 8880%} 8881 8882// Replicate scalar constant to packed char values in Double register 8883instruct Repl4C_immI(regD dst, immI con, o7RegI tmp) %{ 8884 match(Set dst (Replicate4C con)); 8885 effect(KILL tmp); 8886 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4C($con)" %} 8887 ins_encode %{ 8888 // XXX This is a quick fix for 6833573. 8889 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 8890 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 8891 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 8892 %} 8893 ins_pipe(loadConFD); 8894%} 8895 8896// Replicate scalar to packed short values into stack slot 8897instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8898 effect(DEF dst, USE src); 8899 format %{ "SLLX $src,48,$dst\n\t" 8900 "SRLX $dst,16,O7\n\t" 8901 "OR $dst,O7,$dst\n\t" 8902 "SRLX $dst,32,O7\n\t" 8903 "OR $dst,O7,$dst\t! replicate4S" %} 8904 ins_encode( enc_repl4s(src, dst) ); 8905 ins_pipe(ialu_reg); 8906%} 8907 8908// Replicate scalar to packed short values into stack slot 8909instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8910 match(Set dst (Replicate4S src)); 8911 expand %{ 8912 iRegL tmp; 8913 Repl4S_reg_helper(tmp, src); 8914 regL_to_stkD(dst, tmp); 8915 %} 8916%} 8917 8918// Replicate scalar constant to packed short values in Double register 8919instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 8920 match(Set dst (Replicate4S con)); 8921 effect(KILL tmp); 8922 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 8923 ins_encode %{ 8924 // XXX This is a quick fix for 6833573. 8925 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 8926 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 8927 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 8928 %} 8929 ins_pipe(loadConFD); 8930%} 8931 8932// Replicate scalar to packed int values in Double register 8933instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8934 effect(DEF dst, USE src); 8935 format %{ "SLLX $src,32,$dst\n\t" 8936 "SRLX $dst,32,O7\n\t" 8937 "OR $dst,O7,$dst\t! replicate2I" %} 8938 ins_encode( enc_repl2i(src, dst)); 8939 ins_pipe(ialu_reg); 8940%} 8941 8942// Replicate scalar to packed int values in Double register 8943instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8944 match(Set dst (Replicate2I src)); 8945 expand %{ 8946 iRegL tmp; 8947 Repl2I_reg_helper(tmp, src); 8948 regL_to_stkD(dst, tmp); 8949 %} 8950%} 8951 8952// Replicate scalar zero constant to packed int values in Double register 8953instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 8954 match(Set dst (Replicate2I con)); 8955 effect(KILL tmp); 8956 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 8957 ins_encode %{ 8958 // XXX This is a quick fix for 6833573. 8959 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 8960 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 8961 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 8962 %} 8963 ins_pipe(loadConFD); 8964%} 8965 8966//----------Control Flow Instructions------------------------------------------ 8967// Compare Instructions 8968// Compare Integers 8969instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8970 match(Set icc (CmpI op1 op2)); 8971 effect( DEF icc, USE op1, USE op2 ); 8972 8973 size(4); 8974 format %{ "CMP $op1,$op2" %} 8975 opcode(Assembler::subcc_op3, Assembler::arith_op); 8976 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8977 ins_pipe(ialu_cconly_reg_reg); 8978%} 8979 8980instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8981 match(Set icc (CmpU op1 op2)); 8982 8983 size(4); 8984 format %{ "CMP $op1,$op2\t! unsigned" %} 8985 opcode(Assembler::subcc_op3, Assembler::arith_op); 8986 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8987 ins_pipe(ialu_cconly_reg_reg); 8988%} 8989 8990instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8991 match(Set icc (CmpI op1 op2)); 8992 effect( DEF icc, USE op1 ); 8993 8994 size(4); 8995 format %{ "CMP $op1,$op2" %} 8996 opcode(Assembler::subcc_op3, Assembler::arith_op); 8997 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8998 ins_pipe(ialu_cconly_reg_imm); 8999%} 9000 9001instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 9002 match(Set icc (CmpI (AndI op1 op2) zero)); 9003 9004 size(4); 9005 format %{ "BTST $op2,$op1" %} 9006 opcode(Assembler::andcc_op3, Assembler::arith_op); 9007 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9008 ins_pipe(ialu_cconly_reg_reg_zero); 9009%} 9010 9011instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 9012 match(Set icc (CmpI (AndI op1 op2) zero)); 9013 9014 size(4); 9015 format %{ "BTST $op2,$op1" %} 9016 opcode(Assembler::andcc_op3, Assembler::arith_op); 9017 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9018 ins_pipe(ialu_cconly_reg_imm_zero); 9019%} 9020 9021instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 9022 match(Set xcc (CmpL op1 op2)); 9023 effect( DEF xcc, USE op1, USE op2 ); 9024 9025 size(4); 9026 format %{ "CMP $op1,$op2\t\t! long" %} 9027 opcode(Assembler::subcc_op3, Assembler::arith_op); 9028 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9029 ins_pipe(ialu_cconly_reg_reg); 9030%} 9031 9032instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 9033 match(Set xcc (CmpL op1 con)); 9034 effect( DEF xcc, USE op1, USE con ); 9035 9036 size(4); 9037 format %{ "CMP $op1,$con\t\t! long" %} 9038 opcode(Assembler::subcc_op3, Assembler::arith_op); 9039 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 9040 ins_pipe(ialu_cconly_reg_reg); 9041%} 9042 9043instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 9044 match(Set xcc (CmpL (AndL op1 op2) zero)); 9045 effect( DEF xcc, USE op1, USE op2 ); 9046 9047 size(4); 9048 format %{ "BTST $op1,$op2\t\t! long" %} 9049 opcode(Assembler::andcc_op3, Assembler::arith_op); 9050 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9051 ins_pipe(ialu_cconly_reg_reg); 9052%} 9053 9054// useful for checking the alignment of a pointer: 9055instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 9056 match(Set xcc (CmpL (AndL op1 con) zero)); 9057 effect( DEF xcc, USE op1, USE con ); 9058 9059 size(4); 9060 format %{ "BTST $op1,$con\t\t! long" %} 9061 opcode(Assembler::andcc_op3, Assembler::arith_op); 9062 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 9063 ins_pipe(ialu_cconly_reg_reg); 9064%} 9065 9066instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 9067 match(Set icc (CmpU op1 op2)); 9068 9069 size(4); 9070 format %{ "CMP $op1,$op2\t! unsigned" %} 9071 opcode(Assembler::subcc_op3, Assembler::arith_op); 9072 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9073 ins_pipe(ialu_cconly_reg_imm); 9074%} 9075 9076// Compare Pointers 9077instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 9078 match(Set pcc (CmpP op1 op2)); 9079 9080 size(4); 9081 format %{ "CMP $op1,$op2\t! ptr" %} 9082 opcode(Assembler::subcc_op3, Assembler::arith_op); 9083 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9084 ins_pipe(ialu_cconly_reg_reg); 9085%} 9086 9087instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 9088 match(Set pcc (CmpP op1 op2)); 9089 9090 size(4); 9091 format %{ "CMP $op1,$op2\t! ptr" %} 9092 opcode(Assembler::subcc_op3, Assembler::arith_op); 9093 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9094 ins_pipe(ialu_cconly_reg_imm); 9095%} 9096 9097// Compare Narrow oops 9098instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 9099 match(Set icc (CmpN op1 op2)); 9100 9101 size(4); 9102 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9103 opcode(Assembler::subcc_op3, Assembler::arith_op); 9104 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 9105 ins_pipe(ialu_cconly_reg_reg); 9106%} 9107 9108instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 9109 match(Set icc (CmpN op1 op2)); 9110 9111 size(4); 9112 format %{ "CMP $op1,$op2\t! compressed ptr" %} 9113 opcode(Assembler::subcc_op3, Assembler::arith_op); 9114 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 9115 ins_pipe(ialu_cconly_reg_imm); 9116%} 9117 9118//----------Max and Min-------------------------------------------------------- 9119// Min Instructions 9120// Conditional move for min 9121instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9122 effect( USE_DEF op2, USE op1, USE icc ); 9123 9124 size(4); 9125 format %{ "MOVlt icc,$op1,$op2\t! min" %} 9126 opcode(Assembler::less); 9127 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9128 ins_pipe(ialu_reg_flags); 9129%} 9130 9131// Min Register with Register. 9132instruct minI_eReg(iRegI op1, iRegI op2) %{ 9133 match(Set op2 (MinI op1 op2)); 9134 ins_cost(DEFAULT_COST*2); 9135 expand %{ 9136 flagsReg icc; 9137 compI_iReg(icc,op1,op2); 9138 cmovI_reg_lt(op2,op1,icc); 9139 %} 9140%} 9141 9142// Max Instructions 9143// Conditional move for max 9144instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 9145 effect( USE_DEF op2, USE op1, USE icc ); 9146 format %{ "MOVgt icc,$op1,$op2\t! max" %} 9147 opcode(Assembler::greater); 9148 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 9149 ins_pipe(ialu_reg_flags); 9150%} 9151 9152// Max Register with Register 9153instruct maxI_eReg(iRegI op1, iRegI op2) %{ 9154 match(Set op2 (MaxI op1 op2)); 9155 ins_cost(DEFAULT_COST*2); 9156 expand %{ 9157 flagsReg icc; 9158 compI_iReg(icc,op1,op2); 9159 cmovI_reg_gt(op2,op1,icc); 9160 %} 9161%} 9162 9163 9164//----------Float Compares---------------------------------------------------- 9165// Compare floating, generate condition code 9166instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 9167 match(Set fcc (CmpF src1 src2)); 9168 9169 size(4); 9170 format %{ "FCMPs $fcc,$src1,$src2" %} 9171 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 9172 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 9173 ins_pipe(faddF_fcc_reg_reg_zero); 9174%} 9175 9176instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 9177 match(Set fcc (CmpD src1 src2)); 9178 9179 size(4); 9180 format %{ "FCMPd $fcc,$src1,$src2" %} 9181 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 9182 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 9183 ins_pipe(faddD_fcc_reg_reg_zero); 9184%} 9185 9186 9187// Compare floating, generate -1,0,1 9188instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 9189 match(Set dst (CmpF3 src1 src2)); 9190 effect(KILL fcc0); 9191 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9192 format %{ "fcmpl $dst,$src1,$src2" %} 9193 // Primary = float 9194 opcode( true ); 9195 ins_encode( floating_cmp( dst, src1, src2 ) ); 9196 ins_pipe( floating_cmp ); 9197%} 9198 9199instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 9200 match(Set dst (CmpD3 src1 src2)); 9201 effect(KILL fcc0); 9202 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 9203 format %{ "dcmpl $dst,$src1,$src2" %} 9204 // Primary = double (not float) 9205 opcode( false ); 9206 ins_encode( floating_cmp( dst, src1, src2 ) ); 9207 ins_pipe( floating_cmp ); 9208%} 9209 9210//----------Branches--------------------------------------------------------- 9211// Jump 9212// (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 9213instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 9214 match(Jump switch_val); 9215 9216 ins_cost(350); 9217 9218 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 9219 "LD [O7 + $switch_val], O7\n\t" 9220 "JUMP O7" 9221 %} 9222 ins_encode %{ 9223 // Calculate table address into a register. 9224 Register table_reg; 9225 Register label_reg = O7; 9226 if (constant_offset() == 0) { 9227 table_reg = $constanttablebase; 9228 } else { 9229 table_reg = O7; 9230 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 9231 __ add($constanttablebase, con_offset, table_reg); 9232 } 9233 9234 // Jump to base address + switch value 9235 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 9236 __ jmp(label_reg, G0); 9237 __ delayed()->nop(); 9238 %} 9239 ins_pipe(ialu_reg_reg); 9240%} 9241 9242// Direct Branch. Use V8 version with longer range. 9243instruct branch(label labl) %{ 9244 match(Goto); 9245 effect(USE labl); 9246 9247 size(8); 9248 ins_cost(BRANCH_COST); 9249 format %{ "BA $labl" %} 9250 ins_encode %{ 9251 Label* L = $labl$$label; 9252 __ ba(*L); 9253 __ delayed()->nop(); 9254 %} 9255 ins_pipe(br); 9256%} 9257 9258// Direct Branch, short with no delay slot 9259instruct branch_short(label labl) %{ 9260 match(Goto); 9261 predicate(UseCBCond); 9262 effect(USE labl); 9263 9264 size(4); 9265 ins_cost(BRANCH_COST); 9266 format %{ "BA $labl\t! short branch" %} 9267 ins_encode %{ 9268 Label* L = $labl$$label; 9269 assert(__ use_cbcond(*L), "back to back cbcond"); 9270 __ ba_short(*L); 9271 %} 9272 ins_short_branch(1); 9273 ins_avoid_back_to_back(1); 9274 ins_pipe(cbcond_reg_imm); 9275%} 9276 9277// Conditional Direct Branch 9278instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 9279 match(If cmp icc); 9280 effect(USE labl); 9281 9282 size(8); 9283 ins_cost(BRANCH_COST); 9284 format %{ "BP$cmp $icc,$labl" %} 9285 // Prim = bits 24-22, Secnd = bits 31-30 9286 ins_encode( enc_bp( labl, cmp, icc ) ); 9287 ins_pipe(br_cc); 9288%} 9289 9290instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9291 match(If cmp icc); 9292 effect(USE labl); 9293 9294 ins_cost(BRANCH_COST); 9295 format %{ "BP$cmp $icc,$labl" %} 9296 // Prim = bits 24-22, Secnd = bits 31-30 9297 ins_encode( enc_bp( labl, cmp, icc ) ); 9298 ins_pipe(br_cc); 9299%} 9300 9301instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9302 match(If cmp pcc); 9303 effect(USE labl); 9304 9305 size(8); 9306 ins_cost(BRANCH_COST); 9307 format %{ "BP$cmp $pcc,$labl" %} 9308 ins_encode %{ 9309 Label* L = $labl$$label; 9310 Assembler::Predict predict_taken = 9311 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9312 9313 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9314 __ delayed()->nop(); 9315 %} 9316 ins_pipe(br_cc); 9317%} 9318 9319instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9320 match(If cmp fcc); 9321 effect(USE labl); 9322 9323 size(8); 9324 ins_cost(BRANCH_COST); 9325 format %{ "FBP$cmp $fcc,$labl" %} 9326 ins_encode %{ 9327 Label* L = $labl$$label; 9328 Assembler::Predict predict_taken = 9329 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9330 9331 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 9332 __ delayed()->nop(); 9333 %} 9334 ins_pipe(br_fcc); 9335%} 9336 9337instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9338 match(CountedLoopEnd cmp icc); 9339 effect(USE labl); 9340 9341 size(8); 9342 ins_cost(BRANCH_COST); 9343 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9344 // Prim = bits 24-22, Secnd = bits 31-30 9345 ins_encode( enc_bp( labl, cmp, icc ) ); 9346 ins_pipe(br_cc); 9347%} 9348 9349instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9350 match(CountedLoopEnd cmp icc); 9351 effect(USE labl); 9352 9353 size(8); 9354 ins_cost(BRANCH_COST); 9355 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9356 // Prim = bits 24-22, Secnd = bits 31-30 9357 ins_encode( enc_bp( labl, cmp, icc ) ); 9358 ins_pipe(br_cc); 9359%} 9360 9361// Compare and branch instructions 9362instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9363 match(If cmp (CmpI op1 op2)); 9364 effect(USE labl, KILL icc); 9365 9366 size(12); 9367 ins_cost(BRANCH_COST); 9368 format %{ "CMP $op1,$op2\t! int\n\t" 9369 "BP$cmp $labl" %} 9370 ins_encode %{ 9371 Label* L = $labl$$label; 9372 Assembler::Predict predict_taken = 9373 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9374 __ cmp($op1$$Register, $op2$$Register); 9375 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9376 __ delayed()->nop(); 9377 %} 9378 ins_pipe(cmp_br_reg_reg); 9379%} 9380 9381instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9382 match(If cmp (CmpI op1 op2)); 9383 effect(USE labl, KILL icc); 9384 9385 size(12); 9386 ins_cost(BRANCH_COST); 9387 format %{ "CMP $op1,$op2\t! int\n\t" 9388 "BP$cmp $labl" %} 9389 ins_encode %{ 9390 Label* L = $labl$$label; 9391 Assembler::Predict predict_taken = 9392 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9393 __ cmp($op1$$Register, $op2$$constant); 9394 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9395 __ delayed()->nop(); 9396 %} 9397 ins_pipe(cmp_br_reg_imm); 9398%} 9399 9400instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9401 match(If cmp (CmpU op1 op2)); 9402 effect(USE labl, KILL icc); 9403 9404 size(12); 9405 ins_cost(BRANCH_COST); 9406 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9407 "BP$cmp $labl" %} 9408 ins_encode %{ 9409 Label* L = $labl$$label; 9410 Assembler::Predict predict_taken = 9411 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9412 __ cmp($op1$$Register, $op2$$Register); 9413 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9414 __ delayed()->nop(); 9415 %} 9416 ins_pipe(cmp_br_reg_reg); 9417%} 9418 9419instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9420 match(If cmp (CmpU op1 op2)); 9421 effect(USE labl, KILL icc); 9422 9423 size(12); 9424 ins_cost(BRANCH_COST); 9425 format %{ "CMP $op1,$op2\t! unsigned\n\t" 9426 "BP$cmp $labl" %} 9427 ins_encode %{ 9428 Label* L = $labl$$label; 9429 Assembler::Predict predict_taken = 9430 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9431 __ cmp($op1$$Register, $op2$$constant); 9432 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9433 __ delayed()->nop(); 9434 %} 9435 ins_pipe(cmp_br_reg_imm); 9436%} 9437 9438instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9439 match(If cmp (CmpL op1 op2)); 9440 effect(USE labl, KILL xcc); 9441 9442 size(12); 9443 ins_cost(BRANCH_COST); 9444 format %{ "CMP $op1,$op2\t! long\n\t" 9445 "BP$cmp $labl" %} 9446 ins_encode %{ 9447 Label* L = $labl$$label; 9448 Assembler::Predict predict_taken = 9449 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9450 __ cmp($op1$$Register, $op2$$Register); 9451 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9452 __ delayed()->nop(); 9453 %} 9454 ins_pipe(cmp_br_reg_reg); 9455%} 9456 9457instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9458 match(If cmp (CmpL op1 op2)); 9459 effect(USE labl, KILL xcc); 9460 9461 size(12); 9462 ins_cost(BRANCH_COST); 9463 format %{ "CMP $op1,$op2\t! long\n\t" 9464 "BP$cmp $labl" %} 9465 ins_encode %{ 9466 Label* L = $labl$$label; 9467 Assembler::Predict predict_taken = 9468 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9469 __ cmp($op1$$Register, $op2$$constant); 9470 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9471 __ delayed()->nop(); 9472 %} 9473 ins_pipe(cmp_br_reg_imm); 9474%} 9475 9476// Compare Pointers and branch 9477instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9478 match(If cmp (CmpP op1 op2)); 9479 effect(USE labl, KILL pcc); 9480 9481 size(12); 9482 ins_cost(BRANCH_COST); 9483 format %{ "CMP $op1,$op2\t! ptr\n\t" 9484 "B$cmp $labl" %} 9485 ins_encode %{ 9486 Label* L = $labl$$label; 9487 Assembler::Predict predict_taken = 9488 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9489 __ cmp($op1$$Register, $op2$$Register); 9490 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9491 __ delayed()->nop(); 9492 %} 9493 ins_pipe(cmp_br_reg_reg); 9494%} 9495 9496instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9497 match(If cmp (CmpP op1 null)); 9498 effect(USE labl, KILL pcc); 9499 9500 size(12); 9501 ins_cost(BRANCH_COST); 9502 format %{ "CMP $op1,0\t! ptr\n\t" 9503 "B$cmp $labl" %} 9504 ins_encode %{ 9505 Label* L = $labl$$label; 9506 Assembler::Predict predict_taken = 9507 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9508 __ cmp($op1$$Register, G0); 9509 // bpr() is not used here since it has shorter distance. 9510 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9511 __ delayed()->nop(); 9512 %} 9513 ins_pipe(cmp_br_reg_reg); 9514%} 9515 9516instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9517 match(If cmp (CmpN op1 op2)); 9518 effect(USE labl, KILL icc); 9519 9520 size(12); 9521 ins_cost(BRANCH_COST); 9522 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9523 "BP$cmp $labl" %} 9524 ins_encode %{ 9525 Label* L = $labl$$label; 9526 Assembler::Predict predict_taken = 9527 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9528 __ cmp($op1$$Register, $op2$$Register); 9529 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9530 __ delayed()->nop(); 9531 %} 9532 ins_pipe(cmp_br_reg_reg); 9533%} 9534 9535instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9536 match(If cmp (CmpN op1 null)); 9537 effect(USE labl, KILL icc); 9538 9539 size(12); 9540 ins_cost(BRANCH_COST); 9541 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9542 "BP$cmp $labl" %} 9543 ins_encode %{ 9544 Label* L = $labl$$label; 9545 Assembler::Predict predict_taken = 9546 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9547 __ cmp($op1$$Register, G0); 9548 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9549 __ delayed()->nop(); 9550 %} 9551 ins_pipe(cmp_br_reg_reg); 9552%} 9553 9554// Loop back branch 9555instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9556 match(CountedLoopEnd cmp (CmpI op1 op2)); 9557 effect(USE labl, KILL icc); 9558 9559 size(12); 9560 ins_cost(BRANCH_COST); 9561 format %{ "CMP $op1,$op2\t! int\n\t" 9562 "BP$cmp $labl\t! Loop end" %} 9563 ins_encode %{ 9564 Label* L = $labl$$label; 9565 Assembler::Predict predict_taken = 9566 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9567 __ cmp($op1$$Register, $op2$$Register); 9568 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9569 __ delayed()->nop(); 9570 %} 9571 ins_pipe(cmp_br_reg_reg); 9572%} 9573 9574instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9575 match(CountedLoopEnd cmp (CmpI op1 op2)); 9576 effect(USE labl, KILL icc); 9577 9578 size(12); 9579 ins_cost(BRANCH_COST); 9580 format %{ "CMP $op1,$op2\t! int\n\t" 9581 "BP$cmp $labl\t! Loop end" %} 9582 ins_encode %{ 9583 Label* L = $labl$$label; 9584 Assembler::Predict predict_taken = 9585 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9586 __ cmp($op1$$Register, $op2$$constant); 9587 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9588 __ delayed()->nop(); 9589 %} 9590 ins_pipe(cmp_br_reg_imm); 9591%} 9592 9593// Short compare and branch instructions 9594instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9595 match(If cmp (CmpI op1 op2)); 9596 predicate(UseCBCond); 9597 effect(USE labl, KILL icc); 9598 9599 size(4); 9600 ins_cost(BRANCH_COST); 9601 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9602 ins_encode %{ 9603 Label* L = $labl$$label; 9604 assert(__ use_cbcond(*L), "back to back cbcond"); 9605 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9606 %} 9607 ins_short_branch(1); 9608 ins_avoid_back_to_back(1); 9609 ins_pipe(cbcond_reg_reg); 9610%} 9611 9612instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9613 match(If cmp (CmpI op1 op2)); 9614 predicate(UseCBCond); 9615 effect(USE labl, KILL icc); 9616 9617 size(4); 9618 ins_cost(BRANCH_COST); 9619 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9620 ins_encode %{ 9621 Label* L = $labl$$label; 9622 assert(__ use_cbcond(*L), "back to back cbcond"); 9623 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9624 %} 9625 ins_short_branch(1); 9626 ins_avoid_back_to_back(1); 9627 ins_pipe(cbcond_reg_imm); 9628%} 9629 9630instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9631 match(If cmp (CmpU op1 op2)); 9632 predicate(UseCBCond); 9633 effect(USE labl, KILL icc); 9634 9635 size(4); 9636 ins_cost(BRANCH_COST); 9637 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9638 ins_encode %{ 9639 Label* L = $labl$$label; 9640 assert(__ use_cbcond(*L), "back to back cbcond"); 9641 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9642 %} 9643 ins_short_branch(1); 9644 ins_avoid_back_to_back(1); 9645 ins_pipe(cbcond_reg_reg); 9646%} 9647 9648instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9649 match(If cmp (CmpU op1 op2)); 9650 predicate(UseCBCond); 9651 effect(USE labl, KILL icc); 9652 9653 size(4); 9654 ins_cost(BRANCH_COST); 9655 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9656 ins_encode %{ 9657 Label* L = $labl$$label; 9658 assert(__ use_cbcond(*L), "back to back cbcond"); 9659 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9660 %} 9661 ins_short_branch(1); 9662 ins_avoid_back_to_back(1); 9663 ins_pipe(cbcond_reg_imm); 9664%} 9665 9666instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9667 match(If cmp (CmpL op1 op2)); 9668 predicate(UseCBCond); 9669 effect(USE labl, KILL xcc); 9670 9671 size(4); 9672 ins_cost(BRANCH_COST); 9673 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9674 ins_encode %{ 9675 Label* L = $labl$$label; 9676 assert(__ use_cbcond(*L), "back to back cbcond"); 9677 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9678 %} 9679 ins_short_branch(1); 9680 ins_avoid_back_to_back(1); 9681 ins_pipe(cbcond_reg_reg); 9682%} 9683 9684instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9685 match(If cmp (CmpL op1 op2)); 9686 predicate(UseCBCond); 9687 effect(USE labl, KILL xcc); 9688 9689 size(4); 9690 ins_cost(BRANCH_COST); 9691 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9692 ins_encode %{ 9693 Label* L = $labl$$label; 9694 assert(__ use_cbcond(*L), "back to back cbcond"); 9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9696 %} 9697 ins_short_branch(1); 9698 ins_avoid_back_to_back(1); 9699 ins_pipe(cbcond_reg_imm); 9700%} 9701 9702// Compare Pointers and branch 9703instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9704 match(If cmp (CmpP op1 op2)); 9705 predicate(UseCBCond); 9706 effect(USE labl, KILL pcc); 9707 9708 size(4); 9709 ins_cost(BRANCH_COST); 9710#ifdef _LP64 9711 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9712#else 9713 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %} 9714#endif 9715 ins_encode %{ 9716 Label* L = $labl$$label; 9717 assert(__ use_cbcond(*L), "back to back cbcond"); 9718 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9719 %} 9720 ins_short_branch(1); 9721 ins_avoid_back_to_back(1); 9722 ins_pipe(cbcond_reg_reg); 9723%} 9724 9725instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9726 match(If cmp (CmpP op1 null)); 9727 predicate(UseCBCond); 9728 effect(USE labl, KILL pcc); 9729 9730 size(4); 9731 ins_cost(BRANCH_COST); 9732#ifdef _LP64 9733 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9734#else 9735 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %} 9736#endif 9737 ins_encode %{ 9738 Label* L = $labl$$label; 9739 assert(__ use_cbcond(*L), "back to back cbcond"); 9740 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9741 %} 9742 ins_short_branch(1); 9743 ins_avoid_back_to_back(1); 9744 ins_pipe(cbcond_reg_reg); 9745%} 9746 9747instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9748 match(If cmp (CmpN op1 op2)); 9749 predicate(UseCBCond); 9750 effect(USE labl, KILL icc); 9751 9752 size(4); 9753 ins_cost(BRANCH_COST); 9754 format %{ "CWB$cmp $op1,op2,$labl\t! compressed ptr" %} 9755 ins_encode %{ 9756 Label* L = $labl$$label; 9757 assert(__ use_cbcond(*L), "back to back cbcond"); 9758 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9759 %} 9760 ins_short_branch(1); 9761 ins_avoid_back_to_back(1); 9762 ins_pipe(cbcond_reg_reg); 9763%} 9764 9765instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9766 match(If cmp (CmpN op1 null)); 9767 predicate(UseCBCond); 9768 effect(USE labl, KILL icc); 9769 9770 size(4); 9771 ins_cost(BRANCH_COST); 9772 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9773 ins_encode %{ 9774 Label* L = $labl$$label; 9775 assert(__ use_cbcond(*L), "back to back cbcond"); 9776 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9777 %} 9778 ins_short_branch(1); 9779 ins_avoid_back_to_back(1); 9780 ins_pipe(cbcond_reg_reg); 9781%} 9782 9783// Loop back branch 9784instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9785 match(CountedLoopEnd cmp (CmpI op1 op2)); 9786 predicate(UseCBCond); 9787 effect(USE labl, KILL icc); 9788 9789 size(4); 9790 ins_cost(BRANCH_COST); 9791 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9792 ins_encode %{ 9793 Label* L = $labl$$label; 9794 assert(__ use_cbcond(*L), "back to back cbcond"); 9795 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9796 %} 9797 ins_short_branch(1); 9798 ins_avoid_back_to_back(1); 9799 ins_pipe(cbcond_reg_reg); 9800%} 9801 9802instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9803 match(CountedLoopEnd cmp (CmpI op1 op2)); 9804 predicate(UseCBCond); 9805 effect(USE labl, KILL icc); 9806 9807 size(4); 9808 ins_cost(BRANCH_COST); 9809 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9810 ins_encode %{ 9811 Label* L = $labl$$label; 9812 assert(__ use_cbcond(*L), "back to back cbcond"); 9813 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9814 %} 9815 ins_short_branch(1); 9816 ins_avoid_back_to_back(1); 9817 ins_pipe(cbcond_reg_imm); 9818%} 9819 9820// Branch-on-register tests all 64 bits. We assume that values 9821// in 64-bit registers always remains zero or sign extended 9822// unless our code munges the high bits. Interrupts can chop 9823// the high order bits to zero or sign at any time. 9824instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9825 match(If cmp (CmpI op1 zero)); 9826 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9827 effect(USE labl); 9828 9829 size(8); 9830 ins_cost(BRANCH_COST); 9831 format %{ "BR$cmp $op1,$labl" %} 9832 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9833 ins_pipe(br_reg); 9834%} 9835 9836instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9837 match(If cmp (CmpP op1 null)); 9838 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9839 effect(USE labl); 9840 9841 size(8); 9842 ins_cost(BRANCH_COST); 9843 format %{ "BR$cmp $op1,$labl" %} 9844 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9845 ins_pipe(br_reg); 9846%} 9847 9848instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9849 match(If cmp (CmpL op1 zero)); 9850 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9851 effect(USE labl); 9852 9853 size(8); 9854 ins_cost(BRANCH_COST); 9855 format %{ "BR$cmp $op1,$labl" %} 9856 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9857 ins_pipe(br_reg); 9858%} 9859 9860 9861// ============================================================================ 9862// Long Compare 9863// 9864// Currently we hold longs in 2 registers. Comparing such values efficiently 9865// is tricky. The flavor of compare used depends on whether we are testing 9866// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9867// The GE test is the negated LT test. The LE test can be had by commuting 9868// the operands (yielding a GE test) and then negating; negate again for the 9869// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9870// NE test is negated from that. 9871 9872// Due to a shortcoming in the ADLC, it mixes up expressions like: 9873// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9874// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9875// are collapsed internally in the ADLC's dfa-gen code. The match for 9876// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9877// foo match ends up with the wrong leaf. One fix is to not match both 9878// reg-reg and reg-zero forms of long-compare. This is unfortunate because 9879// both forms beat the trinary form of long-compare and both are very useful 9880// on Intel which has so few registers. 9881 9882instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9883 match(If cmp xcc); 9884 effect(USE labl); 9885 9886 size(8); 9887 ins_cost(BRANCH_COST); 9888 format %{ "BP$cmp $xcc,$labl" %} 9889 ins_encode %{ 9890 Label* L = $labl$$label; 9891 Assembler::Predict predict_taken = 9892 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9893 9894 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9895 __ delayed()->nop(); 9896 %} 9897 ins_pipe(br_cc); 9898%} 9899 9900// Manifest a CmpL3 result in an integer register. Very painful. 9901// This is the test to avoid. 9902instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9903 match(Set dst (CmpL3 src1 src2) ); 9904 effect( KILL ccr ); 9905 ins_cost(6*DEFAULT_COST); 9906 size(24); 9907 format %{ "CMP $src1,$src2\t\t! long\n" 9908 "\tBLT,a,pn done\n" 9909 "\tMOV -1,$dst\t! delay slot\n" 9910 "\tBGT,a,pn done\n" 9911 "\tMOV 1,$dst\t! delay slot\n" 9912 "\tCLR $dst\n" 9913 "done:" %} 9914 ins_encode( cmpl_flag(src1,src2,dst) ); 9915 ins_pipe(cmpL_reg); 9916%} 9917 9918// Conditional move 9919instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9920 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9921 ins_cost(150); 9922 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9923 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9924 ins_pipe(ialu_reg); 9925%} 9926 9927instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9928 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9929 ins_cost(140); 9930 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9931 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9932 ins_pipe(ialu_imm); 9933%} 9934 9935instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9936 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9937 ins_cost(150); 9938 format %{ "MOV$cmp $xcc,$src,$dst" %} 9939 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9940 ins_pipe(ialu_reg); 9941%} 9942 9943instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9944 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9945 ins_cost(140); 9946 format %{ "MOV$cmp $xcc,$src,$dst" %} 9947 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9948 ins_pipe(ialu_imm); 9949%} 9950 9951instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9952 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9953 ins_cost(150); 9954 format %{ "MOV$cmp $xcc,$src,$dst" %} 9955 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9956 ins_pipe(ialu_reg); 9957%} 9958 9959instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9960 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9961 ins_cost(150); 9962 format %{ "MOV$cmp $xcc,$src,$dst" %} 9963 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9964 ins_pipe(ialu_reg); 9965%} 9966 9967instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9968 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9969 ins_cost(140); 9970 format %{ "MOV$cmp $xcc,$src,$dst" %} 9971 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9972 ins_pipe(ialu_imm); 9973%} 9974 9975instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9976 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9977 ins_cost(150); 9978 opcode(0x101); 9979 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9980 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9981 ins_pipe(int_conditional_float_move); 9982%} 9983 9984instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9985 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9986 ins_cost(150); 9987 opcode(0x102); 9988 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9989 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9990 ins_pipe(int_conditional_float_move); 9991%} 9992 9993// ============================================================================ 9994// Safepoint Instruction 9995instruct safePoint_poll(iRegP poll) %{ 9996 match(SafePoint poll); 9997 effect(USE poll); 9998 9999 size(4); 10000#ifdef _LP64 10001 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 10002#else 10003 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 10004#endif 10005 ins_encode %{ 10006 __ relocate(relocInfo::poll_type); 10007 __ ld_ptr($poll$$Register, 0, G0); 10008 %} 10009 ins_pipe(loadPollP); 10010%} 10011 10012// ============================================================================ 10013// Call Instructions 10014// Call Java Static Instruction 10015instruct CallStaticJavaDirect( method meth ) %{ 10016 match(CallStaticJava); 10017 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 10018 effect(USE meth); 10019 10020 size(8); 10021 ins_cost(CALL_COST); 10022 format %{ "CALL,static ; NOP ==> " %} 10023 ins_encode( Java_Static_Call( meth ), call_epilog ); 10024 ins_pipe(simple_call); 10025%} 10026 10027// Call Java Static Instruction (method handle version) 10028instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 10029 match(CallStaticJava); 10030 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 10031 effect(USE meth, KILL l7_mh_SP_save); 10032 10033 size(8); 10034 ins_cost(CALL_COST); 10035 format %{ "CALL,static/MethodHandle" %} 10036 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 10037 ins_pipe(simple_call); 10038%} 10039 10040// Call Java Dynamic Instruction 10041instruct CallDynamicJavaDirect( method meth ) %{ 10042 match(CallDynamicJava); 10043 effect(USE meth); 10044 10045 ins_cost(CALL_COST); 10046 format %{ "SET (empty),R_G5\n\t" 10047 "CALL,dynamic ; NOP ==> " %} 10048 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 10049 ins_pipe(call); 10050%} 10051 10052// Call Runtime Instruction 10053instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 10054 match(CallRuntime); 10055 effect(USE meth, KILL l7); 10056 ins_cost(CALL_COST); 10057 format %{ "CALL,runtime" %} 10058 ins_encode( Java_To_Runtime( meth ), 10059 call_epilog, adjust_long_from_native_call ); 10060 ins_pipe(simple_call); 10061%} 10062 10063// Call runtime without safepoint - same as CallRuntime 10064instruct CallLeafDirect(method meth, l7RegP l7) %{ 10065 match(CallLeaf); 10066 effect(USE meth, KILL l7); 10067 ins_cost(CALL_COST); 10068 format %{ "CALL,runtime leaf" %} 10069 ins_encode( Java_To_Runtime( meth ), 10070 call_epilog, 10071 adjust_long_from_native_call ); 10072 ins_pipe(simple_call); 10073%} 10074 10075// Call runtime without safepoint - same as CallLeaf 10076instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 10077 match(CallLeafNoFP); 10078 effect(USE meth, KILL l7); 10079 ins_cost(CALL_COST); 10080 format %{ "CALL,runtime leaf nofp" %} 10081 ins_encode( Java_To_Runtime( meth ), 10082 call_epilog, 10083 adjust_long_from_native_call ); 10084 ins_pipe(simple_call); 10085%} 10086 10087// Tail Call; Jump from runtime stub to Java code. 10088// Also known as an 'interprocedural jump'. 10089// Target of jump will eventually return to caller. 10090// TailJump below removes the return address. 10091instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 10092 match(TailCall jump_target method_oop ); 10093 10094 ins_cost(CALL_COST); 10095 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 10096 ins_encode(form_jmpl(jump_target)); 10097 ins_pipe(tail_call); 10098%} 10099 10100 10101// Return Instruction 10102instruct Ret() %{ 10103 match(Return); 10104 10105 // The epilogue node did the ret already. 10106 size(0); 10107 format %{ "! return" %} 10108 ins_encode(); 10109 ins_pipe(empty); 10110%} 10111 10112 10113// Tail Jump; remove the return address; jump to target. 10114// TailCall above leaves the return address around. 10115// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 10116// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 10117// "restore" before this instruction (in Epilogue), we need to materialize it 10118// in %i0. 10119instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 10120 match( TailJump jump_target ex_oop ); 10121 ins_cost(CALL_COST); 10122 format %{ "! discard R_O7\n\t" 10123 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 10124 ins_encode(form_jmpl_set_exception_pc(jump_target)); 10125 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 10126 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 10127 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 10128 ins_pipe(tail_call); 10129%} 10130 10131// Create exception oop: created by stack-crawling runtime code. 10132// Created exception is now available to this handler, and is setup 10133// just prior to jumping to this handler. No code emitted. 10134instruct CreateException( o0RegP ex_oop ) 10135%{ 10136 match(Set ex_oop (CreateEx)); 10137 ins_cost(0); 10138 10139 size(0); 10140 // use the following format syntax 10141 format %{ "! exception oop is in R_O0; no code emitted" %} 10142 ins_encode(); 10143 ins_pipe(empty); 10144%} 10145 10146 10147// Rethrow exception: 10148// The exception oop will come in the first argument position. 10149// Then JUMP (not call) to the rethrow stub code. 10150instruct RethrowException() 10151%{ 10152 match(Rethrow); 10153 ins_cost(CALL_COST); 10154 10155 // use the following format syntax 10156 format %{ "Jmp rethrow_stub" %} 10157 ins_encode(enc_rethrow); 10158 ins_pipe(tail_call); 10159%} 10160 10161 10162// Die now 10163instruct ShouldNotReachHere( ) 10164%{ 10165 match(Halt); 10166 ins_cost(CALL_COST); 10167 10168 size(4); 10169 // Use the following format syntax 10170 format %{ "ILLTRAP ; ShouldNotReachHere" %} 10171 ins_encode( form2_illtrap() ); 10172 ins_pipe(tail_call); 10173%} 10174 10175// ============================================================================ 10176// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10177// array for an instance of the superklass. Set a hidden internal cache on a 10178// hit (cache is checked with exposed code in gen_subtype_check()). Return 10179// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10180instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 10181 match(Set index (PartialSubtypeCheck sub super)); 10182 effect( KILL pcc, KILL o7 ); 10183 ins_cost(DEFAULT_COST*10); 10184 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 10185 ins_encode( enc_PartialSubtypeCheck() ); 10186 ins_pipe(partial_subtype_check_pipe); 10187%} 10188 10189instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 10190 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 10191 effect( KILL idx, KILL o7 ); 10192 ins_cost(DEFAULT_COST*10); 10193 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 10194 ins_encode( enc_PartialSubtypeCheck() ); 10195 ins_pipe(partial_subtype_check_pipe); 10196%} 10197 10198 10199// ============================================================================ 10200// inlined locking and unlocking 10201 10202instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 10203 match(Set pcc (FastLock object box)); 10204 10205 effect(KILL scratch, TEMP scratch2); 10206 ins_cost(100); 10207 10208 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 10209 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 10210 ins_pipe(long_memory_op); 10211%} 10212 10213 10214instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 10215 match(Set pcc (FastUnlock object box)); 10216 effect(KILL scratch, TEMP scratch2); 10217 ins_cost(100); 10218 10219 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 10220 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 10221 ins_pipe(long_memory_op); 10222%} 10223 10224// Count and Base registers are fixed because the allocator cannot 10225// kill unknown registers. The encodings are generic. 10226instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 10227 match(Set dummy (ClearArray cnt base)); 10228 effect(TEMP temp, KILL ccr); 10229 ins_cost(300); 10230 format %{ "MOV $cnt,$temp\n" 10231 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 10232 " BRge loop\t\t! Clearing loop\n" 10233 " STX G0,[$base+$temp]\t! delay slot" %} 10234 ins_encode( enc_Clear_Array(cnt, base, temp) ); 10235 ins_pipe(long_memory_op); 10236%} 10237 10238instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 10239 o7RegI tmp, flagsReg ccr) %{ 10240 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 10241 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 10242 ins_cost(300); 10243 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 10244 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 10245 ins_pipe(long_memory_op); 10246%} 10247 10248instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 10249 o7RegI tmp, flagsReg ccr) %{ 10250 match(Set result (StrEquals (Binary str1 str2) cnt)); 10251 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 10252 ins_cost(300); 10253 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 10254 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 10255 ins_pipe(long_memory_op); 10256%} 10257 10258instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 10259 o7RegI tmp2, flagsReg ccr) %{ 10260 match(Set result (AryEq ary1 ary2)); 10261 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 10262 ins_cost(300); 10263 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 10264 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 10265 ins_pipe(long_memory_op); 10266%} 10267 10268 10269//---------- Zeros Count Instructions ------------------------------------------ 10270 10271instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10272 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10273 match(Set dst (CountLeadingZerosI src)); 10274 effect(TEMP dst, TEMP tmp, KILL cr); 10275 10276 // x |= (x >> 1); 10277 // x |= (x >> 2); 10278 // x |= (x >> 4); 10279 // x |= (x >> 8); 10280 // x |= (x >> 16); 10281 // return (WORDBITS - popc(x)); 10282 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10283 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10284 "OR $dst,$tmp,$dst\n\t" 10285 "SRL $dst,2,$tmp\n\t" 10286 "OR $dst,$tmp,$dst\n\t" 10287 "SRL $dst,4,$tmp\n\t" 10288 "OR $dst,$tmp,$dst\n\t" 10289 "SRL $dst,8,$tmp\n\t" 10290 "OR $dst,$tmp,$dst\n\t" 10291 "SRL $dst,16,$tmp\n\t" 10292 "OR $dst,$tmp,$dst\n\t" 10293 "POPC $dst,$dst\n\t" 10294 "MOV 32,$tmp\n\t" 10295 "SUB $tmp,$dst,$dst" %} 10296 ins_encode %{ 10297 Register Rdst = $dst$$Register; 10298 Register Rsrc = $src$$Register; 10299 Register Rtmp = $tmp$$Register; 10300 __ srl(Rsrc, 1, Rtmp); 10301 __ srl(Rsrc, 0, Rdst); 10302 __ or3(Rdst, Rtmp, Rdst); 10303 __ srl(Rdst, 2, Rtmp); 10304 __ or3(Rdst, Rtmp, Rdst); 10305 __ srl(Rdst, 4, Rtmp); 10306 __ or3(Rdst, Rtmp, Rdst); 10307 __ srl(Rdst, 8, Rtmp); 10308 __ or3(Rdst, Rtmp, Rdst); 10309 __ srl(Rdst, 16, Rtmp); 10310 __ or3(Rdst, Rtmp, Rdst); 10311 __ popc(Rdst, Rdst); 10312 __ mov(BitsPerInt, Rtmp); 10313 __ sub(Rtmp, Rdst, Rdst); 10314 %} 10315 ins_pipe(ialu_reg); 10316%} 10317 10318instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10319 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10320 match(Set dst (CountLeadingZerosL src)); 10321 effect(TEMP dst, TEMP tmp, KILL cr); 10322 10323 // x |= (x >> 1); 10324 // x |= (x >> 2); 10325 // x |= (x >> 4); 10326 // x |= (x >> 8); 10327 // x |= (x >> 16); 10328 // x |= (x >> 32); 10329 // return (WORDBITS - popc(x)); 10330 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10331 "OR $src,$tmp,$dst\n\t" 10332 "SRLX $dst,2,$tmp\n\t" 10333 "OR $dst,$tmp,$dst\n\t" 10334 "SRLX $dst,4,$tmp\n\t" 10335 "OR $dst,$tmp,$dst\n\t" 10336 "SRLX $dst,8,$tmp\n\t" 10337 "OR $dst,$tmp,$dst\n\t" 10338 "SRLX $dst,16,$tmp\n\t" 10339 "OR $dst,$tmp,$dst\n\t" 10340 "SRLX $dst,32,$tmp\n\t" 10341 "OR $dst,$tmp,$dst\n\t" 10342 "POPC $dst,$dst\n\t" 10343 "MOV 64,$tmp\n\t" 10344 "SUB $tmp,$dst,$dst" %} 10345 ins_encode %{ 10346 Register Rdst = $dst$$Register; 10347 Register Rsrc = $src$$Register; 10348 Register Rtmp = $tmp$$Register; 10349 __ srlx(Rsrc, 1, Rtmp); 10350 __ or3( Rsrc, Rtmp, Rdst); 10351 __ srlx(Rdst, 2, Rtmp); 10352 __ or3( Rdst, Rtmp, Rdst); 10353 __ srlx(Rdst, 4, Rtmp); 10354 __ or3( Rdst, Rtmp, Rdst); 10355 __ srlx(Rdst, 8, Rtmp); 10356 __ or3( Rdst, Rtmp, Rdst); 10357 __ srlx(Rdst, 16, Rtmp); 10358 __ or3( Rdst, Rtmp, Rdst); 10359 __ srlx(Rdst, 32, Rtmp); 10360 __ or3( Rdst, Rtmp, Rdst); 10361 __ popc(Rdst, Rdst); 10362 __ mov(BitsPerLong, Rtmp); 10363 __ sub(Rtmp, Rdst, Rdst); 10364 %} 10365 ins_pipe(ialu_reg); 10366%} 10367 10368instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ 10369 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10370 match(Set dst (CountTrailingZerosI src)); 10371 effect(TEMP dst, KILL cr); 10372 10373 // return popc(~x & (x - 1)); 10374 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10375 "ANDN $dst,$src,$dst\n\t" 10376 "SRL $dst,R_G0,$dst\n\t" 10377 "POPC $dst,$dst" %} 10378 ins_encode %{ 10379 Register Rdst = $dst$$Register; 10380 Register Rsrc = $src$$Register; 10381 __ sub(Rsrc, 1, Rdst); 10382 __ andn(Rdst, Rsrc, Rdst); 10383 __ srl(Rdst, G0, Rdst); 10384 __ popc(Rdst, Rdst); 10385 %} 10386 ins_pipe(ialu_reg); 10387%} 10388 10389instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ 10390 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10391 match(Set dst (CountTrailingZerosL src)); 10392 effect(TEMP dst, KILL cr); 10393 10394 // return popc(~x & (x - 1)); 10395 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10396 "ANDN $dst,$src,$dst\n\t" 10397 "POPC $dst,$dst" %} 10398 ins_encode %{ 10399 Register Rdst = $dst$$Register; 10400 Register Rsrc = $src$$Register; 10401 __ sub(Rsrc, 1, Rdst); 10402 __ andn(Rdst, Rsrc, Rdst); 10403 __ popc(Rdst, Rdst); 10404 %} 10405 ins_pipe(ialu_reg); 10406%} 10407 10408 10409//---------- Population Count Instructions ------------------------------------- 10410 10411instruct popCountI(iRegI dst, iRegI src) %{ 10412 predicate(UsePopCountInstruction); 10413 match(Set dst (PopCountI src)); 10414 10415 format %{ "POPC $src, $dst" %} 10416 ins_encode %{ 10417 __ popc($src$$Register, $dst$$Register); 10418 %} 10419 ins_pipe(ialu_reg); 10420%} 10421 10422// Note: Long.bitCount(long) returns an int. 10423instruct popCountL(iRegI dst, iRegL src) %{ 10424 predicate(UsePopCountInstruction); 10425 match(Set dst (PopCountL src)); 10426 10427 format %{ "POPC $src, $dst" %} 10428 ins_encode %{ 10429 __ popc($src$$Register, $dst$$Register); 10430 %} 10431 ins_pipe(ialu_reg); 10432%} 10433 10434 10435// ============================================================================ 10436//------------Bytes reverse-------------------------------------------------- 10437 10438instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10439 match(Set dst (ReverseBytesI src)); 10440 10441 // Op cost is artificially doubled to make sure that load or store 10442 // instructions are preferred over this one which requires a spill 10443 // onto a stack slot. 10444 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10445 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10446 10447 ins_encode %{ 10448 __ set($src$$disp + STACK_BIAS, O7); 10449 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10450 %} 10451 ins_pipe( iload_mem ); 10452%} 10453 10454instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10455 match(Set dst (ReverseBytesL src)); 10456 10457 // Op cost is artificially doubled to make sure that load or store 10458 // instructions are preferred over this one which requires a spill 10459 // onto a stack slot. 10460 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10461 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10462 10463 ins_encode %{ 10464 __ set($src$$disp + STACK_BIAS, O7); 10465 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10466 %} 10467 ins_pipe( iload_mem ); 10468%} 10469 10470instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10471 match(Set dst (ReverseBytesUS src)); 10472 10473 // Op cost is artificially doubled to make sure that load or store 10474 // instructions are preferred over this one which requires a spill 10475 // onto a stack slot. 10476 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10477 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10478 10479 ins_encode %{ 10480 // the value was spilled as an int so bias the load 10481 __ set($src$$disp + STACK_BIAS + 2, O7); 10482 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10483 %} 10484 ins_pipe( iload_mem ); 10485%} 10486 10487instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10488 match(Set dst (ReverseBytesS src)); 10489 10490 // Op cost is artificially doubled to make sure that load or store 10491 // instructions are preferred over this one which requires a spill 10492 // onto a stack slot. 10493 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10494 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10495 10496 ins_encode %{ 10497 // the value was spilled as an int so bias the load 10498 __ set($src$$disp + STACK_BIAS + 2, O7); 10499 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10500 %} 10501 ins_pipe( iload_mem ); 10502%} 10503 10504// Load Integer reversed byte order 10505instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10506 match(Set dst (ReverseBytesI (LoadI src))); 10507 10508 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10509 size(4); 10510 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10511 10512 ins_encode %{ 10513 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10514 %} 10515 ins_pipe(iload_mem); 10516%} 10517 10518// Load Long - aligned and reversed 10519instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10520 match(Set dst (ReverseBytesL (LoadL src))); 10521 10522 ins_cost(MEMORY_REF_COST); 10523 size(4); 10524 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10525 10526 ins_encode %{ 10527 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10528 %} 10529 ins_pipe(iload_mem); 10530%} 10531 10532// Load unsigned short / char reversed byte order 10533instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10534 match(Set dst (ReverseBytesUS (LoadUS src))); 10535 10536 ins_cost(MEMORY_REF_COST); 10537 size(4); 10538 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10539 10540 ins_encode %{ 10541 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10542 %} 10543 ins_pipe(iload_mem); 10544%} 10545 10546// Load short reversed byte order 10547instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10548 match(Set dst (ReverseBytesS (LoadS src))); 10549 10550 ins_cost(MEMORY_REF_COST); 10551 size(4); 10552 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10553 10554 ins_encode %{ 10555 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10556 %} 10557 ins_pipe(iload_mem); 10558%} 10559 10560// Store Integer reversed byte order 10561instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10562 match(Set dst (StoreI dst (ReverseBytesI src))); 10563 10564 ins_cost(MEMORY_REF_COST); 10565 size(4); 10566 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10567 10568 ins_encode %{ 10569 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10570 %} 10571 ins_pipe(istore_mem_reg); 10572%} 10573 10574// Store Long reversed byte order 10575instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10576 match(Set dst (StoreL dst (ReverseBytesL src))); 10577 10578 ins_cost(MEMORY_REF_COST); 10579 size(4); 10580 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10581 10582 ins_encode %{ 10583 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10584 %} 10585 ins_pipe(istore_mem_reg); 10586%} 10587 10588// Store unsighed short/char reversed byte order 10589instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10590 match(Set dst (StoreC dst (ReverseBytesUS src))); 10591 10592 ins_cost(MEMORY_REF_COST); 10593 size(4); 10594 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10595 10596 ins_encode %{ 10597 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10598 %} 10599 ins_pipe(istore_mem_reg); 10600%} 10601 10602// Store short reversed byte order 10603instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10604 match(Set dst (StoreC dst (ReverseBytesS src))); 10605 10606 ins_cost(MEMORY_REF_COST); 10607 size(4); 10608 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10609 10610 ins_encode %{ 10611 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10612 %} 10613 ins_pipe(istore_mem_reg); 10614%} 10615 10616//----------PEEPHOLE RULES----------------------------------------------------- 10617// These must follow all instruction definitions as they use the names 10618// defined in the instructions definitions. 10619// 10620// peepmatch ( root_instr_name [preceding_instruction]* ); 10621// 10622// peepconstraint %{ 10623// (instruction_number.operand_name relational_op instruction_number.operand_name 10624// [, ...] ); 10625// // instruction numbers are zero-based using left to right order in peepmatch 10626// 10627// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10628// // provide an instruction_number.operand_name for each operand that appears 10629// // in the replacement instruction's match rule 10630// 10631// ---------VM FLAGS--------------------------------------------------------- 10632// 10633// All peephole optimizations can be turned off using -XX:-OptoPeephole 10634// 10635// Each peephole rule is given an identifying number starting with zero and 10636// increasing by one in the order seen by the parser. An individual peephole 10637// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10638// on the command-line. 10639// 10640// ---------CURRENT LIMITATIONS---------------------------------------------- 10641// 10642// Only match adjacent instructions in same basic block 10643// Only equality constraints 10644// Only constraints between operands, not (0.dest_reg == EAX_enc) 10645// Only one replacement instruction 10646// 10647// ---------EXAMPLE---------------------------------------------------------- 10648// 10649// // pertinent parts of existing instructions in architecture description 10650// instruct movI(eRegI dst, eRegI src) %{ 10651// match(Set dst (CopyI src)); 10652// %} 10653// 10654// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10655// match(Set dst (AddI dst src)); 10656// effect(KILL cr); 10657// %} 10658// 10659// // Change (inc mov) to lea 10660// peephole %{ 10661// // increment preceeded by register-register move 10662// peepmatch ( incI_eReg movI ); 10663// // require that the destination register of the increment 10664// // match the destination register of the move 10665// peepconstraint ( 0.dst == 1.dst ); 10666// // construct a replacement instruction that sets 10667// // the destination to ( move's source register + one ) 10668// peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10669// %} 10670// 10671 10672// // Change load of spilled value to only a spill 10673// instruct storeI(memory mem, eRegI src) %{ 10674// match(Set mem (StoreI mem src)); 10675// %} 10676// 10677// instruct loadI(eRegI dst, memory mem) %{ 10678// match(Set dst (LoadI mem)); 10679// %} 10680// 10681// peephole %{ 10682// peepmatch ( loadI storeI ); 10683// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10684// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10685// %} 10686 10687//----------SMARTSPILL RULES--------------------------------------------------- 10688// These must follow all instruction definitions as they use the names 10689// defined in the instructions definitions. 10690// 10691// SPARC will probably not have any of these rules due to RISC instruction set. 10692 10693//----------PIPELINE----------------------------------------------------------- 10694// Rules which define the behavior of the target architectures pipeline. 10695