1// 2// Copyright (c) 1998, 2017, Oracle and/or its affiliates. All rights reserved. 3// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4// 5// This code is free software; you can redistribute it and/or modify it 6// under the terms of the GNU General Public License version 2 only, as 7// published by the Free Software Foundation. 8// 9// This code is distributed in the hope that it will be useful, but WITHOUT 10// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12// version 2 for more details (a copy is included in the LICENSE file that 13// accompanied this code). 14// 15// You should have received a copy of the GNU General Public License version 16// 2 along with this work; if not, write to the Free Software Foundation, 17// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18// 19// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20// or visit www.oracle.com if you need additional information or have any 21// questions. 22// 23// 24 25// SPARC Architecture Description File 26 27//----------REGISTER DEFINITION BLOCK------------------------------------------ 28// This information is used by the matcher and the register allocator to 29// describe individual registers and classes of registers within the target 30// archtecture. 31register %{ 32//----------Architecture Description Register Definitions---------------------- 33// General Registers 34// "reg_def" name ( register save type, C convention save type, 35// ideal register type, encoding, vm name ); 36// Register Save Types: 37// 38// NS = No-Save: The register allocator assumes that these registers 39// can be used without saving upon entry to the method, & 40// that they do not need to be saved at call sites. 41// 42// SOC = Save-On-Call: The register allocator assumes that these registers 43// can be used without saving upon entry to the method, 44// but that they must be saved at call sites. 45// 46// SOE = Save-On-Entry: The register allocator assumes that these registers 47// must be saved before using them upon entry to the 48// method, but they do not need to be saved at call 49// sites. 50// 51// AS = Always-Save: The register allocator assumes that these registers 52// must be saved before using them upon entry to the 53// method, & that they must be saved at call sites. 54// 55// Ideal Register Type is used to determine how to save & restore a 56// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 57// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 58// 59// The encoding number is the actual bit-pattern placed into the opcodes. 60 61 62// ---------------------------- 63// Integer/Long Registers 64// ---------------------------- 65 66// Need to expose the hi/lo aspect of 64-bit registers 67// This register set is used for both the 64-bit build and 68// the 32-bit build with 1-register longs. 69 70// Global Registers 0-7 71reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 72reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 73reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 74reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 75reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 76reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 77reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 78reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 79reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 80reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 81reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 82reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 83reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 84reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 85reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 86reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 87 88// Output Registers 0-7 89reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 90reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 91reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 92reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 93reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 94reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 95reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 96reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 97reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 98reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 99reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 100reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 101reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 102reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 103reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 104reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 105 106// Local Registers 0-7 107reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 108reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 109reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 110reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 111reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 112reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 113reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 114reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 115reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 116reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 117reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 118reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 119reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 120reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 121reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 122reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 123 124// Input Registers 0-7 125reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 126reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 127reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 128reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 129reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 130reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 131reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 132reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 133reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 134reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 135reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 136reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 137reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 138reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 139reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 140reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 141 142// ---------------------------- 143// Float/Double Registers 144// ---------------------------- 145 146// Float Registers 147reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 148reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 149reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 150reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 151reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 152reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 153reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 154reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 155reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 156reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 157reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 158reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 159reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 160reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 161reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 162reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 163reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 164reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 165reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 166reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 167reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 168reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 169reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 170reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 171reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 172reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 173reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 174reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 175reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 176reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 177reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 178reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 179 180// Double Registers 181// The rules of ADL require that double registers be defined in pairs. 182// Each pair must be two 32-bit values, but not necessarily a pair of 183// single float registers. In each pair, ADLC-assigned register numbers 184// must be adjacent, with the lower number even. Finally, when the 185// CPU stores such a register pair to memory, the word associated with 186// the lower ADLC-assigned number must be stored to the lower address. 187 188// These definitions specify the actual bit encodings of the sparc 189// double fp register numbers. FloatRegisterImpl in register_sparc.hpp 190// wants 0-63, so we have to convert every time we want to use fp regs 191// with the macroassembler, using reg_to_DoubleFloatRegister_object(). 192// 255 is a flag meaning "don't go here". 193// I believe we can't handle callee-save doubles D32 and up until 194// the place in the sparc stack crawler that asserts on the 255 is 195// fixed up. 196reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 197reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 198reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 199reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 200reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 201reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 202reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 203reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 204reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 205reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 206reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 207reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 208reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 209reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 210reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 211reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 212reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 213reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 214reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 215reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 216reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 217reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 218reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 219reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 220reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 221reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 222reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 223reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 224reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 225reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 226reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 227reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 228 229 230// ---------------------------- 231// Special Registers 232// Condition Codes Flag Registers 233// I tried to break out ICC and XCC but it's not very pretty. 234// Every Sparc instruction which defs/kills one also kills the other. 235// Hence every compare instruction which defs one kind of flags ends 236// up needing a kill of the other. 237reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 238 239reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 240reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 241reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 242reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 243 244// ---------------------------- 245// Specify the enum values for the registers. These enums are only used by the 246// OptoReg "class". We can convert these enum values at will to VMReg when needed 247// for visibility to the rest of the vm. The order of this enum influences the 248// register allocator so having the freedom to set this order and not be stuck 249// with the order that is natural for the rest of the vm is worth it. 250alloc_class chunk0( 251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 255 256// Note that a register is not allocatable unless it is also mentioned 257// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 258 259alloc_class chunk1( 260 // The first registers listed here are those most likely to be used 261 // as temporaries. We move F0..F7 away from the front of the list, 262 // to reduce the likelihood of interferences with parameters and 263 // return values. Likewise, we avoid using F0/F1 for parameters, 264 // since they are used for return values. 265 // This FPU fine-tuning is worth about 1% on the SPEC geomean. 266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 274 275alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 276 277//----------Architecture Description Register Classes-------------------------- 278// Several register classes are automatically defined based upon information in 279// this architecture description. 280// 1) reg_class inline_cache_reg ( as defined in frame section ) 281// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 282// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 283// 284 285// G0 is not included in integer class since it has special meaning. 286reg_class g0_reg(R_G0); 287 288// ---------------------------- 289// Integer Register Classes 290// ---------------------------- 291// Exclusions from i_reg: 292// R_G0: hardwired zero 293// R_G2: reserved by HotSpot to the TLS register (invariant within Java) 294// R_G6: reserved by Solaris ABI to tools 295// R_G7: reserved by Solaris ABI to libthread 296// R_O7: Used as a temp in many encodings 297reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 298 299// Class for all integer registers, except the G registers. This is used for 300// encodings which use G registers as temps. The regular inputs to such 301// instructions use a "notemp_" prefix, as a hack to ensure that the allocator 302// will not put an input into a temp register. 303reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 304 305reg_class g1_regI(R_G1); 306reg_class g3_regI(R_G3); 307reg_class g4_regI(R_G4); 308reg_class o0_regI(R_O0); 309reg_class o7_regI(R_O7); 310 311// ---------------------------- 312// Pointer Register Classes 313// ---------------------------- 314// 64-bit build means 64-bit pointers means hi/lo pairs 315reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 316 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 317 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 318 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 319// Lock encodings use G3 and G4 internally 320reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 321 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 322 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 323 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 324// Special class for storeP instructions, which can store SP or RPC to TLS. 325// It is also used for memory addressing, allowing direct TLS addressing. 326reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 327 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 328 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 329 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 330// R_L7 is the lowest-priority callee-save (i.e., NS) register 331// We use it to save R_G2 across calls out of Java. 332reg_class l7_regP(R_L7H,R_L7); 333 334// Other special pointer regs 335reg_class g1_regP(R_G1H,R_G1); 336reg_class g2_regP(R_G2H,R_G2); 337reg_class g3_regP(R_G3H,R_G3); 338reg_class g4_regP(R_G4H,R_G4); 339reg_class g5_regP(R_G5H,R_G5); 340reg_class i0_regP(R_I0H,R_I0); 341reg_class o0_regP(R_O0H,R_O0); 342reg_class o1_regP(R_O1H,R_O1); 343reg_class o2_regP(R_O2H,R_O2); 344reg_class o7_regP(R_O7H,R_O7); 345 346 347// ---------------------------- 348// Long Register Classes 349// ---------------------------- 350// Longs in 1 register. Aligned adjacent hi/lo pairs. 351// Note: O7 is never in this class; it is sometimes used as an encoding temp. 352reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 353 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 354// 64-bit, longs in 1 register: use all 64-bit integer registers 355 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 356 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 357 ); 358 359reg_class g1_regL(R_G1H,R_G1); 360reg_class g3_regL(R_G3H,R_G3); 361reg_class o2_regL(R_O2H,R_O2); 362reg_class o7_regL(R_O7H,R_O7); 363 364// ---------------------------- 365// Special Class for Condition Code Flags Register 366reg_class int_flags(CCR); 367reg_class float_flags(FCC0,FCC1,FCC2,FCC3); 368reg_class float_flag0(FCC0); 369 370 371// ---------------------------- 372// Float Point Register Classes 373// ---------------------------- 374// Skip F30/F31, they are reserved for mem-mem copies 375reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 376 377// Paired floating point registers--they show up in the same order as the floats, 378// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 379reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 380 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 381 /* Use extra V9 double registers; this AD file does not support V8 */ 382 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 383 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 384 ); 385 386// Paired floating point registers--they show up in the same order as the floats, 387// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 388// This class is usable for mis-aligned loads as happen in I2C adapters. 389reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 390 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 391%} 392 393//----------DEFINITION BLOCK--------------------------------------------------- 394// Define name --> value mappings to inform the ADLC of an integer valued name 395// Current support includes integer values in the range [0, 0x7FFFFFFF] 396// Format: 397// int_def <name> ( <int_value>, <expression>); 398// Generated Code in ad_<arch>.hpp 399// #define <name> (<expression>) 400// // value == <int_value> 401// Generated code in ad_<arch>.cpp adlc_verification() 402// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 403// 404definitions %{ 405// The default cost (of an ALU instruction). 406 int_def DEFAULT_COST ( 100, 100); 407 int_def HUGE_COST (1000000, 1000000); 408 409// Memory refs are twice as expensive as run-of-the-mill. 410 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 411 412// Branches are even more expensive. 413 int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 414 int_def CALL_COST ( 300, DEFAULT_COST * 3); 415%} 416 417 418//----------SOURCE BLOCK------------------------------------------------------- 419// This is a block of C++ code which provides values, functions, and 420// definitions necessary in the rest of the architecture description 421source_hpp %{ 422// Header information of the source block. 423// Method declarations/definitions which are used outside 424// the ad-scope can conveniently be defined here. 425// 426// To keep related declarations/definitions/uses close together, 427// we switch between source %{ }% and source_hpp %{ }% freely as needed. 428 429// Must be visible to the DFA in dfa_sparc.cpp 430extern bool can_branch_register( Node *bol, Node *cmp ); 431 432extern bool use_block_zeroing(Node* count); 433 434// Macros to extract hi & lo halves from a long pair. 435// G0 is not part of any long pair, so assert on that. 436// Prevents accidentally using G1 instead of G0. 437#define LONG_HI_REG(x) (x) 438#define LONG_LO_REG(x) (x) 439 440class CallStubImpl { 441 442 //-------------------------------------------------------------- 443 //---< Used for optimization in Compile::Shorten_branches >--- 444 //-------------------------------------------------------------- 445 446 public: 447 // Size of call trampoline stub. 448 static uint size_call_trampoline() { 449 return 0; // no call trampolines on this platform 450 } 451 452 // number of relocations needed by a call trampoline stub 453 static uint reloc_call_trampoline() { 454 return 0; // no call trampolines on this platform 455 } 456}; 457 458class HandlerImpl { 459 460 public: 461 462 static int emit_exception_handler(CodeBuffer &cbuf); 463 static int emit_deopt_handler(CodeBuffer& cbuf); 464 465 static uint size_exception_handler() { 466 return ( NativeJump::instruction_size ); // sethi;jmp;nop 467 } 468 469 static uint size_deopt_handler() { 470 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 471 } 472}; 473 474%} 475 476source %{ 477#define __ _masm. 478 479// tertiary op of a LoadP or StoreP encoding 480#define REGP_OP true 481 482static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 483static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 484static Register reg_to_register_object(int register_encoding); 485 486// Used by the DFA in dfa_sparc.cpp. 487// Check for being able to use a V9 branch-on-register. Requires a 488// compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 489// extended. Doesn't work following an integer ADD, for example, because of 490// overflow (-1 incremented yields 0 plus a carry in the high-order word). On 491// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 492// replace them with zero, which could become sign-extension in a different OS 493// release. There's no obvious reason why an interrupt will ever fill these 494// bits with non-zero junk (the registers are reloaded with standard LD 495// instructions which either zero-fill or sign-fill). 496bool can_branch_register( Node *bol, Node *cmp ) { 497 if( !BranchOnRegister ) return false; 498 if( cmp->Opcode() == Op_CmpP ) 499 return true; // No problems with pointer compares 500 if( cmp->Opcode() == Op_CmpL ) 501 return true; // No problems with long compares 502 503 if( !SparcV9RegsHiBitsZero ) return false; 504 if( bol->as_Bool()->_test._test != BoolTest::ne && 505 bol->as_Bool()->_test._test != BoolTest::eq ) 506 return false; 507 508 // Check for comparing against a 'safe' value. Any operation which 509 // clears out the high word is safe. Thus, loads and certain shifts 510 // are safe, as are non-negative constants. Any operation which 511 // preserves zero bits in the high word is safe as long as each of its 512 // inputs are safe. Thus, phis and bitwise booleans are safe if their 513 // inputs are safe. At present, the only important case to recognize 514 // seems to be loads. Constants should fold away, and shifts & 515 // logicals can use the 'cc' forms. 516 Node *x = cmp->in(1); 517 if( x->is_Load() ) return true; 518 if( x->is_Phi() ) { 519 for( uint i = 1; i < x->req(); i++ ) 520 if( !x->in(i)->is_Load() ) 521 return false; 522 return true; 523 } 524 return false; 525} 526 527bool use_block_zeroing(Node* count) { 528 // Use BIS for zeroing if count is not constant 529 // or it is >= BlockZeroingLowLimit. 530 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit); 531} 532 533// **************************************************************************** 534 535// REQUIRED FUNCTIONALITY 536 537// !!!!! Special hack to get all type of calls to specify the byte offset 538// from the start of the call to the point where the return address 539// will point. 540// The "return address" is the address of the call instruction, plus 8. 541 542int MachCallStaticJavaNode::ret_addr_offset() { 543 int offset = NativeCall::instruction_size; // call; delay slot 544 if (_method_handle_invoke) 545 offset += 4; // restore SP 546 return offset; 547} 548 549int MachCallDynamicJavaNode::ret_addr_offset() { 550 int vtable_index = this->_vtable_index; 551 if (vtable_index < 0) { 552 // must be invalid_vtable_index, not nonvirtual_vtable_index 553 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 554 return (NativeMovConstReg::instruction_size + 555 NativeCall::instruction_size); // sethi; setlo; call; delay slot 556 } else { 557 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 558 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 559 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 560 int klass_load_size; 561 if (UseCompressedClassPointers) { 562 assert(Universe::heap() != NULL, "java heap should be initialized"); 563 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 564 } else { 565 klass_load_size = 1*BytesPerInstWord; 566 } 567 if (Assembler::is_simm13(v_off)) { 568 return klass_load_size + 569 (2*BytesPerInstWord + // ld_ptr, ld_ptr 570 NativeCall::instruction_size); // call; delay slot 571 } else { 572 return klass_load_size + 573 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 574 NativeCall::instruction_size); // call; delay slot 575 } 576 } 577} 578 579int MachCallRuntimeNode::ret_addr_offset() { 580 if (MacroAssembler::is_far_target(entry_point())) { 581 return NativeFarCall::instruction_size; 582 } else { 583 return NativeCall::instruction_size; 584 } 585} 586 587// Indicate if the safepoint node needs the polling page as an input. 588// Since Sparc does not have absolute addressing, it does. 589bool SafePointNode::needs_polling_address_input() { 590 return true; 591} 592 593// emit an interrupt that is caught by the debugger (for debugging compiler) 594void emit_break(CodeBuffer &cbuf) { 595 MacroAssembler _masm(&cbuf); 596 __ breakpoint_trap(); 597} 598 599#ifndef PRODUCT 600void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 601 st->print("TA"); 602} 603#endif 604 605void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 606 emit_break(cbuf); 607} 608 609uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 610 return MachNode::size(ra_); 611} 612 613// Traceable jump 614void emit_jmpl(CodeBuffer &cbuf, int jump_target) { 615 MacroAssembler _masm(&cbuf); 616 Register rdest = reg_to_register_object(jump_target); 617 __ JMP(rdest, 0); 618 __ delayed()->nop(); 619} 620 621// Traceable jump and set exception pc 622void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 623 MacroAssembler _masm(&cbuf); 624 Register rdest = reg_to_register_object(jump_target); 625 __ JMP(rdest, 0); 626 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 627} 628 629void emit_nop(CodeBuffer &cbuf) { 630 MacroAssembler _masm(&cbuf); 631 __ nop(); 632} 633 634void emit_illtrap(CodeBuffer &cbuf) { 635 MacroAssembler _masm(&cbuf); 636 __ illtrap(0); 637} 638 639 640intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 641 assert(n->rule() != loadUB_rule, ""); 642 643 intptr_t offset = 0; 644 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 645 const Node* addr = n->get_base_and_disp(offset, adr_type); 646 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 647 assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 648 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 649 atype = atype->add_offset(offset); 650 assert(disp32 == offset, "wrong disp32"); 651 return atype->_offset; 652} 653 654 655intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 656 assert(n->rule() != loadUB_rule, ""); 657 658 intptr_t offset = 0; 659 Node* addr = n->in(2); 660 assert(addr->bottom_type()->isa_oopptr() == atype, ""); 661 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 662 Node* a = addr->in(2/*AddPNode::Address*/); 663 Node* o = addr->in(3/*AddPNode::Offset*/); 664 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 665 atype = a->bottom_type()->is_ptr()->add_offset(offset); 666 assert(atype->isa_oop_ptr(), "still an oop"); 667 } 668 offset = atype->is_ptr()->_offset; 669 if (offset != Type::OffsetBot) offset += disp32; 670 return offset; 671} 672 673static inline jlong replicate_immI(int con, int count, int width) { 674 // Load a constant replicated "count" times with width "width" 675 assert(count*width == 8 && width <= 4, "sanity"); 676 int bit_width = width * 8; 677 jlong val = con; 678 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits 679 for (int i = 0; i < count - 1; i++) { 680 val |= (val << bit_width); 681 } 682 return val; 683} 684 685static inline jlong replicate_immF(float con) { 686 // Replicate float con 2 times and pack into vector. 687 int val = *((int*)&con); 688 jlong lval = val; 689 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 690 return lval; 691} 692 693// Standard Sparc opcode form2 field breakdown 694static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 695 f0 &= (1<<19)-1; // Mask displacement to 19 bits 696 int op = (f30 << 30) | 697 (f29 << 29) | 698 (f25 << 25) | 699 (f22 << 22) | 700 (f20 << 20) | 701 (f19 << 19) | 702 (f0 << 0); 703 cbuf.insts()->emit_int32(op); 704} 705 706// Standard Sparc opcode form2 field breakdown 707static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 708 f0 >>= 10; // Drop 10 bits 709 f0 &= (1<<22)-1; // Mask displacement to 22 bits 710 int op = (f30 << 30) | 711 (f25 << 25) | 712 (f22 << 22) | 713 (f0 << 0); 714 cbuf.insts()->emit_int32(op); 715} 716 717// Standard Sparc opcode form3 field breakdown 718static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 719 int op = (f30 << 30) | 720 (f25 << 25) | 721 (f19 << 19) | 722 (f14 << 14) | 723 (f5 << 5) | 724 (f0 << 0); 725 cbuf.insts()->emit_int32(op); 726} 727 728// Standard Sparc opcode form3 field breakdown 729static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 730 simm13 &= (1<<13)-1; // Mask to 13 bits 731 int op = (f30 << 30) | 732 (f25 << 25) | 733 (f19 << 19) | 734 (f14 << 14) | 735 (1 << 13) | // bit to indicate immediate-mode 736 (simm13<<0); 737 cbuf.insts()->emit_int32(op); 738} 739 740static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 741 simm10 &= (1<<10)-1; // Mask to 10 bits 742 emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 743} 744 745#ifdef ASSERT 746// Helper function for VerifyOops in emit_form3_mem_reg 747void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 748 warning("VerifyOops encountered unexpected instruction:"); 749 n->dump(2); 750 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 751} 752#endif 753 754 755void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary, 756 int src1_enc, int disp32, int src2_enc, int dst_enc) { 757 758#ifdef ASSERT 759 // The following code implements the +VerifyOops feature. 760 // It verifies oop values which are loaded into or stored out of 761 // the current method activation. +VerifyOops complements techniques 762 // like ScavengeALot, because it eagerly inspects oops in transit, 763 // as they enter or leave the stack, as opposed to ScavengeALot, 764 // which inspects oops "at rest", in the stack or heap, at safepoints. 765 // For this reason, +VerifyOops can sometimes detect bugs very close 766 // to their point of creation. It can also serve as a cross-check 767 // on the validity of oop maps, when used toegether with ScavengeALot. 768 769 // It would be good to verify oops at other points, especially 770 // when an oop is used as a base pointer for a load or store. 771 // This is presently difficult, because it is hard to know when 772 // a base address is biased or not. (If we had such information, 773 // it would be easy and useful to make a two-argument version of 774 // verify_oop which unbiases the base, and performs verification.) 775 776 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 777 bool is_verified_oop_base = false; 778 bool is_verified_oop_load = false; 779 bool is_verified_oop_store = false; 780 int tmp_enc = -1; 781 if (VerifyOops && src1_enc != R_SP_enc) { 782 // classify the op, mainly for an assert check 783 int st_op = 0, ld_op = 0; 784 switch (primary) { 785 case Assembler::stb_op3: st_op = Op_StoreB; break; 786 case Assembler::sth_op3: st_op = Op_StoreC; break; 787 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 788 case Assembler::stw_op3: st_op = Op_StoreI; break; 789 case Assembler::std_op3: st_op = Op_StoreL; break; 790 case Assembler::stf_op3: st_op = Op_StoreF; break; 791 case Assembler::stdf_op3: st_op = Op_StoreD; break; 792 793 case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 794 case Assembler::ldub_op3: ld_op = Op_LoadUB; break; 795 case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 796 case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 797 case Assembler::ldx_op3: // may become LoadP or stay LoadI 798 case Assembler::ldsw_op3: // may become LoadP or stay LoadI 799 case Assembler::lduw_op3: ld_op = Op_LoadI; break; 800 case Assembler::ldd_op3: ld_op = Op_LoadL; break; 801 case Assembler::ldf_op3: ld_op = Op_LoadF; break; 802 case Assembler::lddf_op3: ld_op = Op_LoadD; break; 803 case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 804 805 default: ShouldNotReachHere(); 806 } 807 if (tertiary == REGP_OP) { 808 if (st_op == Op_StoreI) st_op = Op_StoreP; 809 else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 810 else ShouldNotReachHere(); 811 if (st_op) { 812 // a store 813 // inputs are (0:control, 1:memory, 2:address, 3:value) 814 Node* n2 = n->in(3); 815 if (n2 != NULL) { 816 const Type* t = n2->bottom_type(); 817 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 818 } 819 } else { 820 // a load 821 const Type* t = n->bottom_type(); 822 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 823 } 824 } 825 826 if (ld_op) { 827 // a Load 828 // inputs are (0:control, 1:memory, 2:address) 829 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 830 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 831 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 832 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 833 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 834 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 835 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 836 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 837 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 838 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 839 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 840 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) && 841 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) && 842 !(n->rule() == loadUB_rule)) { 843 verify_oops_warning(n, n->ideal_Opcode(), ld_op); 844 } 845 } else if (st_op) { 846 // a Store 847 // inputs are (0:control, 1:memory, 2:address, 3:value) 848 if (!(n->ideal_Opcode()==st_op) && // Following are special cases 849 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 850 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 851 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 852 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 853 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) && 854 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 855 verify_oops_warning(n, n->ideal_Opcode(), st_op); 856 } 857 } 858 859 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 860 Node* addr = n->in(2); 861 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 862 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 863 if (atype != NULL) { 864 intptr_t offset = get_offset_from_base(n, atype, disp32); 865 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 866 if (offset != offset_2) { 867 get_offset_from_base(n, atype, disp32); 868 get_offset_from_base_2(n, atype, disp32); 869 } 870 assert(offset == offset_2, "different offsets"); 871 if (offset == disp32) { 872 // we now know that src1 is a true oop pointer 873 is_verified_oop_base = true; 874 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 875 if( primary == Assembler::ldd_op3 ) { 876 is_verified_oop_base = false; // Cannot 'ldd' into O7 877 } else { 878 tmp_enc = dst_enc; 879 dst_enc = R_O7_enc; // Load into O7; preserve source oop 880 assert(src1_enc != dst_enc, ""); 881 } 882 } 883 } 884 if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 885 || offset == oopDesc::mark_offset_in_bytes())) { 886 // loading the mark should not be allowed either, but 887 // we don't check this since it conflicts with InlineObjectHash 888 // usage of LoadINode to get the mark. We could keep the 889 // check if we create a new LoadMarkNode 890 // but do not verify the object before its header is initialized 891 ShouldNotReachHere(); 892 } 893 } 894 } 895 } 896 } 897#endif 898 899 uint instr = (Assembler::ldst_op << 30) 900 | (dst_enc << 25) 901 | (primary << 19) 902 | (src1_enc << 14); 903 904 uint index = src2_enc; 905 int disp = disp32; 906 907 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) { 908 disp += STACK_BIAS; 909 // Check that stack offset fits, load into O7 if not 910 if (!Assembler::is_simm13(disp)) { 911 MacroAssembler _masm(&cbuf); 912 __ set(disp, O7); 913 if (index != R_G0_enc) { 914 __ add(O7, reg_to_register_object(index), O7); 915 } 916 index = R_O7_enc; 917 disp = 0; 918 } 919 } 920 921 if( disp == 0 ) { 922 // use reg-reg form 923 // bit 13 is already zero 924 instr |= index; 925 } else { 926 // use reg-imm form 927 instr |= 0x00002000; // set bit 13 to one 928 instr |= disp & 0x1FFF; 929 } 930 931 cbuf.insts()->emit_int32(instr); 932 933#ifdef ASSERT 934 if (VerifyOops) { 935 MacroAssembler _masm(&cbuf); 936 if (is_verified_oop_base) { 937 __ verify_oop(reg_to_register_object(src1_enc)); 938 } 939 if (is_verified_oop_store) { 940 __ verify_oop(reg_to_register_object(dst_enc)); 941 } 942 if (tmp_enc != -1) { 943 __ mov(O7, reg_to_register_object(tmp_enc)); 944 } 945 if (is_verified_oop_load) { 946 __ verify_oop(reg_to_register_object(dst_enc)); 947 } 948 } 949#endif 950} 951 952void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) { 953 // The method which records debug information at every safepoint 954 // expects the call to be the first instruction in the snippet as 955 // it creates a PcDesc structure which tracks the offset of a call 956 // from the start of the codeBlob. This offset is computed as 957 // code_end() - code_begin() of the code which has been emitted 958 // so far. 959 // In this particular case we have skirted around the problem by 960 // putting the "mov" instruction in the delay slot but the problem 961 // may bite us again at some other point and a cleaner/generic 962 // solution using relocations would be needed. 963 MacroAssembler _masm(&cbuf); 964 __ set_inst_mark(); 965 966 // We flush the current window just so that there is a valid stack copy 967 // the fact that the current window becomes active again instantly is 968 // not a problem there is nothing live in it. 969 970#ifdef ASSERT 971 int startpos = __ offset(); 972#endif /* ASSERT */ 973 974 __ call((address)entry_point, rspec); 975 976 if (preserve_g2) __ delayed()->mov(G2, L7); 977 else __ delayed()->nop(); 978 979 if (preserve_g2) __ mov(L7, G2); 980 981#ifdef ASSERT 982 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 983 // Trash argument dump slots. 984 __ set(0xb0b8ac0db0b8ac0d, G1); 985 __ mov(G1, G5); 986 __ stx(G1, SP, STACK_BIAS + 0x80); 987 __ stx(G1, SP, STACK_BIAS + 0x88); 988 __ stx(G1, SP, STACK_BIAS + 0x90); 989 __ stx(G1, SP, STACK_BIAS + 0x98); 990 __ stx(G1, SP, STACK_BIAS + 0xA0); 991 __ stx(G1, SP, STACK_BIAS + 0xA8); 992 } 993#endif /*ASSERT*/ 994} 995 996//============================================================================= 997// REQUIRED FUNCTIONALITY for encoding 998void emit_lo(CodeBuffer &cbuf, int val) { } 999void emit_hi(CodeBuffer &cbuf, int val) { } 1000 1001 1002//============================================================================= 1003const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask(); 1004 1005int Compile::ConstantTable::calculate_table_base_offset() const { 1006 if (UseRDPCForConstantTableBase) { 1007 // The table base offset might be less but then it fits into 1008 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit). 1009 return Assembler::min_simm13(); 1010 } else { 1011 int offset = -(size() / 2); 1012 if (!Assembler::is_simm13(offset)) { 1013 offset = Assembler::min_simm13(); 1014 } 1015 return offset; 1016 } 1017} 1018 1019bool MachConstantBaseNode::requires_postalloc_expand() const { return false; } 1020void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1021 ShouldNotReachHere(); 1022} 1023 1024void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1025 Compile* C = ra_->C; 1026 Compile::ConstantTable& constant_table = C->constant_table(); 1027 MacroAssembler _masm(&cbuf); 1028 1029 Register r = as_Register(ra_->get_encode(this)); 1030 CodeSection* consts_section = __ code()->consts(); 1031 int consts_size = consts_section->align_at_start(consts_section->size()); 1032 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size); 1033 1034 if (UseRDPCForConstantTableBase) { 1035 // For the following RDPC logic to work correctly the consts 1036 // section must be allocated right before the insts section. This 1037 // assert checks for that. The layout and the SECT_* constants 1038 // are defined in src/share/vm/asm/codeBuffer.hpp. 1039 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be"); 1040 int insts_offset = __ offset(); 1041 1042 // Layout: 1043 // 1044 // |----------- consts section ------------|----------- insts section -----------... 1045 // |------ constant table -----|- padding -|------------------x---- 1046 // \ current PC (RDPC instruction) 1047 // |<------------- consts_size ----------->|<- insts_offset ->| 1048 // \ table base 1049 // The table base offset is later added to the load displacement 1050 // so it has to be negative. 1051 int table_base_offset = -(consts_size + insts_offset); 1052 int disp; 1053 1054 // If the displacement from the current PC to the constant table 1055 // base fits into simm13 we set the constant table base to the 1056 // current PC. 1057 if (Assembler::is_simm13(table_base_offset)) { 1058 constant_table.set_table_base_offset(table_base_offset); 1059 disp = 0; 1060 } else { 1061 // Otherwise we set the constant table base offset to the 1062 // maximum negative displacement of load instructions to keep 1063 // the disp as small as possible: 1064 // 1065 // |<------------- consts_size ----------->|<- insts_offset ->| 1066 // |<--------- min_simm13 --------->|<-------- disp --------->| 1067 // \ table base 1068 table_base_offset = Assembler::min_simm13(); 1069 constant_table.set_table_base_offset(table_base_offset); 1070 disp = (consts_size + insts_offset) + table_base_offset; 1071 } 1072 1073 __ rdpc(r); 1074 1075 if (disp == 0) { 1076 // Emitting an additional 'nop' instruction in order not to cause a code 1077 // size adjustment in the code following the table setup (if the instruction 1078 // immediately following after this section is a CTI). 1079 __ nop(); 1080 } 1081 else { 1082 assert(r != O7, "need temporary"); 1083 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r); 1084 } 1085 } 1086 else { 1087 // Materialize the constant table base. 1088 address baseaddr = consts_section->start() + -(constant_table.table_base_offset()); 1089 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr); 1090 AddressLiteral base(baseaddr, rspec); 1091 __ set(base, r); 1092 } 1093} 1094 1095uint MachConstantBaseNode::size(PhaseRegAlloc*) const { 1096 if (UseRDPCForConstantTableBase) { 1097 // This is really the worst case but generally it's only 1 instruction. 1098 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord; 1099 } else { 1100 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord; 1101 } 1102} 1103 1104#ifndef PRODUCT 1105void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1106 char reg[128]; 1107 ra_->dump_register(this, reg); 1108 if (UseRDPCForConstantTableBase) { 1109 st->print("RDPC %s\t! constant table base", reg); 1110 } else { 1111 st->print("SET &constanttable,%s\t! constant table base", reg); 1112 } 1113} 1114#endif 1115 1116 1117//============================================================================= 1118 1119#ifndef PRODUCT 1120void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1121 Compile* C = ra_->C; 1122 1123 for (int i = 0; i < OptoPrologueNops; i++) { 1124 st->print_cr("NOP"); st->print("\t"); 1125 } 1126 1127 if( VerifyThread ) { 1128 st->print_cr("Verify_Thread"); st->print("\t"); 1129 } 1130 1131 size_t framesize = C->frame_size_in_bytes(); 1132 int bangsize = C->bang_size_in_bytes(); 1133 1134 // Calls to C2R adapters often do not accept exceptional returns. 1135 // We require that their callers must bang for them. But be careful, because 1136 // some VM calls (such as call site linkage) can use several kilobytes of 1137 // stack. But the stack safety zone should account for that. 1138 // See bugs 4446381, 4468289, 4497237. 1139 if (C->need_stack_bang(bangsize)) { 1140 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t"); 1141 } 1142 1143 if (Assembler::is_simm13(-framesize)) { 1144 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize); 1145 } else { 1146 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1147 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t"); 1148 st->print ("SAVE R_SP,R_G3,R_SP"); 1149 } 1150 1151} 1152#endif 1153 1154void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1155 Compile* C = ra_->C; 1156 MacroAssembler _masm(&cbuf); 1157 1158 for (int i = 0; i < OptoPrologueNops; i++) { 1159 __ nop(); 1160 } 1161 1162 __ verify_thread(); 1163 1164 size_t framesize = C->frame_size_in_bytes(); 1165 assert(framesize >= 16*wordSize, "must have room for reg. save area"); 1166 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 1167 int bangsize = C->bang_size_in_bytes(); 1168 1169 // Calls to C2R adapters often do not accept exceptional returns. 1170 // We require that their callers must bang for them. But be careful, because 1171 // some VM calls (such as call site linkage) can use several kilobytes of 1172 // stack. But the stack safety zone should account for that. 1173 // See bugs 4446381, 4468289, 4497237. 1174 if (C->need_stack_bang(bangsize)) { 1175 __ generate_stack_overflow_check(bangsize); 1176 } 1177 1178 if (Assembler::is_simm13(-framesize)) { 1179 __ save(SP, -framesize, SP); 1180 } else { 1181 __ sethi(-framesize & ~0x3ff, G3); 1182 __ add(G3, -framesize & 0x3ff, G3); 1183 __ save(SP, G3, SP); 1184 } 1185 C->set_frame_complete( __ offset() ); 1186 1187 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) { 1188 // NOTE: We set the table base offset here because users might be 1189 // emitted before MachConstantBaseNode. 1190 Compile::ConstantTable& constant_table = C->constant_table(); 1191 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset()); 1192 } 1193} 1194 1195uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1196 return MachNode::size(ra_); 1197} 1198 1199int MachPrologNode::reloc() const { 1200 return 10; // a large enough number 1201} 1202 1203//============================================================================= 1204#ifndef PRODUCT 1205void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1206 Compile* C = ra_->C; 1207 1208 if(do_polling() && ra_->C->is_method_compilation()) { 1209 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 1210 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 1211 } 1212 1213 if(do_polling()) { 1214 if (UseCBCond && !ra_->C->is_method_compilation()) { 1215 st->print("NOP\n\t"); 1216 } 1217 st->print("RET\n\t"); 1218 } 1219 1220 st->print("RESTORE"); 1221} 1222#endif 1223 1224void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1225 MacroAssembler _masm(&cbuf); 1226 Compile* C = ra_->C; 1227 1228 __ verify_thread(); 1229 1230 if (StackReservedPages > 0 && C->has_reserved_stack_access()) { 1231 __ reserved_stack_check(); 1232 } 1233 1234 // If this does safepoint polling, then do it here 1235 if(do_polling() && ra_->C->is_method_compilation()) { 1236 AddressLiteral polling_page(os::get_polling_page()); 1237 __ sethi(polling_page, L0); 1238 __ relocate(relocInfo::poll_return_type); 1239 __ ld_ptr(L0, 0, G0); 1240 } 1241 1242 // If this is a return, then stuff the restore in the delay slot 1243 if(do_polling()) { 1244 if (UseCBCond && !ra_->C->is_method_compilation()) { 1245 // Insert extra padding for the case when the epilogue is preceded by 1246 // a cbcond jump, which can't be followed by a CTI instruction 1247 __ nop(); 1248 } 1249 __ ret(); 1250 __ delayed()->restore(); 1251 } else { 1252 __ restore(); 1253 } 1254} 1255 1256uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1257 return MachNode::size(ra_); 1258} 1259 1260int MachEpilogNode::reloc() const { 1261 return 16; // a large enough number 1262} 1263 1264const Pipeline * MachEpilogNode::pipeline() const { 1265 return MachNode::pipeline_class(); 1266} 1267 1268int MachEpilogNode::safepoint_offset() const { 1269 assert( do_polling(), "no return for this epilog node"); 1270 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord; 1271} 1272 1273//============================================================================= 1274 1275// Figure out which register class each belongs in: rc_int, rc_float, rc_stack 1276enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1277static enum RC rc_class( OptoReg::Name reg ) { 1278 if (!OptoReg::is_valid(reg)) return rc_bad; 1279 if (OptoReg::is_stack(reg)) return rc_stack; 1280 VMReg r = OptoReg::as_VMReg(reg); 1281 if (r->is_Register()) return rc_int; 1282 assert(r->is_FloatRegister(), "must be"); 1283 return rc_float; 1284} 1285 1286#ifndef PRODUCT 1287ATTRIBUTE_PRINTF(2, 3) 1288static void print_helper(outputStream* st, const char* format, ...) { 1289 if (st->position() > 0) { 1290 st->cr(); 1291 st->sp(); 1292 } 1293 va_list ap; 1294 va_start(ap, format); 1295 st->vprint(format, ap); 1296 va_end(ap); 1297} 1298#endif // !PRODUCT 1299 1300static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) { 1301 if (cbuf) { 1302 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 1303 } 1304#ifndef PRODUCT 1305 else { 1306 if (is_load) { 1307 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg)); 1308 } else { 1309 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset); 1310 } 1311 } 1312#endif 1313} 1314 1315static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) { 1316 if (cbuf) { 1317 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]); 1318 } 1319#ifndef PRODUCT 1320 else { 1321 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst)); 1322 } 1323#endif 1324} 1325 1326static void mach_spill_copy_implementation_helper(const MachNode* mach, 1327 CodeBuffer *cbuf, 1328 PhaseRegAlloc *ra_, 1329 outputStream* st) { 1330 // Get registers to move 1331 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1)); 1332 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1)); 1333 OptoReg::Name dst_second = ra_->get_reg_second(mach); 1334 OptoReg::Name dst_first = ra_->get_reg_first(mach); 1335 1336 enum RC src_second_rc = rc_class(src_second); 1337 enum RC src_first_rc = rc_class(src_first); 1338 enum RC dst_second_rc = rc_class(dst_second); 1339 enum RC dst_first_rc = rc_class(dst_first); 1340 1341 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register"); 1342 1343 if (src_first == dst_first && src_second == dst_second) { 1344 return; // Self copy, no move 1345 } 1346 1347 // -------------------------------------- 1348 // Check for mem-mem move. Load into unused float registers and fall into 1349 // the float-store case. 1350 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) { 1351 int offset = ra_->reg2offset(src_first); 1352 // Further check for aligned-adjacent pair, so we can use a double load 1353 if ((src_first&1) == 0 && src_first+1 == src_second) { 1354 src_second = OptoReg::Name(R_F31_num); 1355 src_second_rc = rc_float; 1356 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st); 1357 } else { 1358 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st); 1359 } 1360 src_first = OptoReg::Name(R_F30_num); 1361 src_first_rc = rc_float; 1362 } 1363 1364 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 1365 int offset = ra_->reg2offset(src_second); 1366 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st); 1367 src_second = OptoReg::Name(R_F31_num); 1368 src_second_rc = rc_float; 1369 } 1370 1371 // -------------------------------------- 1372 // Check for float->int copy; requires a trip through memory 1373 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) { 1374 int offset = frame::register_save_words*wordSize; 1375 if (cbuf) { 1376 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16); 1377 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1378 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1379 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16); 1380 } 1381#ifndef PRODUCT 1382 else { 1383 print_helper(st, "SUB R_SP,16,R_SP"); 1384 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1385 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1386 print_helper(st, "ADD R_SP,16,R_SP"); 1387 } 1388#endif 1389 } 1390 1391 // Check for float->int copy on T4 1392 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) { 1393 // Further check for aligned-adjacent pair, so we can use a double move 1394 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1395 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st); 1396 return; 1397 } 1398 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st); 1399 } 1400 // Check for int->float copy on T4 1401 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) { 1402 // Further check for aligned-adjacent pair, so we can use a double move 1403 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1404 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st); 1405 return; 1406 } 1407 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st); 1408 } 1409 1410 // -------------------------------------- 1411 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 1412 // In such cases, I have to do the big-endian swap. For aligned targets, the 1413 // hardware does the flop for me. Doubles are always aligned, so no problem 1414 // there. Misaligned sources only come from native-long-returns (handled 1415 // special below). 1416 1417 // -------------------------------------- 1418 // Check for integer reg-reg copy 1419 if (src_first_rc == rc_int && dst_first_rc == rc_int) { 1420 // Else normal reg-reg copy 1421 assert(src_second != dst_first, "smashed second before evacuating it"); 1422 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st); 1423 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers"); 1424 // This moves an aligned adjacent pair. 1425 // See if we are done. 1426 if (src_first + 1 == src_second && dst_first + 1 == dst_second) { 1427 return; 1428 } 1429 } 1430 1431 // Check for integer store 1432 if (src_first_rc == rc_int && dst_first_rc == rc_stack) { 1433 int offset = ra_->reg2offset(dst_first); 1434 // Further check for aligned-adjacent pair, so we can use a double store 1435 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1436 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st); 1437 return; 1438 } 1439 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st); 1440 } 1441 1442 // Check for integer load 1443 if (dst_first_rc == rc_int && src_first_rc == rc_stack) { 1444 int offset = ra_->reg2offset(src_first); 1445 // Further check for aligned-adjacent pair, so we can use a double load 1446 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1447 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st); 1448 return; 1449 } 1450 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st); 1451 } 1452 1453 // Check for float reg-reg copy 1454 if (src_first_rc == rc_float && dst_first_rc == rc_float) { 1455 // Further check for aligned-adjacent pair, so we can use a double move 1456 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1457 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st); 1458 return; 1459 } 1460 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st); 1461 } 1462 1463 // Check for float store 1464 if (src_first_rc == rc_float && dst_first_rc == rc_stack) { 1465 int offset = ra_->reg2offset(dst_first); 1466 // Further check for aligned-adjacent pair, so we can use a double store 1467 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1468 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st); 1469 return; 1470 } 1471 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st); 1472 } 1473 1474 // Check for float load 1475 if (dst_first_rc == rc_float && src_first_rc == rc_stack) { 1476 int offset = ra_->reg2offset(src_first); 1477 // Further check for aligned-adjacent pair, so we can use a double load 1478 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) { 1479 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st); 1480 return; 1481 } 1482 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st); 1483 } 1484 1485 // -------------------------------------------------------------------- 1486 // Check for hi bits still needing moving. Only happens for misaligned 1487 // arguments to native calls. 1488 if (src_second == dst_second) { 1489 return; // Self copy; no move 1490 } 1491 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad"); 1492 1493 Unimplemented(); 1494} 1495 1496uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, 1497 PhaseRegAlloc *ra_, 1498 bool do_size, 1499 outputStream* st) const { 1500 assert(!do_size, "not supported"); 1501 mach_spill_copy_implementation_helper(this, cbuf, ra_, st); 1502 return 0; 1503} 1504 1505#ifndef PRODUCT 1506void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1507 implementation( NULL, ra_, false, st ); 1508} 1509#endif 1510 1511void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1512 implementation( &cbuf, ra_, false, NULL ); 1513} 1514 1515uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1516 return MachNode::size(ra_); 1517} 1518 1519//============================================================================= 1520#ifndef PRODUCT 1521void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const { 1522 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1523} 1524#endif 1525 1526void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1527 MacroAssembler _masm(&cbuf); 1528 for (int i = 0; i < _count; i += 1) { 1529 __ nop(); 1530 } 1531} 1532 1533uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1534 return 4 * _count; 1535} 1536 1537 1538//============================================================================= 1539#ifndef PRODUCT 1540void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1541 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1542 int reg = ra_->get_reg_first(this); 1543 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1544} 1545#endif 1546 1547void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1548 MacroAssembler _masm(&cbuf); 1549 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1550 int reg = ra_->get_encode(this); 1551 1552 if (Assembler::is_simm13(offset)) { 1553 __ add(SP, offset, reg_to_register_object(reg)); 1554 } else { 1555 __ set(offset, O7); 1556 __ add(SP, O7, reg_to_register_object(reg)); 1557 } 1558} 1559 1560uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1561 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1562 assert(ra_ == ra_->C->regalloc(), "sanity"); 1563 return ra_->C->scratch_emit_size(this); 1564} 1565 1566//============================================================================= 1567#ifndef PRODUCT 1568void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1569 st->print_cr("\nUEP:"); 1570 if (UseCompressedClassPointers) { 1571 assert(Universe::heap() != NULL, "java heap should be initialized"); 1572 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1573 if (Universe::narrow_klass_base() != 0) { 1574 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base"); 1575 if (Universe::narrow_klass_shift() != 0) { 1576 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1577 } 1578 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1579 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base"); 1580 } else { 1581 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5"); 1582 } 1583 } else { 1584 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1585 } 1586 st->print_cr("\tCMP R_G5,R_G3" ); 1587 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1588} 1589#endif 1590 1591void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1592 MacroAssembler _masm(&cbuf); 1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1594 Register temp_reg = G3; 1595 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1596 1597 // Load klass from receiver 1598 __ load_klass(O0, temp_reg); 1599 // Compare against expected klass 1600 __ cmp(temp_reg, G5_ic_reg); 1601 // Branch to miss code, checks xcc or icc depending 1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1603} 1604 1605uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1606 return MachNode::size(ra_); 1607} 1608 1609 1610//============================================================================= 1611 1612 1613// Emit exception handler code. 1614int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) { 1615 Register temp_reg = G3; 1616 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1617 MacroAssembler _masm(&cbuf); 1618 1619 address base = __ start_a_stub(size_exception_handler()); 1620 if (base == NULL) { 1621 ciEnv::current()->record_failure("CodeCache is full"); 1622 return 0; // CodeBuffer::expand failed 1623 } 1624 1625 int offset = __ offset(); 1626 1627 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1628 __ delayed()->nop(); 1629 1630 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1631 1632 __ end_a_stub(); 1633 1634 return offset; 1635} 1636 1637int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1638 // Can't use any of the current frame's registers as we may have deopted 1639 // at a poll and everything (including G3) can be live. 1640 Register temp_reg = L0; 1641 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1642 MacroAssembler _masm(&cbuf); 1643 1644 address base = __ start_a_stub(size_deopt_handler()); 1645 if (base == NULL) { 1646 ciEnv::current()->record_failure("CodeCache is full"); 1647 return 0; // CodeBuffer::expand failed 1648 } 1649 1650 int offset = __ offset(); 1651 __ save_frame(0); 1652 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1653 __ delayed()->restore(); 1654 1655 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1656 1657 __ end_a_stub(); 1658 return offset; 1659 1660} 1661 1662// Given a register encoding, produce a Integer Register object 1663static Register reg_to_register_object(int register_encoding) { 1664 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1665 return as_Register(register_encoding); 1666} 1667 1668// Given a register encoding, produce a single-precision Float Register object 1669static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1670 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1671 return as_SingleFloatRegister(register_encoding); 1672} 1673 1674// Given a register encoding, produce a double-precision Float Register object 1675static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1676 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1677 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1678 return as_DoubleFloatRegister(register_encoding); 1679} 1680 1681const bool Matcher::match_rule_supported(int opcode) { 1682 if (!has_match_rule(opcode)) 1683 return false; 1684 1685 switch (opcode) { 1686 case Op_CountLeadingZerosI: 1687 case Op_CountLeadingZerosL: 1688 case Op_CountTrailingZerosI: 1689 case Op_CountTrailingZerosL: 1690 case Op_PopCountI: 1691 case Op_PopCountL: 1692 if (!UsePopCountInstruction) 1693 return false; 1694 case Op_CompareAndSwapL: 1695 case Op_CompareAndSwapP: 1696 if (!VM_Version::supports_cx8()) 1697 return false; 1698 break; 1699 } 1700 1701 return true; // Per default match rules are supported. 1702} 1703 1704const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 1705 1706 // TODO 1707 // identify extra cases that we might want to provide match rules for 1708 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 1709 bool ret_value = match_rule_supported(opcode); 1710 // Add rules here. 1711 1712 return ret_value; // Per default match rules are supported. 1713} 1714 1715const bool Matcher::has_predicated_vectors(void) { 1716 return false; 1717} 1718 1719const int Matcher::float_pressure(int default_pressure_threshold) { 1720 return default_pressure_threshold; 1721} 1722 1723int Matcher::regnum_to_fpu_offset(int regnum) { 1724 return regnum - 32; // The FP registers are in the second chunk 1725} 1726 1727#ifdef ASSERT 1728address last_rethrow = NULL; // debugging aid for Rethrow encoding 1729#endif 1730 1731// Vector width in bytes 1732const int Matcher::vector_width_in_bytes(BasicType bt) { 1733 assert(MaxVectorSize == 8, ""); 1734 return 8; 1735} 1736 1737// Vector ideal reg 1738const uint Matcher::vector_ideal_reg(int size) { 1739 assert(MaxVectorSize == 8, ""); 1740 return Op_RegD; 1741} 1742 1743const uint Matcher::vector_shift_count_ideal_reg(int size) { 1744 fatal("vector shift is not supported"); 1745 return Node::NotAMachineReg; 1746} 1747 1748// Limits on vector size (number of elements) loaded into vector. 1749const int Matcher::max_vector_size(const BasicType bt) { 1750 assert(is_java_primitive(bt), "only primitive type vectors"); 1751 return vector_width_in_bytes(bt)/type2aelembytes(bt); 1752} 1753 1754const int Matcher::min_vector_size(const BasicType bt) { 1755 return max_vector_size(bt); // Same as max. 1756} 1757 1758// SPARC doesn't support misaligned vectors store/load. 1759const bool Matcher::misaligned_vectors_ok() { 1760 return false; 1761} 1762 1763// Current (2013) SPARC platforms need to read original key 1764// to construct decryption expanded key 1765const bool Matcher::pass_original_key_for_aes() { 1766 return true; 1767} 1768 1769// NOTE: All currently supported SPARC HW provides fast conversion. 1770const bool Matcher::convL2FSupported(void) { return true; } 1771 1772// Is this branch offset short enough that a short branch can be used? 1773// 1774// NOTE: If the platform does not provide any short branch variants, then 1775// this method should return false for offset 0. 1776bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 1777 // The passed offset is relative to address of the branch. 1778 // Don't need to adjust the offset. 1779 return UseCBCond && Assembler::is_simm12(offset); 1780} 1781 1782const bool Matcher::isSimpleConstant64(jlong value) { 1783 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1784 // Depends on optimizations in MacroAssembler::setx. 1785 int hi = (int)(value >> 32); 1786 int lo = (int)(value & ~0); 1787 return (hi == 0) || (hi == -1) || (lo == 0); 1788} 1789 1790// No scaling for the parameter the ClearArray node. 1791const bool Matcher::init_array_count_is_in_bytes = true; 1792 1793// No additional cost for CMOVL. 1794const int Matcher::long_cmove_cost() { return 0; } 1795 1796// CMOVF/CMOVD are expensive on e.g., T4 and SPARC64. 1797const int Matcher::float_cmove_cost() { 1798 return VM_Version::has_fast_cmove() ? 0 : ConditionalMoveLimit; 1799} 1800 1801// Does the CPU require late expand (see block.cpp for description of late expand)? 1802const bool Matcher::require_postalloc_expand = false; 1803 1804// Do we need to mask the count passed to shift instructions or does 1805// the cpu only look at the lower 5/6 bits anyway? 1806const bool Matcher::need_masked_shift_count = false; 1807 1808bool Matcher::narrow_oop_use_complex_address() { 1809 assert(UseCompressedOops, "only for compressed oops code"); 1810 return false; 1811} 1812 1813bool Matcher::narrow_klass_use_complex_address() { 1814 assert(UseCompressedClassPointers, "only for compressed klass code"); 1815 return false; 1816} 1817 1818bool Matcher::const_oop_prefer_decode() { 1819 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1820 // Prefer ConN+DecodeN over ConP in simple compressed oops mode. 1821 // return Universe::narrow_oop_base() == NULL; 1822 return true; 1823} 1824 1825bool Matcher::const_klass_prefer_decode() { 1826 // TODO: Check if loading ConP from TOC in heap-based mode is better: 1827 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode. 1828 // return Universe::narrow_klass_base() == NULL; 1829 return true; 1830} 1831 1832// Is it better to copy float constants, or load them directly from memory? 1833// Intel can load a float constant from a direct address, requiring no 1834// extra registers. Most RISCs will have to materialize an address into a 1835// register first, so they would do better to copy the constant from stack. 1836const bool Matcher::rematerialize_float_constants = false; 1837 1838// If CPU can load and store mis-aligned doubles directly then no fixup is 1839// needed. Else we split the double into 2 integer pieces and move it 1840// piece-by-piece. Only happens when passing doubles into C code as the 1841// Java calling convention forces doubles to be aligned. 1842const bool Matcher::misaligned_doubles_ok = true; 1843 1844// No-op on SPARC. 1845void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1846} 1847 1848// Advertise here if the CPU requires explicit rounding operations 1849// to implement the UseStrictFP mode. 1850const bool Matcher::strict_fp_requires_explicit_rounding = false; 1851 1852// Are floats converted to double when stored to stack during deoptimization? 1853// Sparc does not handle callee-save floats. 1854bool Matcher::float_in_double() { return false; } 1855 1856// Do ints take an entire long register or just half? 1857// Note that we if-def off of _LP64. 1858// The relevant question is how the int is callee-saved. In _LP64 1859// the whole long is written but de-opt'ing will have to extract 1860// the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1861const bool Matcher::int_in_long = true; 1862 1863// Return whether or not this register is ever used as an argument. This 1864// function is used on startup to build the trampoline stubs in generateOptoStub. 1865// Registers not mentioned will be killed by the VM call in the trampoline, and 1866// arguments in those registers not be available to the callee. 1867bool Matcher::can_be_java_arg( int reg ) { 1868 // Standard sparc 6 args in registers 1869 if( reg == R_I0_num || 1870 reg == R_I1_num || 1871 reg == R_I2_num || 1872 reg == R_I3_num || 1873 reg == R_I4_num || 1874 reg == R_I5_num ) return true; 1875 // 64-bit builds can pass 64-bit pointers and longs in 1876 // the high I registers 1877 if( reg == R_I0H_num || 1878 reg == R_I1H_num || 1879 reg == R_I2H_num || 1880 reg == R_I3H_num || 1881 reg == R_I4H_num || 1882 reg == R_I5H_num ) return true; 1883 1884 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1885 return true; 1886 } 1887 1888 // A few float args in registers 1889 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1890 1891 return false; 1892} 1893 1894bool Matcher::is_spillable_arg( int reg ) { 1895 return can_be_java_arg(reg); 1896} 1897 1898bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) { 1899 // Use hardware SDIVX instruction when it is 1900 // faster than a code which use multiply. 1901 return VM_Version::has_fast_idiv(); 1902} 1903 1904// Register for DIVI projection of divmodI 1905RegMask Matcher::divI_proj_mask() { 1906 ShouldNotReachHere(); 1907 return RegMask(); 1908} 1909 1910// Register for MODI projection of divmodI 1911RegMask Matcher::modI_proj_mask() { 1912 ShouldNotReachHere(); 1913 return RegMask(); 1914} 1915 1916// Register for DIVL projection of divmodL 1917RegMask Matcher::divL_proj_mask() { 1918 ShouldNotReachHere(); 1919 return RegMask(); 1920} 1921 1922// Register for MODL projection of divmodL 1923RegMask Matcher::modL_proj_mask() { 1924 ShouldNotReachHere(); 1925 return RegMask(); 1926} 1927 1928const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1929 return L7_REGP_mask(); 1930} 1931 1932 1933const bool Matcher::convi2l_type_required = true; 1934 1935// Should the Matcher clone shifts on addressing modes, expecting them 1936// to be subsumed into complex addressing expressions or compute them 1937// into registers? 1938bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 1939 return clone_base_plus_offset_address(m, mstack, address_visited); 1940} 1941 1942void Compile::reshape_address(AddPNode* addp) { 1943} 1944 1945%} 1946 1947 1948// The intptr_t operand types, defined by textual substitution. 1949// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1950#define immX immL 1951#define immX13 immL13 1952#define immX13m7 immL13m7 1953#define iRegX iRegL 1954#define g1RegX g1RegL 1955 1956//----------ENCODING BLOCK----------------------------------------------------- 1957// This block specifies the encoding classes used by the compiler to output 1958// byte streams. Encoding classes are parameterized macros used by 1959// Machine Instruction Nodes in order to generate the bit encoding of the 1960// instruction. Operands specify their base encoding interface with the 1961// interface keyword. There are currently supported four interfaces, 1962// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1963// operand to generate a function which returns its register number when 1964// queried. CONST_INTER causes an operand to generate a function which 1965// returns the value of the constant when queried. MEMORY_INTER causes an 1966// operand to generate four functions which return the Base Register, the 1967// Index Register, the Scale Value, and the Offset Value of the operand when 1968// queried. COND_INTER causes an operand to generate six functions which 1969// return the encoding code (ie - encoding bits for the instruction) 1970// associated with each basic boolean condition for a conditional instruction. 1971// 1972// Instructions specify two basic values for encoding. Again, a function 1973// is available to check if the constant displacement is an oop. They use the 1974// ins_encode keyword to specify their encoding classes (which must be 1975// a sequence of enc_class names, and their parameters, specified in 1976// the encoding block), and they use the 1977// opcode keyword to specify, in order, their primary, secondary, and 1978// tertiary opcode. Only the opcode sections which a particular instruction 1979// needs for encoding need to be specified. 1980encode %{ 1981 enc_class enc_untested %{ 1982#ifdef ASSERT 1983 MacroAssembler _masm(&cbuf); 1984 __ untested("encoding"); 1985#endif 1986 %} 1987 1988 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1989 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary, 1990 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1991 %} 1992 1993 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1994 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 1995 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1996 %} 1997 1998 enc_class form3_mem_prefetch_read( memory mem ) %{ 1999 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2000 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 2001 %} 2002 2003 enc_class form3_mem_prefetch_write( memory mem ) %{ 2004 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, 2005 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 2006 %} 2007 2008 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 2009 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2010 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2011 guarantee($mem$$index == R_G0_enc, "double index?"); 2012 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 2013 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 2014 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 2015 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 2016 %} 2017 2018 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 2019 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4"); 2020 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4"); 2021 guarantee($mem$$index == R_G0_enc, "double index?"); 2022 // Load long with 2 instructions 2023 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 2024 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 2025 %} 2026 2027 //%%% form3_mem_plus_4_reg is a hack--get rid of it 2028 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 2029 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 2030 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 2031 %} 2032 2033 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 2034 // Encode a reg-reg copy. If it is useless, then empty encoding. 2035 if( $rs2$$reg != $rd$$reg ) 2036 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 2037 %} 2038 2039 // Target lo half of long 2040 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 2041 // Encode a reg-reg copy. If it is useless, then empty encoding. 2042 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 2043 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 2044 %} 2045 2046 // Source lo half of long 2047 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 2048 // Encode a reg-reg copy. If it is useless, then empty encoding. 2049 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 2050 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 2051 %} 2052 2053 // Target hi half of long 2054 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 2055 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 2056 %} 2057 2058 // Source lo half of long, and leave it sign extended. 2059 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 2060 // Sign extend low half 2061 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 2062 %} 2063 2064 // Source hi half of long, and leave it sign extended. 2065 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2066 // Shift high half to low half 2067 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2068 %} 2069 2070 // Source hi half of long 2071 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2072 // Encode a reg-reg copy. If it is useless, then empty encoding. 2073 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2074 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2075 %} 2076 2077 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2078 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2079 %} 2080 2081 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2082 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2083 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2084 %} 2085 2086 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2087 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2088 // clear if nothing else is happening 2089 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2090 // blt,a,pn done 2091 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2092 // mov dst,-1 in delay slot 2093 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2094 %} 2095 2096 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2097 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2098 %} 2099 2100 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2101 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2102 %} 2103 2104 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2105 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2106 %} 2107 2108 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2109 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2110 %} 2111 2112 enc_class move_return_pc_to_o1() %{ 2113 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2114 %} 2115 2116 /* %%% merge with enc_to_bool */ 2117 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2118 MacroAssembler _masm(&cbuf); 2119 2120 Register src_reg = reg_to_register_object($src$$reg); 2121 Register dst_reg = reg_to_register_object($dst$$reg); 2122 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2123 %} 2124 2125 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2126 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2127 MacroAssembler _masm(&cbuf); 2128 2129 Register p_reg = reg_to_register_object($p$$reg); 2130 Register q_reg = reg_to_register_object($q$$reg); 2131 Register y_reg = reg_to_register_object($y$$reg); 2132 Register tmp_reg = reg_to_register_object($tmp$$reg); 2133 2134 __ subcc( p_reg, q_reg, p_reg ); 2135 __ add ( p_reg, y_reg, tmp_reg ); 2136 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2137 %} 2138 2139 enc_class form_d2i_helper(regD src, regF dst) %{ 2140 // fcmp %fcc0,$src,$src 2141 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2142 // branch %fcc0 not-nan, predict taken 2143 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2144 // fdtoi $src,$dst 2145 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2146 // fitos $dst,$dst (if nan) 2147 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2148 // clear $dst (if nan) 2149 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2150 // carry on here... 2151 %} 2152 2153 enc_class form_d2l_helper(regD src, regD dst) %{ 2154 // fcmp %fcc0,$src,$src check for NAN 2155 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2156 // branch %fcc0 not-nan, predict taken 2157 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2158 // fdtox $src,$dst convert in delay slot 2159 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2160 // fxtod $dst,$dst (if nan) 2161 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2162 // clear $dst (if nan) 2163 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2164 // carry on here... 2165 %} 2166 2167 enc_class form_f2i_helper(regF src, regF dst) %{ 2168 // fcmps %fcc0,$src,$src 2169 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2170 // branch %fcc0 not-nan, predict taken 2171 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2172 // fstoi $src,$dst 2173 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2174 // fitos $dst,$dst (if nan) 2175 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2176 // clear $dst (if nan) 2177 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2178 // carry on here... 2179 %} 2180 2181 enc_class form_f2l_helper(regF src, regD dst) %{ 2182 // fcmps %fcc0,$src,$src 2183 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2184 // branch %fcc0 not-nan, predict taken 2185 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2186 // fstox $src,$dst 2187 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2188 // fxtod $dst,$dst (if nan) 2189 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2190 // clear $dst (if nan) 2191 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2192 // carry on here... 2193 %} 2194 2195 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2196 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2197 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2198 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2199 2200 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2201 2202 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2203 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2204 2205 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2206 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2207 %} 2208 2209 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2210 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2211 %} 2212 2213 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2214 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2215 %} 2216 2217 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2218 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2219 %} 2220 2221 enc_class form3_convI2F(regF rs2, regF rd) %{ 2222 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2223 %} 2224 2225 // Encloding class for traceable jumps 2226 enc_class form_jmpl(g3RegP dest) %{ 2227 emit_jmpl(cbuf, $dest$$reg); 2228 %} 2229 2230 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2231 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2232 %} 2233 2234 enc_class form2_nop() %{ 2235 emit_nop(cbuf); 2236 %} 2237 2238 enc_class form2_illtrap() %{ 2239 emit_illtrap(cbuf); 2240 %} 2241 2242 2243 // Compare longs and convert into -1, 0, 1. 2244 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2245 // CMP $src1,$src2 2246 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2247 // blt,a,pn done 2248 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2249 // mov dst,-1 in delay slot 2250 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2251 // bgt,a,pn done 2252 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2253 // mov dst,1 in delay slot 2254 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2255 // CLR $dst 2256 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2257 %} 2258 2259 enc_class enc_PartialSubtypeCheck() %{ 2260 MacroAssembler _masm(&cbuf); 2261 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2262 __ delayed()->nop(); 2263 %} 2264 2265 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{ 2266 MacroAssembler _masm(&cbuf); 2267 Label* L = $labl$$label; 2268 Assembler::Predict predict_taken = 2269 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2270 2271 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 2272 __ delayed()->nop(); 2273 %} 2274 2275 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2276 MacroAssembler _masm(&cbuf); 2277 Label* L = $labl$$label; 2278 Assembler::Predict predict_taken = 2279 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 2280 2281 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L); 2282 __ delayed()->nop(); 2283 %} 2284 2285 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2286 int op = (Assembler::arith_op << 30) | 2287 ($dst$$reg << 25) | 2288 (Assembler::movcc_op3 << 19) | 2289 (1 << 18) | // cc2 bit for 'icc' 2290 ($cmp$$cmpcode << 14) | 2291 (0 << 13) | // select register move 2292 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2293 ($src$$reg << 0); 2294 cbuf.insts()->emit_int32(op); 2295 %} 2296 2297 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2298 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2299 int op = (Assembler::arith_op << 30) | 2300 ($dst$$reg << 25) | 2301 (Assembler::movcc_op3 << 19) | 2302 (1 << 18) | // cc2 bit for 'icc' 2303 ($cmp$$cmpcode << 14) | 2304 (1 << 13) | // select immediate move 2305 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2306 (simm11 << 0); 2307 cbuf.insts()->emit_int32(op); 2308 %} 2309 2310 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2311 int op = (Assembler::arith_op << 30) | 2312 ($dst$$reg << 25) | 2313 (Assembler::movcc_op3 << 19) | 2314 (0 << 18) | // cc2 bit for 'fccX' 2315 ($cmp$$cmpcode << 14) | 2316 (0 << 13) | // select register move 2317 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2318 ($src$$reg << 0); 2319 cbuf.insts()->emit_int32(op); 2320 %} 2321 2322 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2323 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2324 int op = (Assembler::arith_op << 30) | 2325 ($dst$$reg << 25) | 2326 (Assembler::movcc_op3 << 19) | 2327 (0 << 18) | // cc2 bit for 'fccX' 2328 ($cmp$$cmpcode << 14) | 2329 (1 << 13) | // select immediate move 2330 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2331 (simm11 << 0); 2332 cbuf.insts()->emit_int32(op); 2333 %} 2334 2335 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2336 int op = (Assembler::arith_op << 30) | 2337 ($dst$$reg << 25) | 2338 (Assembler::fpop2_op3 << 19) | 2339 (0 << 18) | 2340 ($cmp$$cmpcode << 14) | 2341 (1 << 13) | // select register move 2342 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2343 ($primary << 5) | // select single, double or quad 2344 ($src$$reg << 0); 2345 cbuf.insts()->emit_int32(op); 2346 %} 2347 2348 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2349 int op = (Assembler::arith_op << 30) | 2350 ($dst$$reg << 25) | 2351 (Assembler::fpop2_op3 << 19) | 2352 (0 << 18) | 2353 ($cmp$$cmpcode << 14) | 2354 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2355 ($primary << 5) | // select single, double or quad 2356 ($src$$reg << 0); 2357 cbuf.insts()->emit_int32(op); 2358 %} 2359 2360 // Used by the MIN/MAX encodings. Same as a CMOV, but 2361 // the condition comes from opcode-field instead of an argument. 2362 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2363 int op = (Assembler::arith_op << 30) | 2364 ($dst$$reg << 25) | 2365 (Assembler::movcc_op3 << 19) | 2366 (1 << 18) | // cc2 bit for 'icc' 2367 ($primary << 14) | 2368 (0 << 13) | // select register move 2369 (0 << 11) | // cc1, cc0 bits for 'icc' 2370 ($src$$reg << 0); 2371 cbuf.insts()->emit_int32(op); 2372 %} 2373 2374 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2375 int op = (Assembler::arith_op << 30) | 2376 ($dst$$reg << 25) | 2377 (Assembler::movcc_op3 << 19) | 2378 (6 << 16) | // cc2 bit for 'xcc' 2379 ($primary << 14) | 2380 (0 << 13) | // select register move 2381 (0 << 11) | // cc1, cc0 bits for 'icc' 2382 ($src$$reg << 0); 2383 cbuf.insts()->emit_int32(op); 2384 %} 2385 2386 enc_class Set13( immI13 src, iRegI rd ) %{ 2387 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2388 %} 2389 2390 enc_class SetHi22( immI src, iRegI rd ) %{ 2391 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2392 %} 2393 2394 enc_class Set32( immI src, iRegI rd ) %{ 2395 MacroAssembler _masm(&cbuf); 2396 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2397 %} 2398 2399 enc_class call_epilog %{ 2400 if( VerifyStackAtCalls ) { 2401 MacroAssembler _masm(&cbuf); 2402 int framesize = ra_->C->frame_size_in_bytes(); 2403 Register temp_reg = G3; 2404 __ add(SP, framesize, temp_reg); 2405 __ cmp(temp_reg, FP); 2406 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2407 } 2408 %} 2409 2410 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2411 // to G1 so the register allocator will not have to deal with the misaligned register 2412 // pair. 2413 enc_class adjust_long_from_native_call %{ 2414 %} 2415 2416 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2417 // CALL directly to the runtime 2418 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2419 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true); 2420 %} 2421 2422 enc_class preserve_SP %{ 2423 MacroAssembler _masm(&cbuf); 2424 __ mov(SP, L7_mh_SP_save); 2425 %} 2426 2427 enc_class restore_SP %{ 2428 MacroAssembler _masm(&cbuf); 2429 __ mov(L7_mh_SP_save, SP); 2430 %} 2431 2432 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2433 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2434 // who we intended to call. 2435 if (!_method) { 2436 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec()); 2437 } else { 2438 int method_index = resolved_method_index(cbuf); 2439 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 2440 : static_call_Relocation::spec(method_index); 2441 emit_call_reloc(cbuf, $meth$$method, rspec); 2442 2443 // Emit stub for static call. 2444 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 2445 if (stub == NULL) { 2446 ciEnv::current()->record_failure("CodeCache is full"); 2447 return; 2448 } 2449 } 2450 %} 2451 2452 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2453 MacroAssembler _masm(&cbuf); 2454 __ set_inst_mark(); 2455 int vtable_index = this->_vtable_index; 2456 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2457 if (vtable_index < 0) { 2458 // must be invalid_vtable_index, not nonvirtual_vtable_index 2459 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 2460 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2461 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2462 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2463 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf)); 2464 } else { 2465 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2466 // Just go thru the vtable 2467 // get receiver klass (receiver already checked for non-null) 2468 // If we end up going thru a c2i adapter interpreter expects method in G5 2469 int off = __ offset(); 2470 __ load_klass(O0, G3_scratch); 2471 int klass_load_size; 2472 if (UseCompressedClassPointers) { 2473 assert(Universe::heap() != NULL, "java heap should be initialized"); 2474 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord; 2475 } else { 2476 klass_load_size = 1*BytesPerInstWord; 2477 } 2478 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes(); 2479 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 2480 if (Assembler::is_simm13(v_off)) { 2481 __ ld_ptr(G3, v_off, G5_method); 2482 } else { 2483 // Generate 2 instructions 2484 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2485 __ or3(G5_method, v_off & 0x3ff, G5_method); 2486 // ld_ptr, set_hi, set 2487 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2488 "Unexpected instruction size(s)"); 2489 __ ld_ptr(G3, G5_method, G5_method); 2490 } 2491 // NOTE: for vtable dispatches, the vtable entry will never be null. 2492 // However it may very well end up in handle_wrong_method if the 2493 // method is abstract for the particular class. 2494 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch); 2495 // jump to target (either compiled code or c2iadapter) 2496 __ jmpl(G3_scratch, G0, O7); 2497 __ delayed()->nop(); 2498 } 2499 %} 2500 2501 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2502 MacroAssembler _masm(&cbuf); 2503 2504 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2505 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2506 // we might be calling a C2I adapter which needs it. 2507 2508 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2509 // Load nmethod 2510 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg); 2511 2512 // CALL to compiled java, indirect the contents of G3 2513 __ set_inst_mark(); 2514 __ callr(temp_reg, G0); 2515 __ delayed()->nop(); 2516 %} 2517 2518enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2519 MacroAssembler _masm(&cbuf); 2520 Register Rdividend = reg_to_register_object($src1$$reg); 2521 Register Rdivisor = reg_to_register_object($src2$$reg); 2522 Register Rresult = reg_to_register_object($dst$$reg); 2523 2524 __ sra(Rdivisor, 0, Rdivisor); 2525 __ sra(Rdividend, 0, Rdividend); 2526 __ sdivx(Rdividend, Rdivisor, Rresult); 2527%} 2528 2529enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2530 MacroAssembler _masm(&cbuf); 2531 2532 Register Rdividend = reg_to_register_object($src1$$reg); 2533 int divisor = $imm$$constant; 2534 Register Rresult = reg_to_register_object($dst$$reg); 2535 2536 __ sra(Rdividend, 0, Rdividend); 2537 __ sdivx(Rdividend, divisor, Rresult); 2538%} 2539 2540enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2541 MacroAssembler _masm(&cbuf); 2542 Register Rsrc1 = reg_to_register_object($src1$$reg); 2543 Register Rsrc2 = reg_to_register_object($src2$$reg); 2544 Register Rdst = reg_to_register_object($dst$$reg); 2545 2546 __ sra( Rsrc1, 0, Rsrc1 ); 2547 __ sra( Rsrc2, 0, Rsrc2 ); 2548 __ mulx( Rsrc1, Rsrc2, Rdst ); 2549 __ srlx( Rdst, 32, Rdst ); 2550%} 2551 2552enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2553 MacroAssembler _masm(&cbuf); 2554 Register Rdividend = reg_to_register_object($src1$$reg); 2555 Register Rdivisor = reg_to_register_object($src2$$reg); 2556 Register Rresult = reg_to_register_object($dst$$reg); 2557 Register Rscratch = reg_to_register_object($scratch$$reg); 2558 2559 assert(Rdividend != Rscratch, ""); 2560 assert(Rdivisor != Rscratch, ""); 2561 2562 __ sra(Rdividend, 0, Rdividend); 2563 __ sra(Rdivisor, 0, Rdivisor); 2564 __ sdivx(Rdividend, Rdivisor, Rscratch); 2565 __ mulx(Rscratch, Rdivisor, Rscratch); 2566 __ sub(Rdividend, Rscratch, Rresult); 2567%} 2568 2569enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2570 MacroAssembler _masm(&cbuf); 2571 2572 Register Rdividend = reg_to_register_object($src1$$reg); 2573 int divisor = $imm$$constant; 2574 Register Rresult = reg_to_register_object($dst$$reg); 2575 Register Rscratch = reg_to_register_object($scratch$$reg); 2576 2577 assert(Rdividend != Rscratch, ""); 2578 2579 __ sra(Rdividend, 0, Rdividend); 2580 __ sdivx(Rdividend, divisor, Rscratch); 2581 __ mulx(Rscratch, divisor, Rscratch); 2582 __ sub(Rdividend, Rscratch, Rresult); 2583%} 2584 2585enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2586 MacroAssembler _masm(&cbuf); 2587 2588 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2589 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2590 2591 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2592%} 2593 2594enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2595 MacroAssembler _masm(&cbuf); 2596 2597 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2598 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2599 2600 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2601%} 2602 2603enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2604 MacroAssembler _masm(&cbuf); 2605 2606 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2607 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2608 2609 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2610%} 2611 2612enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2613 MacroAssembler _masm(&cbuf); 2614 2615 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2616 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2617 2618 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2619%} 2620 2621enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2622 MacroAssembler _masm(&cbuf); 2623 2624 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2625 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2626 2627 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2628%} 2629 2630 2631 2632enc_class fmadds (sflt_reg dst, sflt_reg a, sflt_reg b, sflt_reg c) %{ 2633 MacroAssembler _masm(&cbuf); 2634 2635 FloatRegister Frd = reg_to_SingleFloatRegister_object($dst$$reg); 2636 FloatRegister Fra = reg_to_SingleFloatRegister_object($a$$reg); 2637 FloatRegister Frb = reg_to_SingleFloatRegister_object($b$$reg); 2638 FloatRegister Frc = reg_to_SingleFloatRegister_object($c$$reg); 2639 2640 __ fmadd(FloatRegisterImpl::S, Fra, Frb, Frc, Frd); 2641%} 2642 2643enc_class fmaddd (dflt_reg dst, dflt_reg a, dflt_reg b, dflt_reg c) %{ 2644 MacroAssembler _masm(&cbuf); 2645 2646 FloatRegister Frd = reg_to_DoubleFloatRegister_object($dst$$reg); 2647 FloatRegister Fra = reg_to_DoubleFloatRegister_object($a$$reg); 2648 FloatRegister Frb = reg_to_DoubleFloatRegister_object($b$$reg); 2649 FloatRegister Frc = reg_to_DoubleFloatRegister_object($c$$reg); 2650 2651 __ fmadd(FloatRegisterImpl::D, Fra, Frb, Frc, Frd); 2652%} 2653 2654 2655 2656 2657enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2658 MacroAssembler _masm(&cbuf); 2659 2660 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2661 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2662 2663 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2664%} 2665 2666enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2667 MacroAssembler _masm(&cbuf); 2668 2669 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2670 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2671 2672 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2673%} 2674 2675enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2676 MacroAssembler _masm(&cbuf); 2677 2678 Register Roop = reg_to_register_object($oop$$reg); 2679 Register Rbox = reg_to_register_object($box$$reg); 2680 Register Rscratch = reg_to_register_object($scratch$$reg); 2681 Register Rmark = reg_to_register_object($scratch2$$reg); 2682 2683 assert(Roop != Rscratch, ""); 2684 assert(Roop != Rmark, ""); 2685 assert(Rbox != Rscratch, ""); 2686 assert(Rbox != Rmark, ""); 2687 2688 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2689%} 2690 2691enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2692 MacroAssembler _masm(&cbuf); 2693 2694 Register Roop = reg_to_register_object($oop$$reg); 2695 Register Rbox = reg_to_register_object($box$$reg); 2696 Register Rscratch = reg_to_register_object($scratch$$reg); 2697 Register Rmark = reg_to_register_object($scratch2$$reg); 2698 2699 assert(Roop != Rscratch, ""); 2700 assert(Roop != Rmark, ""); 2701 assert(Rbox != Rscratch, ""); 2702 assert(Rbox != Rmark, ""); 2703 2704 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2705 %} 2706 2707 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2708 MacroAssembler _masm(&cbuf); 2709 Register Rmem = reg_to_register_object($mem$$reg); 2710 Register Rold = reg_to_register_object($old$$reg); 2711 Register Rnew = reg_to_register_object($new$$reg); 2712 2713 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2714 __ cmp( Rold, Rnew ); 2715 %} 2716 2717 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2718 Register Rmem = reg_to_register_object($mem$$reg); 2719 Register Rold = reg_to_register_object($old$$reg); 2720 Register Rnew = reg_to_register_object($new$$reg); 2721 2722 MacroAssembler _masm(&cbuf); 2723 __ mov(Rnew, O7); 2724 __ casx(Rmem, Rold, O7); 2725 __ cmp( Rold, O7 ); 2726 %} 2727 2728 // raw int cas, used for compareAndSwap 2729 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2730 Register Rmem = reg_to_register_object($mem$$reg); 2731 Register Rold = reg_to_register_object($old$$reg); 2732 Register Rnew = reg_to_register_object($new$$reg); 2733 2734 MacroAssembler _masm(&cbuf); 2735 __ mov(Rnew, O7); 2736 __ cas(Rmem, Rold, O7); 2737 __ cmp( Rold, O7 ); 2738 %} 2739 2740 // raw int cas without using tmp register for compareAndExchange 2741 enc_class enc_casi_exch( iRegP mem, iRegL old, iRegL new) %{ 2742 Register Rmem = reg_to_register_object($mem$$reg); 2743 Register Rold = reg_to_register_object($old$$reg); 2744 Register Rnew = reg_to_register_object($new$$reg); 2745 2746 MacroAssembler _masm(&cbuf); 2747 __ cas(Rmem, Rold, Rnew); 2748 %} 2749 2750 // 64-bit cas without using tmp register for compareAndExchange 2751 enc_class enc_casx_exch( iRegP mem, iRegL old, iRegL new) %{ 2752 Register Rmem = reg_to_register_object($mem$$reg); 2753 Register Rold = reg_to_register_object($old$$reg); 2754 Register Rnew = reg_to_register_object($new$$reg); 2755 2756 MacroAssembler _masm(&cbuf); 2757 __ casx(Rmem, Rold, Rnew); 2758 %} 2759 2760 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2761 Register Rres = reg_to_register_object($res$$reg); 2762 2763 MacroAssembler _masm(&cbuf); 2764 __ mov(1, Rres); 2765 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2766 %} 2767 2768 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2769 Register Rres = reg_to_register_object($res$$reg); 2770 2771 MacroAssembler _masm(&cbuf); 2772 __ mov(1, Rres); 2773 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2774 %} 2775 2776 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2777 MacroAssembler _masm(&cbuf); 2778 Register Rdst = reg_to_register_object($dst$$reg); 2779 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2780 : reg_to_DoubleFloatRegister_object($src1$$reg); 2781 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2782 : reg_to_DoubleFloatRegister_object($src2$$reg); 2783 2784 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2785 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2786 %} 2787 2788 enc_class enc_rethrow() %{ 2789 cbuf.set_insts_mark(); 2790 Register temp_reg = G3; 2791 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 2792 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 2793 MacroAssembler _masm(&cbuf); 2794#ifdef ASSERT 2795 __ save_frame(0); 2796 AddressLiteral last_rethrow_addrlit(&last_rethrow); 2797 __ sethi(last_rethrow_addrlit, L1); 2798 Address addr(L1, last_rethrow_addrlit.low10()); 2799 __ rdpc(L2); 2800 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 2801 __ st_ptr(L2, addr); 2802 __ restore(); 2803#endif 2804 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 2805 __ delayed()->nop(); 2806 %} 2807 2808 enc_class emit_mem_nop() %{ 2809 // Generates the instruction LDUXA [o6,g0],#0x82,g0 2810 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 2811 %} 2812 2813 enc_class emit_fadd_nop() %{ 2814 // Generates the instruction FMOVS f31,f31 2815 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 2816 %} 2817 2818 enc_class emit_br_nop() %{ 2819 // Generates the instruction BPN,PN . 2820 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 2821 %} 2822 2823 enc_class enc_membar_acquire %{ 2824 MacroAssembler _masm(&cbuf); 2825 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 2826 %} 2827 2828 enc_class enc_membar_release %{ 2829 MacroAssembler _masm(&cbuf); 2830 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 2831 %} 2832 2833 enc_class enc_membar_volatile %{ 2834 MacroAssembler _masm(&cbuf); 2835 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 2836 %} 2837 2838%} 2839 2840//----------FRAME-------------------------------------------------------------- 2841// Definition of frame structure and management information. 2842// 2843// S T A C K L A Y O U T Allocators stack-slot number 2844// | (to get allocators register number 2845// G Owned by | | v add VMRegImpl::stack0) 2846// r CALLER | | 2847// o | +--------+ pad to even-align allocators stack-slot 2848// w V | pad0 | numbers; owned by CALLER 2849// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 2850// h ^ | in | 5 2851// | | args | 4 Holes in incoming args owned by SELF 2852// | | | | 3 2853// | | +--------+ 2854// V | | old out| Empty on Intel, window on Sparc 2855// | old |preserve| Must be even aligned. 2856// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 2857// | | in | 3 area for Intel ret address 2858// Owned by |preserve| Empty on Sparc. 2859// SELF +--------+ 2860// | | pad2 | 2 pad to align old SP 2861// | +--------+ 1 2862// | | locks | 0 2863// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 2864// | | pad1 | 11 pad to align new SP 2865// | +--------+ 2866// | | | 10 2867// | | spills | 9 spills 2868// V | | 8 (pad0 slot for callee) 2869// -----------+--------+----> Matcher::_out_arg_limit, unaligned 2870// ^ | out | 7 2871// | | args | 6 Holes in outgoing args owned by CALLEE 2872// Owned by +--------+ 2873// CALLEE | new out| 6 Empty on Intel, window on Sparc 2874// | new |preserve| Must be even-aligned. 2875// | SP-+--------+----> Matcher::_new_SP, even aligned 2876// | | | 2877// 2878// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 2879// known from SELF's arguments and the Java calling convention. 2880// Region 6-7 is determined per call site. 2881// Note 2: If the calling convention leaves holes in the incoming argument 2882// area, those holes are owned by SELF. Holes in the outgoing area 2883// are owned by the CALLEE. Holes should not be nessecary in the 2884// incoming area, as the Java calling convention is completely under 2885// the control of the AD file. Doubles can be sorted and packed to 2886// avoid holes. Holes in the outgoing arguments may be necessary for 2887// varargs C calling conventions. 2888// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 2889// even aligned with pad0 as needed. 2890// Region 6 is even aligned. Region 6-7 is NOT even aligned; 2891// region 6-11 is even aligned; it may be padded out more so that 2892// the region from SP to FP meets the minimum stack alignment. 2893 2894frame %{ 2895 // What direction does stack grow in (assumed to be same for native & Java) 2896 stack_direction(TOWARDS_LOW); 2897 2898 // These two registers define part of the calling convention 2899 // between compiled code and the interpreter. 2900 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C 2901 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 2902 2903 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 2904 cisc_spilling_operand_name(indOffset); 2905 2906 // Number of stack slots consumed by a Monitor enter 2907 sync_stack_slots(2); 2908 2909 // Compiled code's Frame Pointer 2910 frame_pointer(R_SP); 2911 2912 // Stack alignment requirement 2913 stack_alignment(StackAlignmentInBytes); 2914 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 2915 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 2916 2917 // Number of stack slots between incoming argument block and the start of 2918 // a new frame. The PROLOG must add this many slots to the stack. The 2919 // EPILOG must remove this many slots. 2920 in_preserve_stack_slots(0); 2921 2922 // Number of outgoing stack slots killed above the out_preserve_stack_slots 2923 // for calls to C. Supports the var-args backing area for register parms. 2924 // ADLC doesn't support parsing expressions, so I folded the math by hand. 2925 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 2926 varargs_C_out_slots_killed(12); 2927 2928 // The after-PROLOG location of the return address. Location of 2929 // return address specifies a type (REG or STACK) and a number 2930 // representing the register number (i.e. - use a register name) or 2931 // stack slot. 2932 return_addr(REG R_I7); // Ret Addr is in register I7 2933 2934 // Body of function which returns an OptoRegs array locating 2935 // arguments either in registers or in stack slots for calling 2936 // java 2937 calling_convention %{ 2938 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 2939 2940 %} 2941 2942 // Body of function which returns an OptoRegs array locating 2943 // arguments either in registers or in stack slots for calling 2944 // C. 2945 c_calling_convention %{ 2946 // This is obviously always outgoing 2947 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 2948 %} 2949 2950 // Location of native (C/C++) and interpreter return values. This is specified to 2951 // be the same as Java. In the 32-bit VM, long values are actually returned from 2952 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 2953 // to and from the register pairs is done by the appropriate call and epilog 2954 // opcodes. This simplifies the register allocator. 2955 c_return_value %{ 2956 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2957 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2958 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2959 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2960 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2961 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2962 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2963 %} 2964 2965 // Location of compiled Java return values. Same as C 2966 return_value %{ 2967 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 2968 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 2969 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 2970 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 2971 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 2972 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 2973 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 2974 %} 2975 2976%} 2977 2978 2979//----------ATTRIBUTES--------------------------------------------------------- 2980//----------Operand Attributes------------------------------------------------- 2981op_attrib op_cost(1); // Required cost attribute 2982 2983//----------Instruction Attributes--------------------------------------------- 2984ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 2985ins_attrib ins_size(32); // Required size attribute (in bits) 2986 2987// avoid_back_to_back attribute is an expression that must return 2988// one of the following values defined in MachNode: 2989// AVOID_NONE - instruction can be placed anywhere 2990// AVOID_BEFORE - instruction cannot be placed after an 2991// instruction with MachNode::AVOID_AFTER 2992// AVOID_AFTER - the next instruction cannot be the one 2993// with MachNode::AVOID_BEFORE 2994// AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at 2995// the same time 2996ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE); 2997 2998ins_attrib ins_short_branch(0); // Required flag: is this instruction a 2999 // non-matching short branch variant of some 3000 // long branch? 3001 3002//----------OPERANDS----------------------------------------------------------- 3003// Operand definitions must precede instruction definitions for correct parsing 3004// in the ADLC because operands constitute user defined types which are used in 3005// instruction definitions. 3006 3007//----------Simple Operands---------------------------------------------------- 3008// Immediate Operands 3009// Integer Immediate: 32-bit 3010operand immI() %{ 3011 match(ConI); 3012 3013 op_cost(0); 3014 // formats are generated automatically for constants and base registers 3015 format %{ %} 3016 interface(CONST_INTER); 3017%} 3018 3019// Integer Immediate: 0-bit 3020operand immI0() %{ 3021 predicate(n->get_int() == 0); 3022 match(ConI); 3023 op_cost(0); 3024 3025 format %{ %} 3026 interface(CONST_INTER); 3027%} 3028 3029// Integer Immediate: 5-bit 3030operand immI5() %{ 3031 predicate(Assembler::is_simm5(n->get_int())); 3032 match(ConI); 3033 op_cost(0); 3034 format %{ %} 3035 interface(CONST_INTER); 3036%} 3037 3038// Integer Immediate: 8-bit 3039operand immI8() %{ 3040 predicate(Assembler::is_simm8(n->get_int())); 3041 match(ConI); 3042 op_cost(0); 3043 format %{ %} 3044 interface(CONST_INTER); 3045%} 3046 3047// Integer Immediate: the value 10 3048operand immI10() %{ 3049 predicate(n->get_int() == 10); 3050 match(ConI); 3051 op_cost(0); 3052 3053 format %{ %} 3054 interface(CONST_INTER); 3055%} 3056 3057// Integer Immediate: 11-bit 3058operand immI11() %{ 3059 predicate(Assembler::is_simm11(n->get_int())); 3060 match(ConI); 3061 op_cost(0); 3062 format %{ %} 3063 interface(CONST_INTER); 3064%} 3065 3066// Integer Immediate: 13-bit 3067operand immI13() %{ 3068 predicate(Assembler::is_simm13(n->get_int())); 3069 match(ConI); 3070 op_cost(0); 3071 3072 format %{ %} 3073 interface(CONST_INTER); 3074%} 3075 3076// Integer Immediate: 13-bit minus 7 3077operand immI13m7() %{ 3078 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3079 match(ConI); 3080 op_cost(0); 3081 3082 format %{ %} 3083 interface(CONST_INTER); 3084%} 3085 3086// Integer Immediate: 16-bit 3087operand immI16() %{ 3088 predicate(Assembler::is_simm16(n->get_int())); 3089 match(ConI); 3090 op_cost(0); 3091 format %{ %} 3092 interface(CONST_INTER); 3093%} 3094 3095// Integer Immediate: the values 1-31 3096operand immI_1_31() %{ 3097 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3098 match(ConI); 3099 op_cost(0); 3100 3101 format %{ %} 3102 interface(CONST_INTER); 3103%} 3104 3105// Integer Immediate: the values 32-63 3106operand immI_32_63() %{ 3107 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3108 match(ConI); 3109 op_cost(0); 3110 3111 format %{ %} 3112 interface(CONST_INTER); 3113%} 3114 3115// Immediates for special shifts (sign extend) 3116 3117// Integer Immediate: the value 16 3118operand immI_16() %{ 3119 predicate(n->get_int() == 16); 3120 match(ConI); 3121 op_cost(0); 3122 3123 format %{ %} 3124 interface(CONST_INTER); 3125%} 3126 3127// Integer Immediate: the value 24 3128operand immI_24() %{ 3129 predicate(n->get_int() == 24); 3130 match(ConI); 3131 op_cost(0); 3132 3133 format %{ %} 3134 interface(CONST_INTER); 3135%} 3136// Integer Immediate: the value 255 3137operand immI_255() %{ 3138 predicate( n->get_int() == 255 ); 3139 match(ConI); 3140 op_cost(0); 3141 3142 format %{ %} 3143 interface(CONST_INTER); 3144%} 3145 3146// Integer Immediate: the value 65535 3147operand immI_65535() %{ 3148 predicate(n->get_int() == 65535); 3149 match(ConI); 3150 op_cost(0); 3151 3152 format %{ %} 3153 interface(CONST_INTER); 3154%} 3155 3156// Integer Immediate: the values 0-31 3157operand immU5() %{ 3158 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3159 match(ConI); 3160 op_cost(0); 3161 3162 format %{ %} 3163 interface(CONST_INTER); 3164%} 3165 3166// Integer Immediate: 6-bit 3167operand immU6() %{ 3168 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3169 match(ConI); 3170 op_cost(0); 3171 format %{ %} 3172 interface(CONST_INTER); 3173%} 3174 3175// Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13) 3176operand immU12() %{ 3177 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3178 match(ConI); 3179 op_cost(0); 3180 3181 format %{ %} 3182 interface(CONST_INTER); 3183%} 3184 3185// Unsigned Long Immediate: 12-bit (non-negative that fits in simm13) 3186operand immUL12() %{ 3187 predicate((0 <= n->get_long()) && (n->get_long() == (int)n->get_long()) && Assembler::is_simm13((int)n->get_long())); 3188 match(ConL); 3189 op_cost(0); 3190 3191 format %{ %} 3192 interface(CONST_INTER); 3193%} 3194 3195// Integer Immediate non-negative 3196operand immU31() 3197%{ 3198 predicate(n->get_int() >= 0); 3199 match(ConI); 3200 3201 op_cost(0); 3202 format %{ %} 3203 interface(CONST_INTER); 3204%} 3205 3206// Long Immediate: the value FF 3207operand immL_FF() %{ 3208 predicate( n->get_long() == 0xFFL ); 3209 match(ConL); 3210 op_cost(0); 3211 3212 format %{ %} 3213 interface(CONST_INTER); 3214%} 3215 3216// Long Immediate: the value FFFF 3217operand immL_FFFF() %{ 3218 predicate( n->get_long() == 0xFFFFL ); 3219 match(ConL); 3220 op_cost(0); 3221 3222 format %{ %} 3223 interface(CONST_INTER); 3224%} 3225 3226// Pointer Immediate: 32 or 64-bit 3227operand immP() %{ 3228 match(ConP); 3229 3230 op_cost(5); 3231 // formats are generated automatically for constants and base registers 3232 format %{ %} 3233 interface(CONST_INTER); 3234%} 3235 3236// Pointer Immediate: 64-bit 3237operand immP_set() %{ 3238 predicate(!VM_Version::has_fast_ld()); 3239 match(ConP); 3240 3241 op_cost(5); 3242 // formats are generated automatically for constants and base registers 3243 format %{ %} 3244 interface(CONST_INTER); 3245%} 3246 3247// Pointer Immediate: 64-bit 3248// From Niagara2 processors on a load should be better than materializing. 3249operand immP_load() %{ 3250 predicate(VM_Version::has_fast_ld() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3))); 3251 match(ConP); 3252 3253 op_cost(5); 3254 // formats are generated automatically for constants and base registers 3255 format %{ %} 3256 interface(CONST_INTER); 3257%} 3258 3259// Pointer Immediate: 64-bit 3260operand immP_no_oop_cheap() %{ 3261 predicate(VM_Version::has_fast_ld() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3)); 3262 match(ConP); 3263 3264 op_cost(5); 3265 // formats are generated automatically for constants and base registers 3266 format %{ %} 3267 interface(CONST_INTER); 3268%} 3269 3270operand immP13() %{ 3271 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3272 match(ConP); 3273 op_cost(0); 3274 3275 format %{ %} 3276 interface(CONST_INTER); 3277%} 3278 3279operand immP0() %{ 3280 predicate(n->get_ptr() == 0); 3281 match(ConP); 3282 op_cost(0); 3283 3284 format %{ %} 3285 interface(CONST_INTER); 3286%} 3287 3288operand immP_poll() %{ 3289 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3290 match(ConP); 3291 3292 // formats are generated automatically for constants and base registers 3293 format %{ %} 3294 interface(CONST_INTER); 3295%} 3296 3297// Pointer Immediate 3298operand immN() 3299%{ 3300 match(ConN); 3301 3302 op_cost(10); 3303 format %{ %} 3304 interface(CONST_INTER); 3305%} 3306 3307operand immNKlass() 3308%{ 3309 match(ConNKlass); 3310 3311 op_cost(10); 3312 format %{ %} 3313 interface(CONST_INTER); 3314%} 3315 3316// NULL Pointer Immediate 3317operand immN0() 3318%{ 3319 predicate(n->get_narrowcon() == 0); 3320 match(ConN); 3321 3322 op_cost(0); 3323 format %{ %} 3324 interface(CONST_INTER); 3325%} 3326 3327operand immL() %{ 3328 match(ConL); 3329 op_cost(40); 3330 // formats are generated automatically for constants and base registers 3331 format %{ %} 3332 interface(CONST_INTER); 3333%} 3334 3335operand immL0() %{ 3336 predicate(n->get_long() == 0L); 3337 match(ConL); 3338 op_cost(0); 3339 // formats are generated automatically for constants and base registers 3340 format %{ %} 3341 interface(CONST_INTER); 3342%} 3343 3344// Integer Immediate: 5-bit 3345operand immL5() %{ 3346 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long())); 3347 match(ConL); 3348 op_cost(0); 3349 format %{ %} 3350 interface(CONST_INTER); 3351%} 3352 3353// Long Immediate: 13-bit 3354operand immL13() %{ 3355 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3356 match(ConL); 3357 op_cost(0); 3358 3359 format %{ %} 3360 interface(CONST_INTER); 3361%} 3362 3363// Long Immediate: 13-bit minus 7 3364operand immL13m7() %{ 3365 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3366 match(ConL); 3367 op_cost(0); 3368 3369 format %{ %} 3370 interface(CONST_INTER); 3371%} 3372 3373// Long Immediate: low 32-bit mask 3374operand immL_32bits() %{ 3375 predicate(n->get_long() == 0xFFFFFFFFL); 3376 match(ConL); 3377 op_cost(0); 3378 3379 format %{ %} 3380 interface(CONST_INTER); 3381%} 3382 3383// Long Immediate: cheap (materialize in <= 3 instructions) 3384operand immL_cheap() %{ 3385 predicate(!VM_Version::has_fast_ld() || MacroAssembler::insts_for_set64(n->get_long()) <= 3); 3386 match(ConL); 3387 op_cost(0); 3388 3389 format %{ %} 3390 interface(CONST_INTER); 3391%} 3392 3393// Long Immediate: expensive (materialize in > 3 instructions) 3394operand immL_expensive() %{ 3395 predicate(VM_Version::has_fast_ld() && MacroAssembler::insts_for_set64(n->get_long()) > 3); 3396 match(ConL); 3397 op_cost(0); 3398 3399 format %{ %} 3400 interface(CONST_INTER); 3401%} 3402 3403// Double Immediate 3404operand immD() %{ 3405 match(ConD); 3406 3407 op_cost(40); 3408 format %{ %} 3409 interface(CONST_INTER); 3410%} 3411 3412// Double Immediate: +0.0d 3413operand immD0() %{ 3414 predicate(jlong_cast(n->getd()) == 0); 3415 match(ConD); 3416 3417 op_cost(0); 3418 format %{ %} 3419 interface(CONST_INTER); 3420%} 3421 3422// Float Immediate 3423operand immF() %{ 3424 match(ConF); 3425 3426 op_cost(20); 3427 format %{ %} 3428 interface(CONST_INTER); 3429%} 3430 3431// Float Immediate: +0.0f 3432operand immF0() %{ 3433 predicate(jint_cast(n->getf()) == 0); 3434 match(ConF); 3435 3436 op_cost(0); 3437 format %{ %} 3438 interface(CONST_INTER); 3439%} 3440 3441// Integer Register Operands 3442// Integer Register 3443operand iRegI() %{ 3444 constraint(ALLOC_IN_RC(int_reg)); 3445 match(RegI); 3446 3447 match(notemp_iRegI); 3448 match(g1RegI); 3449 match(o0RegI); 3450 match(iRegIsafe); 3451 3452 format %{ %} 3453 interface(REG_INTER); 3454%} 3455 3456operand notemp_iRegI() %{ 3457 constraint(ALLOC_IN_RC(notemp_int_reg)); 3458 match(RegI); 3459 3460 match(o0RegI); 3461 3462 format %{ %} 3463 interface(REG_INTER); 3464%} 3465 3466operand o0RegI() %{ 3467 constraint(ALLOC_IN_RC(o0_regI)); 3468 match(iRegI); 3469 3470 format %{ %} 3471 interface(REG_INTER); 3472%} 3473 3474// Pointer Register 3475operand iRegP() %{ 3476 constraint(ALLOC_IN_RC(ptr_reg)); 3477 match(RegP); 3478 3479 match(lock_ptr_RegP); 3480 match(g1RegP); 3481 match(g2RegP); 3482 match(g3RegP); 3483 match(g4RegP); 3484 match(i0RegP); 3485 match(o0RegP); 3486 match(o1RegP); 3487 match(l7RegP); 3488 3489 format %{ %} 3490 interface(REG_INTER); 3491%} 3492 3493operand sp_ptr_RegP() %{ 3494 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3495 match(RegP); 3496 match(iRegP); 3497 3498 format %{ %} 3499 interface(REG_INTER); 3500%} 3501 3502operand lock_ptr_RegP() %{ 3503 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3504 match(RegP); 3505 match(i0RegP); 3506 match(o0RegP); 3507 match(o1RegP); 3508 match(l7RegP); 3509 3510 format %{ %} 3511 interface(REG_INTER); 3512%} 3513 3514operand g1RegP() %{ 3515 constraint(ALLOC_IN_RC(g1_regP)); 3516 match(iRegP); 3517 3518 format %{ %} 3519 interface(REG_INTER); 3520%} 3521 3522operand g2RegP() %{ 3523 constraint(ALLOC_IN_RC(g2_regP)); 3524 match(iRegP); 3525 3526 format %{ %} 3527 interface(REG_INTER); 3528%} 3529 3530operand g3RegP() %{ 3531 constraint(ALLOC_IN_RC(g3_regP)); 3532 match(iRegP); 3533 3534 format %{ %} 3535 interface(REG_INTER); 3536%} 3537 3538operand g1RegI() %{ 3539 constraint(ALLOC_IN_RC(g1_regI)); 3540 match(iRegI); 3541 3542 format %{ %} 3543 interface(REG_INTER); 3544%} 3545 3546operand g3RegI() %{ 3547 constraint(ALLOC_IN_RC(g3_regI)); 3548 match(iRegI); 3549 3550 format %{ %} 3551 interface(REG_INTER); 3552%} 3553 3554operand g4RegI() %{ 3555 constraint(ALLOC_IN_RC(g4_regI)); 3556 match(iRegI); 3557 3558 format %{ %} 3559 interface(REG_INTER); 3560%} 3561 3562operand g4RegP() %{ 3563 constraint(ALLOC_IN_RC(g4_regP)); 3564 match(iRegP); 3565 3566 format %{ %} 3567 interface(REG_INTER); 3568%} 3569 3570operand i0RegP() %{ 3571 constraint(ALLOC_IN_RC(i0_regP)); 3572 match(iRegP); 3573 3574 format %{ %} 3575 interface(REG_INTER); 3576%} 3577 3578operand o0RegP() %{ 3579 constraint(ALLOC_IN_RC(o0_regP)); 3580 match(iRegP); 3581 3582 format %{ %} 3583 interface(REG_INTER); 3584%} 3585 3586operand o1RegP() %{ 3587 constraint(ALLOC_IN_RC(o1_regP)); 3588 match(iRegP); 3589 3590 format %{ %} 3591 interface(REG_INTER); 3592%} 3593 3594operand o2RegP() %{ 3595 constraint(ALLOC_IN_RC(o2_regP)); 3596 match(iRegP); 3597 3598 format %{ %} 3599 interface(REG_INTER); 3600%} 3601 3602operand o7RegP() %{ 3603 constraint(ALLOC_IN_RC(o7_regP)); 3604 match(iRegP); 3605 3606 format %{ %} 3607 interface(REG_INTER); 3608%} 3609 3610operand l7RegP() %{ 3611 constraint(ALLOC_IN_RC(l7_regP)); 3612 match(iRegP); 3613 3614 format %{ %} 3615 interface(REG_INTER); 3616%} 3617 3618operand o7RegI() %{ 3619 constraint(ALLOC_IN_RC(o7_regI)); 3620 match(iRegI); 3621 3622 format %{ %} 3623 interface(REG_INTER); 3624%} 3625 3626operand iRegN() %{ 3627 constraint(ALLOC_IN_RC(int_reg)); 3628 match(RegN); 3629 3630 format %{ %} 3631 interface(REG_INTER); 3632%} 3633 3634// Long Register 3635operand iRegL() %{ 3636 constraint(ALLOC_IN_RC(long_reg)); 3637 match(RegL); 3638 3639 format %{ %} 3640 interface(REG_INTER); 3641%} 3642 3643operand o2RegL() %{ 3644 constraint(ALLOC_IN_RC(o2_regL)); 3645 match(iRegL); 3646 3647 format %{ %} 3648 interface(REG_INTER); 3649%} 3650 3651operand o7RegL() %{ 3652 constraint(ALLOC_IN_RC(o7_regL)); 3653 match(iRegL); 3654 3655 format %{ %} 3656 interface(REG_INTER); 3657%} 3658 3659operand g1RegL() %{ 3660 constraint(ALLOC_IN_RC(g1_regL)); 3661 match(iRegL); 3662 3663 format %{ %} 3664 interface(REG_INTER); 3665%} 3666 3667operand g3RegL() %{ 3668 constraint(ALLOC_IN_RC(g3_regL)); 3669 match(iRegL); 3670 3671 format %{ %} 3672 interface(REG_INTER); 3673%} 3674 3675// Int Register safe 3676// This is 64bit safe 3677operand iRegIsafe() %{ 3678 constraint(ALLOC_IN_RC(long_reg)); 3679 3680 match(iRegI); 3681 3682 format %{ %} 3683 interface(REG_INTER); 3684%} 3685 3686// Condition Code Flag Register 3687operand flagsReg() %{ 3688 constraint(ALLOC_IN_RC(int_flags)); 3689 match(RegFlags); 3690 3691 format %{ "ccr" %} // both ICC and XCC 3692 interface(REG_INTER); 3693%} 3694 3695// Condition Code Register, unsigned comparisons. 3696operand flagsRegU() %{ 3697 constraint(ALLOC_IN_RC(int_flags)); 3698 match(RegFlags); 3699 3700 format %{ "icc_U" %} 3701 interface(REG_INTER); 3702%} 3703 3704// Condition Code Register, pointer comparisons. 3705operand flagsRegP() %{ 3706 constraint(ALLOC_IN_RC(int_flags)); 3707 match(RegFlags); 3708 3709 format %{ "xcc_P" %} 3710 interface(REG_INTER); 3711%} 3712 3713// Condition Code Register, long comparisons. 3714operand flagsRegL() %{ 3715 constraint(ALLOC_IN_RC(int_flags)); 3716 match(RegFlags); 3717 3718 format %{ "xcc_L" %} 3719 interface(REG_INTER); 3720%} 3721 3722// Condition Code Register, unsigned long comparisons. 3723operand flagsRegUL() %{ 3724 constraint(ALLOC_IN_RC(int_flags)); 3725 match(RegFlags); 3726 3727 format %{ "xcc_UL" %} 3728 interface(REG_INTER); 3729%} 3730 3731// Condition Code Register, floating comparisons, unordered same as "less". 3732operand flagsRegF() %{ 3733 constraint(ALLOC_IN_RC(float_flags)); 3734 match(RegFlags); 3735 match(flagsRegF0); 3736 3737 format %{ %} 3738 interface(REG_INTER); 3739%} 3740 3741operand flagsRegF0() %{ 3742 constraint(ALLOC_IN_RC(float_flag0)); 3743 match(RegFlags); 3744 3745 format %{ %} 3746 interface(REG_INTER); 3747%} 3748 3749 3750// Condition Code Flag Register used by long compare 3751operand flagsReg_long_LTGE() %{ 3752 constraint(ALLOC_IN_RC(int_flags)); 3753 match(RegFlags); 3754 format %{ "icc_LTGE" %} 3755 interface(REG_INTER); 3756%} 3757operand flagsReg_long_EQNE() %{ 3758 constraint(ALLOC_IN_RC(int_flags)); 3759 match(RegFlags); 3760 format %{ "icc_EQNE" %} 3761 interface(REG_INTER); 3762%} 3763operand flagsReg_long_LEGT() %{ 3764 constraint(ALLOC_IN_RC(int_flags)); 3765 match(RegFlags); 3766 format %{ "icc_LEGT" %} 3767 interface(REG_INTER); 3768%} 3769 3770 3771operand regD() %{ 3772 constraint(ALLOC_IN_RC(dflt_reg)); 3773 match(RegD); 3774 3775 match(regD_low); 3776 3777 format %{ %} 3778 interface(REG_INTER); 3779%} 3780 3781operand regF() %{ 3782 constraint(ALLOC_IN_RC(sflt_reg)); 3783 match(RegF); 3784 3785 format %{ %} 3786 interface(REG_INTER); 3787%} 3788 3789operand regD_low() %{ 3790 constraint(ALLOC_IN_RC(dflt_low_reg)); 3791 match(regD); 3792 3793 format %{ %} 3794 interface(REG_INTER); 3795%} 3796 3797// Special Registers 3798 3799// Method Register 3800operand inline_cache_regP(iRegP reg) %{ 3801 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 3802 match(reg); 3803 format %{ %} 3804 interface(REG_INTER); 3805%} 3806 3807operand interpreter_method_oop_regP(iRegP reg) %{ 3808 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 3809 match(reg); 3810 format %{ %} 3811 interface(REG_INTER); 3812%} 3813 3814 3815//----------Complex Operands--------------------------------------------------- 3816// Indirect Memory Reference 3817operand indirect(sp_ptr_RegP reg) %{ 3818 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3819 match(reg); 3820 3821 op_cost(100); 3822 format %{ "[$reg]" %} 3823 interface(MEMORY_INTER) %{ 3824 base($reg); 3825 index(0x0); 3826 scale(0x0); 3827 disp(0x0); 3828 %} 3829%} 3830 3831// Indirect with simm13 Offset 3832operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 3833 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3834 match(AddP reg offset); 3835 3836 op_cost(100); 3837 format %{ "[$reg + $offset]" %} 3838 interface(MEMORY_INTER) %{ 3839 base($reg); 3840 index(0x0); 3841 scale(0x0); 3842 disp($offset); 3843 %} 3844%} 3845 3846// Indirect with simm13 Offset minus 7 3847operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 3848 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3849 match(AddP reg offset); 3850 3851 op_cost(100); 3852 format %{ "[$reg + $offset]" %} 3853 interface(MEMORY_INTER) %{ 3854 base($reg); 3855 index(0x0); 3856 scale(0x0); 3857 disp($offset); 3858 %} 3859%} 3860 3861// Note: Intel has a swapped version also, like this: 3862//operand indOffsetX(iRegI reg, immP offset) %{ 3863// constraint(ALLOC_IN_RC(int_reg)); 3864// match(AddP offset reg); 3865// 3866// op_cost(100); 3867// format %{ "[$reg + $offset]" %} 3868// interface(MEMORY_INTER) %{ 3869// base($reg); 3870// index(0x0); 3871// scale(0x0); 3872// disp($offset); 3873// %} 3874//%} 3875//// However, it doesn't make sense for SPARC, since 3876// we have no particularly good way to embed oops in 3877// single instructions. 3878 3879// Indirect with Register Index 3880operand indIndex(iRegP addr, iRegX index) %{ 3881 constraint(ALLOC_IN_RC(ptr_reg)); 3882 match(AddP addr index); 3883 3884 op_cost(100); 3885 format %{ "[$addr + $index]" %} 3886 interface(MEMORY_INTER) %{ 3887 base($addr); 3888 index($index); 3889 scale(0x0); 3890 disp(0x0); 3891 %} 3892%} 3893 3894//----------Special Memory Operands-------------------------------------------- 3895// Stack Slot Operand - This operand is used for loading and storing temporary 3896// values on the stack where a match requires a value to 3897// flow through memory. 3898operand stackSlotI(sRegI reg) %{ 3899 constraint(ALLOC_IN_RC(stack_slots)); 3900 op_cost(100); 3901 //match(RegI); 3902 format %{ "[$reg]" %} 3903 interface(MEMORY_INTER) %{ 3904 base(0xE); // R_SP 3905 index(0x0); 3906 scale(0x0); 3907 disp($reg); // Stack Offset 3908 %} 3909%} 3910 3911operand stackSlotP(sRegP reg) %{ 3912 constraint(ALLOC_IN_RC(stack_slots)); 3913 op_cost(100); 3914 //match(RegP); 3915 format %{ "[$reg]" %} 3916 interface(MEMORY_INTER) %{ 3917 base(0xE); // R_SP 3918 index(0x0); 3919 scale(0x0); 3920 disp($reg); // Stack Offset 3921 %} 3922%} 3923 3924operand stackSlotF(sRegF reg) %{ 3925 constraint(ALLOC_IN_RC(stack_slots)); 3926 op_cost(100); 3927 //match(RegF); 3928 format %{ "[$reg]" %} 3929 interface(MEMORY_INTER) %{ 3930 base(0xE); // R_SP 3931 index(0x0); 3932 scale(0x0); 3933 disp($reg); // Stack Offset 3934 %} 3935%} 3936operand stackSlotD(sRegD reg) %{ 3937 constraint(ALLOC_IN_RC(stack_slots)); 3938 op_cost(100); 3939 //match(RegD); 3940 format %{ "[$reg]" %} 3941 interface(MEMORY_INTER) %{ 3942 base(0xE); // R_SP 3943 index(0x0); 3944 scale(0x0); 3945 disp($reg); // Stack Offset 3946 %} 3947%} 3948operand stackSlotL(sRegL reg) %{ 3949 constraint(ALLOC_IN_RC(stack_slots)); 3950 op_cost(100); 3951 //match(RegL); 3952 format %{ "[$reg]" %} 3953 interface(MEMORY_INTER) %{ 3954 base(0xE); // R_SP 3955 index(0x0); 3956 scale(0x0); 3957 disp($reg); // Stack Offset 3958 %} 3959%} 3960 3961// Operands for expressing Control Flow 3962// NOTE: Label is a predefined operand which should not be redefined in 3963// the AD file. It is generically handled within the ADLC. 3964 3965//----------Conditional Branch Operands---------------------------------------- 3966// Comparison Op - This is the operation of the comparison, and is limited to 3967// the following set of codes: 3968// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 3969// 3970// Other attributes of the comparison, such as unsignedness, are specified 3971// by the comparison instruction that sets a condition code flags register. 3972// That result is represented by a flags operand whose subtype is appropriate 3973// to the unsignedness (etc.) of the comparison. 3974// 3975// Later, the instruction which matches both the Comparison Op (a Bool) and 3976// the flags (produced by the Cmp) specifies the coding of the comparison op 3977// by matching a specific subtype of Bool operand below, such as cmpOpU. 3978 3979operand cmpOp() %{ 3980 match(Bool); 3981 3982 format %{ "" %} 3983 interface(COND_INTER) %{ 3984 equal(0x1); 3985 not_equal(0x9); 3986 less(0x3); 3987 greater_equal(0xB); 3988 less_equal(0x2); 3989 greater(0xA); 3990 overflow(0x7); 3991 no_overflow(0xF); 3992 %} 3993%} 3994 3995// Comparison Op, unsigned 3996operand cmpOpU() %{ 3997 match(Bool); 3998 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 3999 n->as_Bool()->_test._test != BoolTest::no_overflow); 4000 4001 format %{ "u" %} 4002 interface(COND_INTER) %{ 4003 equal(0x1); 4004 not_equal(0x9); 4005 less(0x5); 4006 greater_equal(0xD); 4007 less_equal(0x4); 4008 greater(0xC); 4009 overflow(0x7); 4010 no_overflow(0xF); 4011 %} 4012%} 4013 4014// Comparison Op, pointer (same as unsigned) 4015operand cmpOpP() %{ 4016 match(Bool); 4017 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4018 n->as_Bool()->_test._test != BoolTest::no_overflow); 4019 4020 format %{ "p" %} 4021 interface(COND_INTER) %{ 4022 equal(0x1); 4023 not_equal(0x9); 4024 less(0x5); 4025 greater_equal(0xD); 4026 less_equal(0x4); 4027 greater(0xC); 4028 overflow(0x7); 4029 no_overflow(0xF); 4030 %} 4031%} 4032 4033// Comparison Op, branch-register encoding 4034operand cmpOp_reg() %{ 4035 match(Bool); 4036 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4037 n->as_Bool()->_test._test != BoolTest::no_overflow); 4038 4039 format %{ "" %} 4040 interface(COND_INTER) %{ 4041 equal (0x1); 4042 not_equal (0x5); 4043 less (0x3); 4044 greater_equal(0x7); 4045 less_equal (0x2); 4046 greater (0x6); 4047 overflow(0x7); // not supported 4048 no_overflow(0xF); // not supported 4049 %} 4050%} 4051 4052// Comparison Code, floating, unordered same as less 4053operand cmpOpF() %{ 4054 match(Bool); 4055 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4056 n->as_Bool()->_test._test != BoolTest::no_overflow); 4057 4058 format %{ "fl" %} 4059 interface(COND_INTER) %{ 4060 equal(0x9); 4061 not_equal(0x1); 4062 less(0x3); 4063 greater_equal(0xB); 4064 less_equal(0xE); 4065 greater(0x6); 4066 4067 overflow(0x7); // not supported 4068 no_overflow(0xF); // not supported 4069 %} 4070%} 4071 4072// Used by long compare 4073operand cmpOp_commute() %{ 4074 match(Bool); 4075 predicate(n->as_Bool()->_test._test != BoolTest::overflow && 4076 n->as_Bool()->_test._test != BoolTest::no_overflow); 4077 4078 format %{ "" %} 4079 interface(COND_INTER) %{ 4080 equal(0x1); 4081 not_equal(0x9); 4082 less(0xA); 4083 greater_equal(0x2); 4084 less_equal(0xB); 4085 greater(0x3); 4086 overflow(0x7); 4087 no_overflow(0xF); 4088 %} 4089%} 4090 4091//----------OPERAND CLASSES---------------------------------------------------- 4092// Operand Classes are groups of operands that are used to simplify 4093// instruction definitions by not requiring the AD writer to specify separate 4094// instructions for every form of operand when the instruction accepts 4095// multiple operand types with the same basic encoding and format. The classic 4096// case of this is memory operands. 4097opclass memory( indirect, indOffset13, indIndex ); 4098opclass indIndexMemory( indIndex ); 4099 4100//----------PIPELINE----------------------------------------------------------- 4101pipeline %{ 4102 4103//----------ATTRIBUTES--------------------------------------------------------- 4104attributes %{ 4105 fixed_size_instructions; // Fixed size instructions 4106 branch_has_delay_slot; // Branch has delay slot following 4107 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4108 instruction_unit_size = 4; // An instruction is 4 bytes long 4109 instruction_fetch_unit_size = 16; // The processor fetches one line 4110 instruction_fetch_units = 1; // of 16 bytes 4111 4112 // List of nop instructions 4113 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4114%} 4115 4116//----------RESOURCES---------------------------------------------------------- 4117// Resources are the functional units available to the machine 4118resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4119 4120//----------PIPELINE DESCRIPTION----------------------------------------------- 4121// Pipeline Description specifies the stages in the machine's pipeline 4122 4123pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4124 4125//----------PIPELINE CLASSES--------------------------------------------------- 4126// Pipeline Classes describe the stages in which input and output are 4127// referenced by the hardware pipeline. 4128 4129// Integer ALU reg-reg operation 4130pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4131 single_instruction; 4132 dst : E(write); 4133 src1 : R(read); 4134 src2 : R(read); 4135 IALU : R; 4136%} 4137 4138// Integer ALU reg-reg long operation 4139pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4140 instruction_count(2); 4141 dst : E(write); 4142 src1 : R(read); 4143 src2 : R(read); 4144 IALU : R; 4145 IALU : R; 4146%} 4147 4148// Integer ALU reg-reg long dependent operation 4149pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4150 instruction_count(1); multiple_bundles; 4151 dst : E(write); 4152 src1 : R(read); 4153 src2 : R(read); 4154 cr : E(write); 4155 IALU : R(2); 4156%} 4157 4158// Integer ALU reg-imm operaion 4159pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4160 single_instruction; 4161 dst : E(write); 4162 src1 : R(read); 4163 IALU : R; 4164%} 4165 4166// Integer ALU reg-reg operation with condition code 4167pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4168 single_instruction; 4169 dst : E(write); 4170 cr : E(write); 4171 src1 : R(read); 4172 src2 : R(read); 4173 IALU : R; 4174%} 4175 4176// Integer ALU reg-imm operation with condition code 4177pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4178 single_instruction; 4179 dst : E(write); 4180 cr : E(write); 4181 src1 : R(read); 4182 IALU : R; 4183%} 4184 4185// Integer ALU zero-reg operation 4186pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4187 single_instruction; 4188 dst : E(write); 4189 src2 : R(read); 4190 IALU : R; 4191%} 4192 4193// Integer ALU zero-reg operation with condition code only 4194pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4195 single_instruction; 4196 cr : E(write); 4197 src : R(read); 4198 IALU : R; 4199%} 4200 4201// Integer ALU reg-reg operation with condition code only 4202pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4203 single_instruction; 4204 cr : E(write); 4205 src1 : R(read); 4206 src2 : R(read); 4207 IALU : R; 4208%} 4209 4210// Integer ALU reg-imm operation with condition code only 4211pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4212 single_instruction; 4213 cr : E(write); 4214 src1 : R(read); 4215 IALU : R; 4216%} 4217 4218// Integer ALU reg-reg-zero operation with condition code only 4219pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4220 single_instruction; 4221 cr : E(write); 4222 src1 : R(read); 4223 src2 : R(read); 4224 IALU : R; 4225%} 4226 4227// Integer ALU reg-imm-zero operation with condition code only 4228pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4229 single_instruction; 4230 cr : E(write); 4231 src1 : R(read); 4232 IALU : R; 4233%} 4234 4235// Integer ALU reg-reg operation with condition code, src1 modified 4236pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4237 single_instruction; 4238 cr : E(write); 4239 src1 : E(write); 4240 src1 : R(read); 4241 src2 : R(read); 4242 IALU : R; 4243%} 4244 4245// Integer ALU reg-imm operation with condition code, src1 modified 4246pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4247 single_instruction; 4248 cr : E(write); 4249 src1 : E(write); 4250 src1 : R(read); 4251 IALU : R; 4252%} 4253 4254pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4255 multiple_bundles; 4256 dst : E(write)+4; 4257 cr : E(write); 4258 src1 : R(read); 4259 src2 : R(read); 4260 IALU : R(3); 4261 BR : R(2); 4262%} 4263 4264// Integer ALU operation 4265pipe_class ialu_none(iRegI dst) %{ 4266 single_instruction; 4267 dst : E(write); 4268 IALU : R; 4269%} 4270 4271// Integer ALU reg operation 4272pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4273 single_instruction; may_have_no_code; 4274 dst : E(write); 4275 src : R(read); 4276 IALU : R; 4277%} 4278 4279// Integer ALU reg conditional operation 4280// This instruction has a 1 cycle stall, and cannot execute 4281// in the same cycle as the instruction setting the condition 4282// code. We kludge this by pretending to read the condition code 4283// 1 cycle earlier, and by marking the functional units as busy 4284// for 2 cycles with the result available 1 cycle later than 4285// is really the case. 4286pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4287 single_instruction; 4288 op2_out : C(write); 4289 op1 : R(read); 4290 cr : R(read); // This is really E, with a 1 cycle stall 4291 BR : R(2); 4292 MS : R(2); 4293%} 4294 4295pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4296 instruction_count(1); multiple_bundles; 4297 dst : C(write)+1; 4298 src : R(read)+1; 4299 IALU : R(1); 4300 BR : E(2); 4301 MS : E(2); 4302%} 4303 4304// Integer ALU reg operation 4305pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4306 single_instruction; may_have_no_code; 4307 dst : E(write); 4308 src : R(read); 4309 IALU : R; 4310%} 4311pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4312 single_instruction; may_have_no_code; 4313 dst : E(write); 4314 src : R(read); 4315 IALU : R; 4316%} 4317 4318// Two integer ALU reg operations 4319pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4320 instruction_count(2); 4321 dst : E(write); 4322 src : R(read); 4323 A0 : R; 4324 A1 : R; 4325%} 4326 4327// Two integer ALU reg operations 4328pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4329 instruction_count(2); may_have_no_code; 4330 dst : E(write); 4331 src : R(read); 4332 A0 : R; 4333 A1 : R; 4334%} 4335 4336// Integer ALU imm operation 4337pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4338 single_instruction; 4339 dst : E(write); 4340 IALU : R; 4341%} 4342 4343// Integer ALU reg-reg with carry operation 4344pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4345 single_instruction; 4346 dst : E(write); 4347 src1 : R(read); 4348 src2 : R(read); 4349 IALU : R; 4350%} 4351 4352// Integer ALU cc operation 4353pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4354 single_instruction; 4355 dst : E(write); 4356 cc : R(read); 4357 IALU : R; 4358%} 4359 4360// Integer ALU cc / second IALU operation 4361pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4362 instruction_count(1); multiple_bundles; 4363 dst : E(write)+1; 4364 src : R(read); 4365 IALU : R; 4366%} 4367 4368// Integer ALU cc / second IALU operation 4369pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4370 instruction_count(1); multiple_bundles; 4371 dst : E(write)+1; 4372 p : R(read); 4373 q : R(read); 4374 IALU : R; 4375%} 4376 4377// Integer ALU hi-lo-reg operation 4378pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4379 instruction_count(1); multiple_bundles; 4380 dst : E(write)+1; 4381 IALU : R(2); 4382%} 4383 4384// Float ALU hi-lo-reg operation (with temp) 4385pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4386 instruction_count(1); multiple_bundles; 4387 dst : E(write)+1; 4388 IALU : R(2); 4389%} 4390 4391// Long Constant 4392pipe_class loadConL( iRegL dst, immL src ) %{ 4393 instruction_count(2); multiple_bundles; 4394 dst : E(write)+1; 4395 IALU : R(2); 4396 IALU : R(2); 4397%} 4398 4399// Pointer Constant 4400pipe_class loadConP( iRegP dst, immP src ) %{ 4401 instruction_count(0); multiple_bundles; 4402 fixed_latency(6); 4403%} 4404 4405// Polling Address 4406pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4407 instruction_count(0); multiple_bundles; 4408 fixed_latency(6); 4409%} 4410 4411// Long Constant small 4412pipe_class loadConLlo( iRegL dst, immL src ) %{ 4413 instruction_count(2); 4414 dst : E(write); 4415 IALU : R; 4416 IALU : R; 4417%} 4418 4419// [PHH] This is wrong for 64-bit. See LdImmF/D. 4420pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4421 instruction_count(1); multiple_bundles; 4422 src : R(read); 4423 dst : M(write)+1; 4424 IALU : R; 4425 MS : E; 4426%} 4427 4428// Integer ALU nop operation 4429pipe_class ialu_nop() %{ 4430 single_instruction; 4431 IALU : R; 4432%} 4433 4434// Integer ALU nop operation 4435pipe_class ialu_nop_A0() %{ 4436 single_instruction; 4437 A0 : R; 4438%} 4439 4440// Integer ALU nop operation 4441pipe_class ialu_nop_A1() %{ 4442 single_instruction; 4443 A1 : R; 4444%} 4445 4446// Integer Multiply reg-reg operation 4447pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4448 single_instruction; 4449 dst : E(write); 4450 src1 : R(read); 4451 src2 : R(read); 4452 MS : R(5); 4453%} 4454 4455// Integer Multiply reg-imm operation 4456pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4457 single_instruction; 4458 dst : E(write); 4459 src1 : R(read); 4460 MS : R(5); 4461%} 4462 4463pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4464 single_instruction; 4465 dst : E(write)+4; 4466 src1 : R(read); 4467 src2 : R(read); 4468 MS : R(6); 4469%} 4470 4471pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4472 single_instruction; 4473 dst : E(write)+4; 4474 src1 : R(read); 4475 MS : R(6); 4476%} 4477 4478// Integer Divide reg-reg 4479pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4480 instruction_count(1); multiple_bundles; 4481 dst : E(write); 4482 temp : E(write); 4483 src1 : R(read); 4484 src2 : R(read); 4485 temp : R(read); 4486 MS : R(38); 4487%} 4488 4489// Integer Divide reg-imm 4490pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4491 instruction_count(1); multiple_bundles; 4492 dst : E(write); 4493 temp : E(write); 4494 src1 : R(read); 4495 temp : R(read); 4496 MS : R(38); 4497%} 4498 4499// Long Divide 4500pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4501 dst : E(write)+71; 4502 src1 : R(read); 4503 src2 : R(read)+1; 4504 MS : R(70); 4505%} 4506 4507pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4508 dst : E(write)+71; 4509 src1 : R(read); 4510 MS : R(70); 4511%} 4512 4513// Floating Point Add Float 4514pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4515 single_instruction; 4516 dst : X(write); 4517 src1 : E(read); 4518 src2 : E(read); 4519 FA : R; 4520%} 4521 4522// Floating Point Add Double 4523pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4524 single_instruction; 4525 dst : X(write); 4526 src1 : E(read); 4527 src2 : E(read); 4528 FA : R; 4529%} 4530 4531// Floating Point Conditional Move based on integer flags 4532pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4533 single_instruction; 4534 dst : X(write); 4535 src : E(read); 4536 cr : R(read); 4537 FA : R(2); 4538 BR : R(2); 4539%} 4540 4541// Floating Point Conditional Move based on integer flags 4542pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4543 single_instruction; 4544 dst : X(write); 4545 src : E(read); 4546 cr : R(read); 4547 FA : R(2); 4548 BR : R(2); 4549%} 4550 4551// Floating Point Multiply Float 4552pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4553 single_instruction; 4554 dst : X(write); 4555 src1 : E(read); 4556 src2 : E(read); 4557 FM : R; 4558%} 4559 4560// Floating Point Multiply Double 4561pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4562 single_instruction; 4563 dst : X(write); 4564 src1 : E(read); 4565 src2 : E(read); 4566 FM : R; 4567%} 4568 4569// Floating Point Divide Float 4570pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4571 single_instruction; 4572 dst : X(write); 4573 src1 : E(read); 4574 src2 : E(read); 4575 FM : R; 4576 FDIV : C(14); 4577%} 4578 4579// Floating Point Divide Double 4580pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4581 single_instruction; 4582 dst : X(write); 4583 src1 : E(read); 4584 src2 : E(read); 4585 FM : R; 4586 FDIV : C(17); 4587%} 4588 4589// Fused floating-point multiply-add float. 4590pipe_class fmaF_regx4(regF dst, regF src1, regF src2, regF src3) %{ 4591 single_instruction; 4592 dst : X(write); 4593 src1 : E(read); 4594 src2 : E(read); 4595 src3 : E(read); 4596 FM : R; 4597%} 4598 4599// Fused gloating-point multiply-add double. 4600pipe_class fmaD_regx4(regD dst, regD src1, regD src2, regD src3) %{ 4601 single_instruction; 4602 dst : X(write); 4603 src1 : E(read); 4604 src2 : E(read); 4605 src3 : E(read); 4606 FM : R; 4607%} 4608 4609// Floating Point Move/Negate/Abs Float 4610pipe_class faddF_reg(regF dst, regF src) %{ 4611 single_instruction; 4612 dst : W(write); 4613 src : E(read); 4614 FA : R(1); 4615%} 4616 4617// Floating Point Move/Negate/Abs Double 4618pipe_class faddD_reg(regD dst, regD src) %{ 4619 single_instruction; 4620 dst : W(write); 4621 src : E(read); 4622 FA : R; 4623%} 4624 4625// Floating Point Convert F->D 4626pipe_class fcvtF2D(regD dst, regF src) %{ 4627 single_instruction; 4628 dst : X(write); 4629 src : E(read); 4630 FA : R; 4631%} 4632 4633// Floating Point Convert I->D 4634pipe_class fcvtI2D(regD dst, regF src) %{ 4635 single_instruction; 4636 dst : X(write); 4637 src : E(read); 4638 FA : R; 4639%} 4640 4641// Floating Point Convert LHi->D 4642pipe_class fcvtLHi2D(regD dst, regD src) %{ 4643 single_instruction; 4644 dst : X(write); 4645 src : E(read); 4646 FA : R; 4647%} 4648 4649// Floating Point Convert L->D 4650pipe_class fcvtL2D(regD dst, regF src) %{ 4651 single_instruction; 4652 dst : X(write); 4653 src : E(read); 4654 FA : R; 4655%} 4656 4657// Floating Point Convert L->F 4658pipe_class fcvtL2F(regD dst, regF src) %{ 4659 single_instruction; 4660 dst : X(write); 4661 src : E(read); 4662 FA : R; 4663%} 4664 4665// Floating Point Convert D->F 4666pipe_class fcvtD2F(regD dst, regF src) %{ 4667 single_instruction; 4668 dst : X(write); 4669 src : E(read); 4670 FA : R; 4671%} 4672 4673// Floating Point Convert I->L 4674pipe_class fcvtI2L(regD dst, regF src) %{ 4675 single_instruction; 4676 dst : X(write); 4677 src : E(read); 4678 FA : R; 4679%} 4680 4681// Floating Point Convert D->F 4682pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4683 instruction_count(1); multiple_bundles; 4684 dst : X(write)+6; 4685 src : E(read); 4686 FA : R; 4687%} 4688 4689// Floating Point Convert D->L 4690pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4691 instruction_count(1); multiple_bundles; 4692 dst : X(write)+6; 4693 src : E(read); 4694 FA : R; 4695%} 4696 4697// Floating Point Convert F->I 4698pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4699 instruction_count(1); multiple_bundles; 4700 dst : X(write)+6; 4701 src : E(read); 4702 FA : R; 4703%} 4704 4705// Floating Point Convert F->L 4706pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4707 instruction_count(1); multiple_bundles; 4708 dst : X(write)+6; 4709 src : E(read); 4710 FA : R; 4711%} 4712 4713// Floating Point Convert I->F 4714pipe_class fcvtI2F(regF dst, regF src) %{ 4715 single_instruction; 4716 dst : X(write); 4717 src : E(read); 4718 FA : R; 4719%} 4720 4721// Floating Point Compare 4722pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4723 single_instruction; 4724 cr : X(write); 4725 src1 : E(read); 4726 src2 : E(read); 4727 FA : R; 4728%} 4729 4730// Floating Point Compare 4731pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4732 single_instruction; 4733 cr : X(write); 4734 src1 : E(read); 4735 src2 : E(read); 4736 FA : R; 4737%} 4738 4739// Floating Add Nop 4740pipe_class fadd_nop() %{ 4741 single_instruction; 4742 FA : R; 4743%} 4744 4745// Integer Store to Memory 4746pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4747 single_instruction; 4748 mem : R(read); 4749 src : C(read); 4750 MS : R; 4751%} 4752 4753// Integer Store to Memory 4754pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4755 single_instruction; 4756 mem : R(read); 4757 src : C(read); 4758 MS : R; 4759%} 4760 4761// Integer Store Zero to Memory 4762pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4763 single_instruction; 4764 mem : R(read); 4765 MS : R; 4766%} 4767 4768// Special Stack Slot Store 4769pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4770 single_instruction; 4771 stkSlot : R(read); 4772 src : C(read); 4773 MS : R; 4774%} 4775 4776// Special Stack Slot Store 4777pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4778 instruction_count(2); multiple_bundles; 4779 stkSlot : R(read); 4780 src : C(read); 4781 MS : R(2); 4782%} 4783 4784// Float Store 4785pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4786 single_instruction; 4787 mem : R(read); 4788 src : C(read); 4789 MS : R; 4790%} 4791 4792// Float Store 4793pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4794 single_instruction; 4795 mem : R(read); 4796 MS : R; 4797%} 4798 4799// Double Store 4800pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4801 instruction_count(1); 4802 mem : R(read); 4803 src : C(read); 4804 MS : R; 4805%} 4806 4807// Double Store 4808pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4809 single_instruction; 4810 mem : R(read); 4811 MS : R; 4812%} 4813 4814// Special Stack Slot Float Store 4815pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4816 single_instruction; 4817 stkSlot : R(read); 4818 src : C(read); 4819 MS : R; 4820%} 4821 4822// Special Stack Slot Double Store 4823pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4824 single_instruction; 4825 stkSlot : R(read); 4826 src : C(read); 4827 MS : R; 4828%} 4829 4830// Integer Load (when sign bit propagation not needed) 4831pipe_class iload_mem(iRegI dst, memory mem) %{ 4832 single_instruction; 4833 mem : R(read); 4834 dst : C(write); 4835 MS : R; 4836%} 4837 4838// Integer Load from stack operand 4839pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 4840 single_instruction; 4841 mem : R(read); 4842 dst : C(write); 4843 MS : R; 4844%} 4845 4846// Integer Load (when sign bit propagation or masking is needed) 4847pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 4848 single_instruction; 4849 mem : R(read); 4850 dst : M(write); 4851 MS : R; 4852%} 4853 4854// Float Load 4855pipe_class floadF_mem(regF dst, memory mem) %{ 4856 single_instruction; 4857 mem : R(read); 4858 dst : M(write); 4859 MS : R; 4860%} 4861 4862// Float Load 4863pipe_class floadD_mem(regD dst, memory mem) %{ 4864 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 4865 mem : R(read); 4866 dst : M(write); 4867 MS : R; 4868%} 4869 4870// Float Load 4871pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 4872 single_instruction; 4873 stkSlot : R(read); 4874 dst : M(write); 4875 MS : R; 4876%} 4877 4878// Float Load 4879pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 4880 single_instruction; 4881 stkSlot : R(read); 4882 dst : M(write); 4883 MS : R; 4884%} 4885 4886// Memory Nop 4887pipe_class mem_nop() %{ 4888 single_instruction; 4889 MS : R; 4890%} 4891 4892pipe_class sethi(iRegP dst, immI src) %{ 4893 single_instruction; 4894 dst : E(write); 4895 IALU : R; 4896%} 4897 4898pipe_class loadPollP(iRegP poll) %{ 4899 single_instruction; 4900 poll : R(read); 4901 MS : R; 4902%} 4903 4904pipe_class br(Universe br, label labl) %{ 4905 single_instruction_with_delay_slot; 4906 BR : R; 4907%} 4908 4909pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 4910 single_instruction_with_delay_slot; 4911 cr : E(read); 4912 BR : R; 4913%} 4914 4915pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 4916 single_instruction_with_delay_slot; 4917 op1 : E(read); 4918 BR : R; 4919 MS : R; 4920%} 4921 4922// Compare and branch 4923pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{ 4924 instruction_count(2); has_delay_slot; 4925 cr : E(write); 4926 src1 : R(read); 4927 src2 : R(read); 4928 IALU : R; 4929 BR : R; 4930%} 4931 4932// Compare and branch 4933pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{ 4934 instruction_count(2); has_delay_slot; 4935 cr : E(write); 4936 src1 : R(read); 4937 IALU : R; 4938 BR : R; 4939%} 4940 4941// Compare and branch using cbcond 4942pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{ 4943 single_instruction; 4944 src1 : E(read); 4945 src2 : E(read); 4946 IALU : R; 4947 BR : R; 4948%} 4949 4950// Compare and branch using cbcond 4951pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{ 4952 single_instruction; 4953 src1 : E(read); 4954 IALU : R; 4955 BR : R; 4956%} 4957 4958pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 4959 single_instruction_with_delay_slot; 4960 cr : E(read); 4961 BR : R; 4962%} 4963 4964pipe_class br_nop() %{ 4965 single_instruction; 4966 BR : R; 4967%} 4968 4969pipe_class simple_call(method meth) %{ 4970 instruction_count(2); multiple_bundles; force_serialization; 4971 fixed_latency(100); 4972 BR : R(1); 4973 MS : R(1); 4974 A0 : R(1); 4975%} 4976 4977pipe_class compiled_call(method meth) %{ 4978 instruction_count(1); multiple_bundles; force_serialization; 4979 fixed_latency(100); 4980 MS : R(1); 4981%} 4982 4983pipe_class call(method meth) %{ 4984 instruction_count(0); multiple_bundles; force_serialization; 4985 fixed_latency(100); 4986%} 4987 4988pipe_class tail_call(Universe ignore, label labl) %{ 4989 single_instruction; has_delay_slot; 4990 fixed_latency(100); 4991 BR : R(1); 4992 MS : R(1); 4993%} 4994 4995pipe_class ret(Universe ignore) %{ 4996 single_instruction; has_delay_slot; 4997 BR : R(1); 4998 MS : R(1); 4999%} 5000 5001pipe_class ret_poll(g3RegP poll) %{ 5002 instruction_count(3); has_delay_slot; 5003 poll : E(read); 5004 MS : R; 5005%} 5006 5007// The real do-nothing guy 5008pipe_class empty( ) %{ 5009 instruction_count(0); 5010%} 5011 5012pipe_class long_memory_op() %{ 5013 instruction_count(0); multiple_bundles; force_serialization; 5014 fixed_latency(25); 5015 MS : R(1); 5016%} 5017 5018// Check-cast 5019pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5020 array : R(read); 5021 match : R(read); 5022 IALU : R(2); 5023 BR : R(2); 5024 MS : R; 5025%} 5026 5027// Convert FPU flags into +1,0,-1 5028pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5029 src1 : E(read); 5030 src2 : E(read); 5031 dst : E(write); 5032 FA : R; 5033 MS : R(2); 5034 BR : R(2); 5035%} 5036 5037// Compare for p < q, and conditionally add y 5038pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5039 p : E(read); 5040 q : E(read); 5041 y : E(read); 5042 IALU : R(3) 5043%} 5044 5045// Perform a compare, then move conditionally in a branch delay slot. 5046pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5047 src2 : E(read); 5048 srcdst : E(read); 5049 IALU : R; 5050 BR : R; 5051%} 5052 5053// Define the class for the Nop node 5054define %{ 5055 MachNop = ialu_nop; 5056%} 5057 5058%} 5059 5060//----------INSTRUCTIONS------------------------------------------------------- 5061 5062//------------Special Stack Slot instructions - no match rules----------------- 5063instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5064 // No match rule to avoid chain rule match. 5065 effect(DEF dst, USE src); 5066 ins_cost(MEMORY_REF_COST); 5067 format %{ "LDF $src,$dst\t! stkI to regF" %} 5068 opcode(Assembler::ldf_op3); 5069 ins_encode(simple_form3_mem_reg(src, dst)); 5070 ins_pipe(floadF_stk); 5071%} 5072 5073instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5074 // No match rule to avoid chain rule match. 5075 effect(DEF dst, USE src); 5076 ins_cost(MEMORY_REF_COST); 5077 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5078 opcode(Assembler::lddf_op3); 5079 ins_encode(simple_form3_mem_reg(src, dst)); 5080 ins_pipe(floadD_stk); 5081%} 5082 5083instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5084 // No match rule to avoid chain rule match. 5085 effect(DEF dst, USE src); 5086 ins_cost(MEMORY_REF_COST); 5087 format %{ "STF $src,$dst\t! regF to stkI" %} 5088 opcode(Assembler::stf_op3); 5089 ins_encode(simple_form3_mem_reg(dst, src)); 5090 ins_pipe(fstoreF_stk_reg); 5091%} 5092 5093instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5094 // No match rule to avoid chain rule match. 5095 effect(DEF dst, USE src); 5096 ins_cost(MEMORY_REF_COST); 5097 format %{ "STDF $src,$dst\t! regD to stkL" %} 5098 opcode(Assembler::stdf_op3); 5099 ins_encode(simple_form3_mem_reg(dst, src)); 5100 ins_pipe(fstoreD_stk_reg); 5101%} 5102 5103instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5104 effect(DEF dst, USE src); 5105 ins_cost(MEMORY_REF_COST*2); 5106 format %{ "STW $src,$dst.hi\t! long\n\t" 5107 "STW R_G0,$dst.lo" %} 5108 opcode(Assembler::stw_op3); 5109 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5110 ins_pipe(lstoreI_stk_reg); 5111%} 5112 5113instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5114 // No match rule to avoid chain rule match. 5115 effect(DEF dst, USE src); 5116 ins_cost(MEMORY_REF_COST); 5117 format %{ "STX $src,$dst\t! regL to stkD" %} 5118 opcode(Assembler::stx_op3); 5119 ins_encode(simple_form3_mem_reg( dst, src ) ); 5120 ins_pipe(istore_stk_reg); 5121%} 5122 5123//---------- Chain stack slots between similar types -------- 5124 5125// Load integer from stack slot 5126instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5127 match(Set dst src); 5128 ins_cost(MEMORY_REF_COST); 5129 5130 format %{ "LDUW $src,$dst\t!stk" %} 5131 opcode(Assembler::lduw_op3); 5132 ins_encode(simple_form3_mem_reg( src, dst ) ); 5133 ins_pipe(iload_mem); 5134%} 5135 5136// Store integer to stack slot 5137instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5138 match(Set dst src); 5139 ins_cost(MEMORY_REF_COST); 5140 5141 format %{ "STW $src,$dst\t!stk" %} 5142 opcode(Assembler::stw_op3); 5143 ins_encode(simple_form3_mem_reg( dst, src ) ); 5144 ins_pipe(istore_mem_reg); 5145%} 5146 5147// Load long from stack slot 5148instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5149 match(Set dst src); 5150 5151 ins_cost(MEMORY_REF_COST); 5152 format %{ "LDX $src,$dst\t! long" %} 5153 opcode(Assembler::ldx_op3); 5154 ins_encode(simple_form3_mem_reg( src, dst ) ); 5155 ins_pipe(iload_mem); 5156%} 5157 5158// Store long to stack slot 5159instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5160 match(Set dst src); 5161 5162 ins_cost(MEMORY_REF_COST); 5163 format %{ "STX $src,$dst\t! long" %} 5164 opcode(Assembler::stx_op3); 5165 ins_encode(simple_form3_mem_reg( dst, src ) ); 5166 ins_pipe(istore_mem_reg); 5167%} 5168 5169// Load pointer from stack slot, 64-bit encoding 5170instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5171 match(Set dst src); 5172 ins_cost(MEMORY_REF_COST); 5173 format %{ "LDX $src,$dst\t!ptr" %} 5174 opcode(Assembler::ldx_op3); 5175 ins_encode(simple_form3_mem_reg( src, dst ) ); 5176 ins_pipe(iload_mem); 5177%} 5178 5179// Store pointer to stack slot 5180instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5181 match(Set dst src); 5182 ins_cost(MEMORY_REF_COST); 5183 format %{ "STX $src,$dst\t!ptr" %} 5184 opcode(Assembler::stx_op3); 5185 ins_encode(simple_form3_mem_reg( dst, src ) ); 5186 ins_pipe(istore_mem_reg); 5187%} 5188 5189//------------Special Nop instructions for bundling - no match rules----------- 5190// Nop using the A0 functional unit 5191instruct Nop_A0() %{ 5192 ins_cost(0); 5193 5194 format %{ "NOP ! Alu Pipeline" %} 5195 opcode(Assembler::or_op3, Assembler::arith_op); 5196 ins_encode( form2_nop() ); 5197 ins_pipe(ialu_nop_A0); 5198%} 5199 5200// Nop using the A1 functional unit 5201instruct Nop_A1( ) %{ 5202 ins_cost(0); 5203 5204 format %{ "NOP ! Alu Pipeline" %} 5205 opcode(Assembler::or_op3, Assembler::arith_op); 5206 ins_encode( form2_nop() ); 5207 ins_pipe(ialu_nop_A1); 5208%} 5209 5210// Nop using the memory functional unit 5211instruct Nop_MS( ) %{ 5212 ins_cost(0); 5213 5214 format %{ "NOP ! Memory Pipeline" %} 5215 ins_encode( emit_mem_nop ); 5216 ins_pipe(mem_nop); 5217%} 5218 5219// Nop using the floating add functional unit 5220instruct Nop_FA( ) %{ 5221 ins_cost(0); 5222 5223 format %{ "NOP ! Floating Add Pipeline" %} 5224 ins_encode( emit_fadd_nop ); 5225 ins_pipe(fadd_nop); 5226%} 5227 5228// Nop using the branch functional unit 5229instruct Nop_BR( ) %{ 5230 ins_cost(0); 5231 5232 format %{ "NOP ! Branch Pipeline" %} 5233 ins_encode( emit_br_nop ); 5234 ins_pipe(br_nop); 5235%} 5236 5237//----------Load/Store/Move Instructions--------------------------------------- 5238//----------Load Instructions-------------------------------------------------- 5239// Load Byte (8bit signed) 5240instruct loadB(iRegI dst, memory mem) %{ 5241 match(Set dst (LoadB mem)); 5242 ins_cost(MEMORY_REF_COST); 5243 5244 size(4); 5245 format %{ "LDSB $mem,$dst\t! byte" %} 5246 ins_encode %{ 5247 __ ldsb($mem$$Address, $dst$$Register); 5248 %} 5249 ins_pipe(iload_mask_mem); 5250%} 5251 5252// Load Byte (8bit signed) into a Long Register 5253instruct loadB2L(iRegL dst, memory mem) %{ 5254 match(Set dst (ConvI2L (LoadB mem))); 5255 ins_cost(MEMORY_REF_COST); 5256 5257 size(4); 5258 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5259 ins_encode %{ 5260 __ ldsb($mem$$Address, $dst$$Register); 5261 %} 5262 ins_pipe(iload_mask_mem); 5263%} 5264 5265// Load Unsigned Byte (8bit UNsigned) into an int reg 5266instruct loadUB(iRegI dst, memory mem) %{ 5267 match(Set dst (LoadUB mem)); 5268 ins_cost(MEMORY_REF_COST); 5269 5270 size(4); 5271 format %{ "LDUB $mem,$dst\t! ubyte" %} 5272 ins_encode %{ 5273 __ ldub($mem$$Address, $dst$$Register); 5274 %} 5275 ins_pipe(iload_mem); 5276%} 5277 5278// Load Unsigned Byte (8bit UNsigned) into a Long Register 5279instruct loadUB2L(iRegL dst, memory mem) %{ 5280 match(Set dst (ConvI2L (LoadUB mem))); 5281 ins_cost(MEMORY_REF_COST); 5282 5283 size(4); 5284 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5285 ins_encode %{ 5286 __ ldub($mem$$Address, $dst$$Register); 5287 %} 5288 ins_pipe(iload_mem); 5289%} 5290 5291// Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register 5292instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{ 5293 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5294 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5295 5296 size(2*4); 5297 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t" 5298 "AND $dst,right_n_bits($mask, 8),$dst" %} 5299 ins_encode %{ 5300 __ ldub($mem$$Address, $dst$$Register); 5301 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register); 5302 %} 5303 ins_pipe(iload_mem); 5304%} 5305 5306// Load Short (16bit signed) 5307instruct loadS(iRegI dst, memory mem) %{ 5308 match(Set dst (LoadS mem)); 5309 ins_cost(MEMORY_REF_COST); 5310 5311 size(4); 5312 format %{ "LDSH $mem,$dst\t! short" %} 5313 ins_encode %{ 5314 __ ldsh($mem$$Address, $dst$$Register); 5315 %} 5316 ins_pipe(iload_mask_mem); 5317%} 5318 5319// Load Short (16 bit signed) to Byte (8 bit signed) 5320instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5321 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5322 ins_cost(MEMORY_REF_COST); 5323 5324 size(4); 5325 5326 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5327 ins_encode %{ 5328 __ ldsb($mem$$Address, $dst$$Register, 1); 5329 %} 5330 ins_pipe(iload_mask_mem); 5331%} 5332 5333// Load Short (16bit signed) into a Long Register 5334instruct loadS2L(iRegL dst, memory mem) %{ 5335 match(Set dst (ConvI2L (LoadS mem))); 5336 ins_cost(MEMORY_REF_COST); 5337 5338 size(4); 5339 format %{ "LDSH $mem,$dst\t! short -> long" %} 5340 ins_encode %{ 5341 __ ldsh($mem$$Address, $dst$$Register); 5342 %} 5343 ins_pipe(iload_mask_mem); 5344%} 5345 5346// Load Unsigned Short/Char (16bit UNsigned) 5347instruct loadUS(iRegI dst, memory mem) %{ 5348 match(Set dst (LoadUS mem)); 5349 ins_cost(MEMORY_REF_COST); 5350 5351 size(4); 5352 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5353 ins_encode %{ 5354 __ lduh($mem$$Address, $dst$$Register); 5355 %} 5356 ins_pipe(iload_mem); 5357%} 5358 5359// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5360instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5361 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5362 ins_cost(MEMORY_REF_COST); 5363 5364 size(4); 5365 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5366 ins_encode %{ 5367 __ ldsb($mem$$Address, $dst$$Register, 1); 5368 %} 5369 ins_pipe(iload_mask_mem); 5370%} 5371 5372// Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5373instruct loadUS2L(iRegL dst, memory mem) %{ 5374 match(Set dst (ConvI2L (LoadUS mem))); 5375 ins_cost(MEMORY_REF_COST); 5376 5377 size(4); 5378 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5379 ins_encode %{ 5380 __ lduh($mem$$Address, $dst$$Register); 5381 %} 5382 ins_pipe(iload_mem); 5383%} 5384 5385// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5386instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5387 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5388 ins_cost(MEMORY_REF_COST); 5389 5390 size(4); 5391 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5392 ins_encode %{ 5393 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5394 %} 5395 ins_pipe(iload_mem); 5396%} 5397 5398// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5399instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5400 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5401 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5402 5403 size(2*4); 5404 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5405 "AND $dst,$mask,$dst" %} 5406 ins_encode %{ 5407 Register Rdst = $dst$$Register; 5408 __ lduh($mem$$Address, Rdst); 5409 __ and3(Rdst, $mask$$constant, Rdst); 5410 %} 5411 ins_pipe(iload_mem); 5412%} 5413 5414// Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register 5415instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5416 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5417 effect(TEMP dst, TEMP tmp); 5418 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5419 5420 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t" 5421 "SET right_n_bits($mask, 16),$tmp\n\t" 5422 "AND $dst,$tmp,$dst" %} 5423 ins_encode %{ 5424 Register Rdst = $dst$$Register; 5425 Register Rtmp = $tmp$$Register; 5426 __ lduh($mem$$Address, Rdst); 5427 __ set($mask$$constant & right_n_bits(16), Rtmp); 5428 __ and3(Rdst, Rtmp, Rdst); 5429 %} 5430 ins_pipe(iload_mem); 5431%} 5432 5433// Load Integer 5434instruct loadI(iRegI dst, memory mem) %{ 5435 match(Set dst (LoadI mem)); 5436 ins_cost(MEMORY_REF_COST); 5437 5438 size(4); 5439 format %{ "LDUW $mem,$dst\t! int" %} 5440 ins_encode %{ 5441 __ lduw($mem$$Address, $dst$$Register); 5442 %} 5443 ins_pipe(iload_mem); 5444%} 5445 5446// Load Integer to Byte (8 bit signed) 5447instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5448 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5449 ins_cost(MEMORY_REF_COST); 5450 5451 size(4); 5452 5453 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5454 ins_encode %{ 5455 __ ldsb($mem$$Address, $dst$$Register, 3); 5456 %} 5457 ins_pipe(iload_mask_mem); 5458%} 5459 5460// Load Integer to Unsigned Byte (8 bit UNsigned) 5461instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5462 match(Set dst (AndI (LoadI mem) mask)); 5463 ins_cost(MEMORY_REF_COST); 5464 5465 size(4); 5466 5467 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5468 ins_encode %{ 5469 __ ldub($mem$$Address, $dst$$Register, 3); 5470 %} 5471 ins_pipe(iload_mask_mem); 5472%} 5473 5474// Load Integer to Short (16 bit signed) 5475instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5476 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5477 ins_cost(MEMORY_REF_COST); 5478 5479 size(4); 5480 5481 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5482 ins_encode %{ 5483 __ ldsh($mem$$Address, $dst$$Register, 2); 5484 %} 5485 ins_pipe(iload_mask_mem); 5486%} 5487 5488// Load Integer to Unsigned Short (16 bit UNsigned) 5489instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5490 match(Set dst (AndI (LoadI mem) mask)); 5491 ins_cost(MEMORY_REF_COST); 5492 5493 size(4); 5494 5495 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5496 ins_encode %{ 5497 __ lduh($mem$$Address, $dst$$Register, 2); 5498 %} 5499 ins_pipe(iload_mask_mem); 5500%} 5501 5502// Load Integer into a Long Register 5503instruct loadI2L(iRegL dst, memory mem) %{ 5504 match(Set dst (ConvI2L (LoadI mem))); 5505 ins_cost(MEMORY_REF_COST); 5506 5507 size(4); 5508 format %{ "LDSW $mem,$dst\t! int -> long" %} 5509 ins_encode %{ 5510 __ ldsw($mem$$Address, $dst$$Register); 5511 %} 5512 ins_pipe(iload_mask_mem); 5513%} 5514 5515// Load Integer with mask 0xFF into a Long Register 5516instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5517 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5518 ins_cost(MEMORY_REF_COST); 5519 5520 size(4); 5521 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5522 ins_encode %{ 5523 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5524 %} 5525 ins_pipe(iload_mem); 5526%} 5527 5528// Load Integer with mask 0xFFFF into a Long Register 5529instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5530 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5531 ins_cost(MEMORY_REF_COST); 5532 5533 size(4); 5534 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5535 ins_encode %{ 5536 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5537 %} 5538 ins_pipe(iload_mem); 5539%} 5540 5541// Load Integer with a 12-bit mask into a Long Register 5542instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{ 5543 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5544 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5545 5546 size(2*4); 5547 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t" 5548 "AND $dst,$mask,$dst" %} 5549 ins_encode %{ 5550 Register Rdst = $dst$$Register; 5551 __ lduw($mem$$Address, Rdst); 5552 __ and3(Rdst, $mask$$constant, Rdst); 5553 %} 5554 ins_pipe(iload_mem); 5555%} 5556 5557// Load Integer with a 31-bit mask into a Long Register 5558instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{ 5559 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5560 effect(TEMP dst, TEMP tmp); 5561 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5562 5563 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t" 5564 "SET $mask,$tmp\n\t" 5565 "AND $dst,$tmp,$dst" %} 5566 ins_encode %{ 5567 Register Rdst = $dst$$Register; 5568 Register Rtmp = $tmp$$Register; 5569 __ lduw($mem$$Address, Rdst); 5570 __ set($mask$$constant, Rtmp); 5571 __ and3(Rdst, Rtmp, Rdst); 5572 %} 5573 ins_pipe(iload_mem); 5574%} 5575 5576// Load Unsigned Integer into a Long Register 5577instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{ 5578 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5579 ins_cost(MEMORY_REF_COST); 5580 5581 size(4); 5582 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5583 ins_encode %{ 5584 __ lduw($mem$$Address, $dst$$Register); 5585 %} 5586 ins_pipe(iload_mem); 5587%} 5588 5589// Load Long - aligned 5590instruct loadL(iRegL dst, memory mem ) %{ 5591 match(Set dst (LoadL mem)); 5592 ins_cost(MEMORY_REF_COST); 5593 5594 size(4); 5595 format %{ "LDX $mem,$dst\t! long" %} 5596 ins_encode %{ 5597 __ ldx($mem$$Address, $dst$$Register); 5598 %} 5599 ins_pipe(iload_mem); 5600%} 5601 5602// Load Long - UNaligned 5603instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5604 match(Set dst (LoadL_unaligned mem)); 5605 effect(KILL tmp); 5606 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5607 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5608 "\tLDUW $mem ,$dst\n" 5609 "\tSLLX #32, $dst, $dst\n" 5610 "\tOR $dst, R_O7, $dst" %} 5611 opcode(Assembler::lduw_op3); 5612 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5613 ins_pipe(iload_mem); 5614%} 5615 5616// Load Range 5617instruct loadRange(iRegI dst, memory mem) %{ 5618 match(Set dst (LoadRange mem)); 5619 ins_cost(MEMORY_REF_COST); 5620 5621 format %{ "LDUW $mem,$dst\t! range" %} 5622 opcode(Assembler::lduw_op3); 5623 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5624 ins_pipe(iload_mem); 5625%} 5626 5627// Load Integer into %f register (for fitos/fitod) 5628instruct loadI_freg(regF dst, memory mem) %{ 5629 match(Set dst (LoadI mem)); 5630 ins_cost(MEMORY_REF_COST); 5631 5632 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5633 opcode(Assembler::ldf_op3); 5634 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5635 ins_pipe(floadF_mem); 5636%} 5637 5638// Load Pointer 5639instruct loadP(iRegP dst, memory mem) %{ 5640 match(Set dst (LoadP mem)); 5641 ins_cost(MEMORY_REF_COST); 5642 size(4); 5643 5644 format %{ "LDX $mem,$dst\t! ptr" %} 5645 ins_encode %{ 5646 __ ldx($mem$$Address, $dst$$Register); 5647 %} 5648 ins_pipe(iload_mem); 5649%} 5650 5651// Load Compressed Pointer 5652instruct loadN(iRegN dst, memory mem) %{ 5653 match(Set dst (LoadN mem)); 5654 ins_cost(MEMORY_REF_COST); 5655 size(4); 5656 5657 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5658 ins_encode %{ 5659 __ lduw($mem$$Address, $dst$$Register); 5660 %} 5661 ins_pipe(iload_mem); 5662%} 5663 5664// Load Klass Pointer 5665instruct loadKlass(iRegP dst, memory mem) %{ 5666 match(Set dst (LoadKlass mem)); 5667 ins_cost(MEMORY_REF_COST); 5668 size(4); 5669 5670 format %{ "LDX $mem,$dst\t! klass ptr" %} 5671 ins_encode %{ 5672 __ ldx($mem$$Address, $dst$$Register); 5673 %} 5674 ins_pipe(iload_mem); 5675%} 5676 5677// Load narrow Klass Pointer 5678instruct loadNKlass(iRegN dst, memory mem) %{ 5679 match(Set dst (LoadNKlass mem)); 5680 ins_cost(MEMORY_REF_COST); 5681 size(4); 5682 5683 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5684 ins_encode %{ 5685 __ lduw($mem$$Address, $dst$$Register); 5686 %} 5687 ins_pipe(iload_mem); 5688%} 5689 5690// Load Double 5691instruct loadD(regD dst, memory mem) %{ 5692 match(Set dst (LoadD mem)); 5693 ins_cost(MEMORY_REF_COST); 5694 5695 format %{ "LDDF $mem,$dst" %} 5696 opcode(Assembler::lddf_op3); 5697 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5698 ins_pipe(floadD_mem); 5699%} 5700 5701// Load Double - UNaligned 5702instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5703 match(Set dst (LoadD_unaligned mem)); 5704 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5705 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5706 "\tLDF $mem+4,$dst.lo\t!" %} 5707 opcode(Assembler::ldf_op3); 5708 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5709 ins_pipe(iload_mem); 5710%} 5711 5712// Load Float 5713instruct loadF(regF dst, memory mem) %{ 5714 match(Set dst (LoadF mem)); 5715 ins_cost(MEMORY_REF_COST); 5716 5717 format %{ "LDF $mem,$dst" %} 5718 opcode(Assembler::ldf_op3); 5719 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5720 ins_pipe(floadF_mem); 5721%} 5722 5723// Load Constant 5724instruct loadConI( iRegI dst, immI src ) %{ 5725 match(Set dst src); 5726 ins_cost(DEFAULT_COST * 3/2); 5727 format %{ "SET $src,$dst" %} 5728 ins_encode( Set32(src, dst) ); 5729 ins_pipe(ialu_hi_lo_reg); 5730%} 5731 5732instruct loadConI13( iRegI dst, immI13 src ) %{ 5733 match(Set dst src); 5734 5735 size(4); 5736 format %{ "MOV $src,$dst" %} 5737 ins_encode( Set13( src, dst ) ); 5738 ins_pipe(ialu_imm); 5739%} 5740 5741instruct loadConP_set(iRegP dst, immP_set con) %{ 5742 match(Set dst con); 5743 ins_cost(DEFAULT_COST * 3/2); 5744 format %{ "SET $con,$dst\t! ptr" %} 5745 ins_encode %{ 5746 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc(); 5747 intptr_t val = $con$$constant; 5748 if (constant_reloc == relocInfo::oop_type) { 5749 __ set_oop_constant((jobject) val, $dst$$Register); 5750 } else if (constant_reloc == relocInfo::metadata_type) { 5751 __ set_metadata_constant((Metadata*)val, $dst$$Register); 5752 } else { // non-oop pointers, e.g. card mark base, heap top 5753 assert(constant_reloc == relocInfo::none, "unexpected reloc type"); 5754 __ set(val, $dst$$Register); 5755 } 5756 %} 5757 ins_pipe(loadConP); 5758%} 5759 5760instruct loadConP_load(iRegP dst, immP_load con) %{ 5761 match(Set dst con); 5762 ins_cost(MEMORY_REF_COST); 5763 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %} 5764 ins_encode %{ 5765 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5766 __ ld_ptr($constanttablebase, con_offset, $dst$$Register); 5767 %} 5768 ins_pipe(loadConP); 5769%} 5770 5771instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{ 5772 match(Set dst con); 5773 ins_cost(DEFAULT_COST * 3/2); 5774 format %{ "SET $con,$dst\t! non-oop ptr" %} 5775 ins_encode %{ 5776 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) { 5777 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register); 5778 } else { 5779 __ set($con$$constant, $dst$$Register); 5780 } 5781 %} 5782 ins_pipe(loadConP); 5783%} 5784 5785instruct loadConP0(iRegP dst, immP0 src) %{ 5786 match(Set dst src); 5787 5788 size(4); 5789 format %{ "CLR $dst\t!ptr" %} 5790 ins_encode %{ 5791 __ clr($dst$$Register); 5792 %} 5793 ins_pipe(ialu_imm); 5794%} 5795 5796instruct loadConP_poll(iRegP dst, immP_poll src) %{ 5797 match(Set dst src); 5798 ins_cost(DEFAULT_COST); 5799 format %{ "SET $src,$dst\t!ptr" %} 5800 ins_encode %{ 5801 AddressLiteral polling_page(os::get_polling_page()); 5802 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 5803 %} 5804 ins_pipe(loadConP_poll); 5805%} 5806 5807instruct loadConN0(iRegN dst, immN0 src) %{ 5808 match(Set dst src); 5809 5810 size(4); 5811 format %{ "CLR $dst\t! compressed NULL ptr" %} 5812 ins_encode %{ 5813 __ clr($dst$$Register); 5814 %} 5815 ins_pipe(ialu_imm); 5816%} 5817 5818instruct loadConN(iRegN dst, immN src) %{ 5819 match(Set dst src); 5820 ins_cost(DEFAULT_COST * 3/2); 5821 format %{ "SET $src,$dst\t! compressed ptr" %} 5822 ins_encode %{ 5823 Register dst = $dst$$Register; 5824 __ set_narrow_oop((jobject)$src$$constant, dst); 5825 %} 5826 ins_pipe(ialu_hi_lo_reg); 5827%} 5828 5829instruct loadConNKlass(iRegN dst, immNKlass src) %{ 5830 match(Set dst src); 5831 ins_cost(DEFAULT_COST * 3/2); 5832 format %{ "SET $src,$dst\t! compressed klass ptr" %} 5833 ins_encode %{ 5834 Register dst = $dst$$Register; 5835 __ set_narrow_klass((Klass*)$src$$constant, dst); 5836 %} 5837 ins_pipe(ialu_hi_lo_reg); 5838%} 5839 5840// Materialize long value (predicated by immL_cheap). 5841instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{ 5842 match(Set dst con); 5843 effect(KILL tmp); 5844 ins_cost(DEFAULT_COST * 3); 5845 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %} 5846 ins_encode %{ 5847 __ set64($con$$constant, $dst$$Register, $tmp$$Register); 5848 %} 5849 ins_pipe(loadConL); 5850%} 5851 5852// Load long value from constant table (predicated by immL_expensive). 5853instruct loadConL_ldx(iRegL dst, immL_expensive con) %{ 5854 match(Set dst con); 5855 ins_cost(MEMORY_REF_COST); 5856 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %} 5857 ins_encode %{ 5858 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register); 5859 __ ldx($constanttablebase, con_offset, $dst$$Register); 5860 %} 5861 ins_pipe(loadConL); 5862%} 5863 5864instruct loadConL0( iRegL dst, immL0 src ) %{ 5865 match(Set dst src); 5866 ins_cost(DEFAULT_COST); 5867 size(4); 5868 format %{ "CLR $dst\t! long" %} 5869 ins_encode( Set13( src, dst ) ); 5870 ins_pipe(ialu_imm); 5871%} 5872 5873instruct loadConL13( iRegL dst, immL13 src ) %{ 5874 match(Set dst src); 5875 ins_cost(DEFAULT_COST * 2); 5876 5877 size(4); 5878 format %{ "MOV $src,$dst\t! long" %} 5879 ins_encode( Set13( src, dst ) ); 5880 ins_pipe(ialu_imm); 5881%} 5882 5883instruct loadConF(regF dst, immF con, o7RegI tmp) %{ 5884 match(Set dst con); 5885 effect(KILL tmp); 5886 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %} 5887 ins_encode %{ 5888 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5889 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister); 5890 %} 5891 ins_pipe(loadConFD); 5892%} 5893 5894instruct loadConD(regD dst, immD con, o7RegI tmp) %{ 5895 match(Set dst con); 5896 effect(KILL tmp); 5897 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %} 5898 ins_encode %{ 5899 // XXX This is a quick fix for 6833573. 5900 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister); 5901 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register); 5902 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 5903 %} 5904 ins_pipe(loadConFD); 5905%} 5906 5907// Prefetch instructions for allocation. 5908// Must be safe to execute with invalid address (cannot fault). 5909 5910instruct prefetchAlloc( memory mem ) %{ 5911 predicate(AllocatePrefetchInstr == 0); 5912 match( PrefetchAllocation mem ); 5913 ins_cost(MEMORY_REF_COST); 5914 5915 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %} 5916 opcode(Assembler::prefetch_op3); 5917 ins_encode( form3_mem_prefetch_write( mem ) ); 5918 ins_pipe(iload_mem); 5919%} 5920 5921// Use BIS instruction to prefetch for allocation. 5922// Could fault, need space at the end of TLAB. 5923instruct prefetchAlloc_bis( iRegP dst ) %{ 5924 predicate(AllocatePrefetchInstr == 1); 5925 match( PrefetchAllocation dst ); 5926 ins_cost(MEMORY_REF_COST); 5927 size(4); 5928 5929 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %} 5930 ins_encode %{ 5931 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY); 5932 %} 5933 ins_pipe(istore_mem_reg); 5934%} 5935 5936// Next code is used for finding next cache line address to prefetch. 5937instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{ 5938 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 5939 ins_cost(DEFAULT_COST); 5940 size(4); 5941 5942 format %{ "AND $src,$mask,$dst\t! next cache line address" %} 5943 ins_encode %{ 5944 __ and3($src$$Register, $mask$$constant, $dst$$Register); 5945 %} 5946 ins_pipe(ialu_reg_imm); 5947%} 5948 5949//----------Store Instructions------------------------------------------------- 5950// Store Byte 5951instruct storeB(memory mem, iRegI src) %{ 5952 match(Set mem (StoreB mem src)); 5953 ins_cost(MEMORY_REF_COST); 5954 5955 format %{ "STB $src,$mem\t! byte" %} 5956 opcode(Assembler::stb_op3); 5957 ins_encode(simple_form3_mem_reg( mem, src ) ); 5958 ins_pipe(istore_mem_reg); 5959%} 5960 5961instruct storeB0(memory mem, immI0 src) %{ 5962 match(Set mem (StoreB mem src)); 5963 ins_cost(MEMORY_REF_COST); 5964 5965 format %{ "STB $src,$mem\t! byte" %} 5966 opcode(Assembler::stb_op3); 5967 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5968 ins_pipe(istore_mem_zero); 5969%} 5970 5971instruct storeCM0(memory mem, immI0 src) %{ 5972 match(Set mem (StoreCM mem src)); 5973 ins_cost(MEMORY_REF_COST); 5974 5975 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 5976 opcode(Assembler::stb_op3); 5977 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5978 ins_pipe(istore_mem_zero); 5979%} 5980 5981// Store Char/Short 5982instruct storeC(memory mem, iRegI src) %{ 5983 match(Set mem (StoreC mem src)); 5984 ins_cost(MEMORY_REF_COST); 5985 5986 format %{ "STH $src,$mem\t! short" %} 5987 opcode(Assembler::sth_op3); 5988 ins_encode(simple_form3_mem_reg( mem, src ) ); 5989 ins_pipe(istore_mem_reg); 5990%} 5991 5992instruct storeC0(memory mem, immI0 src) %{ 5993 match(Set mem (StoreC mem src)); 5994 ins_cost(MEMORY_REF_COST); 5995 5996 format %{ "STH $src,$mem\t! short" %} 5997 opcode(Assembler::sth_op3); 5998 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 5999 ins_pipe(istore_mem_zero); 6000%} 6001 6002// Store Integer 6003instruct storeI(memory mem, iRegI src) %{ 6004 match(Set mem (StoreI mem src)); 6005 ins_cost(MEMORY_REF_COST); 6006 6007 format %{ "STW $src,$mem" %} 6008 opcode(Assembler::stw_op3); 6009 ins_encode(simple_form3_mem_reg( mem, src ) ); 6010 ins_pipe(istore_mem_reg); 6011%} 6012 6013// Store Long 6014instruct storeL(memory mem, iRegL src) %{ 6015 match(Set mem (StoreL mem src)); 6016 ins_cost(MEMORY_REF_COST); 6017 format %{ "STX $src,$mem\t! long" %} 6018 opcode(Assembler::stx_op3); 6019 ins_encode(simple_form3_mem_reg( mem, src ) ); 6020 ins_pipe(istore_mem_reg); 6021%} 6022 6023instruct storeI0(memory mem, immI0 src) %{ 6024 match(Set mem (StoreI mem src)); 6025 ins_cost(MEMORY_REF_COST); 6026 6027 format %{ "STW $src,$mem" %} 6028 opcode(Assembler::stw_op3); 6029 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6030 ins_pipe(istore_mem_zero); 6031%} 6032 6033instruct storeL0(memory mem, immL0 src) %{ 6034 match(Set mem (StoreL mem src)); 6035 ins_cost(MEMORY_REF_COST); 6036 6037 format %{ "STX $src,$mem" %} 6038 opcode(Assembler::stx_op3); 6039 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6040 ins_pipe(istore_mem_zero); 6041%} 6042 6043// Store Integer from float register (used after fstoi) 6044instruct storeI_Freg(memory mem, regF src) %{ 6045 match(Set mem (StoreI mem src)); 6046 ins_cost(MEMORY_REF_COST); 6047 6048 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6049 opcode(Assembler::stf_op3); 6050 ins_encode(simple_form3_mem_reg( mem, src ) ); 6051 ins_pipe(fstoreF_mem_reg); 6052%} 6053 6054// Store Pointer 6055instruct storeP(memory dst, sp_ptr_RegP src) %{ 6056 match(Set dst (StoreP dst src)); 6057 ins_cost(MEMORY_REF_COST); 6058 6059 format %{ "STX $src,$dst\t! ptr" %} 6060 opcode(Assembler::stx_op3, 0, REGP_OP); 6061 ins_encode( form3_mem_reg( dst, src ) ); 6062 ins_pipe(istore_mem_spORreg); 6063%} 6064 6065instruct storeP0(memory dst, immP0 src) %{ 6066 match(Set dst (StoreP dst src)); 6067 ins_cost(MEMORY_REF_COST); 6068 6069 format %{ "STX $src,$dst\t! ptr" %} 6070 opcode(Assembler::stx_op3, 0, REGP_OP); 6071 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6072 ins_pipe(istore_mem_zero); 6073%} 6074 6075// Store Compressed Pointer 6076instruct storeN(memory dst, iRegN src) %{ 6077 match(Set dst (StoreN dst src)); 6078 ins_cost(MEMORY_REF_COST); 6079 size(4); 6080 6081 format %{ "STW $src,$dst\t! compressed ptr" %} 6082 ins_encode %{ 6083 Register base = as_Register($dst$$base); 6084 Register index = as_Register($dst$$index); 6085 Register src = $src$$Register; 6086 if (index != G0) { 6087 __ stw(src, base, index); 6088 } else { 6089 __ stw(src, base, $dst$$disp); 6090 } 6091 %} 6092 ins_pipe(istore_mem_spORreg); 6093%} 6094 6095instruct storeNKlass(memory dst, iRegN src) %{ 6096 match(Set dst (StoreNKlass dst src)); 6097 ins_cost(MEMORY_REF_COST); 6098 size(4); 6099 6100 format %{ "STW $src,$dst\t! compressed klass ptr" %} 6101 ins_encode %{ 6102 Register base = as_Register($dst$$base); 6103 Register index = as_Register($dst$$index); 6104 Register src = $src$$Register; 6105 if (index != G0) { 6106 __ stw(src, base, index); 6107 } else { 6108 __ stw(src, base, $dst$$disp); 6109 } 6110 %} 6111 ins_pipe(istore_mem_spORreg); 6112%} 6113 6114instruct storeN0(memory dst, immN0 src) %{ 6115 match(Set dst (StoreN dst src)); 6116 ins_cost(MEMORY_REF_COST); 6117 size(4); 6118 6119 format %{ "STW $src,$dst\t! compressed ptr" %} 6120 ins_encode %{ 6121 Register base = as_Register($dst$$base); 6122 Register index = as_Register($dst$$index); 6123 if (index != G0) { 6124 __ stw(0, base, index); 6125 } else { 6126 __ stw(0, base, $dst$$disp); 6127 } 6128 %} 6129 ins_pipe(istore_mem_zero); 6130%} 6131 6132// Store Double 6133instruct storeD( memory mem, regD src) %{ 6134 match(Set mem (StoreD mem src)); 6135 ins_cost(MEMORY_REF_COST); 6136 6137 format %{ "STDF $src,$mem" %} 6138 opcode(Assembler::stdf_op3); 6139 ins_encode(simple_form3_mem_reg( mem, src ) ); 6140 ins_pipe(fstoreD_mem_reg); 6141%} 6142 6143instruct storeD0( memory mem, immD0 src) %{ 6144 match(Set mem (StoreD mem src)); 6145 ins_cost(MEMORY_REF_COST); 6146 6147 format %{ "STX $src,$mem" %} 6148 opcode(Assembler::stx_op3); 6149 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6150 ins_pipe(fstoreD_mem_zero); 6151%} 6152 6153// Store Float 6154instruct storeF( memory mem, regF src) %{ 6155 match(Set mem (StoreF mem src)); 6156 ins_cost(MEMORY_REF_COST); 6157 6158 format %{ "STF $src,$mem" %} 6159 opcode(Assembler::stf_op3); 6160 ins_encode(simple_form3_mem_reg( mem, src ) ); 6161 ins_pipe(fstoreF_mem_reg); 6162%} 6163 6164instruct storeF0( memory mem, immF0 src) %{ 6165 match(Set mem (StoreF mem src)); 6166 ins_cost(MEMORY_REF_COST); 6167 6168 format %{ "STW $src,$mem\t! storeF0" %} 6169 opcode(Assembler::stw_op3); 6170 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6171 ins_pipe(fstoreF_mem_zero); 6172%} 6173 6174// Convert oop pointer into compressed form 6175instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6176 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6177 match(Set dst (EncodeP src)); 6178 format %{ "encode_heap_oop $src, $dst" %} 6179 ins_encode %{ 6180 __ encode_heap_oop($src$$Register, $dst$$Register); 6181 %} 6182 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE); 6183 ins_pipe(ialu_reg); 6184%} 6185 6186instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6187 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6188 match(Set dst (EncodeP src)); 6189 format %{ "encode_heap_oop_not_null $src, $dst" %} 6190 ins_encode %{ 6191 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6192 %} 6193 ins_pipe(ialu_reg); 6194%} 6195 6196instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6197 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6198 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6199 match(Set dst (DecodeN src)); 6200 format %{ "decode_heap_oop $src, $dst" %} 6201 ins_encode %{ 6202 __ decode_heap_oop($src$$Register, $dst$$Register); 6203 %} 6204 ins_pipe(ialu_reg); 6205%} 6206 6207instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6208 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6209 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6210 match(Set dst (DecodeN src)); 6211 format %{ "decode_heap_oop_not_null $src, $dst" %} 6212 ins_encode %{ 6213 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6214 %} 6215 ins_pipe(ialu_reg); 6216%} 6217 6218instruct encodeKlass_not_null(iRegN dst, iRegP src) %{ 6219 match(Set dst (EncodePKlass src)); 6220 format %{ "encode_klass_not_null $src, $dst" %} 6221 ins_encode %{ 6222 __ encode_klass_not_null($src$$Register, $dst$$Register); 6223 %} 6224 ins_pipe(ialu_reg); 6225%} 6226 6227instruct decodeKlass_not_null(iRegP dst, iRegN src) %{ 6228 match(Set dst (DecodeNKlass src)); 6229 format %{ "decode_klass_not_null $src, $dst" %} 6230 ins_encode %{ 6231 __ decode_klass_not_null($src$$Register, $dst$$Register); 6232 %} 6233 ins_pipe(ialu_reg); 6234%} 6235 6236//----------MemBar Instructions----------------------------------------------- 6237// Memory barrier flavors 6238 6239instruct membar_acquire() %{ 6240 match(MemBarAcquire); 6241 match(LoadFence); 6242 ins_cost(4*MEMORY_REF_COST); 6243 6244 size(0); 6245 format %{ "MEMBAR-acquire" %} 6246 ins_encode( enc_membar_acquire ); 6247 ins_pipe(long_memory_op); 6248%} 6249 6250instruct membar_acquire_lock() %{ 6251 match(MemBarAcquireLock); 6252 ins_cost(0); 6253 6254 size(0); 6255 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6256 ins_encode( ); 6257 ins_pipe(empty); 6258%} 6259 6260instruct membar_release() %{ 6261 match(MemBarRelease); 6262 match(StoreFence); 6263 ins_cost(4*MEMORY_REF_COST); 6264 6265 size(0); 6266 format %{ "MEMBAR-release" %} 6267 ins_encode( enc_membar_release ); 6268 ins_pipe(long_memory_op); 6269%} 6270 6271instruct membar_release_lock() %{ 6272 match(MemBarReleaseLock); 6273 ins_cost(0); 6274 6275 size(0); 6276 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6277 ins_encode( ); 6278 ins_pipe(empty); 6279%} 6280 6281instruct membar_volatile() %{ 6282 match(MemBarVolatile); 6283 ins_cost(4*MEMORY_REF_COST); 6284 6285 size(4); 6286 format %{ "MEMBAR-volatile" %} 6287 ins_encode( enc_membar_volatile ); 6288 ins_pipe(long_memory_op); 6289%} 6290 6291instruct unnecessary_membar_volatile() %{ 6292 match(MemBarVolatile); 6293 predicate(Matcher::post_store_load_barrier(n)); 6294 ins_cost(0); 6295 6296 size(0); 6297 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6298 ins_encode( ); 6299 ins_pipe(empty); 6300%} 6301 6302instruct membar_storestore() %{ 6303 match(MemBarStoreStore); 6304 ins_cost(0); 6305 6306 size(0); 6307 format %{ "!MEMBAR-storestore (empty encoding)" %} 6308 ins_encode( ); 6309 ins_pipe(empty); 6310%} 6311 6312//----------Register Move Instructions----------------------------------------- 6313instruct roundDouble_nop(regD dst) %{ 6314 match(Set dst (RoundDouble dst)); 6315 ins_cost(0); 6316 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6317 ins_encode( ); 6318 ins_pipe(empty); 6319%} 6320 6321 6322instruct roundFloat_nop(regF dst) %{ 6323 match(Set dst (RoundFloat dst)); 6324 ins_cost(0); 6325 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6326 ins_encode( ); 6327 ins_pipe(empty); 6328%} 6329 6330 6331// Cast Index to Pointer for unsafe natives 6332instruct castX2P(iRegX src, iRegP dst) %{ 6333 match(Set dst (CastX2P src)); 6334 6335 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6336 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6337 ins_pipe(ialu_reg); 6338%} 6339 6340// Cast Pointer to Index for unsafe natives 6341instruct castP2X(iRegP src, iRegX dst) %{ 6342 match(Set dst (CastP2X src)); 6343 6344 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6345 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6346 ins_pipe(ialu_reg); 6347%} 6348 6349instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6350 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6351 match(Set stkSlot src); // chain rule 6352 ins_cost(MEMORY_REF_COST); 6353 format %{ "STDF $src,$stkSlot\t!stk" %} 6354 opcode(Assembler::stdf_op3); 6355 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6356 ins_pipe(fstoreD_stk_reg); 6357%} 6358 6359instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6360 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6361 match(Set dst stkSlot); // chain rule 6362 ins_cost(MEMORY_REF_COST); 6363 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6364 opcode(Assembler::lddf_op3); 6365 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6366 ins_pipe(floadD_stk); 6367%} 6368 6369instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6370 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6371 match(Set stkSlot src); // chain rule 6372 ins_cost(MEMORY_REF_COST); 6373 format %{ "STF $src,$stkSlot\t!stk" %} 6374 opcode(Assembler::stf_op3); 6375 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6376 ins_pipe(fstoreF_stk_reg); 6377%} 6378 6379//----------Conditional Move--------------------------------------------------- 6380// Conditional move 6381instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6382 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6383 ins_cost(150); 6384 format %{ "MOV$cmp $pcc,$src,$dst" %} 6385 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6386 ins_pipe(ialu_reg); 6387%} 6388 6389instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6390 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6391 ins_cost(140); 6392 format %{ "MOV$cmp $pcc,$src,$dst" %} 6393 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6394 ins_pipe(ialu_imm); 6395%} 6396 6397instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6398 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6399 ins_cost(150); 6400 size(4); 6401 format %{ "MOV$cmp $icc,$src,$dst" %} 6402 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6403 ins_pipe(ialu_reg); 6404%} 6405 6406instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6407 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6408 ins_cost(140); 6409 size(4); 6410 format %{ "MOV$cmp $icc,$src,$dst" %} 6411 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6412 ins_pipe(ialu_imm); 6413%} 6414 6415instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6416 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6417 ins_cost(150); 6418 size(4); 6419 format %{ "MOV$cmp $icc,$src,$dst" %} 6420 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6421 ins_pipe(ialu_reg); 6422%} 6423 6424instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6425 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6426 ins_cost(140); 6427 size(4); 6428 format %{ "MOV$cmp $icc,$src,$dst" %} 6429 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6430 ins_pipe(ialu_imm); 6431%} 6432 6433instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6434 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6435 ins_cost(150); 6436 size(4); 6437 format %{ "MOV$cmp $fcc,$src,$dst" %} 6438 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6439 ins_pipe(ialu_reg); 6440%} 6441 6442instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6443 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6444 ins_cost(140); 6445 size(4); 6446 format %{ "MOV$cmp $fcc,$src,$dst" %} 6447 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6448 ins_pipe(ialu_imm); 6449%} 6450 6451// Conditional move for RegN. Only cmov(reg,reg). 6452instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6453 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6454 ins_cost(150); 6455 format %{ "MOV$cmp $pcc,$src,$dst" %} 6456 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6457 ins_pipe(ialu_reg); 6458%} 6459 6460// This instruction also works with CmpN so we don't need cmovNN_reg. 6461instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6462 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6463 ins_cost(150); 6464 size(4); 6465 format %{ "MOV$cmp $icc,$src,$dst" %} 6466 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6467 ins_pipe(ialu_reg); 6468%} 6469 6470// This instruction also works with CmpN so we don't need cmovNN_reg. 6471instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6472 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6473 ins_cost(150); 6474 size(4); 6475 format %{ "MOV$cmp $icc,$src,$dst" %} 6476 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6477 ins_pipe(ialu_reg); 6478%} 6479 6480instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6481 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6482 ins_cost(150); 6483 size(4); 6484 format %{ "MOV$cmp $fcc,$src,$dst" %} 6485 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6486 ins_pipe(ialu_reg); 6487%} 6488 6489// Conditional move 6490instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6491 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6492 ins_cost(150); 6493 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6494 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6495 ins_pipe(ialu_reg); 6496%} 6497 6498instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6499 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6500 ins_cost(140); 6501 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6502 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6503 ins_pipe(ialu_imm); 6504%} 6505 6506// This instruction also works with CmpN so we don't need cmovPN_reg. 6507instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6508 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6509 ins_cost(150); 6510 6511 size(4); 6512 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6513 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6514 ins_pipe(ialu_reg); 6515%} 6516 6517instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6518 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6519 ins_cost(150); 6520 6521 size(4); 6522 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6523 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6524 ins_pipe(ialu_reg); 6525%} 6526 6527instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6528 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6529 ins_cost(140); 6530 6531 size(4); 6532 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6533 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6534 ins_pipe(ialu_imm); 6535%} 6536 6537instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6538 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6539 ins_cost(140); 6540 6541 size(4); 6542 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6543 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6544 ins_pipe(ialu_imm); 6545%} 6546 6547instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6548 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6549 ins_cost(150); 6550 size(4); 6551 format %{ "MOV$cmp $fcc,$src,$dst" %} 6552 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6553 ins_pipe(ialu_imm); 6554%} 6555 6556instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6557 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6558 ins_cost(140); 6559 size(4); 6560 format %{ "MOV$cmp $fcc,$src,$dst" %} 6561 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6562 ins_pipe(ialu_imm); 6563%} 6564 6565// Conditional move 6566instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6567 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6568 ins_cost(150); 6569 opcode(0x101); 6570 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6571 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6572 ins_pipe(int_conditional_float_move); 6573%} 6574 6575instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6576 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6577 ins_cost(150); 6578 6579 size(4); 6580 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6581 opcode(0x101); 6582 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6583 ins_pipe(int_conditional_float_move); 6584%} 6585 6586instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6587 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6588 ins_cost(150); 6589 6590 size(4); 6591 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6592 opcode(0x101); 6593 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6594 ins_pipe(int_conditional_float_move); 6595%} 6596 6597// Conditional move, 6598instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6599 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6600 ins_cost(150); 6601 size(4); 6602 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6603 opcode(0x1); 6604 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6605 ins_pipe(int_conditional_double_move); 6606%} 6607 6608// Conditional move 6609instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6610 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6611 ins_cost(150); 6612 size(4); 6613 opcode(0x102); 6614 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6615 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6616 ins_pipe(int_conditional_double_move); 6617%} 6618 6619instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6620 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6621 ins_cost(150); 6622 6623 size(4); 6624 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6625 opcode(0x102); 6626 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6627 ins_pipe(int_conditional_double_move); 6628%} 6629 6630instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6631 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6632 ins_cost(150); 6633 6634 size(4); 6635 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6636 opcode(0x102); 6637 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6638 ins_pipe(int_conditional_double_move); 6639%} 6640 6641// Conditional move, 6642instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6643 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6644 ins_cost(150); 6645 size(4); 6646 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6647 opcode(0x2); 6648 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6649 ins_pipe(int_conditional_double_move); 6650%} 6651 6652// Conditional move 6653instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6654 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6655 ins_cost(150); 6656 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6657 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6658 ins_pipe(ialu_reg); 6659%} 6660 6661instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6662 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6663 ins_cost(140); 6664 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6665 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6666 ins_pipe(ialu_imm); 6667%} 6668 6669instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6670 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6671 ins_cost(150); 6672 6673 size(4); 6674 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6675 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6676 ins_pipe(ialu_reg); 6677%} 6678 6679 6680instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6681 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6682 ins_cost(150); 6683 6684 size(4); 6685 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6686 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6687 ins_pipe(ialu_reg); 6688%} 6689 6690 6691instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6692 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6693 ins_cost(150); 6694 6695 size(4); 6696 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6697 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6698 ins_pipe(ialu_reg); 6699%} 6700 6701 6702 6703//----------OS and Locking Instructions---------------------------------------- 6704 6705// This name is KNOWN by the ADLC and cannot be changed. 6706// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6707// for this guy. 6708instruct tlsLoadP(g2RegP dst) %{ 6709 match(Set dst (ThreadLocal)); 6710 6711 size(0); 6712 ins_cost(0); 6713 format %{ "# TLS is in G2" %} 6714 ins_encode( /*empty encoding*/ ); 6715 ins_pipe(ialu_none); 6716%} 6717 6718instruct checkCastPP( iRegP dst ) %{ 6719 match(Set dst (CheckCastPP dst)); 6720 6721 size(0); 6722 format %{ "# checkcastPP of $dst" %} 6723 ins_encode( /*empty encoding*/ ); 6724 ins_pipe(empty); 6725%} 6726 6727 6728instruct castPP( iRegP dst ) %{ 6729 match(Set dst (CastPP dst)); 6730 format %{ "# castPP of $dst" %} 6731 ins_encode( /*empty encoding*/ ); 6732 ins_pipe(empty); 6733%} 6734 6735instruct castII( iRegI dst ) %{ 6736 match(Set dst (CastII dst)); 6737 format %{ "# castII of $dst" %} 6738 ins_encode( /*empty encoding*/ ); 6739 ins_cost(0); 6740 ins_pipe(empty); 6741%} 6742 6743//----------Arithmetic Instructions-------------------------------------------- 6744// Addition Instructions 6745// Register Addition 6746instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6747 match(Set dst (AddI src1 src2)); 6748 6749 size(4); 6750 format %{ "ADD $src1,$src2,$dst" %} 6751 ins_encode %{ 6752 __ add($src1$$Register, $src2$$Register, $dst$$Register); 6753 %} 6754 ins_pipe(ialu_reg_reg); 6755%} 6756 6757// Immediate Addition 6758instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 6759 match(Set dst (AddI src1 src2)); 6760 6761 size(4); 6762 format %{ "ADD $src1,$src2,$dst" %} 6763 opcode(Assembler::add_op3, Assembler::arith_op); 6764 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6765 ins_pipe(ialu_reg_imm); 6766%} 6767 6768// Pointer Register Addition 6769instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 6770 match(Set dst (AddP src1 src2)); 6771 6772 size(4); 6773 format %{ "ADD $src1,$src2,$dst" %} 6774 opcode(Assembler::add_op3, Assembler::arith_op); 6775 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6776 ins_pipe(ialu_reg_reg); 6777%} 6778 6779// Pointer Immediate Addition 6780instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 6781 match(Set dst (AddP src1 src2)); 6782 6783 size(4); 6784 format %{ "ADD $src1,$src2,$dst" %} 6785 opcode(Assembler::add_op3, Assembler::arith_op); 6786 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 6787 ins_pipe(ialu_reg_imm); 6788%} 6789 6790// Long Addition 6791instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 6792 match(Set dst (AddL src1 src2)); 6793 6794 size(4); 6795 format %{ "ADD $src1,$src2,$dst\t! long" %} 6796 opcode(Assembler::add_op3, Assembler::arith_op); 6797 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 6798 ins_pipe(ialu_reg_reg); 6799%} 6800 6801instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 6802 match(Set dst (AddL src1 con)); 6803 6804 size(4); 6805 format %{ "ADD $src1,$con,$dst" %} 6806 opcode(Assembler::add_op3, Assembler::arith_op); 6807 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 6808 ins_pipe(ialu_reg_imm); 6809%} 6810 6811//----------Conditional_store-------------------------------------------------- 6812// Conditional-store of the updated heap-top. 6813// Used during allocation of the shared heap. 6814// Sets flags (EQ) on success. Implemented with a CASA on Sparc. 6815 6816// LoadP-locked. Same as a regular pointer load when used with a compare-swap 6817instruct loadPLocked(iRegP dst, memory mem) %{ 6818 match(Set dst (LoadPLocked mem)); 6819 ins_cost(MEMORY_REF_COST); 6820 6821 format %{ "LDX $mem,$dst\t! ptr" %} 6822 opcode(Assembler::ldx_op3, 0, REGP_OP); 6823 ins_encode( form3_mem_reg( mem, dst ) ); 6824 ins_pipe(iload_mem); 6825%} 6826 6827instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 6828 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 6829 effect( KILL newval ); 6830 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 6831 "CMP R_G3,$oldval\t\t! See if we made progress" %} 6832 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 6833 ins_pipe( long_memory_op ); 6834%} 6835 6836// Conditional-store of an int value. 6837instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 6838 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 6839 effect( KILL newval ); 6840 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6841 "CMP $oldval,$newval\t\t! See if we made progress" %} 6842 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6843 ins_pipe( long_memory_op ); 6844%} 6845 6846// Conditional-store of a long value. 6847instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 6848 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 6849 effect( KILL newval ); 6850 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 6851 "CMP $oldval,$newval\t\t! See if we made progress" %} 6852 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 6853 ins_pipe( long_memory_op ); 6854%} 6855 6856// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 6857 6858instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6859 predicate(VM_Version::supports_cx8()); 6860 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 6861 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval))); 6862 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6863 format %{ 6864 "MOV $newval,O7\n\t" 6865 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6866 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6867 "MOV 1,$res\n\t" 6868 "MOVne xcc,R_G0,$res" 6869 %} 6870 ins_encode( enc_casx(mem_ptr, oldval, newval), 6871 enc_lflags_ne_to_boolean(res) ); 6872 ins_pipe( long_memory_op ); 6873%} 6874 6875 6876instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6877 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 6878 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval))); 6879 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6880 format %{ 6881 "MOV $newval,O7\n\t" 6882 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6883 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6884 "MOV 1,$res\n\t" 6885 "MOVne icc,R_G0,$res" 6886 %} 6887 ins_encode( enc_casi(mem_ptr, oldval, newval), 6888 enc_iflags_ne_to_boolean(res) ); 6889 ins_pipe( long_memory_op ); 6890%} 6891 6892instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6893 predicate(VM_Version::supports_cx8()); 6894 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 6895 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval))); 6896 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6897 format %{ 6898 "MOV $newval,O7\n\t" 6899 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6900 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6901 "MOV 1,$res\n\t" 6902 "MOVne xcc,R_G0,$res" 6903 %} 6904 ins_encode( enc_casx(mem_ptr, oldval, newval), 6905 enc_lflags_ne_to_boolean(res) ); 6906 ins_pipe( long_memory_op ); 6907%} 6908 6909instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 6910 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 6911 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval))); 6912 effect( USE mem_ptr, KILL ccr, KILL tmp1); 6913 format %{ 6914 "MOV $newval,O7\n\t" 6915 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 6916 "CMP $oldval,O7\t\t! See if we made progress\n\t" 6917 "MOV 1,$res\n\t" 6918 "MOVne icc,R_G0,$res" 6919 %} 6920 ins_encode( enc_casi(mem_ptr, oldval, newval), 6921 enc_iflags_ne_to_boolean(res) ); 6922 ins_pipe( long_memory_op ); 6923%} 6924 6925instruct compareAndExchangeI(iRegP mem_ptr, iRegI oldval, iRegI newval) 6926%{ 6927 match(Set newval (CompareAndExchangeI mem_ptr (Binary oldval newval))); 6928 effect( USE mem_ptr ); 6929 6930 format %{ 6931 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6932 %} 6933 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6934 ins_pipe( long_memory_op ); 6935%} 6936 6937instruct compareAndExchangeL(iRegP mem_ptr, iRegL oldval, iRegL newval) 6938%{ 6939 match(Set newval (CompareAndExchangeL mem_ptr (Binary oldval newval))); 6940 effect( USE mem_ptr ); 6941 6942 format %{ 6943 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6944 %} 6945 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6946 ins_pipe( long_memory_op ); 6947%} 6948 6949instruct compareAndExchangeP(iRegP mem_ptr, iRegP oldval, iRegP newval) 6950%{ 6951 match(Set newval (CompareAndExchangeP mem_ptr (Binary oldval newval))); 6952 effect( USE mem_ptr ); 6953 6954 format %{ 6955 "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6956 %} 6957 ins_encode( enc_casx_exch(mem_ptr, oldval, newval) ); 6958 ins_pipe( long_memory_op ); 6959%} 6960 6961instruct compareAndExchangeN(iRegP mem_ptr, iRegN oldval, iRegN newval) 6962%{ 6963 match(Set newval (CompareAndExchangeN mem_ptr (Binary oldval newval))); 6964 effect( USE mem_ptr ); 6965 6966 format %{ 6967 "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr] and set $newval=[$mem_ptr]\n\t" 6968 %} 6969 ins_encode( enc_casi_exch(mem_ptr, oldval, newval) ); 6970 ins_pipe( long_memory_op ); 6971%} 6972 6973instruct xchgI( memory mem, iRegI newval) %{ 6974 match(Set newval (GetAndSetI mem newval)); 6975 format %{ "SWAP [$mem],$newval" %} 6976 size(4); 6977 ins_encode %{ 6978 __ swap($mem$$Address, $newval$$Register); 6979 %} 6980 ins_pipe( long_memory_op ); 6981%} 6982 6983 6984instruct xchgN( memory mem, iRegN newval) %{ 6985 match(Set newval (GetAndSetN mem newval)); 6986 format %{ "SWAP [$mem],$newval" %} 6987 size(4); 6988 ins_encode %{ 6989 __ swap($mem$$Address, $newval$$Register); 6990 %} 6991 ins_pipe( long_memory_op ); 6992%} 6993 6994//--------------------- 6995// Subtraction Instructions 6996// Register Subtraction 6997instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6998 match(Set dst (SubI src1 src2)); 6999 7000 size(4); 7001 format %{ "SUB $src1,$src2,$dst" %} 7002 opcode(Assembler::sub_op3, Assembler::arith_op); 7003 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7004 ins_pipe(ialu_reg_reg); 7005%} 7006 7007// Immediate Subtraction 7008instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7009 match(Set dst (SubI src1 src2)); 7010 7011 size(4); 7012 format %{ "SUB $src1,$src2,$dst" %} 7013 opcode(Assembler::sub_op3, Assembler::arith_op); 7014 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7015 ins_pipe(ialu_reg_imm); 7016%} 7017 7018instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7019 match(Set dst (SubI zero src2)); 7020 7021 size(4); 7022 format %{ "NEG $src2,$dst" %} 7023 opcode(Assembler::sub_op3, Assembler::arith_op); 7024 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7025 ins_pipe(ialu_zero_reg); 7026%} 7027 7028// Long subtraction 7029instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7030 match(Set dst (SubL src1 src2)); 7031 7032 size(4); 7033 format %{ "SUB $src1,$src2,$dst\t! long" %} 7034 opcode(Assembler::sub_op3, Assembler::arith_op); 7035 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7036 ins_pipe(ialu_reg_reg); 7037%} 7038 7039// Immediate Subtraction 7040instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7041 match(Set dst (SubL src1 con)); 7042 7043 size(4); 7044 format %{ "SUB $src1,$con,$dst\t! long" %} 7045 opcode(Assembler::sub_op3, Assembler::arith_op); 7046 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7047 ins_pipe(ialu_reg_imm); 7048%} 7049 7050// Long negation 7051instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7052 match(Set dst (SubL zero src2)); 7053 7054 size(4); 7055 format %{ "NEG $src2,$dst\t! long" %} 7056 opcode(Assembler::sub_op3, Assembler::arith_op); 7057 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7058 ins_pipe(ialu_zero_reg); 7059%} 7060 7061// Multiplication Instructions 7062// Integer Multiplication 7063// Register Multiplication 7064instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7065 match(Set dst (MulI src1 src2)); 7066 7067 size(4); 7068 format %{ "MULX $src1,$src2,$dst" %} 7069 opcode(Assembler::mulx_op3, Assembler::arith_op); 7070 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7071 ins_pipe(imul_reg_reg); 7072%} 7073 7074// Immediate Multiplication 7075instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7076 match(Set dst (MulI src1 src2)); 7077 7078 size(4); 7079 format %{ "MULX $src1,$src2,$dst" %} 7080 opcode(Assembler::mulx_op3, Assembler::arith_op); 7081 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7082 ins_pipe(imul_reg_imm); 7083%} 7084 7085instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7086 match(Set dst (MulL src1 src2)); 7087 ins_cost(DEFAULT_COST * 5); 7088 size(4); 7089 format %{ "MULX $src1,$src2,$dst\t! long" %} 7090 opcode(Assembler::mulx_op3, Assembler::arith_op); 7091 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7092 ins_pipe(mulL_reg_reg); 7093%} 7094 7095// Immediate Multiplication 7096instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7097 match(Set dst (MulL src1 src2)); 7098 ins_cost(DEFAULT_COST * 5); 7099 size(4); 7100 format %{ "MULX $src1,$src2,$dst" %} 7101 opcode(Assembler::mulx_op3, Assembler::arith_op); 7102 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7103 ins_pipe(mulL_reg_imm); 7104%} 7105 7106// Integer Division 7107// Register Division 7108instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7109 match(Set dst (DivI src1 src2)); 7110 ins_cost((2+71)*DEFAULT_COST); 7111 7112 format %{ "SRA $src2,0,$src2\n\t" 7113 "SRA $src1,0,$src1\n\t" 7114 "SDIVX $src1,$src2,$dst" %} 7115 ins_encode( idiv_reg( src1, src2, dst ) ); 7116 ins_pipe(sdiv_reg_reg); 7117%} 7118 7119// Immediate Division 7120instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7121 match(Set dst (DivI src1 src2)); 7122 ins_cost((2+71)*DEFAULT_COST); 7123 7124 format %{ "SRA $src1,0,$src1\n\t" 7125 "SDIVX $src1,$src2,$dst" %} 7126 ins_encode( idiv_imm( src1, src2, dst ) ); 7127 ins_pipe(sdiv_reg_imm); 7128%} 7129 7130//----------Div-By-10-Expansion------------------------------------------------ 7131// Extract hi bits of a 32x32->64 bit multiply. 7132// Expand rule only, not matched 7133instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7134 effect( DEF dst, USE src1, USE src2 ); 7135 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7136 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7137 ins_encode( enc_mul_hi(dst,src1,src2)); 7138 ins_pipe(sdiv_reg_reg); 7139%} 7140 7141// Magic constant, reciprocal of 10 7142instruct loadConI_x66666667(iRegIsafe dst) %{ 7143 effect( DEF dst ); 7144 7145 size(8); 7146 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7147 ins_encode( Set32(0x66666667, dst) ); 7148 ins_pipe(ialu_hi_lo_reg); 7149%} 7150 7151// Register Shift Right Arithmetic Long by 32-63 7152instruct sra_31( iRegI dst, iRegI src ) %{ 7153 effect( DEF dst, USE src ); 7154 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7155 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7156 ins_pipe(ialu_reg_reg); 7157%} 7158 7159// Arithmetic Shift Right by 8-bit immediate 7160instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7161 effect( DEF dst, USE src ); 7162 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7163 opcode(Assembler::sra_op3, Assembler::arith_op); 7164 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7165 ins_pipe(ialu_reg_imm); 7166%} 7167 7168// Integer DIV with 10 7169instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7170 match(Set dst (DivI src div)); 7171 ins_cost((6+6)*DEFAULT_COST); 7172 expand %{ 7173 iRegIsafe tmp1; // Killed temps; 7174 iRegIsafe tmp2; // Killed temps; 7175 iRegI tmp3; // Killed temps; 7176 iRegI tmp4; // Killed temps; 7177 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7178 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7179 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7180 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7181 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7182 %} 7183%} 7184 7185// Register Long Division 7186instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7187 match(Set dst (DivL src1 src2)); 7188 ins_cost(DEFAULT_COST*71); 7189 size(4); 7190 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7191 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7192 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7193 ins_pipe(divL_reg_reg); 7194%} 7195 7196// Register Long Division 7197instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7198 match(Set dst (DivL src1 src2)); 7199 ins_cost(DEFAULT_COST*71); 7200 size(4); 7201 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7202 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7203 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7204 ins_pipe(divL_reg_imm); 7205%} 7206 7207// Integer Remainder 7208// Register Remainder 7209instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7210 match(Set dst (ModI src1 src2)); 7211 effect( KILL ccr, KILL temp); 7212 7213 format %{ "SREM $src1,$src2,$dst" %} 7214 ins_encode( irem_reg(src1, src2, dst, temp) ); 7215 ins_pipe(sdiv_reg_reg); 7216%} 7217 7218// Immediate Remainder 7219instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7220 match(Set dst (ModI src1 src2)); 7221 effect( KILL ccr, KILL temp); 7222 7223 format %{ "SREM $src1,$src2,$dst" %} 7224 ins_encode( irem_imm(src1, src2, dst, temp) ); 7225 ins_pipe(sdiv_reg_imm); 7226%} 7227 7228// Register Long Remainder 7229instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7230 effect(DEF dst, USE src1, USE src2); 7231 size(4); 7232 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7233 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7234 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7235 ins_pipe(divL_reg_reg); 7236%} 7237 7238// Register Long Division 7239instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7240 effect(DEF dst, USE src1, USE src2); 7241 size(4); 7242 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7243 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7244 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7245 ins_pipe(divL_reg_imm); 7246%} 7247 7248instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7249 effect(DEF dst, USE src1, USE src2); 7250 size(4); 7251 format %{ "MULX $src1,$src2,$dst\t! long" %} 7252 opcode(Assembler::mulx_op3, Assembler::arith_op); 7253 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7254 ins_pipe(mulL_reg_reg); 7255%} 7256 7257// Immediate Multiplication 7258instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7259 effect(DEF dst, USE src1, USE src2); 7260 size(4); 7261 format %{ "MULX $src1,$src2,$dst" %} 7262 opcode(Assembler::mulx_op3, Assembler::arith_op); 7263 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7264 ins_pipe(mulL_reg_imm); 7265%} 7266 7267instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7268 effect(DEF dst, USE src1, USE src2); 7269 size(4); 7270 format %{ "SUB $src1,$src2,$dst\t! long" %} 7271 opcode(Assembler::sub_op3, Assembler::arith_op); 7272 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7273 ins_pipe(ialu_reg_reg); 7274%} 7275 7276instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7277 effect(DEF dst, USE src1, USE src2); 7278 size(4); 7279 format %{ "SUB $src1,$src2,$dst\t! long" %} 7280 opcode(Assembler::sub_op3, Assembler::arith_op); 7281 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7282 ins_pipe(ialu_reg_reg); 7283%} 7284 7285// Register Long Remainder 7286instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7287 match(Set dst (ModL src1 src2)); 7288 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7289 expand %{ 7290 iRegL tmp1; 7291 iRegL tmp2; 7292 divL_reg_reg_1(tmp1, src1, src2); 7293 mulL_reg_reg_1(tmp2, tmp1, src2); 7294 subL_reg_reg_1(dst, src1, tmp2); 7295 %} 7296%} 7297 7298// Register Long Remainder 7299instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7300 match(Set dst (ModL src1 src2)); 7301 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7302 expand %{ 7303 iRegL tmp1; 7304 iRegL tmp2; 7305 divL_reg_imm13_1(tmp1, src1, src2); 7306 mulL_reg_imm13_1(tmp2, tmp1, src2); 7307 subL_reg_reg_2 (dst, src1, tmp2); 7308 %} 7309%} 7310 7311// Integer Shift Instructions 7312// Register Shift Left 7313instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7314 match(Set dst (LShiftI src1 src2)); 7315 7316 size(4); 7317 format %{ "SLL $src1,$src2,$dst" %} 7318 opcode(Assembler::sll_op3, Assembler::arith_op); 7319 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7320 ins_pipe(ialu_reg_reg); 7321%} 7322 7323// Register Shift Left Immediate 7324instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7325 match(Set dst (LShiftI src1 src2)); 7326 7327 size(4); 7328 format %{ "SLL $src1,$src2,$dst" %} 7329 opcode(Assembler::sll_op3, Assembler::arith_op); 7330 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7331 ins_pipe(ialu_reg_imm); 7332%} 7333 7334// Register Shift Left 7335instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7336 match(Set dst (LShiftL src1 src2)); 7337 7338 size(4); 7339 format %{ "SLLX $src1,$src2,$dst" %} 7340 opcode(Assembler::sllx_op3, Assembler::arith_op); 7341 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7342 ins_pipe(ialu_reg_reg); 7343%} 7344 7345// Register Shift Left Immediate 7346instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7347 match(Set dst (LShiftL src1 src2)); 7348 7349 size(4); 7350 format %{ "SLLX $src1,$src2,$dst" %} 7351 opcode(Assembler::sllx_op3, Assembler::arith_op); 7352 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7353 ins_pipe(ialu_reg_imm); 7354%} 7355 7356// Register Arithmetic Shift Right 7357instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7358 match(Set dst (RShiftI src1 src2)); 7359 size(4); 7360 format %{ "SRA $src1,$src2,$dst" %} 7361 opcode(Assembler::sra_op3, Assembler::arith_op); 7362 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7363 ins_pipe(ialu_reg_reg); 7364%} 7365 7366// Register Arithmetic Shift Right Immediate 7367instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7368 match(Set dst (RShiftI src1 src2)); 7369 7370 size(4); 7371 format %{ "SRA $src1,$src2,$dst" %} 7372 opcode(Assembler::sra_op3, Assembler::arith_op); 7373 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7374 ins_pipe(ialu_reg_imm); 7375%} 7376 7377// Register Shift Right Arithmatic Long 7378instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7379 match(Set dst (RShiftL src1 src2)); 7380 7381 size(4); 7382 format %{ "SRAX $src1,$src2,$dst" %} 7383 opcode(Assembler::srax_op3, Assembler::arith_op); 7384 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7385 ins_pipe(ialu_reg_reg); 7386%} 7387 7388// Register Shift Left Immediate 7389instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7390 match(Set dst (RShiftL src1 src2)); 7391 7392 size(4); 7393 format %{ "SRAX $src1,$src2,$dst" %} 7394 opcode(Assembler::srax_op3, Assembler::arith_op); 7395 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7396 ins_pipe(ialu_reg_imm); 7397%} 7398 7399// Register Shift Right 7400instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7401 match(Set dst (URShiftI src1 src2)); 7402 7403 size(4); 7404 format %{ "SRL $src1,$src2,$dst" %} 7405 opcode(Assembler::srl_op3, Assembler::arith_op); 7406 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7407 ins_pipe(ialu_reg_reg); 7408%} 7409 7410// Register Shift Right Immediate 7411instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7412 match(Set dst (URShiftI src1 src2)); 7413 7414 size(4); 7415 format %{ "SRL $src1,$src2,$dst" %} 7416 opcode(Assembler::srl_op3, Assembler::arith_op); 7417 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7418 ins_pipe(ialu_reg_imm); 7419%} 7420 7421// Register Shift Right 7422instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7423 match(Set dst (URShiftL src1 src2)); 7424 7425 size(4); 7426 format %{ "SRLX $src1,$src2,$dst" %} 7427 opcode(Assembler::srlx_op3, Assembler::arith_op); 7428 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7429 ins_pipe(ialu_reg_reg); 7430%} 7431 7432// Register Shift Right Immediate 7433instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7434 match(Set dst (URShiftL src1 src2)); 7435 7436 size(4); 7437 format %{ "SRLX $src1,$src2,$dst" %} 7438 opcode(Assembler::srlx_op3, Assembler::arith_op); 7439 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7440 ins_pipe(ialu_reg_imm); 7441%} 7442 7443// Register Shift Right Immediate with a CastP2X 7444instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7445 match(Set dst (URShiftL (CastP2X src1) src2)); 7446 size(4); 7447 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7448 opcode(Assembler::srlx_op3, Assembler::arith_op); 7449 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7450 ins_pipe(ialu_reg_imm); 7451%} 7452 7453 7454//----------Floating Point Arithmetic Instructions----------------------------- 7455 7456// Add float single precision 7457instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7458 match(Set dst (AddF src1 src2)); 7459 7460 size(4); 7461 format %{ "FADDS $src1,$src2,$dst" %} 7462 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7463 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7464 ins_pipe(faddF_reg_reg); 7465%} 7466 7467// Add float double precision 7468instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7469 match(Set dst (AddD src1 src2)); 7470 7471 size(4); 7472 format %{ "FADDD $src1,$src2,$dst" %} 7473 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7474 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7475 ins_pipe(faddD_reg_reg); 7476%} 7477 7478// Sub float single precision 7479instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7480 match(Set dst (SubF src1 src2)); 7481 7482 size(4); 7483 format %{ "FSUBS $src1,$src2,$dst" %} 7484 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7485 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7486 ins_pipe(faddF_reg_reg); 7487%} 7488 7489// Sub float double precision 7490instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7491 match(Set dst (SubD src1 src2)); 7492 7493 size(4); 7494 format %{ "FSUBD $src1,$src2,$dst" %} 7495 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7496 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7497 ins_pipe(faddD_reg_reg); 7498%} 7499 7500// Mul float single precision 7501instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7502 match(Set dst (MulF src1 src2)); 7503 7504 size(4); 7505 format %{ "FMULS $src1,$src2,$dst" %} 7506 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7507 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7508 ins_pipe(fmulF_reg_reg); 7509%} 7510 7511// Mul float double precision 7512instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7513 match(Set dst (MulD src1 src2)); 7514 7515 size(4); 7516 format %{ "FMULD $src1,$src2,$dst" %} 7517 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7518 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7519 ins_pipe(fmulD_reg_reg); 7520%} 7521 7522// Div float single precision 7523instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7524 match(Set dst (DivF src1 src2)); 7525 7526 size(4); 7527 format %{ "FDIVS $src1,$src2,$dst" %} 7528 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7529 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7530 ins_pipe(fdivF_reg_reg); 7531%} 7532 7533// Div float double precision 7534instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7535 match(Set dst (DivD src1 src2)); 7536 7537 size(4); 7538 format %{ "FDIVD $src1,$src2,$dst" %} 7539 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7540 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7541 ins_pipe(fdivD_reg_reg); 7542%} 7543 7544// Absolute float double precision 7545instruct absD_reg(regD dst, regD src) %{ 7546 match(Set dst (AbsD src)); 7547 7548 format %{ "FABSd $src,$dst" %} 7549 ins_encode(fabsd(dst, src)); 7550 ins_pipe(faddD_reg); 7551%} 7552 7553// Absolute float single precision 7554instruct absF_reg(regF dst, regF src) %{ 7555 match(Set dst (AbsF src)); 7556 7557 format %{ "FABSs $src,$dst" %} 7558 ins_encode(fabss(dst, src)); 7559 ins_pipe(faddF_reg); 7560%} 7561 7562instruct negF_reg(regF dst, regF src) %{ 7563 match(Set dst (NegF src)); 7564 7565 size(4); 7566 format %{ "FNEGs $src,$dst" %} 7567 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7568 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7569 ins_pipe(faddF_reg); 7570%} 7571 7572instruct negD_reg(regD dst, regD src) %{ 7573 match(Set dst (NegD src)); 7574 7575 format %{ "FNEGd $src,$dst" %} 7576 ins_encode(fnegd(dst, src)); 7577 ins_pipe(faddD_reg); 7578%} 7579 7580// Sqrt float double precision 7581instruct sqrtF_reg_reg(regF dst, regF src) %{ 7582 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7583 7584 size(4); 7585 format %{ "FSQRTS $src,$dst" %} 7586 ins_encode(fsqrts(dst, src)); 7587 ins_pipe(fdivF_reg_reg); 7588%} 7589 7590// Sqrt float double precision 7591instruct sqrtD_reg_reg(regD dst, regD src) %{ 7592 match(Set dst (SqrtD src)); 7593 7594 size(4); 7595 format %{ "FSQRTD $src,$dst" %} 7596 ins_encode(fsqrtd(dst, src)); 7597 ins_pipe(fdivD_reg_reg); 7598%} 7599 7600// Single precision fused floating-point multiply-add (d = a * b + c). 7601instruct fmaF_regx4(regF dst, regF a, regF b, regF c) %{ 7602 predicate(UseFMA); 7603 match(Set dst (FmaF c (Binary a b))); 7604 format %{ "fmadds $a,$b,$c,$dst\t# $dst = $a * $b + $c" %} 7605 ins_encode(fmadds(dst, a, b, c)); 7606 ins_pipe(fmaF_regx4); 7607%} 7608 7609// Double precision fused floating-point multiply-add (d = a * b + c). 7610instruct fmaD_regx4(regD dst, regD a, regD b, regD c) %{ 7611 predicate(UseFMA); 7612 match(Set dst (FmaD c (Binary a b))); 7613 format %{ "fmaddd $a,$b,$c,$dst\t# $dst = $a * $b + $c" %} 7614 ins_encode(fmaddd(dst, a, b, c)); 7615 ins_pipe(fmaD_regx4); 7616%} 7617 7618//----------Logical Instructions----------------------------------------------- 7619// And Instructions 7620// Register And 7621instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7622 match(Set dst (AndI src1 src2)); 7623 7624 size(4); 7625 format %{ "AND $src1,$src2,$dst" %} 7626 opcode(Assembler::and_op3, Assembler::arith_op); 7627 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7628 ins_pipe(ialu_reg_reg); 7629%} 7630 7631// Immediate And 7632instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7633 match(Set dst (AndI src1 src2)); 7634 7635 size(4); 7636 format %{ "AND $src1,$src2,$dst" %} 7637 opcode(Assembler::and_op3, Assembler::arith_op); 7638 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7639 ins_pipe(ialu_reg_imm); 7640%} 7641 7642// Register And Long 7643instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7644 match(Set dst (AndL src1 src2)); 7645 7646 ins_cost(DEFAULT_COST); 7647 size(4); 7648 format %{ "AND $src1,$src2,$dst\t! long" %} 7649 opcode(Assembler::and_op3, Assembler::arith_op); 7650 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7651 ins_pipe(ialu_reg_reg); 7652%} 7653 7654instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7655 match(Set dst (AndL src1 con)); 7656 7657 ins_cost(DEFAULT_COST); 7658 size(4); 7659 format %{ "AND $src1,$con,$dst\t! long" %} 7660 opcode(Assembler::and_op3, Assembler::arith_op); 7661 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7662 ins_pipe(ialu_reg_imm); 7663%} 7664 7665// Or Instructions 7666// Register Or 7667instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7668 match(Set dst (OrI src1 src2)); 7669 7670 size(4); 7671 format %{ "OR $src1,$src2,$dst" %} 7672 opcode(Assembler::or_op3, Assembler::arith_op); 7673 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7674 ins_pipe(ialu_reg_reg); 7675%} 7676 7677// Immediate Or 7678instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7679 match(Set dst (OrI src1 src2)); 7680 7681 size(4); 7682 format %{ "OR $src1,$src2,$dst" %} 7683 opcode(Assembler::or_op3, Assembler::arith_op); 7684 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7685 ins_pipe(ialu_reg_imm); 7686%} 7687 7688// Register Or Long 7689instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7690 match(Set dst (OrL src1 src2)); 7691 7692 ins_cost(DEFAULT_COST); 7693 size(4); 7694 format %{ "OR $src1,$src2,$dst\t! long" %} 7695 opcode(Assembler::or_op3, Assembler::arith_op); 7696 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7697 ins_pipe(ialu_reg_reg); 7698%} 7699 7700instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7701 match(Set dst (OrL src1 con)); 7702 ins_cost(DEFAULT_COST*2); 7703 7704 ins_cost(DEFAULT_COST); 7705 size(4); 7706 format %{ "OR $src1,$con,$dst\t! long" %} 7707 opcode(Assembler::or_op3, Assembler::arith_op); 7708 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7709 ins_pipe(ialu_reg_imm); 7710%} 7711 7712instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7713 match(Set dst (OrL src1 (CastP2X src2))); 7714 7715 ins_cost(DEFAULT_COST); 7716 size(4); 7717 format %{ "OR $src1,$src2,$dst\t! long" %} 7718 opcode(Assembler::or_op3, Assembler::arith_op); 7719 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7720 ins_pipe(ialu_reg_reg); 7721%} 7722 7723// Xor Instructions 7724// Register Xor 7725instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7726 match(Set dst (XorI src1 src2)); 7727 7728 size(4); 7729 format %{ "XOR $src1,$src2,$dst" %} 7730 opcode(Assembler::xor_op3, Assembler::arith_op); 7731 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7732 ins_pipe(ialu_reg_reg); 7733%} 7734 7735// Immediate Xor 7736instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7737 match(Set dst (XorI src1 src2)); 7738 7739 size(4); 7740 format %{ "XOR $src1,$src2,$dst" %} 7741 opcode(Assembler::xor_op3, Assembler::arith_op); 7742 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7743 ins_pipe(ialu_reg_imm); 7744%} 7745 7746// Register Xor Long 7747instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7748 match(Set dst (XorL src1 src2)); 7749 7750 ins_cost(DEFAULT_COST); 7751 size(4); 7752 format %{ "XOR $src1,$src2,$dst\t! long" %} 7753 opcode(Assembler::xor_op3, Assembler::arith_op); 7754 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7755 ins_pipe(ialu_reg_reg); 7756%} 7757 7758instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7759 match(Set dst (XorL src1 con)); 7760 7761 ins_cost(DEFAULT_COST); 7762 size(4); 7763 format %{ "XOR $src1,$con,$dst\t! long" %} 7764 opcode(Assembler::xor_op3, Assembler::arith_op); 7765 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7766 ins_pipe(ialu_reg_imm); 7767%} 7768 7769//----------Convert to Boolean------------------------------------------------- 7770// Nice hack for 32-bit tests but doesn't work for 7771// 64-bit pointers. 7772instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7773 match(Set dst (Conv2B src)); 7774 effect( KILL ccr ); 7775 ins_cost(DEFAULT_COST*2); 7776 format %{ "CMP R_G0,$src\n\t" 7777 "ADDX R_G0,0,$dst" %} 7778 ins_encode( enc_to_bool( src, dst ) ); 7779 ins_pipe(ialu_reg_ialu); 7780%} 7781 7782instruct convP2B( iRegI dst, iRegP src ) %{ 7783 match(Set dst (Conv2B src)); 7784 ins_cost(DEFAULT_COST*2); 7785 format %{ "MOV $src,$dst\n\t" 7786 "MOVRNZ $src,1,$dst" %} 7787 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 7788 ins_pipe(ialu_clr_and_mover); 7789%} 7790 7791instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{ 7792 match(Set dst (CmpLTMask src zero)); 7793 effect(KILL ccr); 7794 size(4); 7795 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %} 7796 ins_encode %{ 7797 __ sra($src$$Register, 31, $dst$$Register); 7798 %} 7799 ins_pipe(ialu_reg_imm); 7800%} 7801 7802instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 7803 match(Set dst (CmpLTMask p q)); 7804 effect( KILL ccr ); 7805 ins_cost(DEFAULT_COST*4); 7806 format %{ "CMP $p,$q\n\t" 7807 "MOV #0,$dst\n\t" 7808 "BLT,a .+8\n\t" 7809 "MOV #-1,$dst" %} 7810 ins_encode( enc_ltmask(p,q,dst) ); 7811 ins_pipe(ialu_reg_reg_ialu); 7812%} 7813 7814instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 7815 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 7816 effect(KILL ccr, TEMP tmp); 7817 ins_cost(DEFAULT_COST*3); 7818 7819 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 7820 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 7821 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %} 7822 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp)); 7823 ins_pipe(cadd_cmpltmask); 7824%} 7825 7826instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{ 7827 match(Set p (AndI (CmpLTMask p q) y)); 7828 effect(KILL ccr); 7829 ins_cost(DEFAULT_COST*3); 7830 7831 format %{ "CMP $p,$q\n\t" 7832 "MOV $y,$p\n\t" 7833 "MOVge G0,$p" %} 7834 ins_encode %{ 7835 __ cmp($p$$Register, $q$$Register); 7836 __ mov($y$$Register, $p$$Register); 7837 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register); 7838 %} 7839 ins_pipe(ialu_reg_reg_ialu); 7840%} 7841 7842//----------------------------------------------------------------- 7843// Direct raw moves between float and general registers using VIS3. 7844 7845// ins_pipe(faddF_reg); 7846instruct MoveF2I_reg_reg(iRegI dst, regF src) %{ 7847 predicate(UseVIS >= 3); 7848 match(Set dst (MoveF2I src)); 7849 7850 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %} 7851 ins_encode %{ 7852 __ movstouw($src$$FloatRegister, $dst$$Register); 7853 %} 7854 ins_pipe(ialu_reg_reg); 7855%} 7856 7857instruct MoveI2F_reg_reg(regF dst, iRegI src) %{ 7858 predicate(UseVIS >= 3); 7859 match(Set dst (MoveI2F src)); 7860 7861 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %} 7862 ins_encode %{ 7863 __ movwtos($src$$Register, $dst$$FloatRegister); 7864 %} 7865 ins_pipe(ialu_reg_reg); 7866%} 7867 7868instruct MoveD2L_reg_reg(iRegL dst, regD src) %{ 7869 predicate(UseVIS >= 3); 7870 match(Set dst (MoveD2L src)); 7871 7872 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %} 7873 ins_encode %{ 7874 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register); 7875 %} 7876 ins_pipe(ialu_reg_reg); 7877%} 7878 7879instruct MoveL2D_reg_reg(regD dst, iRegL src) %{ 7880 predicate(UseVIS >= 3); 7881 match(Set dst (MoveL2D src)); 7882 7883 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %} 7884 ins_encode %{ 7885 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg)); 7886 %} 7887 ins_pipe(ialu_reg_reg); 7888%} 7889 7890 7891// Raw moves between float and general registers using stack. 7892 7893instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 7894 match(Set dst (MoveF2I src)); 7895 effect(DEF dst, USE src); 7896 ins_cost(MEMORY_REF_COST); 7897 7898 format %{ "LDUW $src,$dst\t! MoveF2I" %} 7899 opcode(Assembler::lduw_op3); 7900 ins_encode(simple_form3_mem_reg( src, dst ) ); 7901 ins_pipe(iload_mem); 7902%} 7903 7904instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 7905 match(Set dst (MoveI2F src)); 7906 effect(DEF dst, USE src); 7907 ins_cost(MEMORY_REF_COST); 7908 7909 format %{ "LDF $src,$dst\t! MoveI2F" %} 7910 opcode(Assembler::ldf_op3); 7911 ins_encode(simple_form3_mem_reg(src, dst)); 7912 ins_pipe(floadF_stk); 7913%} 7914 7915instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 7916 match(Set dst (MoveD2L src)); 7917 effect(DEF dst, USE src); 7918 ins_cost(MEMORY_REF_COST); 7919 7920 format %{ "LDX $src,$dst\t! MoveD2L" %} 7921 opcode(Assembler::ldx_op3); 7922 ins_encode(simple_form3_mem_reg( src, dst ) ); 7923 ins_pipe(iload_mem); 7924%} 7925 7926instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 7927 match(Set dst (MoveL2D src)); 7928 effect(DEF dst, USE src); 7929 ins_cost(MEMORY_REF_COST); 7930 7931 format %{ "LDDF $src,$dst\t! MoveL2D" %} 7932 opcode(Assembler::lddf_op3); 7933 ins_encode(simple_form3_mem_reg(src, dst)); 7934 ins_pipe(floadD_stk); 7935%} 7936 7937instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 7938 match(Set dst (MoveF2I src)); 7939 effect(DEF dst, USE src); 7940 ins_cost(MEMORY_REF_COST); 7941 7942 format %{ "STF $src,$dst\t! MoveF2I" %} 7943 opcode(Assembler::stf_op3); 7944 ins_encode(simple_form3_mem_reg(dst, src)); 7945 ins_pipe(fstoreF_stk_reg); 7946%} 7947 7948instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 7949 match(Set dst (MoveI2F src)); 7950 effect(DEF dst, USE src); 7951 ins_cost(MEMORY_REF_COST); 7952 7953 format %{ "STW $src,$dst\t! MoveI2F" %} 7954 opcode(Assembler::stw_op3); 7955 ins_encode(simple_form3_mem_reg( dst, src ) ); 7956 ins_pipe(istore_mem_reg); 7957%} 7958 7959instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 7960 match(Set dst (MoveD2L src)); 7961 effect(DEF dst, USE src); 7962 ins_cost(MEMORY_REF_COST); 7963 7964 format %{ "STDF $src,$dst\t! MoveD2L" %} 7965 opcode(Assembler::stdf_op3); 7966 ins_encode(simple_form3_mem_reg(dst, src)); 7967 ins_pipe(fstoreD_stk_reg); 7968%} 7969 7970instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 7971 match(Set dst (MoveL2D src)); 7972 effect(DEF dst, USE src); 7973 ins_cost(MEMORY_REF_COST); 7974 7975 format %{ "STX $src,$dst\t! MoveL2D" %} 7976 opcode(Assembler::stx_op3); 7977 ins_encode(simple_form3_mem_reg( dst, src ) ); 7978 ins_pipe(istore_mem_reg); 7979%} 7980 7981 7982//----------Arithmetic Conversion Instructions--------------------------------- 7983// The conversions operations are all Alpha sorted. Please keep it that way! 7984 7985instruct convD2F_reg(regF dst, regD src) %{ 7986 match(Set dst (ConvD2F src)); 7987 size(4); 7988 format %{ "FDTOS $src,$dst" %} 7989 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 7990 ins_encode(form3_opf_rs2D_rdF(src, dst)); 7991 ins_pipe(fcvtD2F); 7992%} 7993 7994 7995// Convert a double to an int in a float register. 7996// If the double is a NAN, stuff a zero in instead. 7997instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 7998 effect(DEF dst, USE src, KILL fcc0); 7999 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8000 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8001 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8002 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8003 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8004 "skip:" %} 8005 ins_encode(form_d2i_helper(src,dst)); 8006 ins_pipe(fcvtD2I); 8007%} 8008 8009instruct convD2I_stk(stackSlotI dst, regD src) %{ 8010 match(Set dst (ConvD2I src)); 8011 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8012 expand %{ 8013 regF tmp; 8014 convD2I_helper(tmp, src); 8015 regF_to_stkI(dst, tmp); 8016 %} 8017%} 8018 8019instruct convD2I_reg(iRegI dst, regD src) %{ 8020 predicate(UseVIS >= 3); 8021 match(Set dst (ConvD2I src)); 8022 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8023 expand %{ 8024 regF tmp; 8025 convD2I_helper(tmp, src); 8026 MoveF2I_reg_reg(dst, tmp); 8027 %} 8028%} 8029 8030 8031// Convert a double to a long in a double register. 8032// If the double is a NAN, stuff a zero in instead. 8033instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8034 effect(DEF dst, USE src, KILL fcc0); 8035 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8036 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8037 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8038 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8039 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8040 "skip:" %} 8041 ins_encode(form_d2l_helper(src,dst)); 8042 ins_pipe(fcvtD2L); 8043%} 8044 8045instruct convD2L_stk(stackSlotL dst, regD src) %{ 8046 match(Set dst (ConvD2L src)); 8047 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8048 expand %{ 8049 regD tmp; 8050 convD2L_helper(tmp, src); 8051 regD_to_stkL(dst, tmp); 8052 %} 8053%} 8054 8055instruct convD2L_reg(iRegL dst, regD src) %{ 8056 predicate(UseVIS >= 3); 8057 match(Set dst (ConvD2L src)); 8058 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8059 expand %{ 8060 regD tmp; 8061 convD2L_helper(tmp, src); 8062 MoveD2L_reg_reg(dst, tmp); 8063 %} 8064%} 8065 8066 8067instruct convF2D_reg(regD dst, regF src) %{ 8068 match(Set dst (ConvF2D src)); 8069 format %{ "FSTOD $src,$dst" %} 8070 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8071 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8072 ins_pipe(fcvtF2D); 8073%} 8074 8075 8076// Convert a float to an int in a float register. 8077// If the float is a NAN, stuff a zero in instead. 8078instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8079 effect(DEF dst, USE src, KILL fcc0); 8080 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8081 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8082 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8083 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8084 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8085 "skip:" %} 8086 ins_encode(form_f2i_helper(src,dst)); 8087 ins_pipe(fcvtF2I); 8088%} 8089 8090instruct convF2I_stk(stackSlotI dst, regF src) %{ 8091 match(Set dst (ConvF2I src)); 8092 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8093 expand %{ 8094 regF tmp; 8095 convF2I_helper(tmp, src); 8096 regF_to_stkI(dst, tmp); 8097 %} 8098%} 8099 8100instruct convF2I_reg(iRegI dst, regF src) %{ 8101 predicate(UseVIS >= 3); 8102 match(Set dst (ConvF2I src)); 8103 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8104 expand %{ 8105 regF tmp; 8106 convF2I_helper(tmp, src); 8107 MoveF2I_reg_reg(dst, tmp); 8108 %} 8109%} 8110 8111 8112// Convert a float to a long in a float register. 8113// If the float is a NAN, stuff a zero in instead. 8114instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8115 effect(DEF dst, USE src, KILL fcc0); 8116 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8117 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8118 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8119 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8120 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8121 "skip:" %} 8122 ins_encode(form_f2l_helper(src,dst)); 8123 ins_pipe(fcvtF2L); 8124%} 8125 8126instruct convF2L_stk(stackSlotL dst, regF src) %{ 8127 match(Set dst (ConvF2L src)); 8128 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8129 expand %{ 8130 regD tmp; 8131 convF2L_helper(tmp, src); 8132 regD_to_stkL(dst, tmp); 8133 %} 8134%} 8135 8136instruct convF2L_reg(iRegL dst, regF src) %{ 8137 predicate(UseVIS >= 3); 8138 match(Set dst (ConvF2L src)); 8139 ins_cost(DEFAULT_COST*2 + BRANCH_COST); 8140 expand %{ 8141 regD tmp; 8142 convF2L_helper(tmp, src); 8143 MoveD2L_reg_reg(dst, tmp); 8144 %} 8145%} 8146 8147 8148instruct convI2D_helper(regD dst, regF tmp) %{ 8149 effect(USE tmp, DEF dst); 8150 format %{ "FITOD $tmp,$dst" %} 8151 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8152 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8153 ins_pipe(fcvtI2D); 8154%} 8155 8156instruct convI2D_stk(stackSlotI src, regD dst) %{ 8157 match(Set dst (ConvI2D src)); 8158 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8159 expand %{ 8160 regF tmp; 8161 stkI_to_regF(tmp, src); 8162 convI2D_helper(dst, tmp); 8163 %} 8164%} 8165 8166instruct convI2D_reg(regD_low dst, iRegI src) %{ 8167 predicate(UseVIS >= 3); 8168 match(Set dst (ConvI2D src)); 8169 expand %{ 8170 regF tmp; 8171 MoveI2F_reg_reg(tmp, src); 8172 convI2D_helper(dst, tmp); 8173 %} 8174%} 8175 8176instruct convI2D_mem(regD_low dst, memory mem) %{ 8177 match(Set dst (ConvI2D (LoadI mem))); 8178 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8179 format %{ "LDF $mem,$dst\n\t" 8180 "FITOD $dst,$dst" %} 8181 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8182 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8183 ins_pipe(floadF_mem); 8184%} 8185 8186 8187instruct convI2F_helper(regF dst, regF tmp) %{ 8188 effect(DEF dst, USE tmp); 8189 format %{ "FITOS $tmp,$dst" %} 8190 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8191 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8192 ins_pipe(fcvtI2F); 8193%} 8194 8195instruct convI2F_stk(regF dst, stackSlotI src) %{ 8196 match(Set dst (ConvI2F src)); 8197 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8198 expand %{ 8199 regF tmp; 8200 stkI_to_regF(tmp,src); 8201 convI2F_helper(dst, tmp); 8202 %} 8203%} 8204 8205instruct convI2F_reg(regF dst, iRegI src) %{ 8206 predicate(UseVIS >= 3); 8207 match(Set dst (ConvI2F src)); 8208 ins_cost(DEFAULT_COST); 8209 expand %{ 8210 regF tmp; 8211 MoveI2F_reg_reg(tmp, src); 8212 convI2F_helper(dst, tmp); 8213 %} 8214%} 8215 8216instruct convI2F_mem( regF dst, memory mem ) %{ 8217 match(Set dst (ConvI2F (LoadI mem))); 8218 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8219 format %{ "LDF $mem,$dst\n\t" 8220 "FITOS $dst,$dst" %} 8221 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8222 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8223 ins_pipe(floadF_mem); 8224%} 8225 8226 8227instruct convI2L_reg(iRegL dst, iRegI src) %{ 8228 match(Set dst (ConvI2L src)); 8229 size(4); 8230 format %{ "SRA $src,0,$dst\t! int->long" %} 8231 opcode(Assembler::sra_op3, Assembler::arith_op); 8232 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8233 ins_pipe(ialu_reg_reg); 8234%} 8235 8236// Zero-extend convert int to long 8237instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8238 match(Set dst (AndL (ConvI2L src) mask) ); 8239 size(4); 8240 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8241 opcode(Assembler::srl_op3, Assembler::arith_op); 8242 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8243 ins_pipe(ialu_reg_reg); 8244%} 8245 8246// Zero-extend long 8247instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8248 match(Set dst (AndL src mask) ); 8249 size(4); 8250 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8251 opcode(Assembler::srl_op3, Assembler::arith_op); 8252 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8253 ins_pipe(ialu_reg_reg); 8254%} 8255 8256 8257//----------- 8258// Long to Double conversion using V8 opcodes. 8259// Still useful because cheetah traps and becomes 8260// amazingly slow for some common numbers. 8261 8262// Magic constant, 0x43300000 8263instruct loadConI_x43300000(iRegI dst) %{ 8264 effect(DEF dst); 8265 size(4); 8266 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8267 ins_encode(SetHi22(0x43300000, dst)); 8268 ins_pipe(ialu_none); 8269%} 8270 8271// Magic constant, 0x41f00000 8272instruct loadConI_x41f00000(iRegI dst) %{ 8273 effect(DEF dst); 8274 size(4); 8275 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8276 ins_encode(SetHi22(0x41f00000, dst)); 8277 ins_pipe(ialu_none); 8278%} 8279 8280// Construct a double from two float halves 8281instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8282 effect(DEF dst, USE src1, USE src2); 8283 size(8); 8284 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8285 "FMOVS $src2.lo,$dst.lo" %} 8286 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8287 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8288 ins_pipe(faddD_reg_reg); 8289%} 8290 8291// Convert integer in high half of a double register (in the lower half of 8292// the double register file) to double 8293instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8294 effect(DEF dst, USE src); 8295 size(4); 8296 format %{ "FITOD $src,$dst" %} 8297 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8298 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8299 ins_pipe(fcvtLHi2D); 8300%} 8301 8302// Add float double precision 8303instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8304 effect(DEF dst, USE src1, USE src2); 8305 size(4); 8306 format %{ "FADDD $src1,$src2,$dst" %} 8307 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8308 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8309 ins_pipe(faddD_reg_reg); 8310%} 8311 8312// Sub float double precision 8313instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8314 effect(DEF dst, USE src1, USE src2); 8315 size(4); 8316 format %{ "FSUBD $src1,$src2,$dst" %} 8317 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8318 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8319 ins_pipe(faddD_reg_reg); 8320%} 8321 8322// Mul float double precision 8323instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8324 effect(DEF dst, USE src1, USE src2); 8325 size(4); 8326 format %{ "FMULD $src1,$src2,$dst" %} 8327 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8328 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8329 ins_pipe(fmulD_reg_reg); 8330%} 8331 8332// Long to Double conversion using fast fxtof 8333instruct convL2D_helper(regD dst, regD tmp) %{ 8334 effect(DEF dst, USE tmp); 8335 size(4); 8336 format %{ "FXTOD $tmp,$dst" %} 8337 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8338 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8339 ins_pipe(fcvtL2D); 8340%} 8341 8342instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{ 8343 match(Set dst (ConvL2D src)); 8344 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8345 expand %{ 8346 regD tmp; 8347 stkL_to_regD(tmp, src); 8348 convL2D_helper(dst, tmp); 8349 %} 8350%} 8351 8352instruct convL2D_reg(regD dst, iRegL src) %{ 8353 predicate(UseVIS >= 3); 8354 match(Set dst (ConvL2D src)); 8355 expand %{ 8356 regD tmp; 8357 MoveL2D_reg_reg(tmp, src); 8358 convL2D_helper(dst, tmp); 8359 %} 8360%} 8361 8362// Long to Float conversion using fast fxtof 8363instruct convL2F_helper(regF dst, regD tmp) %{ 8364 effect(DEF dst, USE tmp); 8365 size(4); 8366 format %{ "FXTOS $tmp,$dst" %} 8367 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8368 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8369 ins_pipe(fcvtL2F); 8370%} 8371 8372instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{ 8373 match(Set dst (ConvL2F src)); 8374 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8375 expand %{ 8376 regD tmp; 8377 stkL_to_regD(tmp, src); 8378 convL2F_helper(dst, tmp); 8379 %} 8380%} 8381 8382instruct convL2F_reg(regF dst, iRegL src) %{ 8383 predicate(UseVIS >= 3); 8384 match(Set dst (ConvL2F src)); 8385 ins_cost(DEFAULT_COST); 8386 expand %{ 8387 regD tmp; 8388 MoveL2D_reg_reg(tmp, src); 8389 convL2F_helper(dst, tmp); 8390 %} 8391%} 8392 8393//----------- 8394 8395instruct convL2I_reg(iRegI dst, iRegL src) %{ 8396 match(Set dst (ConvL2I src)); 8397 size(4); 8398 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8399 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8400 ins_pipe(ialu_reg); 8401%} 8402 8403// Register Shift Right Immediate 8404instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8405 match(Set dst (ConvL2I (RShiftL src cnt))); 8406 8407 size(4); 8408 format %{ "SRAX $src,$cnt,$dst" %} 8409 opcode(Assembler::srax_op3, Assembler::arith_op); 8410 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8411 ins_pipe(ialu_reg_imm); 8412%} 8413 8414//----------Control Flow Instructions------------------------------------------ 8415// Compare Instructions 8416// Compare Integers 8417instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8418 match(Set icc (CmpI op1 op2)); 8419 effect( DEF icc, USE op1, USE op2 ); 8420 8421 size(4); 8422 format %{ "CMP $op1,$op2" %} 8423 opcode(Assembler::subcc_op3, Assembler::arith_op); 8424 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8425 ins_pipe(ialu_cconly_reg_reg); 8426%} 8427 8428instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8429 match(Set icc (CmpU op1 op2)); 8430 8431 size(4); 8432 format %{ "CMP $op1,$op2\t! unsigned" %} 8433 opcode(Assembler::subcc_op3, Assembler::arith_op); 8434 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8435 ins_pipe(ialu_cconly_reg_reg); 8436%} 8437 8438instruct compUL_iReg(flagsRegUL xcc, iRegL op1, iRegL op2) %{ 8439 match(Set xcc (CmpUL op1 op2)); 8440 effect(DEF xcc, USE op1, USE op2); 8441 8442 size(4); 8443 format %{ "CMP $op1,$op2\t! unsigned long" %} 8444 opcode(Assembler::subcc_op3, Assembler::arith_op); 8445 ins_encode(form3_rs1_rs2_rd(op1, op2, R_G0)); 8446 ins_pipe(ialu_cconly_reg_reg); 8447%} 8448 8449instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8450 match(Set icc (CmpI op1 op2)); 8451 effect( DEF icc, USE op1 ); 8452 8453 size(4); 8454 format %{ "CMP $op1,$op2" %} 8455 opcode(Assembler::subcc_op3, Assembler::arith_op); 8456 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8457 ins_pipe(ialu_cconly_reg_imm); 8458%} 8459 8460instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8461 match(Set icc (CmpI (AndI op1 op2) zero)); 8462 8463 size(4); 8464 format %{ "BTST $op2,$op1" %} 8465 opcode(Assembler::andcc_op3, Assembler::arith_op); 8466 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8467 ins_pipe(ialu_cconly_reg_reg_zero); 8468%} 8469 8470instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8471 match(Set icc (CmpI (AndI op1 op2) zero)); 8472 8473 size(4); 8474 format %{ "BTST $op2,$op1" %} 8475 opcode(Assembler::andcc_op3, Assembler::arith_op); 8476 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8477 ins_pipe(ialu_cconly_reg_imm_zero); 8478%} 8479 8480instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8481 match(Set xcc (CmpL op1 op2)); 8482 effect( DEF xcc, USE op1, USE op2 ); 8483 8484 size(4); 8485 format %{ "CMP $op1,$op2\t\t! long" %} 8486 opcode(Assembler::subcc_op3, Assembler::arith_op); 8487 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8488 ins_pipe(ialu_cconly_reg_reg); 8489%} 8490 8491instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8492 match(Set xcc (CmpL op1 con)); 8493 effect( DEF xcc, USE op1, USE con ); 8494 8495 size(4); 8496 format %{ "CMP $op1,$con\t\t! long" %} 8497 opcode(Assembler::subcc_op3, Assembler::arith_op); 8498 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8499 ins_pipe(ialu_cconly_reg_reg); 8500%} 8501 8502instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8503 match(Set xcc (CmpL (AndL op1 op2) zero)); 8504 effect( DEF xcc, USE op1, USE op2 ); 8505 8506 size(4); 8507 format %{ "BTST $op1,$op2\t\t! long" %} 8508 opcode(Assembler::andcc_op3, Assembler::arith_op); 8509 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8510 ins_pipe(ialu_cconly_reg_reg); 8511%} 8512 8513// useful for checking the alignment of a pointer: 8514instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8515 match(Set xcc (CmpL (AndL op1 con) zero)); 8516 effect( DEF xcc, USE op1, USE con ); 8517 8518 size(4); 8519 format %{ "BTST $op1,$con\t\t! long" %} 8520 opcode(Assembler::andcc_op3, Assembler::arith_op); 8521 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8522 ins_pipe(ialu_cconly_reg_reg); 8523%} 8524 8525instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{ 8526 match(Set icc (CmpU op1 op2)); 8527 8528 size(4); 8529 format %{ "CMP $op1,$op2\t! unsigned" %} 8530 opcode(Assembler::subcc_op3, Assembler::arith_op); 8531 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8532 ins_pipe(ialu_cconly_reg_imm); 8533%} 8534 8535instruct compUL_iReg_imm13(flagsRegUL xcc, iRegL op1, immUL12 op2) %{ 8536 match(Set xcc (CmpUL op1 op2)); 8537 effect(DEF xcc, USE op1, USE op2); 8538 8539 size(4); 8540 format %{ "CMP $op1,$op2\t! unsigned long" %} 8541 opcode(Assembler::subcc_op3, Assembler::arith_op); 8542 ins_encode(form3_rs1_simm13_rd(op1, op2, R_G0)); 8543 ins_pipe(ialu_cconly_reg_imm); 8544%} 8545 8546// Compare Pointers 8547instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8548 match(Set pcc (CmpP op1 op2)); 8549 8550 size(4); 8551 format %{ "CMP $op1,$op2\t! ptr" %} 8552 opcode(Assembler::subcc_op3, Assembler::arith_op); 8553 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8554 ins_pipe(ialu_cconly_reg_reg); 8555%} 8556 8557instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8558 match(Set pcc (CmpP op1 op2)); 8559 8560 size(4); 8561 format %{ "CMP $op1,$op2\t! ptr" %} 8562 opcode(Assembler::subcc_op3, Assembler::arith_op); 8563 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8564 ins_pipe(ialu_cconly_reg_imm); 8565%} 8566 8567// Compare Narrow oops 8568instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8569 match(Set icc (CmpN op1 op2)); 8570 8571 size(4); 8572 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8573 opcode(Assembler::subcc_op3, Assembler::arith_op); 8574 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8575 ins_pipe(ialu_cconly_reg_reg); 8576%} 8577 8578instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8579 match(Set icc (CmpN op1 op2)); 8580 8581 size(4); 8582 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8583 opcode(Assembler::subcc_op3, Assembler::arith_op); 8584 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8585 ins_pipe(ialu_cconly_reg_imm); 8586%} 8587 8588//----------Max and Min-------------------------------------------------------- 8589// Min Instructions 8590// Conditional move for min 8591instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8592 effect( USE_DEF op2, USE op1, USE icc ); 8593 8594 size(4); 8595 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8596 opcode(Assembler::less); 8597 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8598 ins_pipe(ialu_reg_flags); 8599%} 8600 8601// Min Register with Register. 8602instruct minI_eReg(iRegI op1, iRegI op2) %{ 8603 match(Set op2 (MinI op1 op2)); 8604 ins_cost(DEFAULT_COST*2); 8605 expand %{ 8606 flagsReg icc; 8607 compI_iReg(icc,op1,op2); 8608 cmovI_reg_lt(op2,op1,icc); 8609 %} 8610%} 8611 8612// Max Instructions 8613// Conditional move for max 8614instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8615 effect( USE_DEF op2, USE op1, USE icc ); 8616 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8617 opcode(Assembler::greater); 8618 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8619 ins_pipe(ialu_reg_flags); 8620%} 8621 8622// Max Register with Register 8623instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8624 match(Set op2 (MaxI op1 op2)); 8625 ins_cost(DEFAULT_COST*2); 8626 expand %{ 8627 flagsReg icc; 8628 compI_iReg(icc,op1,op2); 8629 cmovI_reg_gt(op2,op1,icc); 8630 %} 8631%} 8632 8633 8634//----------Float Compares---------------------------------------------------- 8635// Compare floating, generate condition code 8636instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8637 match(Set fcc (CmpF src1 src2)); 8638 8639 size(4); 8640 format %{ "FCMPs $fcc,$src1,$src2" %} 8641 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8642 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8643 ins_pipe(faddF_fcc_reg_reg_zero); 8644%} 8645 8646instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8647 match(Set fcc (CmpD src1 src2)); 8648 8649 size(4); 8650 format %{ "FCMPd $fcc,$src1,$src2" %} 8651 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8652 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8653 ins_pipe(faddD_fcc_reg_reg_zero); 8654%} 8655 8656 8657// Compare floating, generate -1,0,1 8658instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8659 match(Set dst (CmpF3 src1 src2)); 8660 effect(KILL fcc0); 8661 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8662 format %{ "fcmpl $dst,$src1,$src2" %} 8663 // Primary = float 8664 opcode( true ); 8665 ins_encode( floating_cmp( dst, src1, src2 ) ); 8666 ins_pipe( floating_cmp ); 8667%} 8668 8669instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8670 match(Set dst (CmpD3 src1 src2)); 8671 effect(KILL fcc0); 8672 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8673 format %{ "dcmpl $dst,$src1,$src2" %} 8674 // Primary = double (not float) 8675 opcode( false ); 8676 ins_encode( floating_cmp( dst, src1, src2 ) ); 8677 ins_pipe( floating_cmp ); 8678%} 8679 8680//----------Branches--------------------------------------------------------- 8681// Jump 8682// (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8683instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8684 match(Jump switch_val); 8685 effect(TEMP table); 8686 8687 ins_cost(350); 8688 8689 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t" 8690 "LD [O7 + $switch_val], O7\n\t" 8691 "JUMP O7" %} 8692 ins_encode %{ 8693 // Calculate table address into a register. 8694 Register table_reg; 8695 Register label_reg = O7; 8696 // If we are calculating the size of this instruction don't trust 8697 // zero offsets because they might change when 8698 // MachConstantBaseNode decides to optimize the constant table 8699 // base. 8700 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) { 8701 table_reg = $constanttablebase; 8702 } else { 8703 table_reg = O7; 8704 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7); 8705 __ add($constanttablebase, con_offset, table_reg); 8706 } 8707 8708 // Jump to base address + switch value 8709 __ ld_ptr(table_reg, $switch_val$$Register, label_reg); 8710 __ jmp(label_reg, G0); 8711 __ delayed()->nop(); 8712 %} 8713 ins_pipe(ialu_reg_reg); 8714%} 8715 8716// Direct Branch. Use V8 version with longer range. 8717instruct branch(label labl) %{ 8718 match(Goto); 8719 effect(USE labl); 8720 8721 size(8); 8722 ins_cost(BRANCH_COST); 8723 format %{ "BA $labl" %} 8724 ins_encode %{ 8725 Label* L = $labl$$label; 8726 __ ba(*L); 8727 __ delayed()->nop(); 8728 %} 8729 ins_avoid_back_to_back(AVOID_BEFORE); 8730 ins_pipe(br); 8731%} 8732 8733// Direct Branch, short with no delay slot 8734instruct branch_short(label labl) %{ 8735 match(Goto); 8736 predicate(UseCBCond); 8737 effect(USE labl); 8738 8739 size(4); // Assuming no NOP inserted. 8740 ins_cost(BRANCH_COST); 8741 format %{ "BA $labl\t! short branch" %} 8742 ins_encode %{ 8743 Label* L = $labl$$label; 8744 assert(__ use_cbcond(*L), "back to back cbcond"); 8745 __ ba_short(*L); 8746 %} 8747 ins_short_branch(1); 8748 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 8749 ins_pipe(cbcond_reg_imm); 8750%} 8751 8752// Conditional Direct Branch 8753instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8754 match(If cmp icc); 8755 effect(USE labl); 8756 8757 size(8); 8758 ins_cost(BRANCH_COST); 8759 format %{ "BP$cmp $icc,$labl" %} 8760 // Prim = bits 24-22, Secnd = bits 31-30 8761 ins_encode( enc_bp( labl, cmp, icc ) ); 8762 ins_avoid_back_to_back(AVOID_BEFORE); 8763 ins_pipe(br_cc); 8764%} 8765 8766instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8767 match(If cmp icc); 8768 effect(USE labl); 8769 8770 ins_cost(BRANCH_COST); 8771 format %{ "BP$cmp $icc,$labl" %} 8772 // Prim = bits 24-22, Secnd = bits 31-30 8773 ins_encode( enc_bp( labl, cmp, icc ) ); 8774 ins_avoid_back_to_back(AVOID_BEFORE); 8775 ins_pipe(br_cc); 8776%} 8777 8778instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 8779 match(If cmp pcc); 8780 effect(USE labl); 8781 8782 size(8); 8783 ins_cost(BRANCH_COST); 8784 format %{ "BP$cmp $pcc,$labl" %} 8785 ins_encode %{ 8786 Label* L = $labl$$label; 8787 Assembler::Predict predict_taken = 8788 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8789 8790 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 8791 __ delayed()->nop(); 8792 %} 8793 ins_avoid_back_to_back(AVOID_BEFORE); 8794 ins_pipe(br_cc); 8795%} 8796 8797instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 8798 match(If cmp fcc); 8799 effect(USE labl); 8800 8801 size(8); 8802 ins_cost(BRANCH_COST); 8803 format %{ "FBP$cmp $fcc,$labl" %} 8804 ins_encode %{ 8805 Label* L = $labl$$label; 8806 Assembler::Predict predict_taken = 8807 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8808 8809 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L); 8810 __ delayed()->nop(); 8811 %} 8812 ins_avoid_back_to_back(AVOID_BEFORE); 8813 ins_pipe(br_fcc); 8814%} 8815 8816instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 8817 match(CountedLoopEnd cmp icc); 8818 effect(USE labl); 8819 8820 size(8); 8821 ins_cost(BRANCH_COST); 8822 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8823 // Prim = bits 24-22, Secnd = bits 31-30 8824 ins_encode( enc_bp( labl, cmp, icc ) ); 8825 ins_avoid_back_to_back(AVOID_BEFORE); 8826 ins_pipe(br_cc); 8827%} 8828 8829instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 8830 match(CountedLoopEnd cmp icc); 8831 effect(USE labl); 8832 8833 size(8); 8834 ins_cost(BRANCH_COST); 8835 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 8836 // Prim = bits 24-22, Secnd = bits 31-30 8837 ins_encode( enc_bp( labl, cmp, icc ) ); 8838 ins_avoid_back_to_back(AVOID_BEFORE); 8839 ins_pipe(br_cc); 8840%} 8841 8842// Compare and branch instructions 8843instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 8844 match(If cmp (CmpI op1 op2)); 8845 effect(USE labl, KILL icc); 8846 8847 size(12); 8848 ins_cost(BRANCH_COST); 8849 format %{ "CMP $op1,$op2\t! int\n\t" 8850 "BP$cmp $labl" %} 8851 ins_encode %{ 8852 Label* L = $labl$$label; 8853 Assembler::Predict predict_taken = 8854 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8855 __ cmp($op1$$Register, $op2$$Register); 8856 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8857 __ delayed()->nop(); 8858 %} 8859 ins_pipe(cmp_br_reg_reg); 8860%} 8861 8862instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 8863 match(If cmp (CmpI op1 op2)); 8864 effect(USE labl, KILL icc); 8865 8866 size(12); 8867 ins_cost(BRANCH_COST); 8868 format %{ "CMP $op1,$op2\t! int\n\t" 8869 "BP$cmp $labl" %} 8870 ins_encode %{ 8871 Label* L = $labl$$label; 8872 Assembler::Predict predict_taken = 8873 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8874 __ cmp($op1$$Register, $op2$$constant); 8875 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8876 __ delayed()->nop(); 8877 %} 8878 ins_pipe(cmp_br_reg_imm); 8879%} 8880 8881instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 8882 match(If cmp (CmpU op1 op2)); 8883 effect(USE labl, KILL icc); 8884 8885 size(12); 8886 ins_cost(BRANCH_COST); 8887 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8888 "BP$cmp $labl" %} 8889 ins_encode %{ 8890 Label* L = $labl$$label; 8891 Assembler::Predict predict_taken = 8892 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8893 __ cmp($op1$$Register, $op2$$Register); 8894 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8895 __ delayed()->nop(); 8896 %} 8897 ins_pipe(cmp_br_reg_reg); 8898%} 8899 8900instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 8901 match(If cmp (CmpU op1 op2)); 8902 effect(USE labl, KILL icc); 8903 8904 size(12); 8905 ins_cost(BRANCH_COST); 8906 format %{ "CMP $op1,$op2\t! unsigned\n\t" 8907 "BP$cmp $labl" %} 8908 ins_encode %{ 8909 Label* L = $labl$$label; 8910 Assembler::Predict predict_taken = 8911 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8912 __ cmp($op1$$Register, $op2$$constant); 8913 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 8914 __ delayed()->nop(); 8915 %} 8916 ins_pipe(cmp_br_reg_imm); 8917%} 8918 8919instruct cmpUL_reg_branch(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ 8920 match(If cmp (CmpUL op1 op2)); 8921 effect(USE labl, KILL xcc); 8922 8923 size(12); 8924 ins_cost(BRANCH_COST); 8925 format %{ "CMP $op1,$op2\t! unsigned long\n\t" 8926 "BP$cmp $labl" %} 8927 ins_encode %{ 8928 Label* L = $labl$$label; 8929 Assembler::Predict predict_taken = 8930 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8931 __ cmp($op1$$Register, $op2$$Register); 8932 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8933 __ delayed()->nop(); 8934 %} 8935 ins_pipe(cmp_br_reg_reg); 8936%} 8937 8938instruct cmpUL_imm_branch(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ 8939 match(If cmp (CmpUL op1 op2)); 8940 effect(USE labl, KILL xcc); 8941 8942 size(12); 8943 ins_cost(BRANCH_COST); 8944 format %{ "CMP $op1,$op2\t! unsigned long\n\t" 8945 "BP$cmp $labl" %} 8946 ins_encode %{ 8947 Label* L = $labl$$label; 8948 Assembler::Predict predict_taken = 8949 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8950 __ cmp($op1$$Register, $op2$$constant); 8951 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8952 __ delayed()->nop(); 8953 %} 8954 ins_pipe(cmp_br_reg_imm); 8955%} 8956 8957instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 8958 match(If cmp (CmpL op1 op2)); 8959 effect(USE labl, KILL xcc); 8960 8961 size(12); 8962 ins_cost(BRANCH_COST); 8963 format %{ "CMP $op1,$op2\t! long\n\t" 8964 "BP$cmp $labl" %} 8965 ins_encode %{ 8966 Label* L = $labl$$label; 8967 Assembler::Predict predict_taken = 8968 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8969 __ cmp($op1$$Register, $op2$$Register); 8970 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8971 __ delayed()->nop(); 8972 %} 8973 ins_pipe(cmp_br_reg_reg); 8974%} 8975 8976instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 8977 match(If cmp (CmpL op1 op2)); 8978 effect(USE labl, KILL xcc); 8979 8980 size(12); 8981 ins_cost(BRANCH_COST); 8982 format %{ "CMP $op1,$op2\t! long\n\t" 8983 "BP$cmp $labl" %} 8984 ins_encode %{ 8985 Label* L = $labl$$label; 8986 Assembler::Predict predict_taken = 8987 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 8988 __ cmp($op1$$Register, $op2$$constant); 8989 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 8990 __ delayed()->nop(); 8991 %} 8992 ins_pipe(cmp_br_reg_imm); 8993%} 8994 8995// Compare Pointers and branch 8996instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 8997 match(If cmp (CmpP op1 op2)); 8998 effect(USE labl, KILL pcc); 8999 9000 size(12); 9001 ins_cost(BRANCH_COST); 9002 format %{ "CMP $op1,$op2\t! ptr\n\t" 9003 "B$cmp $labl" %} 9004 ins_encode %{ 9005 Label* L = $labl$$label; 9006 Assembler::Predict predict_taken = 9007 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9008 __ cmp($op1$$Register, $op2$$Register); 9009 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9010 __ delayed()->nop(); 9011 %} 9012 ins_pipe(cmp_br_reg_reg); 9013%} 9014 9015instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9016 match(If cmp (CmpP op1 null)); 9017 effect(USE labl, KILL pcc); 9018 9019 size(12); 9020 ins_cost(BRANCH_COST); 9021 format %{ "CMP $op1,0\t! ptr\n\t" 9022 "B$cmp $labl" %} 9023 ins_encode %{ 9024 Label* L = $labl$$label; 9025 Assembler::Predict predict_taken = 9026 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9027 __ cmp($op1$$Register, G0); 9028 // bpr() is not used here since it has shorter distance. 9029 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L); 9030 __ delayed()->nop(); 9031 %} 9032 ins_pipe(cmp_br_reg_reg); 9033%} 9034 9035instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9036 match(If cmp (CmpN op1 op2)); 9037 effect(USE labl, KILL icc); 9038 9039 size(12); 9040 ins_cost(BRANCH_COST); 9041 format %{ "CMP $op1,$op2\t! compressed ptr\n\t" 9042 "BP$cmp $labl" %} 9043 ins_encode %{ 9044 Label* L = $labl$$label; 9045 Assembler::Predict predict_taken = 9046 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9047 __ cmp($op1$$Register, $op2$$Register); 9048 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9049 __ delayed()->nop(); 9050 %} 9051 ins_pipe(cmp_br_reg_reg); 9052%} 9053 9054instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9055 match(If cmp (CmpN op1 null)); 9056 effect(USE labl, KILL icc); 9057 9058 size(12); 9059 ins_cost(BRANCH_COST); 9060 format %{ "CMP $op1,0\t! compressed ptr\n\t" 9061 "BP$cmp $labl" %} 9062 ins_encode %{ 9063 Label* L = $labl$$label; 9064 Assembler::Predict predict_taken = 9065 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9066 __ cmp($op1$$Register, G0); 9067 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9068 __ delayed()->nop(); 9069 %} 9070 ins_pipe(cmp_br_reg_reg); 9071%} 9072 9073// Loop back branch 9074instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9075 match(CountedLoopEnd cmp (CmpI op1 op2)); 9076 effect(USE labl, KILL icc); 9077 9078 size(12); 9079 ins_cost(BRANCH_COST); 9080 format %{ "CMP $op1,$op2\t! int\n\t" 9081 "BP$cmp $labl\t! Loop end" %} 9082 ins_encode %{ 9083 Label* L = $labl$$label; 9084 Assembler::Predict predict_taken = 9085 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9086 __ cmp($op1$$Register, $op2$$Register); 9087 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9088 __ delayed()->nop(); 9089 %} 9090 ins_pipe(cmp_br_reg_reg); 9091%} 9092 9093instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9094 match(CountedLoopEnd cmp (CmpI op1 op2)); 9095 effect(USE labl, KILL icc); 9096 9097 size(12); 9098 ins_cost(BRANCH_COST); 9099 format %{ "CMP $op1,$op2\t! int\n\t" 9100 "BP$cmp $labl\t! Loop end" %} 9101 ins_encode %{ 9102 Label* L = $labl$$label; 9103 Assembler::Predict predict_taken = 9104 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9105 __ cmp($op1$$Register, $op2$$constant); 9106 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L); 9107 __ delayed()->nop(); 9108 %} 9109 ins_pipe(cmp_br_reg_imm); 9110%} 9111 9112// Short compare and branch instructions 9113instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9114 match(If cmp (CmpI op1 op2)); 9115 predicate(UseCBCond); 9116 effect(USE labl, KILL icc); 9117 9118 size(4); // Assuming no NOP inserted. 9119 ins_cost(BRANCH_COST); 9120 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9121 ins_encode %{ 9122 Label* L = $labl$$label; 9123 assert(__ use_cbcond(*L), "back to back cbcond"); 9124 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9125 %} 9126 ins_short_branch(1); 9127 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9128 ins_pipe(cbcond_reg_reg); 9129%} 9130 9131instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9132 match(If cmp (CmpI op1 op2)); 9133 predicate(UseCBCond); 9134 effect(USE labl, KILL icc); 9135 9136 size(4); // Assuming no NOP inserted. 9137 ins_cost(BRANCH_COST); 9138 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %} 9139 ins_encode %{ 9140 Label* L = $labl$$label; 9141 assert(__ use_cbcond(*L), "back to back cbcond"); 9142 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9143 %} 9144 ins_short_branch(1); 9145 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9146 ins_pipe(cbcond_reg_imm); 9147%} 9148 9149instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{ 9150 match(If cmp (CmpU op1 op2)); 9151 predicate(UseCBCond); 9152 effect(USE labl, KILL icc); 9153 9154 size(4); // Assuming no NOP inserted. 9155 ins_cost(BRANCH_COST); 9156 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9157 ins_encode %{ 9158 Label* L = $labl$$label; 9159 assert(__ use_cbcond(*L), "back to back cbcond"); 9160 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9161 %} 9162 ins_short_branch(1); 9163 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9164 ins_pipe(cbcond_reg_reg); 9165%} 9166 9167instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{ 9168 match(If cmp (CmpU op1 op2)); 9169 predicate(UseCBCond); 9170 effect(USE labl, KILL icc); 9171 9172 size(4); // Assuming no NOP inserted. 9173 ins_cost(BRANCH_COST); 9174 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %} 9175 ins_encode %{ 9176 Label* L = $labl$$label; 9177 assert(__ use_cbcond(*L), "back to back cbcond"); 9178 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9179 %} 9180 ins_short_branch(1); 9181 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9182 ins_pipe(cbcond_reg_imm); 9183%} 9184 9185instruct cmpUL_reg_branch_short(cmpOpU cmp, iRegL op1, iRegL op2, label labl, flagsRegUL xcc) %{ 9186 match(If cmp (CmpUL op1 op2)); 9187 predicate(UseCBCond); 9188 effect(USE labl, KILL xcc); 9189 9190 size(4); 9191 ins_cost(BRANCH_COST); 9192 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} 9193 ins_encode %{ 9194 Label* L = $labl$$label; 9195 assert(__ use_cbcond(*L), "back to back cbcond"); 9196 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9197 %} 9198 ins_short_branch(1); 9199 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9200 ins_pipe(cbcond_reg_reg); 9201%} 9202 9203instruct cmpUL_imm_branch_short(cmpOpU cmp, iRegL op1, immL5 op2, label labl, flagsRegUL xcc) %{ 9204 match(If cmp (CmpUL op1 op2)); 9205 predicate(UseCBCond); 9206 effect(USE labl, KILL xcc); 9207 9208 size(4); 9209 ins_cost(BRANCH_COST); 9210 format %{ "CXB$cmp $op1,$op2,$labl\t! unsigned long" %} 9211 ins_encode %{ 9212 Label* L = $labl$$label; 9213 assert(__ use_cbcond(*L), "back to back cbcond"); 9214 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9215 %} 9216 ins_short_branch(1); 9217 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9218 ins_pipe(cbcond_reg_imm); 9219%} 9220 9221instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{ 9222 match(If cmp (CmpL op1 op2)); 9223 predicate(UseCBCond); 9224 effect(USE labl, KILL xcc); 9225 9226 size(4); // Assuming no NOP inserted. 9227 ins_cost(BRANCH_COST); 9228 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9229 ins_encode %{ 9230 Label* L = $labl$$label; 9231 assert(__ use_cbcond(*L), "back to back cbcond"); 9232 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L); 9233 %} 9234 ins_short_branch(1); 9235 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9236 ins_pipe(cbcond_reg_reg); 9237%} 9238 9239instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{ 9240 match(If cmp (CmpL op1 op2)); 9241 predicate(UseCBCond); 9242 effect(USE labl, KILL xcc); 9243 9244 size(4); // Assuming no NOP inserted. 9245 ins_cost(BRANCH_COST); 9246 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %} 9247 ins_encode %{ 9248 Label* L = $labl$$label; 9249 assert(__ use_cbcond(*L), "back to back cbcond"); 9250 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L); 9251 %} 9252 ins_short_branch(1); 9253 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9254 ins_pipe(cbcond_reg_imm); 9255%} 9256 9257// Compare Pointers and branch 9258instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{ 9259 match(If cmp (CmpP op1 op2)); 9260 predicate(UseCBCond); 9261 effect(USE labl, KILL pcc); 9262 9263 size(4); // Assuming no NOP inserted. 9264 ins_cost(BRANCH_COST); 9265 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %} 9266 ins_encode %{ 9267 Label* L = $labl$$label; 9268 assert(__ use_cbcond(*L), "back to back cbcond"); 9269 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L); 9270 %} 9271 ins_short_branch(1); 9272 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9273 ins_pipe(cbcond_reg_reg); 9274%} 9275 9276instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{ 9277 match(If cmp (CmpP op1 null)); 9278 predicate(UseCBCond); 9279 effect(USE labl, KILL pcc); 9280 9281 size(4); // Assuming no NOP inserted. 9282 ins_cost(BRANCH_COST); 9283 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %} 9284 ins_encode %{ 9285 Label* L = $labl$$label; 9286 assert(__ use_cbcond(*L), "back to back cbcond"); 9287 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L); 9288 %} 9289 ins_short_branch(1); 9290 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9291 ins_pipe(cbcond_reg_reg); 9292%} 9293 9294instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{ 9295 match(If cmp (CmpN op1 op2)); 9296 predicate(UseCBCond); 9297 effect(USE labl, KILL icc); 9298 9299 size(4); // Assuming no NOP inserted. 9300 ins_cost(BRANCH_COST); 9301 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %} 9302 ins_encode %{ 9303 Label* L = $labl$$label; 9304 assert(__ use_cbcond(*L), "back to back cbcond"); 9305 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9306 %} 9307 ins_short_branch(1); 9308 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9309 ins_pipe(cbcond_reg_reg); 9310%} 9311 9312instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{ 9313 match(If cmp (CmpN op1 null)); 9314 predicate(UseCBCond); 9315 effect(USE labl, KILL icc); 9316 9317 size(4); // Assuming no NOP inserted. 9318 ins_cost(BRANCH_COST); 9319 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %} 9320 ins_encode %{ 9321 Label* L = $labl$$label; 9322 assert(__ use_cbcond(*L), "back to back cbcond"); 9323 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L); 9324 %} 9325 ins_short_branch(1); 9326 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9327 ins_pipe(cbcond_reg_reg); 9328%} 9329 9330// Loop back branch 9331instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{ 9332 match(CountedLoopEnd cmp (CmpI op1 op2)); 9333 predicate(UseCBCond); 9334 effect(USE labl, KILL icc); 9335 9336 size(4); // Assuming no NOP inserted. 9337 ins_cost(BRANCH_COST); 9338 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9339 ins_encode %{ 9340 Label* L = $labl$$label; 9341 assert(__ use_cbcond(*L), "back to back cbcond"); 9342 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L); 9343 %} 9344 ins_short_branch(1); 9345 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9346 ins_pipe(cbcond_reg_reg); 9347%} 9348 9349instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{ 9350 match(CountedLoopEnd cmp (CmpI op1 op2)); 9351 predicate(UseCBCond); 9352 effect(USE labl, KILL icc); 9353 9354 size(4); // Assuming no NOP inserted. 9355 ins_cost(BRANCH_COST); 9356 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %} 9357 ins_encode %{ 9358 Label* L = $labl$$label; 9359 assert(__ use_cbcond(*L), "back to back cbcond"); 9360 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L); 9361 %} 9362 ins_short_branch(1); 9363 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER); 9364 ins_pipe(cbcond_reg_imm); 9365%} 9366 9367// Branch-on-register tests all 64 bits. We assume that values 9368// in 64-bit registers always remains zero or sign extended 9369// unless our code munges the high bits. Interrupts can chop 9370// the high order bits to zero or sign at any time. 9371instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 9372 match(If cmp (CmpI op1 zero)); 9373 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9374 effect(USE labl); 9375 9376 size(8); 9377 ins_cost(BRANCH_COST); 9378 format %{ "BR$cmp $op1,$labl" %} 9379 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9380 ins_avoid_back_to_back(AVOID_BEFORE); 9381 ins_pipe(br_reg); 9382%} 9383 9384instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 9385 match(If cmp (CmpP op1 null)); 9386 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9387 effect(USE labl); 9388 9389 size(8); 9390 ins_cost(BRANCH_COST); 9391 format %{ "BR$cmp $op1,$labl" %} 9392 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9393 ins_avoid_back_to_back(AVOID_BEFORE); 9394 ins_pipe(br_reg); 9395%} 9396 9397instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 9398 match(If cmp (CmpL op1 zero)); 9399 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 9400 effect(USE labl); 9401 9402 size(8); 9403 ins_cost(BRANCH_COST); 9404 format %{ "BR$cmp $op1,$labl" %} 9405 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9406 ins_avoid_back_to_back(AVOID_BEFORE); 9407 ins_pipe(br_reg); 9408%} 9409 9410 9411// ============================================================================ 9412// Long Compare 9413// 9414// Currently we hold longs in 2 registers. Comparing such values efficiently 9415// is tricky. The flavor of compare used depends on whether we are testing 9416// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9417// The GE test is the negated LT test. The LE test can be had by commuting 9418// the operands (yielding a GE test) and then negating; negate again for the 9419// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9420// NE test is negated from that. 9421 9422// Due to a shortcoming in the ADLC, it mixes up expressions like: 9423// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9424// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9425// are collapsed internally in the ADLC's dfa-gen code. The match for 9426// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9427// foo match ends up with the wrong leaf. One fix is to not match both 9428// reg-reg and reg-zero forms of long-compare. This is unfortunate because 9429// both forms beat the trinary form of long-compare and both are very useful 9430// on Intel which has so few registers. 9431 9432instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9433 match(If cmp xcc); 9434 effect(USE labl); 9435 9436 size(8); 9437 ins_cost(BRANCH_COST); 9438 format %{ "BP$cmp $xcc,$labl" %} 9439 ins_encode %{ 9440 Label* L = $labl$$label; 9441 Assembler::Predict predict_taken = 9442 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9443 9444 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9445 __ delayed()->nop(); 9446 %} 9447 ins_avoid_back_to_back(AVOID_BEFORE); 9448 ins_pipe(br_cc); 9449%} 9450 9451instruct branchConU_long(cmpOpU cmp, flagsRegUL xcc, label labl) %{ 9452 match(If cmp xcc); 9453 effect(USE labl); 9454 9455 size(8); 9456 ins_cost(BRANCH_COST); 9457 format %{ "BP$cmp $xcc,$labl" %} 9458 ins_encode %{ 9459 Label* L = $labl$$label; 9460 Assembler::Predict predict_taken = 9461 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn; 9462 9463 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L); 9464 __ delayed()->nop(); 9465 %} 9466 ins_avoid_back_to_back(AVOID_BEFORE); 9467 ins_pipe(br_cc); 9468%} 9469 9470// Manifest a CmpL3 result in an integer register. Very painful. 9471// This is the test to avoid. 9472instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9473 match(Set dst (CmpL3 src1 src2) ); 9474 effect( KILL ccr ); 9475 ins_cost(6*DEFAULT_COST); 9476 size(24); 9477 format %{ "CMP $src1,$src2\t\t! long\n" 9478 "\tBLT,a,pn done\n" 9479 "\tMOV -1,$dst\t! delay slot\n" 9480 "\tBGT,a,pn done\n" 9481 "\tMOV 1,$dst\t! delay slot\n" 9482 "\tCLR $dst\n" 9483 "done:" %} 9484 ins_encode( cmpl_flag(src1,src2,dst) ); 9485 ins_pipe(cmpL_reg); 9486%} 9487 9488// Conditional move 9489instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9490 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9491 ins_cost(150); 9492 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9493 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9494 ins_pipe(ialu_reg); 9495%} 9496 9497instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9498 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9499 ins_cost(140); 9500 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9501 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9502 ins_pipe(ialu_imm); 9503%} 9504 9505instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9506 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9507 ins_cost(150); 9508 format %{ "MOV$cmp $xcc,$src,$dst" %} 9509 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9510 ins_pipe(ialu_reg); 9511%} 9512 9513instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9514 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9515 ins_cost(140); 9516 format %{ "MOV$cmp $xcc,$src,$dst" %} 9517 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9518 ins_pipe(ialu_imm); 9519%} 9520 9521instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9522 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9523 ins_cost(150); 9524 format %{ "MOV$cmp $xcc,$src,$dst" %} 9525 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9526 ins_pipe(ialu_reg); 9527%} 9528 9529instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9530 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9531 ins_cost(150); 9532 format %{ "MOV$cmp $xcc,$src,$dst" %} 9533 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9534 ins_pipe(ialu_reg); 9535%} 9536 9537instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9538 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9539 ins_cost(140); 9540 format %{ "MOV$cmp $xcc,$src,$dst" %} 9541 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9542 ins_pipe(ialu_imm); 9543%} 9544 9545instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9546 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9547 ins_cost(150); 9548 opcode(0x101); 9549 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9550 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9551 ins_pipe(int_conditional_float_move); 9552%} 9553 9554instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9555 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9556 ins_cost(150); 9557 opcode(0x102); 9558 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9559 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9560 ins_pipe(int_conditional_float_move); 9561%} 9562 9563// ============================================================================ 9564// Safepoint Instruction 9565instruct safePoint_poll(iRegP poll) %{ 9566 match(SafePoint poll); 9567 effect(USE poll); 9568 9569 size(4); 9570 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9571 ins_encode %{ 9572 __ relocate(relocInfo::poll_type); 9573 __ ld_ptr($poll$$Register, 0, G0); 9574 %} 9575 ins_pipe(loadPollP); 9576%} 9577 9578// ============================================================================ 9579// Call Instructions 9580// Call Java Static Instruction 9581instruct CallStaticJavaDirect( method meth ) %{ 9582 match(CallStaticJava); 9583 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9584 effect(USE meth); 9585 9586 size(8); 9587 ins_cost(CALL_COST); 9588 format %{ "CALL,static ; NOP ==> " %} 9589 ins_encode( Java_Static_Call( meth ), call_epilog ); 9590 ins_avoid_back_to_back(AVOID_BEFORE); 9591 ins_pipe(simple_call); 9592%} 9593 9594// Call Java Static Instruction (method handle version) 9595instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9596 match(CallStaticJava); 9597 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9598 effect(USE meth, KILL l7_mh_SP_save); 9599 9600 size(16); 9601 ins_cost(CALL_COST); 9602 format %{ "CALL,static/MethodHandle" %} 9603 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9604 ins_pipe(simple_call); 9605%} 9606 9607// Call Java Dynamic Instruction 9608instruct CallDynamicJavaDirect( method meth ) %{ 9609 match(CallDynamicJava); 9610 effect(USE meth); 9611 9612 ins_cost(CALL_COST); 9613 format %{ "SET (empty),R_G5\n\t" 9614 "CALL,dynamic ; NOP ==> " %} 9615 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9616 ins_pipe(call); 9617%} 9618 9619// Call Runtime Instruction 9620instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9621 match(CallRuntime); 9622 effect(USE meth, KILL l7); 9623 ins_cost(CALL_COST); 9624 format %{ "CALL,runtime" %} 9625 ins_encode( Java_To_Runtime( meth ), 9626 call_epilog, adjust_long_from_native_call ); 9627 ins_avoid_back_to_back(AVOID_BEFORE); 9628 ins_pipe(simple_call); 9629%} 9630 9631// Call runtime without safepoint - same as CallRuntime 9632instruct CallLeafDirect(method meth, l7RegP l7) %{ 9633 match(CallLeaf); 9634 effect(USE meth, KILL l7); 9635 ins_cost(CALL_COST); 9636 format %{ "CALL,runtime leaf" %} 9637 ins_encode( Java_To_Runtime( meth ), 9638 call_epilog, 9639 adjust_long_from_native_call ); 9640 ins_avoid_back_to_back(AVOID_BEFORE); 9641 ins_pipe(simple_call); 9642%} 9643 9644// Call runtime without safepoint - same as CallLeaf 9645instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9646 match(CallLeafNoFP); 9647 effect(USE meth, KILL l7); 9648 ins_cost(CALL_COST); 9649 format %{ "CALL,runtime leaf nofp" %} 9650 ins_encode( Java_To_Runtime( meth ), 9651 call_epilog, 9652 adjust_long_from_native_call ); 9653 ins_avoid_back_to_back(AVOID_BEFORE); 9654 ins_pipe(simple_call); 9655%} 9656 9657// Tail Call; Jump from runtime stub to Java code. 9658// Also known as an 'interprocedural jump'. 9659// Target of jump will eventually return to caller. 9660// TailJump below removes the return address. 9661instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9662 match(TailCall jump_target method_oop ); 9663 9664 ins_cost(CALL_COST); 9665 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9666 ins_encode(form_jmpl(jump_target)); 9667 ins_avoid_back_to_back(AVOID_BEFORE); 9668 ins_pipe(tail_call); 9669%} 9670 9671 9672// Return Instruction 9673instruct Ret() %{ 9674 match(Return); 9675 9676 // The epilogue node did the ret already. 9677 size(0); 9678 format %{ "! return" %} 9679 ins_encode(); 9680 ins_pipe(empty); 9681%} 9682 9683 9684// Tail Jump; remove the return address; jump to target. 9685// TailCall above leaves the return address around. 9686// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9687// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9688// "restore" before this instruction (in Epilogue), we need to materialize it 9689// in %i0. 9690instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9691 match( TailJump jump_target ex_oop ); 9692 ins_cost(CALL_COST); 9693 format %{ "! discard R_O7\n\t" 9694 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9695 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9696 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9697 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9698 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9699 ins_avoid_back_to_back(AVOID_BEFORE); 9700 ins_pipe(tail_call); 9701%} 9702 9703// Create exception oop: created by stack-crawling runtime code. 9704// Created exception is now available to this handler, and is setup 9705// just prior to jumping to this handler. No code emitted. 9706instruct CreateException( o0RegP ex_oop ) 9707%{ 9708 match(Set ex_oop (CreateEx)); 9709 ins_cost(0); 9710 9711 size(0); 9712 // use the following format syntax 9713 format %{ "! exception oop is in R_O0; no code emitted" %} 9714 ins_encode(); 9715 ins_pipe(empty); 9716%} 9717 9718 9719// Rethrow exception: 9720// The exception oop will come in the first argument position. 9721// Then JUMP (not call) to the rethrow stub code. 9722instruct RethrowException() 9723%{ 9724 match(Rethrow); 9725 ins_cost(CALL_COST); 9726 9727 // use the following format syntax 9728 format %{ "Jmp rethrow_stub" %} 9729 ins_encode(enc_rethrow); 9730 ins_avoid_back_to_back(AVOID_BEFORE); 9731 ins_pipe(tail_call); 9732%} 9733 9734 9735// Die now 9736instruct ShouldNotReachHere( ) 9737%{ 9738 match(Halt); 9739 ins_cost(CALL_COST); 9740 9741 size(4); 9742 // Use the following format syntax 9743 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9744 ins_encode( form2_illtrap() ); 9745 ins_pipe(tail_call); 9746%} 9747 9748// ============================================================================ 9749// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9750// array for an instance of the superklass. Set a hidden internal cache on a 9751// hit (cache is checked with exposed code in gen_subtype_check()). Return 9752// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9753instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9754 match(Set index (PartialSubtypeCheck sub super)); 9755 effect( KILL pcc, KILL o7 ); 9756 ins_cost(DEFAULT_COST*10); 9757 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9758 ins_encode( enc_PartialSubtypeCheck() ); 9759 ins_avoid_back_to_back(AVOID_BEFORE); 9760 ins_pipe(partial_subtype_check_pipe); 9761%} 9762 9763instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9764 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9765 effect( KILL idx, KILL o7 ); 9766 ins_cost(DEFAULT_COST*10); 9767 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9768 ins_encode( enc_PartialSubtypeCheck() ); 9769 ins_avoid_back_to_back(AVOID_BEFORE); 9770 ins_pipe(partial_subtype_check_pipe); 9771%} 9772 9773 9774// ============================================================================ 9775// inlined locking and unlocking 9776 9777instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9778 match(Set pcc (FastLock object box)); 9779 9780 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9781 ins_cost(100); 9782 9783 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9784 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9785 ins_pipe(long_memory_op); 9786%} 9787 9788 9789instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{ 9790 match(Set pcc (FastUnlock object box)); 9791 effect(TEMP scratch2, USE_KILL box, KILL scratch); 9792 ins_cost(100); 9793 9794 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %} 9795 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9796 ins_pipe(long_memory_op); 9797%} 9798 9799// The encodings are generic. 9800instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9801 predicate(!use_block_zeroing(n->in(2)) ); 9802 match(Set dummy (ClearArray cnt base)); 9803 effect(TEMP temp, KILL ccr); 9804 ins_cost(300); 9805 format %{ "MOV $cnt,$temp\n" 9806 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9807 " BRge loop\t\t! Clearing loop\n" 9808 " STX G0,[$base+$temp]\t! delay slot" %} 9809 9810 ins_encode %{ 9811 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 9812 Register nof_bytes_arg = $cnt$$Register; 9813 Register nof_bytes_tmp = $temp$$Register; 9814 Register base_pointer_arg = $base$$Register; 9815 9816 Label loop; 9817 __ mov(nof_bytes_arg, nof_bytes_tmp); 9818 9819 // Loop and clear, walking backwards through the array. 9820 // nof_bytes_tmp (if >0) is always the number of bytes to zero 9821 __ bind(loop); 9822 __ deccc(nof_bytes_tmp, 8); 9823 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 9824 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 9825 // %%%% this mini-loop must not cross a cache boundary! 9826 %} 9827 ins_pipe(long_memory_op); 9828%} 9829 9830instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{ 9831 predicate(use_block_zeroing(n->in(2))); 9832 match(Set dummy (ClearArray cnt base)); 9833 effect(USE_KILL cnt, USE_KILL base, KILL ccr); 9834 ins_cost(300); 9835 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9836 9837 ins_encode %{ 9838 9839 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9840 Register to = $base$$Register; 9841 Register count = $cnt$$Register; 9842 9843 Label Ldone; 9844 __ nop(); // Separate short branches 9845 // Use BIS for zeroing (temp is not used). 9846 __ bis_zeroing(to, count, G0, Ldone); 9847 __ bind(Ldone); 9848 9849 %} 9850 ins_pipe(long_memory_op); 9851%} 9852 9853instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{ 9854 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit)); 9855 match(Set dummy (ClearArray cnt base)); 9856 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr); 9857 ins_cost(300); 9858 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %} 9859 9860 ins_encode %{ 9861 9862 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation"); 9863 Register to = $base$$Register; 9864 Register count = $cnt$$Register; 9865 Register temp = $tmp$$Register; 9866 9867 Label Ldone; 9868 __ nop(); // Separate short branches 9869 // Use BIS for zeroing 9870 __ bis_zeroing(to, count, temp, Ldone); 9871 __ bind(Ldone); 9872 9873 %} 9874 ins_pipe(long_memory_op); 9875%} 9876 9877instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9878 o7RegI tmp, flagsReg ccr) %{ 9879 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 9880 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9881 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9882 ins_cost(300); 9883 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9884 ins_encode %{ 9885 __ string_compare($str1$$Register, $str2$$Register, 9886 $cnt1$$Register, $cnt2$$Register, 9887 $tmp$$Register, $tmp$$Register, 9888 $result$$Register, StrIntrinsicNode::LL); 9889 %} 9890 ins_pipe(long_memory_op); 9891%} 9892 9893instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9894 o7RegI tmp, flagsReg ccr) %{ 9895 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 9896 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9897 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9898 ins_cost(300); 9899 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9900 ins_encode %{ 9901 __ string_compare($str1$$Register, $str2$$Register, 9902 $cnt1$$Register, $cnt2$$Register, 9903 $tmp$$Register, $tmp$$Register, 9904 $result$$Register, StrIntrinsicNode::UU); 9905 %} 9906 ins_pipe(long_memory_op); 9907%} 9908 9909instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9910 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9911 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 9912 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9913 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9914 ins_cost(300); 9915 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9916 ins_encode %{ 9917 __ string_compare($str1$$Register, $str2$$Register, 9918 $cnt1$$Register, $cnt2$$Register, 9919 $tmp1$$Register, $tmp2$$Register, 9920 $result$$Register, StrIntrinsicNode::LU); 9921 %} 9922 ins_pipe(long_memory_op); 9923%} 9924 9925instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9926 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{ 9927 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 9928 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9929 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2); 9930 ins_cost(300); 9931 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %} 9932 ins_encode %{ 9933 __ string_compare($str2$$Register, $str1$$Register, 9934 $cnt2$$Register, $cnt1$$Register, 9935 $tmp1$$Register, $tmp2$$Register, 9936 $result$$Register, StrIntrinsicNode::UL); 9937 %} 9938 ins_pipe(long_memory_op); 9939%} 9940 9941instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9942 o7RegI tmp, flagsReg ccr) %{ 9943 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 9944 match(Set result (StrEquals (Binary str1 str2) cnt)); 9945 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9946 ins_cost(300); 9947 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9948 ins_encode %{ 9949 __ array_equals(false, $str1$$Register, $str2$$Register, 9950 $cnt$$Register, $tmp$$Register, 9951 $result$$Register, true /* byte */); 9952 %} 9953 ins_pipe(long_memory_op); 9954%} 9955 9956instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9957 o7RegI tmp, flagsReg ccr) %{ 9958 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 9959 match(Set result (StrEquals (Binary str1 str2) cnt)); 9960 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9961 ins_cost(300); 9962 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %} 9963 ins_encode %{ 9964 __ array_equals(false, $str1$$Register, $str2$$Register, 9965 $cnt$$Register, $tmp$$Register, 9966 $result$$Register, false /* byte */); 9967 %} 9968 ins_pipe(long_memory_op); 9969%} 9970 9971instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9972 o7RegI tmp2, flagsReg ccr) %{ 9973 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 9974 match(Set result (AryEq ary1 ary2)); 9975 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9976 ins_cost(300); 9977 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9978 ins_encode %{ 9979 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9980 $tmp1$$Register, $tmp2$$Register, 9981 $result$$Register, true /* byte */); 9982 %} 9983 ins_pipe(long_memory_op); 9984%} 9985 9986instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9987 o7RegI tmp2, flagsReg ccr) %{ 9988 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 9989 match(Set result (AryEq ary1 ary2)); 9990 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9991 ins_cost(300); 9992 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9993 ins_encode %{ 9994 __ array_equals(true, $ary1$$Register, $ary2$$Register, 9995 $tmp1$$Register, $tmp2$$Register, 9996 $result$$Register, false /* byte */); 9997 %} 9998 ins_pipe(long_memory_op); 9999%} 10000 10001instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR, 10002 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L, 10003 flagsReg ccr) 10004%{ 10005 match(Set resultR (HasNegatives pAryR iSizeR)); 10006 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr); 10007 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %} 10008 ins_encode %{ 10009 __ has_negatives($pAryR$$Register, $iSizeR$$Register, 10010 $resultR$$Register, 10011 $tmp1L$$Register, $tmp2L$$Register, 10012 $tmp3L$$Register, $tmp4L$$Register); 10013 %} 10014 ins_pipe(long_memory_op); 10015%} 10016 10017// char[] to byte[] compression 10018instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{ 10019 predicate(UseVIS < 3); 10020 match(Set result (StrCompressedCopy src (Binary dst len))); 10021 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10022 ins_cost(300); 10023 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %} 10024 ins_encode %{ 10025 Label Ldone; 10026 __ signx($len$$Register); 10027 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn); 10028 __ delayed()->mov($len$$Register, $result$$Register); // copy count 10029 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone); 10030 __ bind(Ldone); 10031 %} 10032 ins_pipe(long_memory_op); 10033%} 10034 10035// fast char[] to byte[] compression using VIS instructions 10036instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, 10037 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4, 10038 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{ 10039 predicate(UseVIS >= 3); 10040 match(Set result (StrCompressedCopy src (Binary dst len))); 10041 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10042 ins_cost(300); 10043 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %} 10044 ins_encode %{ 10045 Label Ldone; 10046 __ signx($len$$Register); 10047 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register, 10048 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, 10049 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone); 10050 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10051 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone); 10052 __ bind(Ldone); 10053 %} 10054 ins_pipe(long_memory_op); 10055%} 10056 10057// byte[] to char[] inflation 10058instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10059 iRegL tmp, flagsReg ccr) %{ 10060 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10061 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10062 ins_cost(300); 10063 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %} 10064 ins_encode %{ 10065 Label Ldone; 10066 __ signx($len$$Register); 10067 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10068 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10069 __ bind(Ldone); 10070 %} 10071 ins_pipe(long_memory_op); 10072%} 10073 10074// fast byte[] to char[] inflation using VIS instructions 10075instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len, 10076 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{ 10077 predicate(UseVIS >= 3); 10078 match(Set dummy (StrInflatedCopy src (Binary dst len))); 10079 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr); 10080 ins_cost(300); 10081 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %} 10082 ins_encode %{ 10083 Label Ldone; 10084 __ signx($len$$Register); 10085 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, 10086 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone); 10087 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone); 10088 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone); 10089 __ bind(Ldone); 10090 %} 10091 ins_pipe(long_memory_op); 10092%} 10093 10094 10095//---------- Zeros Count Instructions ------------------------------------------ 10096 10097instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{ 10098 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10099 match(Set dst (CountLeadingZerosI src)); 10100 effect(TEMP dst, TEMP tmp, KILL cr); 10101 10102 // x |= (x >> 1); 10103 // x |= (x >> 2); 10104 // x |= (x >> 4); 10105 // x |= (x >> 8); 10106 // x |= (x >> 16); 10107 // return (WORDBITS - popc(x)); 10108 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 10109 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 10110 "OR $dst,$tmp,$dst\n\t" 10111 "SRL $dst,2,$tmp\n\t" 10112 "OR $dst,$tmp,$dst\n\t" 10113 "SRL $dst,4,$tmp\n\t" 10114 "OR $dst,$tmp,$dst\n\t" 10115 "SRL $dst,8,$tmp\n\t" 10116 "OR $dst,$tmp,$dst\n\t" 10117 "SRL $dst,16,$tmp\n\t" 10118 "OR $dst,$tmp,$dst\n\t" 10119 "POPC $dst,$dst\n\t" 10120 "MOV 32,$tmp\n\t" 10121 "SUB $tmp,$dst,$dst" %} 10122 ins_encode %{ 10123 Register Rdst = $dst$$Register; 10124 Register Rsrc = $src$$Register; 10125 Register Rtmp = $tmp$$Register; 10126 __ srl(Rsrc, 1, Rtmp); 10127 __ srl(Rsrc, 0, Rdst); 10128 __ or3(Rdst, Rtmp, Rdst); 10129 __ srl(Rdst, 2, Rtmp); 10130 __ or3(Rdst, Rtmp, Rdst); 10131 __ srl(Rdst, 4, Rtmp); 10132 __ or3(Rdst, Rtmp, Rdst); 10133 __ srl(Rdst, 8, Rtmp); 10134 __ or3(Rdst, Rtmp, Rdst); 10135 __ srl(Rdst, 16, Rtmp); 10136 __ or3(Rdst, Rtmp, Rdst); 10137 __ popc(Rdst, Rdst); 10138 __ mov(BitsPerInt, Rtmp); 10139 __ sub(Rtmp, Rdst, Rdst); 10140 %} 10141 ins_pipe(ialu_reg); 10142%} 10143 10144instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{ 10145 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10146 match(Set dst (CountLeadingZerosL src)); 10147 effect(TEMP dst, TEMP tmp, KILL cr); 10148 10149 // x |= (x >> 1); 10150 // x |= (x >> 2); 10151 // x |= (x >> 4); 10152 // x |= (x >> 8); 10153 // x |= (x >> 16); 10154 // x |= (x >> 32); 10155 // return (WORDBITS - popc(x)); 10156 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 10157 "OR $src,$tmp,$dst\n\t" 10158 "SRLX $dst,2,$tmp\n\t" 10159 "OR $dst,$tmp,$dst\n\t" 10160 "SRLX $dst,4,$tmp\n\t" 10161 "OR $dst,$tmp,$dst\n\t" 10162 "SRLX $dst,8,$tmp\n\t" 10163 "OR $dst,$tmp,$dst\n\t" 10164 "SRLX $dst,16,$tmp\n\t" 10165 "OR $dst,$tmp,$dst\n\t" 10166 "SRLX $dst,32,$tmp\n\t" 10167 "OR $dst,$tmp,$dst\n\t" 10168 "POPC $dst,$dst\n\t" 10169 "MOV 64,$tmp\n\t" 10170 "SUB $tmp,$dst,$dst" %} 10171 ins_encode %{ 10172 Register Rdst = $dst$$Register; 10173 Register Rsrc = $src$$Register; 10174 Register Rtmp = $tmp$$Register; 10175 __ srlx(Rsrc, 1, Rtmp); 10176 __ or3( Rsrc, Rtmp, Rdst); 10177 __ srlx(Rdst, 2, Rtmp); 10178 __ or3( Rdst, Rtmp, Rdst); 10179 __ srlx(Rdst, 4, Rtmp); 10180 __ or3( Rdst, Rtmp, Rdst); 10181 __ srlx(Rdst, 8, Rtmp); 10182 __ or3( Rdst, Rtmp, Rdst); 10183 __ srlx(Rdst, 16, Rtmp); 10184 __ or3( Rdst, Rtmp, Rdst); 10185 __ srlx(Rdst, 32, Rtmp); 10186 __ or3( Rdst, Rtmp, Rdst); 10187 __ popc(Rdst, Rdst); 10188 __ mov(BitsPerLong, Rtmp); 10189 __ sub(Rtmp, Rdst, Rdst); 10190 %} 10191 ins_pipe(ialu_reg); 10192%} 10193 10194instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{ 10195 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10196 match(Set dst (CountTrailingZerosI src)); 10197 effect(TEMP dst, KILL cr); 10198 10199 // return popc(~x & (x - 1)); 10200 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 10201 "ANDN $dst,$src,$dst\n\t" 10202 "SRL $dst,R_G0,$dst\n\t" 10203 "POPC $dst,$dst" %} 10204 ins_encode %{ 10205 Register Rdst = $dst$$Register; 10206 Register Rsrc = $src$$Register; 10207 __ sub(Rsrc, 1, Rdst); 10208 __ andn(Rdst, Rsrc, Rdst); 10209 __ srl(Rdst, G0, Rdst); 10210 __ popc(Rdst, Rdst); 10211 %} 10212 ins_pipe(ialu_reg); 10213%} 10214 10215instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{ 10216 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 10217 match(Set dst (CountTrailingZerosL src)); 10218 effect(TEMP dst, KILL cr); 10219 10220 // return popc(~x & (x - 1)); 10221 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 10222 "ANDN $dst,$src,$dst\n\t" 10223 "POPC $dst,$dst" %} 10224 ins_encode %{ 10225 Register Rdst = $dst$$Register; 10226 Register Rsrc = $src$$Register; 10227 __ sub(Rsrc, 1, Rdst); 10228 __ andn(Rdst, Rsrc, Rdst); 10229 __ popc(Rdst, Rdst); 10230 %} 10231 ins_pipe(ialu_reg); 10232%} 10233 10234 10235//---------- Population Count Instructions ------------------------------------- 10236 10237instruct popCountI(iRegIsafe dst, iRegI src) %{ 10238 predicate(UsePopCountInstruction); 10239 match(Set dst (PopCountI src)); 10240 10241 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t" 10242 "POPC $dst, $dst" %} 10243 ins_encode %{ 10244 __ srl($src$$Register, G0, $dst$$Register); 10245 __ popc($dst$$Register, $dst$$Register); 10246 %} 10247 ins_pipe(ialu_reg); 10248%} 10249 10250// Note: Long.bitCount(long) returns an int. 10251instruct popCountL(iRegIsafe dst, iRegL src) %{ 10252 predicate(UsePopCountInstruction); 10253 match(Set dst (PopCountL src)); 10254 10255 format %{ "POPC $src, $dst" %} 10256 ins_encode %{ 10257 __ popc($src$$Register, $dst$$Register); 10258 %} 10259 ins_pipe(ialu_reg); 10260%} 10261 10262 10263// ============================================================================ 10264//------------Bytes reverse-------------------------------------------------- 10265 10266instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 10267 match(Set dst (ReverseBytesI src)); 10268 10269 // Op cost is artificially doubled to make sure that load or store 10270 // instructions are preferred over this one which requires a spill 10271 // onto a stack slot. 10272 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10273 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10274 10275 ins_encode %{ 10276 __ set($src$$disp + STACK_BIAS, O7); 10277 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10278 %} 10279 ins_pipe( iload_mem ); 10280%} 10281 10282instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 10283 match(Set dst (ReverseBytesL src)); 10284 10285 // Op cost is artificially doubled to make sure that load or store 10286 // instructions are preferred over this one which requires a spill 10287 // onto a stack slot. 10288 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10289 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10290 10291 ins_encode %{ 10292 __ set($src$$disp + STACK_BIAS, O7); 10293 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10294 %} 10295 ins_pipe( iload_mem ); 10296%} 10297 10298instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 10299 match(Set dst (ReverseBytesUS src)); 10300 10301 // Op cost is artificially doubled to make sure that load or store 10302 // instructions are preferred over this one which requires a spill 10303 // onto a stack slot. 10304 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10305 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 10306 10307 ins_encode %{ 10308 // the value was spilled as an int so bias the load 10309 __ set($src$$disp + STACK_BIAS + 2, O7); 10310 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10311 %} 10312 ins_pipe( iload_mem ); 10313%} 10314 10315instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 10316 match(Set dst (ReverseBytesS src)); 10317 10318 // Op cost is artificially doubled to make sure that load or store 10319 // instructions are preferred over this one which requires a spill 10320 // onto a stack slot. 10321 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 10322 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 10323 10324 ins_encode %{ 10325 // the value was spilled as an int so bias the load 10326 __ set($src$$disp + STACK_BIAS + 2, O7); 10327 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10328 %} 10329 ins_pipe( iload_mem ); 10330%} 10331 10332// Load Integer reversed byte order 10333instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 10334 match(Set dst (ReverseBytesI (LoadI src))); 10335 10336 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10337 size(4); 10338 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 10339 10340 ins_encode %{ 10341 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10342 %} 10343 ins_pipe(iload_mem); 10344%} 10345 10346// Load Long - aligned and reversed 10347instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 10348 match(Set dst (ReverseBytesL (LoadL src))); 10349 10350 ins_cost(MEMORY_REF_COST); 10351 size(4); 10352 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 10353 10354 ins_encode %{ 10355 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10356 %} 10357 ins_pipe(iload_mem); 10358%} 10359 10360// Load unsigned short / char reversed byte order 10361instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 10362 match(Set dst (ReverseBytesUS (LoadUS src))); 10363 10364 ins_cost(MEMORY_REF_COST); 10365 size(4); 10366 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 10367 10368 ins_encode %{ 10369 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10370 %} 10371 ins_pipe(iload_mem); 10372%} 10373 10374// Load short reversed byte order 10375instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 10376 match(Set dst (ReverseBytesS (LoadS src))); 10377 10378 ins_cost(MEMORY_REF_COST); 10379 size(4); 10380 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 10381 10382 ins_encode %{ 10383 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 10384 %} 10385 ins_pipe(iload_mem); 10386%} 10387 10388// Store Integer reversed byte order 10389instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 10390 match(Set dst (StoreI dst (ReverseBytesI src))); 10391 10392 ins_cost(MEMORY_REF_COST); 10393 size(4); 10394 format %{ "STWA $src, $dst\t!asi=primary_little" %} 10395 10396 ins_encode %{ 10397 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10398 %} 10399 ins_pipe(istore_mem_reg); 10400%} 10401 10402// Store Long reversed byte order 10403instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 10404 match(Set dst (StoreL dst (ReverseBytesL src))); 10405 10406 ins_cost(MEMORY_REF_COST); 10407 size(4); 10408 format %{ "STXA $src, $dst\t!asi=primary_little" %} 10409 10410 ins_encode %{ 10411 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10412 %} 10413 ins_pipe(istore_mem_reg); 10414%} 10415 10416// Store unsighed short/char reversed byte order 10417instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 10418 match(Set dst (StoreC dst (ReverseBytesUS src))); 10419 10420 ins_cost(MEMORY_REF_COST); 10421 size(4); 10422 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10423 10424 ins_encode %{ 10425 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10426 %} 10427 ins_pipe(istore_mem_reg); 10428%} 10429 10430// Store short reversed byte order 10431instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 10432 match(Set dst (StoreC dst (ReverseBytesS src))); 10433 10434 ins_cost(MEMORY_REF_COST); 10435 size(4); 10436 format %{ "STHA $src, $dst\t!asi=primary_little" %} 10437 10438 ins_encode %{ 10439 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 10440 %} 10441 ins_pipe(istore_mem_reg); 10442%} 10443 10444// ====================VECTOR INSTRUCTIONS===================================== 10445 10446// Load Aligned Packed values into a Double Register 10447instruct loadV8(regD dst, memory mem) %{ 10448 predicate(n->as_LoadVector()->memory_size() == 8); 10449 match(Set dst (LoadVector mem)); 10450 ins_cost(MEMORY_REF_COST); 10451 size(4); 10452 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %} 10453 ins_encode %{ 10454 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg)); 10455 %} 10456 ins_pipe(floadD_mem); 10457%} 10458 10459// Store Vector in Double register to memory 10460instruct storeV8(memory mem, regD src) %{ 10461 predicate(n->as_StoreVector()->memory_size() == 8); 10462 match(Set mem (StoreVector mem src)); 10463 ins_cost(MEMORY_REF_COST); 10464 size(4); 10465 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %} 10466 ins_encode %{ 10467 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address); 10468 %} 10469 ins_pipe(fstoreD_mem_reg); 10470%} 10471 10472// Store Zero into vector in memory 10473instruct storeV8B_zero(memory mem, immI0 zero) %{ 10474 predicate(n->as_StoreVector()->memory_size() == 8); 10475 match(Set mem (StoreVector mem (ReplicateB zero))); 10476 ins_cost(MEMORY_REF_COST); 10477 size(4); 10478 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %} 10479 ins_encode %{ 10480 __ stx(G0, $mem$$Address); 10481 %} 10482 ins_pipe(fstoreD_mem_zero); 10483%} 10484 10485instruct storeV4S_zero(memory mem, immI0 zero) %{ 10486 predicate(n->as_StoreVector()->memory_size() == 8); 10487 match(Set mem (StoreVector mem (ReplicateS zero))); 10488 ins_cost(MEMORY_REF_COST); 10489 size(4); 10490 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %} 10491 ins_encode %{ 10492 __ stx(G0, $mem$$Address); 10493 %} 10494 ins_pipe(fstoreD_mem_zero); 10495%} 10496 10497instruct storeV2I_zero(memory mem, immI0 zero) %{ 10498 predicate(n->as_StoreVector()->memory_size() == 8); 10499 match(Set mem (StoreVector mem (ReplicateI zero))); 10500 ins_cost(MEMORY_REF_COST); 10501 size(4); 10502 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %} 10503 ins_encode %{ 10504 __ stx(G0, $mem$$Address); 10505 %} 10506 ins_pipe(fstoreD_mem_zero); 10507%} 10508 10509instruct storeV2F_zero(memory mem, immF0 zero) %{ 10510 predicate(n->as_StoreVector()->memory_size() == 8); 10511 match(Set mem (StoreVector mem (ReplicateF zero))); 10512 ins_cost(MEMORY_REF_COST); 10513 size(4); 10514 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %} 10515 ins_encode %{ 10516 __ stx(G0, $mem$$Address); 10517 %} 10518 ins_pipe(fstoreD_mem_zero); 10519%} 10520 10521// Replicate scalar to packed byte values into Double register 10522instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10523 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3); 10524 match(Set dst (ReplicateB src)); 10525 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10526 format %{ "SLLX $src,56,$tmp\n\t" 10527 "SRLX $tmp, 8,$tmp2\n\t" 10528 "OR $tmp,$tmp2,$tmp\n\t" 10529 "SRLX $tmp,16,$tmp2\n\t" 10530 "OR $tmp,$tmp2,$tmp\n\t" 10531 "SRLX $tmp,32,$tmp2\n\t" 10532 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10533 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10534 ins_encode %{ 10535 Register Rsrc = $src$$Register; 10536 Register Rtmp = $tmp$$Register; 10537 Register Rtmp2 = $tmp2$$Register; 10538 __ sllx(Rsrc, 56, Rtmp); 10539 __ srlx(Rtmp, 8, Rtmp2); 10540 __ or3 (Rtmp, Rtmp2, Rtmp); 10541 __ srlx(Rtmp, 16, Rtmp2); 10542 __ or3 (Rtmp, Rtmp2, Rtmp); 10543 __ srlx(Rtmp, 32, Rtmp2); 10544 __ or3 (Rtmp, Rtmp2, Rtmp); 10545 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10546 %} 10547 ins_pipe(ialu_reg); 10548%} 10549 10550// Replicate scalar to packed byte values into Double stack 10551instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10552 predicate(n->as_Vector()->length() == 8 && UseVIS < 3); 10553 match(Set dst (ReplicateB src)); 10554 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10555 format %{ "SLLX $src,56,$tmp\n\t" 10556 "SRLX $tmp, 8,$tmp2\n\t" 10557 "OR $tmp,$tmp2,$tmp\n\t" 10558 "SRLX $tmp,16,$tmp2\n\t" 10559 "OR $tmp,$tmp2,$tmp\n\t" 10560 "SRLX $tmp,32,$tmp2\n\t" 10561 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t" 10562 "STX $tmp,$dst\t! regL to stkD" %} 10563 ins_encode %{ 10564 Register Rsrc = $src$$Register; 10565 Register Rtmp = $tmp$$Register; 10566 Register Rtmp2 = $tmp2$$Register; 10567 __ sllx(Rsrc, 56, Rtmp); 10568 __ srlx(Rtmp, 8, Rtmp2); 10569 __ or3 (Rtmp, Rtmp2, Rtmp); 10570 __ srlx(Rtmp, 16, Rtmp2); 10571 __ or3 (Rtmp, Rtmp2, Rtmp); 10572 __ srlx(Rtmp, 32, Rtmp2); 10573 __ or3 (Rtmp, Rtmp2, Rtmp); 10574 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10575 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10576 %} 10577 ins_pipe(ialu_reg); 10578%} 10579 10580// Replicate scalar constant to packed byte values in Double register 10581instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{ 10582 predicate(n->as_Vector()->length() == 8); 10583 match(Set dst (ReplicateB con)); 10584 effect(KILL tmp); 10585 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %} 10586 ins_encode %{ 10587 // XXX This is a quick fix for 6833573. 10588 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister); 10589 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register); 10590 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10591 %} 10592 ins_pipe(loadConFD); 10593%} 10594 10595// Replicate scalar to packed char/short values into Double register 10596instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10597 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3); 10598 match(Set dst (ReplicateS src)); 10599 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10600 format %{ "SLLX $src,48,$tmp\n\t" 10601 "SRLX $tmp,16,$tmp2\n\t" 10602 "OR $tmp,$tmp2,$tmp\n\t" 10603 "SRLX $tmp,32,$tmp2\n\t" 10604 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10605 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10606 ins_encode %{ 10607 Register Rsrc = $src$$Register; 10608 Register Rtmp = $tmp$$Register; 10609 Register Rtmp2 = $tmp2$$Register; 10610 __ sllx(Rsrc, 48, Rtmp); 10611 __ srlx(Rtmp, 16, Rtmp2); 10612 __ or3 (Rtmp, Rtmp2, Rtmp); 10613 __ srlx(Rtmp, 32, Rtmp2); 10614 __ or3 (Rtmp, Rtmp2, Rtmp); 10615 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10616 %} 10617 ins_pipe(ialu_reg); 10618%} 10619 10620// Replicate scalar to packed char/short values into Double stack 10621instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10622 predicate(n->as_Vector()->length() == 4 && UseVIS < 3); 10623 match(Set dst (ReplicateS src)); 10624 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10625 format %{ "SLLX $src,48,$tmp\n\t" 10626 "SRLX $tmp,16,$tmp2\n\t" 10627 "OR $tmp,$tmp2,$tmp\n\t" 10628 "SRLX $tmp,32,$tmp2\n\t" 10629 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t" 10630 "STX $tmp,$dst\t! regL to stkD" %} 10631 ins_encode %{ 10632 Register Rsrc = $src$$Register; 10633 Register Rtmp = $tmp$$Register; 10634 Register Rtmp2 = $tmp2$$Register; 10635 __ sllx(Rsrc, 48, Rtmp); 10636 __ srlx(Rtmp, 16, Rtmp2); 10637 __ or3 (Rtmp, Rtmp2, Rtmp); 10638 __ srlx(Rtmp, 32, Rtmp2); 10639 __ or3 (Rtmp, Rtmp2, Rtmp); 10640 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10641 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10642 %} 10643 ins_pipe(ialu_reg); 10644%} 10645 10646// Replicate scalar constant to packed char/short values in Double register 10647instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{ 10648 predicate(n->as_Vector()->length() == 4); 10649 match(Set dst (ReplicateS con)); 10650 effect(KILL tmp); 10651 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %} 10652 ins_encode %{ 10653 // XXX This is a quick fix for 6833573. 10654 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister); 10655 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register); 10656 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10657 %} 10658 ins_pipe(loadConFD); 10659%} 10660 10661// Replicate scalar to packed int values into Double register 10662instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10663 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3); 10664 match(Set dst (ReplicateI src)); 10665 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10666 format %{ "SLLX $src,32,$tmp\n\t" 10667 "SRLX $tmp,32,$tmp2\n\t" 10668 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10669 "MOVXTOD $tmp,$dst\t! MoveL2D" %} 10670 ins_encode %{ 10671 Register Rsrc = $src$$Register; 10672 Register Rtmp = $tmp$$Register; 10673 Register Rtmp2 = $tmp2$$Register; 10674 __ sllx(Rsrc, 32, Rtmp); 10675 __ srlx(Rtmp, 32, Rtmp2); 10676 __ or3 (Rtmp, Rtmp2, Rtmp); 10677 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg)); 10678 %} 10679 ins_pipe(ialu_reg); 10680%} 10681 10682// Replicate scalar to packed int values into Double stack 10683instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{ 10684 predicate(n->as_Vector()->length() == 2 && UseVIS < 3); 10685 match(Set dst (ReplicateI src)); 10686 effect(DEF dst, USE src, TEMP tmp, KILL tmp2); 10687 format %{ "SLLX $src,32,$tmp\n\t" 10688 "SRLX $tmp,32,$tmp2\n\t" 10689 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t" 10690 "STX $tmp,$dst\t! regL to stkD" %} 10691 ins_encode %{ 10692 Register Rsrc = $src$$Register; 10693 Register Rtmp = $tmp$$Register; 10694 Register Rtmp2 = $tmp2$$Register; 10695 __ sllx(Rsrc, 32, Rtmp); 10696 __ srlx(Rtmp, 32, Rtmp2); 10697 __ or3 (Rtmp, Rtmp2, Rtmp); 10698 __ set ($dst$$disp + STACK_BIAS, Rtmp2); 10699 __ stx (Rtmp, Rtmp2, $dst$$base$$Register); 10700 %} 10701 ins_pipe(ialu_reg); 10702%} 10703 10704// Replicate scalar zero constant to packed int values in Double register 10705instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{ 10706 predicate(n->as_Vector()->length() == 2); 10707 match(Set dst (ReplicateI con)); 10708 effect(KILL tmp); 10709 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %} 10710 ins_encode %{ 10711 // XXX This is a quick fix for 6833573. 10712 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister); 10713 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register); 10714 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10715 %} 10716 ins_pipe(loadConFD); 10717%} 10718 10719// Replicate scalar to packed float values into Double stack 10720instruct Repl2F_stk(stackSlotD dst, regF src) %{ 10721 predicate(n->as_Vector()->length() == 2); 10722 match(Set dst (ReplicateF src)); 10723 ins_cost(MEMORY_REF_COST*2); 10724 format %{ "STF $src,$dst.hi\t! packed2F\n\t" 10725 "STF $src,$dst.lo" %} 10726 opcode(Assembler::stf_op3); 10727 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src)); 10728 ins_pipe(fstoreF_stk_reg); 10729%} 10730 10731// Replicate scalar zero constant to packed float values in Double register 10732instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{ 10733 predicate(n->as_Vector()->length() == 2); 10734 match(Set dst (ReplicateF con)); 10735 effect(KILL tmp); 10736 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %} 10737 ins_encode %{ 10738 // XXX This is a quick fix for 6833573. 10739 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister); 10740 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register); 10741 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg)); 10742 %} 10743 ins_pipe(loadConFD); 10744%} 10745 10746//----------PEEPHOLE RULES----------------------------------------------------- 10747// These must follow all instruction definitions as they use the names 10748// defined in the instructions definitions. 10749// 10750// peepmatch ( root_instr_name [preceding_instruction]* ); 10751// 10752// peepconstraint %{ 10753// (instruction_number.operand_name relational_op instruction_number.operand_name 10754// [, ...] ); 10755// // instruction numbers are zero-based using left to right order in peepmatch 10756// 10757// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 10758// // provide an instruction_number.operand_name for each operand that appears 10759// // in the replacement instruction's match rule 10760// 10761// ---------VM FLAGS--------------------------------------------------------- 10762// 10763// All peephole optimizations can be turned off using -XX:-OptoPeephole 10764// 10765// Each peephole rule is given an identifying number starting with zero and 10766// increasing by one in the order seen by the parser. An individual peephole 10767// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 10768// on the command-line. 10769// 10770// ---------CURRENT LIMITATIONS---------------------------------------------- 10771// 10772// Only match adjacent instructions in same basic block 10773// Only equality constraints 10774// Only constraints between operands, not (0.dest_reg == EAX_enc) 10775// Only one replacement instruction 10776// 10777// ---------EXAMPLE---------------------------------------------------------- 10778// 10779// // pertinent parts of existing instructions in architecture description 10780// instruct movI(eRegI dst, eRegI src) %{ 10781// match(Set dst (CopyI src)); 10782// %} 10783// 10784// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 10785// match(Set dst (AddI dst src)); 10786// effect(KILL cr); 10787// %} 10788// 10789// // Change (inc mov) to lea 10790// peephole %{ 10791// // increment preceeded by register-register move 10792// peepmatch ( incI_eReg movI ); 10793// // require that the destination register of the increment 10794// // match the destination register of the move 10795// peepconstraint ( 0.dst == 1.dst ); 10796// // construct a replacement instruction that sets 10797// // the destination to ( move's source register + one ) 10798// peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 10799// %} 10800// 10801 10802// // Change load of spilled value to only a spill 10803// instruct storeI(memory mem, eRegI src) %{ 10804// match(Set mem (StoreI mem src)); 10805// %} 10806// 10807// instruct loadI(eRegI dst, memory mem) %{ 10808// match(Set dst (LoadI mem)); 10809// %} 10810// 10811// peephole %{ 10812// peepmatch ( loadI storeI ); 10813// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 10814// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 10815// %} 10816 10817//----------SMARTSPILL RULES--------------------------------------------------- 10818// These must follow all instruction definitions as they use the names 10819// defined in the instructions definitions. 10820// 10821// SPARC will probably not have any of these rules due to RISC instruction set. 10822 10823//----------PIPELINE----------------------------------------------------------- 10824// Rules which define the behavior of the target architectures pipeline. 10825