sparc.ad revision 1668:3e8fbc61cee8
11638Srgrimes// 21638Srgrimes// Copyright (c) 1998, 2010, Oracle and/or its affiliates. All rights reserved. 31638Srgrimes// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 41638Srgrimes// 51638Srgrimes// This code is free software; you can redistribute it and/or modify it 61638Srgrimes// under the terms of the GNU General Public License version 2 only, as 71638Srgrimes// published by the Free Software Foundation. 81638Srgrimes// 91638Srgrimes// This code is distributed in the hope that it will be useful, but WITHOUT 101638Srgrimes// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 111638Srgrimes// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 121638Srgrimes// version 2 for more details (a copy is included in the LICENSE file that 131638Srgrimes// accompanied this code). 141638Srgrimes// 151638Srgrimes// You should have received a copy of the GNU General Public License version 161638Srgrimes// 2 along with this work; if not, write to the Free Software Foundation, 171638Srgrimes// Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 181638Srgrimes// 191638Srgrimes// Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 201638Srgrimes// or visit www.oracle.com if you need additional information or have any 211638Srgrimes// questions. 221638Srgrimes// 231638Srgrimes// 241638Srgrimes 251638Srgrimes// SPARC Architecture Description File 261638Srgrimes 271638Srgrimes//----------REGISTER DEFINITION BLOCK------------------------------------------ 281638Srgrimes// This information is used by the matcher and the register allocator to 291638Srgrimes// describe individual registers and classes of registers within the target 301638Srgrimes// archtecture. 311638Srgrimesregister %{ 321638Srgrimes//----------Architecture Description Register Definitions---------------------- 331638Srgrimes// General Registers 341638Srgrimes// "reg_def" name ( register save type, C convention save type, 351638Srgrimes// ideal register type, encoding, vm name ); 361638Srgrimes// Register Save Types: 371638Srgrimes// 381638Srgrimes// NS = No-Save: The register allocator assumes that these registers 391638Srgrimes// can be used without saving upon entry to the method, & 401638Srgrimes// that they do not need to be saved at call sites. 411638Srgrimes// 421638Srgrimes// SOC = Save-On-Call: The register allocator assumes that these registers 431638Srgrimes// can be used without saving upon entry to the method, 441638Srgrimes// but that they must be saved at call sites. 451638Srgrimes// 461638Srgrimes// SOE = Save-On-Entry: The register allocator assumes that these registers 471638Srgrimes// must be saved before using them upon entry to the 481638Srgrimes// method, but they do not need to be saved at call 491638Srgrimes// sites. 501638Srgrimes// 511638Srgrimes// AS = Always-Save: The register allocator assumes that these registers 521638Srgrimes// must be saved before using them upon entry to the 531638Srgrimes// method, & that they must be saved at call sites. 541638Srgrimes// 551638Srgrimes// Ideal Register Type is used to determine how to save & restore a 561638Srgrimes// register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 571638Srgrimes// spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 581638Srgrimes// 591638Srgrimes// The encoding number is the actual bit-pattern placed into the opcodes. 601638Srgrimes 611638Srgrimes 621638Srgrimes// ---------------------------- 631638Srgrimes// Integer/Long Registers 641638Srgrimes// ---------------------------- 651638Srgrimes 661638Srgrimes// Need to expose the hi/lo aspect of 64-bit registers 671638Srgrimes// This register set is used for both the 64-bit build and 681638Srgrimes// the 32-bit build with 1-register longs. 691638Srgrimes 701638Srgrimes// Global Registers 0-7 711638Srgrimesreg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next()); 721638Srgrimesreg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg()); 731638Srgrimesreg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next()); 741638Srgrimesreg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg()); 751638Srgrimesreg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next()); 761638Srgrimesreg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg()); 771638Srgrimesreg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next()); 781638Srgrimesreg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg()); 791638Srgrimesreg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next()); 801638Srgrimesreg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg()); 811638Srgrimesreg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next()); 821638Srgrimesreg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg()); 831638Srgrimesreg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next()); 841638Srgrimesreg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg()); 851638Srgrimesreg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next()); 861638Srgrimesreg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg()); 871638Srgrimes 881638Srgrimes// Output Registers 0-7 891638Srgrimesreg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next()); 901638Srgrimesreg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg()); 911638Srgrimesreg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next()); 921638Srgrimesreg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg()); 931638Srgrimesreg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next()); 941638Srgrimesreg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg()); 951638Srgrimesreg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next()); 961638Srgrimesreg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg()); 971638Srgrimesreg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next()); 981638Srgrimesreg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg()); 991638Srgrimesreg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next()); 1001638Srgrimesreg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg()); 1011638Srgrimesreg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next()); 1021638Srgrimesreg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg()); 1031638Srgrimesreg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next()); 1041638Srgrimesreg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg()); 1051638Srgrimes 1061638Srgrimes// Local Registers 0-7 1071638Srgrimesreg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next()); 1081638Srgrimesreg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg()); 1091638Srgrimesreg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next()); 1101638Srgrimesreg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg()); 1111638Srgrimesreg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next()); 1121638Srgrimesreg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg()); 1131638Srgrimesreg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next()); 1141638Srgrimesreg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg()); 1151638Srgrimesreg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next()); 1161638Srgrimesreg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg()); 1171638Srgrimesreg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next()); 1181638Srgrimesreg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg()); 1191638Srgrimesreg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next()); 1201638Srgrimesreg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg()); 1211638Srgrimesreg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next()); 1221638Srgrimesreg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg()); 1231638Srgrimes 1241638Srgrimes// Input Registers 0-7 1251638Srgrimesreg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next()); 1261638Srgrimesreg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg()); 1271638Srgrimesreg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next()); 1281638Srgrimesreg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg()); 1291638Srgrimesreg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next()); 1301638Srgrimesreg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg()); 1311638Srgrimesreg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next()); 1321638Srgrimesreg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg()); 1331638Srgrimesreg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next()); 1341638Srgrimesreg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg()); 1351638Srgrimesreg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next()); 1361638Srgrimesreg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg()); 1371638Srgrimesreg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next()); 1381638Srgrimesreg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg()); 1391638Srgrimesreg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next()); 1401638Srgrimesreg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg()); 1411638Srgrimes 1421638Srgrimes// ---------------------------- 1431638Srgrimes// Float/Double Registers 1441638Srgrimes// ---------------------------- 1451638Srgrimes 1461638Srgrimes// Float Registers 1471638Srgrimesreg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg()); 1481638Srgrimesreg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg()); 1491638Srgrimesreg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg()); 1501638Srgrimesreg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg()); 1511638Srgrimesreg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg()); 1521638Srgrimesreg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg()); 1531638Srgrimesreg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg()); 1541638Srgrimesreg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg()); 1551638Srgrimesreg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg()); 1561638Srgrimesreg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg()); 1571638Srgrimesreg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg()); 1581638Srgrimesreg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg()); 1591638Srgrimesreg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg()); 1601638Srgrimesreg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg()); 1611638Srgrimesreg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg()); 1621638Srgrimesreg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg()); 1631638Srgrimesreg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg()); 1641638Srgrimesreg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg()); 1651638Srgrimesreg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg()); 1661638Srgrimesreg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg()); 1671638Srgrimesreg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg()); 1681638Srgrimesreg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg()); 1691638Srgrimesreg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg()); 1701638Srgrimesreg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg()); 1711638Srgrimesreg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg()); 1721638Srgrimesreg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg()); 1731638Srgrimesreg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg()); 1741638Srgrimesreg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg()); 1751638Srgrimesreg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg()); 1761638Srgrimesreg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg()); 1771638Srgrimesreg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg()); 1781638Srgrimesreg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg()); 1791638Srgrimes 1801638Srgrimes// Double Registers 1811638Srgrimes// The rules of ADL require that double registers be defined in pairs. 1821638Srgrimes// Each pair must be two 32-bit values, but not necessarily a pair of 1831638Srgrimes// single float registers. In each pair, ADLC-assigned register numbers 1841638Srgrimes// must be adjacent, with the lower number even. Finally, when the 1851638Srgrimes// CPU stores such a register pair to memory, the word associated with 1861638Srgrimes// the lower ADLC-assigned number must be stored to the lower address. 1871638Srgrimes 1881638Srgrimes// These definitions specify the actual bit encodings of the sparc 1891638Srgrimes// double fp register numbers. FloatRegisterImpl in register_sparc.hpp 1901638Srgrimes// wants 0-63, so we have to convert every time we want to use fp regs 1911638Srgrimes// with the macroassembler, using reg_to_DoubleFloatRegister_object(). 1921638Srgrimes// 255 is a flag meaning "don't go here". 1931638Srgrimes// I believe we can't handle callee-save doubles D32 and up until 1941638Srgrimes// the place in the sparc stack crawler that asserts on the 255 is 1951638Srgrimes// fixed up. 1961638Srgrimesreg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg()); 1971638Srgrimesreg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next()); 1981638Srgrimesreg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg()); 1991638Srgrimesreg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next()); 2001638Srgrimesreg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg()); 2011638Srgrimesreg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next()); 2021638Srgrimesreg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg()); 2031638Srgrimesreg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next()); 2041638Srgrimesreg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg()); 2051638Srgrimesreg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next()); 2061638Srgrimesreg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg()); 2071638Srgrimesreg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next()); 2081638Srgrimesreg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg()); 2091638Srgrimesreg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next()); 2101638Srgrimesreg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg()); 2111638Srgrimesreg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next()); 2121638Srgrimesreg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg()); 2131638Srgrimesreg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next()); 2141638Srgrimesreg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg()); 2151638Srgrimesreg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next()); 2161638Srgrimesreg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg()); 2171638Srgrimesreg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next()); 2181638Srgrimesreg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg()); 2191638Srgrimesreg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next()); 2201638Srgrimesreg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg()); 2211638Srgrimesreg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next()); 2221638Srgrimesreg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg()); 2231638Srgrimesreg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next()); 2241638Srgrimesreg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg()); 2251638Srgrimesreg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next()); 2261638Srgrimesreg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg()); 2271638Srgrimesreg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next()); 2281638Srgrimes 2291638Srgrimes 2301638Srgrimes// ---------------------------- 2311638Srgrimes// Special Registers 2321638Srgrimes// Condition Codes Flag Registers 2331638Srgrimes// I tried to break out ICC and XCC but it's not very pretty. 2341638Srgrimes// Every Sparc instruction which defs/kills one also kills the other. 2351638Srgrimes// Hence every compare instruction which defs one kind of flags ends 2361638Srgrimes// up needing a kill of the other. 2371638Srgrimesreg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 2381638Srgrimes 2391638Srgrimesreg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad()); 2401638Srgrimesreg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad()); 2411638Srgrimesreg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad()); 2421638Srgrimesreg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad()); 2431638Srgrimes 2441638Srgrimes// ---------------------------- 2451638Srgrimes// Specify the enum values for the registers. These enums are only used by the 2461638Srgrimes// OptoReg "class". We can convert these enum values at will to VMReg when needed 2471638Srgrimes// for visibility to the rest of the vm. The order of this enum influences the 2481638Srgrimes// register allocator so having the freedom to set this order and not be stuck 2491638Srgrimes// with the order that is natural for the rest of the vm is worth it. 2501638Srgrimesalloc_class chunk0( 2511638Srgrimes R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H, 2521638Srgrimes R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H, 2531638Srgrimes R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H, 2541638Srgrimes R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H); 2551638Srgrimes 2561638Srgrimes// Note that a register is not allocatable unless it is also mentioned 2571638Srgrimes// in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg. 2581638Srgrimes 2591638Srgrimesalloc_class chunk1( 2601638Srgrimes // The first registers listed here are those most likely to be used 2611638Srgrimes // as temporaries. We move F0..F7 away from the front of the list, 2621638Srgrimes // to reduce the likelihood of interferences with parameters and 2631638Srgrimes // return values. Likewise, we avoid using F0/F1 for parameters, 2641638Srgrimes // since they are used for return values. 2651638Srgrimes // This FPU fine-tuning is worth about 1% on the SPEC geomean. 2661638Srgrimes R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 2671638Srgrimes R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23, 2681638Srgrimes R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31, 2691638Srgrimes R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values 2701638Srgrimes R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x, 2711638Srgrimes R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 2721638Srgrimes R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x, 2731638Srgrimes R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x); 2741638Srgrimes 2751638Srgrimesalloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3); 2761638Srgrimes 2771638Srgrimes//----------Architecture Description Register Classes-------------------------- 2781638Srgrimes// Several register classes are automatically defined based upon information in 2791638Srgrimes// this architecture description. 2801638Srgrimes// 1) reg_class inline_cache_reg ( as defined in frame section ) 2811638Srgrimes// 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 2821638Srgrimes// 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 2831638Srgrimes// 2841638Srgrimes 2851638Srgrimes// G0 is not included in integer class since it has special meaning. 2861638Srgrimesreg_class g0_reg(R_G0); 2871638Srgrimes 2881638Srgrimes// ---------------------------- 2891638Srgrimes// Integer Register Classes 2901638Srgrimes// ---------------------------- 2911638Srgrimes// Exclusions from i_reg: 2921638Srgrimes// R_G0: hardwired zero 2931638Srgrimes// R_G2: reserved by HotSpot to the TLS register (invariant within Java) 2941638Srgrimes// R_G6: reserved by Solaris ABI to tools 2951638Srgrimes// R_G7: reserved by Solaris ABI to libthread 2961638Srgrimes// R_O7: Used as a temp in many encodings 2971638Srgrimesreg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 2981638Srgrimes 2991638Srgrimes// Class for all integer registers, except the G registers. This is used for 3001638Srgrimes// encodings which use G registers as temps. The regular inputs to such 3011638Srgrimes// instructions use a "notemp_" prefix, as a hack to ensure that the allocator 3021638Srgrimes// will not put an input into a temp register. 3031638Srgrimesreg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 3041638Srgrimes 3051638Srgrimesreg_class g1_regI(R_G1); 3061638Srgrimesreg_class g3_regI(R_G3); 3071638Srgrimesreg_class g4_regI(R_G4); 3081638Srgrimesreg_class o0_regI(R_O0); 3091638Srgrimesreg_class o7_regI(R_O7); 3101638Srgrimes 3111638Srgrimes// ---------------------------- 3121638Srgrimes// Pointer Register Classes 3131638Srgrimes// ---------------------------- 3141638Srgrimes#ifdef _LP64 3151638Srgrimes// 64-bit build means 64-bit pointers means hi/lo pairs 3161638Srgrimesreg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 3171638Srgrimes R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 3181638Srgrimes R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 3191638Srgrimes R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 3201638Srgrimes// Lock encodings use G3 and G4 internally 3211638Srgrimesreg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5, 3221638Srgrimes R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, 3231638Srgrimes R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 3241638Srgrimes R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 ); 3251638Srgrimes// Special class for storeP instructions, which can store SP or RPC to TLS. 3261638Srgrimes// It is also used for memory addressing, allowing direct TLS addressing. 3271638Srgrimesreg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5, 3281638Srgrimes R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP, 3291638Srgrimes R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7, 3301638Srgrimes R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP ); 3311638Srgrimes// R_L7 is the lowest-priority callee-save (i.e., NS) register 3321638Srgrimes// We use it to save R_G2 across calls out of Java. 3331638Srgrimesreg_class l7_regP(R_L7H,R_L7); 3341638Srgrimes 3351638Srgrimes// Other special pointer regs 3361638Srgrimesreg_class g1_regP(R_G1H,R_G1); 3371638Srgrimesreg_class g2_regP(R_G2H,R_G2); 3381638Srgrimesreg_class g3_regP(R_G3H,R_G3); 3391638Srgrimesreg_class g4_regP(R_G4H,R_G4); 3401638Srgrimesreg_class g5_regP(R_G5H,R_G5); 3411638Srgrimesreg_class i0_regP(R_I0H,R_I0); 3421638Srgrimesreg_class o0_regP(R_O0H,R_O0); 3431638Srgrimesreg_class o1_regP(R_O1H,R_O1); 3441638Srgrimesreg_class o2_regP(R_O2H,R_O2); 3451638Srgrimesreg_class o7_regP(R_O7H,R_O7); 3461638Srgrimes 3471638Srgrimes#else // _LP64 3481638Srgrimes// 32-bit build means 32-bit pointers means 1 register. 3491638Srgrimesreg_class ptr_reg( R_G1, R_G3,R_G4,R_G5, 3501638Srgrimes R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 3511638Srgrimes R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 3521638Srgrimes R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 3531638Srgrimes// Lock encodings use G3 and G4 internally 3541638Srgrimesreg_class lock_ptr_reg(R_G1, R_G5, 3551638Srgrimes R_O0,R_O1,R_O2,R_O3,R_O4,R_O5, 3561638Srgrimes R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 3571638Srgrimes R_I0,R_I1,R_I2,R_I3,R_I4,R_I5); 3581638Srgrimes// Special class for storeP instructions, which can store SP or RPC to TLS. 3591638Srgrimes// It is also used for memory addressing, allowing direct TLS addressing. 3601638Srgrimesreg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5, 3611638Srgrimes R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP, 3621638Srgrimes R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7, 3631638Srgrimes R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP); 3641638Srgrimes// R_L7 is the lowest-priority callee-save (i.e., NS) register 3651638Srgrimes// We use it to save R_G2 across calls out of Java. 3661638Srgrimesreg_class l7_regP(R_L7); 3671638Srgrimes 3681638Srgrimes// Other special pointer regs 3691638Srgrimesreg_class g1_regP(R_G1); 3701638Srgrimesreg_class g2_regP(R_G2); 3711638Srgrimesreg_class g3_regP(R_G3); 3721638Srgrimesreg_class g4_regP(R_G4); 3731638Srgrimesreg_class g5_regP(R_G5); 3741638Srgrimesreg_class i0_regP(R_I0); 3751638Srgrimesreg_class o0_regP(R_O0); 3761638Srgrimesreg_class o1_regP(R_O1); 3771638Srgrimesreg_class o2_regP(R_O2); 3781638Srgrimesreg_class o7_regP(R_O7); 3791638Srgrimes#endif // _LP64 3801638Srgrimes 3811638Srgrimes 3821638Srgrimes// ---------------------------- 3831638Srgrimes// Long Register Classes 3841638Srgrimes// ---------------------------- 3851638Srgrimes// Longs in 1 register. Aligned adjacent hi/lo pairs. 3861638Srgrimes// Note: O7 is never in this class; it is sometimes used as an encoding temp. 3871638Srgrimesreg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5 3881638Srgrimes ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5 3891638Srgrimes#ifdef _LP64 3901638Srgrimes// 64-bit, longs in 1 register: use all 64-bit integer registers 3911638Srgrimes// 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's. 3921638Srgrimes ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7 3931638Srgrimes ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 3941638Srgrimes#endif // _LP64 3951638Srgrimes ); 3961638Srgrimes 3971638Srgrimesreg_class g1_regL(R_G1H,R_G1); 3981638Srgrimesreg_class g3_regL(R_G3H,R_G3); 3991638Srgrimesreg_class o2_regL(R_O2H,R_O2); 4001638Srgrimesreg_class o7_regL(R_O7H,R_O7); 4011638Srgrimes 4021638Srgrimes// ---------------------------- 4031638Srgrimes// Special Class for Condition Code Flags Register 4041638Srgrimesreg_class int_flags(CCR); 4051638Srgrimesreg_class float_flags(FCC0,FCC1,FCC2,FCC3); 4061638Srgrimesreg_class float_flag0(FCC0); 4071638Srgrimes 4081638Srgrimes 4091638Srgrimes// ---------------------------- 4101638Srgrimes// Float Point Register Classes 4111638Srgrimes// ---------------------------- 4121638Srgrimes// Skip F30/F31, they are reserved for mem-mem copies 4131638Srgrimesreg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29); 4141638Srgrimes 4151638Srgrimes// Paired floating point registers--they show up in the same order as the floats, 4161638Srgrimes// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 4171638Srgrimesreg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 4181638Srgrimes R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29, 4191638Srgrimes /* Use extra V9 double registers; this AD file does not support V8 */ 4201638Srgrimes R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x, 4211638Srgrimes R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x 4221638Srgrimes ); 4231638Srgrimes 4241638Srgrimes// Paired floating point registers--they show up in the same order as the floats, 4251638Srgrimes// but they are used with the "Op_RegD" type, and always occur in even/odd pairs. 4261638Srgrimes// This class is usable for mis-aligned loads as happen in I2C adapters. 4271638Srgrimesreg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15, 4281638Srgrimes R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31 ); 4291638Srgrimes%} 4301638Srgrimes 4311638Srgrimes//----------DEFINITION BLOCK--------------------------------------------------- 4321638Srgrimes// Define name --> value mappings to inform the ADLC of an integer valued name 4331638Srgrimes// Current support includes integer values in the range [0, 0x7FFFFFFF] 4341638Srgrimes// Format: 4351638Srgrimes// int_def <name> ( <int_value>, <expression>); 4361638Srgrimes// Generated Code in ad_<arch>.hpp 4371638Srgrimes// #define <name> (<expression>) 4381638Srgrimes// // value == <int_value> 4391638Srgrimes// Generated code in ad_<arch>.cpp adlc_verification() 4401638Srgrimes// assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 4411638Srgrimes// 4421638Srgrimesdefinitions %{ 4431638Srgrimes// The default cost (of an ALU instruction). 4441638Srgrimes int_def DEFAULT_COST ( 100, 100); 4451638Srgrimes int_def HUGE_COST (1000000, 1000000); 4461638Srgrimes 4471638Srgrimes// Memory refs are twice as expensive as run-of-the-mill. 4481638Srgrimes int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2); 4491638Srgrimes 4501638Srgrimes// Branches are even more expensive. 4511638Srgrimes int_def BRANCH_COST ( 300, DEFAULT_COST * 3); 4521638Srgrimes int_def CALL_COST ( 300, DEFAULT_COST * 3); 4531638Srgrimes%} 4541638Srgrimes 4551638Srgrimes 4561638Srgrimes//----------SOURCE BLOCK------------------------------------------------------- 4571638Srgrimes// This is a block of C++ code which provides values, functions, and 4581638Srgrimes// definitions necessary in the rest of the architecture description 4591638Srgrimessource_hpp %{ 4601638Srgrimes// Must be visible to the DFA in dfa_sparc.cpp 4611638Srgrimesextern bool can_branch_register( Node *bol, Node *cmp ); 4621638Srgrimes 4631638Srgrimes// Macros to extract hi & lo halves from a long pair. 4641638Srgrimes// G0 is not part of any long pair, so assert on that. 4651638Srgrimes// Prevents accidentally using G1 instead of G0. 4661638Srgrimes#define LONG_HI_REG(x) (x) 4671638Srgrimes#define LONG_LO_REG(x) (x) 4681638Srgrimes 4691638Srgrimes%} 4701638Srgrimes 4711638Srgrimessource %{ 4721638Srgrimes#define __ _masm. 4731638Srgrimes 4741638Srgrimes// Block initializing store 4751638Srgrimes#define ASI_BLK_INIT_QUAD_LDD_P 0xE2 4761638Srgrimes 4771638Srgrimes// tertiary op of a LoadP or StoreP encoding 4781638Srgrimes#define REGP_OP true 4791638Srgrimes 4801638Srgrimesstatic FloatRegister reg_to_SingleFloatRegister_object(int register_encoding); 4811638Srgrimesstatic FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding); 4821638Srgrimesstatic Register reg_to_register_object(int register_encoding); 4831638Srgrimes 4841638Srgrimes// Used by the DFA in dfa_sparc.cpp. 4851638Srgrimes// Check for being able to use a V9 branch-on-register. Requires a 4861638Srgrimes// compare-vs-zero, equal/not-equal, of a value which was zero- or sign- 4871638Srgrimes// extended. Doesn't work following an integer ADD, for example, because of 4881638Srgrimes// overflow (-1 incremented yields 0 plus a carry in the high-order word). On 4891638Srgrimes// 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and 4901638Srgrimes// replace them with zero, which could become sign-extension in a different OS 4911638Srgrimes// release. There's no obvious reason why an interrupt will ever fill these 4921638Srgrimes// bits with non-zero junk (the registers are reloaded with standard LD 4931638Srgrimes// instructions which either zero-fill or sign-fill). 4941638Srgrimesbool can_branch_register( Node *bol, Node *cmp ) { 4951638Srgrimes if( !BranchOnRegister ) return false; 4961638Srgrimes#ifdef _LP64 4971638Srgrimes if( cmp->Opcode() == Op_CmpP ) 4981638Srgrimes return true; // No problems with pointer compares 4991638Srgrimes#endif 5001638Srgrimes if( cmp->Opcode() == Op_CmpL ) 5011638Srgrimes return true; // No problems with long compares 5021638Srgrimes 5031638Srgrimes if( !SparcV9RegsHiBitsZero ) return false; 5041638Srgrimes if( bol->as_Bool()->_test._test != BoolTest::ne && 5051638Srgrimes bol->as_Bool()->_test._test != BoolTest::eq ) 5061638Srgrimes return false; 5071638Srgrimes 5081638Srgrimes // Check for comparing against a 'safe' value. Any operation which 5091638Srgrimes // clears out the high word is safe. Thus, loads and certain shifts 5101638Srgrimes // are safe, as are non-negative constants. Any operation which 5111638Srgrimes // preserves zero bits in the high word is safe as long as each of its 5121638Srgrimes // inputs are safe. Thus, phis and bitwise booleans are safe if their 5131638Srgrimes // inputs are safe. At present, the only important case to recognize 5141638Srgrimes // seems to be loads. Constants should fold away, and shifts & 5151638Srgrimes // logicals can use the 'cc' forms. 5161638Srgrimes Node *x = cmp->in(1); 5171638Srgrimes if( x->is_Load() ) return true; 5181638Srgrimes if( x->is_Phi() ) { 5191638Srgrimes for( uint i = 1; i < x->req(); i++ ) 5201638Srgrimes if( !x->in(i)->is_Load() ) 5211638Srgrimes return false; 5221638Srgrimes return true; 5231638Srgrimes } 5241638Srgrimes return false; 5251638Srgrimes} 5261638Srgrimes 5271638Srgrimes// **************************************************************************** 5281638Srgrimes 5291638Srgrimes// REQUIRED FUNCTIONALITY 5301638Srgrimes 5311638Srgrimes// !!!!! Special hack to get all type of calls to specify the byte offset 5321638Srgrimes// from the start of the call to the point where the return address 5331638Srgrimes// will point. 5341638Srgrimes// The "return address" is the address of the call instruction, plus 8. 5351638Srgrimes 5361638Srgrimesint MachCallStaticJavaNode::ret_addr_offset() { 5371638Srgrimes int offset = NativeCall::instruction_size; // call; delay slot 5381638Srgrimes if (_method_handle_invoke) 5391638Srgrimes offset += 4; // restore SP 5401638Srgrimes return offset; 5411638Srgrimes} 5421638Srgrimes 5431638Srgrimesint MachCallDynamicJavaNode::ret_addr_offset() { 5441638Srgrimes int vtable_index = this->_vtable_index; 5451638Srgrimes if (vtable_index < 0) { 5461638Srgrimes // must be invalid_vtable_index, not nonvirtual_vtable_index 5471638Srgrimes assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 5481638Srgrimes return (NativeMovConstReg::instruction_size + 5491638Srgrimes NativeCall::instruction_size); // sethi; setlo; call; delay slot 5501638Srgrimes } else { 5511638Srgrimes assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 5521638Srgrimes int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 5531638Srgrimes int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 5541638Srgrimes int klass_load_size; 5551638Srgrimes if (UseCompressedOops) { 5561638Srgrimes assert(Universe::heap() != NULL, "java heap should be initialized"); 5571638Srgrimes if (Universe::narrow_oop_base() == NULL) 5581638Srgrimes klass_load_size = 2*BytesPerInstWord; // see MacroAssembler::load_klass() 5591638Srgrimes else 5601638Srgrimes klass_load_size = 3*BytesPerInstWord; 5611638Srgrimes } else { 5621638Srgrimes klass_load_size = 1*BytesPerInstWord; 5631638Srgrimes } 5641638Srgrimes if( Assembler::is_simm13(v_off) ) { 5651638Srgrimes return klass_load_size + 5661638Srgrimes (2*BytesPerInstWord + // ld_ptr, ld_ptr 5671638Srgrimes NativeCall::instruction_size); // call; delay slot 5681638Srgrimes } else { 5691638Srgrimes return klass_load_size + 5701638Srgrimes (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr 5711638Srgrimes NativeCall::instruction_size); // call; delay slot 5721638Srgrimes } 5731638Srgrimes } 5741638Srgrimes} 5751638Srgrimes 5761638Srgrimesint MachCallRuntimeNode::ret_addr_offset() { 5771638Srgrimes#ifdef _LP64 5781638Srgrimes return NativeFarCall::instruction_size; // farcall; delay slot 5791638Srgrimes#else 5801638Srgrimes return NativeCall::instruction_size; // call; delay slot 5811638Srgrimes#endif 5821638Srgrimes} 5831638Srgrimes 5841638Srgrimes// Indicate if the safepoint node needs the polling page as an input. 5851638Srgrimes// Since Sparc does not have absolute addressing, it does. 5861638Srgrimesbool SafePointNode::needs_polling_address_input() { 5871638Srgrimes return true; 5881638Srgrimes} 5891638Srgrimes 5901638Srgrimes// emit an interrupt that is caught by the debugger (for debugging compiler) 5911638Srgrimesvoid emit_break(CodeBuffer &cbuf) { 5921638Srgrimes MacroAssembler _masm(&cbuf); 5931638Srgrimes __ breakpoint_trap(); 5941638Srgrimes} 5951638Srgrimes 5961638Srgrimes#ifndef PRODUCT 5971638Srgrimesvoid MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const { 5981638Srgrimes st->print("TA"); 5991638Srgrimes} 6001638Srgrimes#endif 6011638Srgrimes 6021638Srgrimesvoid MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 6031638Srgrimes emit_break(cbuf); 6041638Srgrimes} 6051638Srgrimes 6061638Srgrimesuint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 6071638Srgrimes return MachNode::size(ra_); 6081638Srgrimes} 6091638Srgrimes 6101638Srgrimes// Traceable jump 6111638Srgrimesvoid emit_jmpl(CodeBuffer &cbuf, int jump_target) { 6121638Srgrimes MacroAssembler _masm(&cbuf); 6131638Srgrimes Register rdest = reg_to_register_object(jump_target); 6141638Srgrimes __ JMP(rdest, 0); 6151638Srgrimes __ delayed()->nop(); 6161638Srgrimes} 6171638Srgrimes 6181638Srgrimes// Traceable jump and set exception pc 6191638Srgrimesvoid emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) { 6201638Srgrimes MacroAssembler _masm(&cbuf); 6211638Srgrimes Register rdest = reg_to_register_object(jump_target); 6221638Srgrimes __ JMP(rdest, 0); 6231638Srgrimes __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc ); 6241638Srgrimes} 6251638Srgrimes 6261638Srgrimesvoid emit_nop(CodeBuffer &cbuf) { 6271638Srgrimes MacroAssembler _masm(&cbuf); 6281638Srgrimes __ nop(); 6291638Srgrimes} 6301638Srgrimes 6311638Srgrimesvoid emit_illtrap(CodeBuffer &cbuf) { 6321638Srgrimes MacroAssembler _masm(&cbuf); 6331638Srgrimes __ illtrap(0); 6341638Srgrimes} 6351638Srgrimes 6361638Srgrimes 6371638Srgrimesintptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) { 6381638Srgrimes assert(n->rule() != loadUB_rule, ""); 6391638Srgrimes 6401638Srgrimes intptr_t offset = 0; 6411638Srgrimes const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP 6421638Srgrimes const Node* addr = n->get_base_and_disp(offset, adr_type); 6431638Srgrimes assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP"); 6441638Srgrimes assert(addr != NULL && addr != (Node*)-1, "invalid addr"); 6451638Srgrimes assert(addr->bottom_type()->isa_oopptr() == atype, ""); 6461638Srgrimes atype = atype->add_offset(offset); 6471638Srgrimes assert(disp32 == offset, "wrong disp32"); 6481638Srgrimes return atype->_offset; 6491638Srgrimes} 6501638Srgrimes 6511638Srgrimes 6521638Srgrimesintptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) { 6531638Srgrimes assert(n->rule() != loadUB_rule, ""); 6541638Srgrimes 6551638Srgrimes intptr_t offset = 0; 6561638Srgrimes Node* addr = n->in(2); 6571638Srgrimes assert(addr->bottom_type()->isa_oopptr() == atype, ""); 6581638Srgrimes if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) { 6591638Srgrimes Node* a = addr->in(2/*AddPNode::Address*/); 6601638Srgrimes Node* o = addr->in(3/*AddPNode::Offset*/); 6611638Srgrimes offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot; 6621638Srgrimes atype = a->bottom_type()->is_ptr()->add_offset(offset); 6631638Srgrimes assert(atype->isa_oop_ptr(), "still an oop"); 6641638Srgrimes } 6651638Srgrimes offset = atype->is_ptr()->_offset; 6661638Srgrimes if (offset != Type::OffsetBot) offset += disp32; 6671638Srgrimes return offset; 6681638Srgrimes} 6691638Srgrimes 6701638Srgrimes// Standard Sparc opcode form2 field breakdown 6711638Srgrimesstatic inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) { 6721638Srgrimes f0 &= (1<<19)-1; // Mask displacement to 19 bits 6731638Srgrimes int op = (f30 << 30) | 6741638Srgrimes (f29 << 29) | 6751638Srgrimes (f25 << 25) | 6761638Srgrimes (f22 << 22) | 6771638Srgrimes (f20 << 20) | 6781638Srgrimes (f19 << 19) | 6791638Srgrimes (f0 << 0); 6801638Srgrimes cbuf.insts()->emit_int32(op); 6811638Srgrimes} 6821638Srgrimes 6831638Srgrimes// Standard Sparc opcode form2 field breakdown 6841638Srgrimesstatic inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) { 6851638Srgrimes f0 >>= 10; // Drop 10 bits 6861638Srgrimes f0 &= (1<<22)-1; // Mask displacement to 22 bits 6871638Srgrimes int op = (f30 << 30) | 6881638Srgrimes (f25 << 25) | 6891638Srgrimes (f22 << 22) | 6901638Srgrimes (f0 << 0); 6911638Srgrimes cbuf.insts()->emit_int32(op); 6921638Srgrimes} 6931638Srgrimes 6941638Srgrimes// Standard Sparc opcode form3 field breakdown 6951638Srgrimesstatic inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) { 6961638Srgrimes int op = (f30 << 30) | 6971638Srgrimes (f25 << 25) | 6981638Srgrimes (f19 << 19) | 6991638Srgrimes (f14 << 14) | 7001638Srgrimes (f5 << 5) | 7011638Srgrimes (f0 << 0); 7021638Srgrimes cbuf.insts()->emit_int32(op); 7031638Srgrimes} 7041638Srgrimes 7051638Srgrimes// Standard Sparc opcode form3 field breakdown 7061638Srgrimesstatic inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) { 7071638Srgrimes simm13 &= (1<<13)-1; // Mask to 13 bits 7081638Srgrimes int op = (f30 << 30) | 7091638Srgrimes (f25 << 25) | 7101638Srgrimes (f19 << 19) | 7111638Srgrimes (f14 << 14) | 7121638Srgrimes (1 << 13) | // bit to indicate immediate-mode 7131638Srgrimes (simm13<<0); 7141638Srgrimes cbuf.insts()->emit_int32(op); 7151638Srgrimes} 7161638Srgrimes 7171638Srgrimesstatic inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) { 7181638Srgrimes simm10 &= (1<<10)-1; // Mask to 10 bits 7191638Srgrimes emit3_simm13(cbuf,f30,f25,f19,f14,simm10); 7201638Srgrimes} 7211638Srgrimes 7221638Srgrimes#ifdef ASSERT 7231638Srgrimes// Helper function for VerifyOops in emit_form3_mem_reg 7241638Srgrimesvoid verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) { 7251638Srgrimes warning("VerifyOops encountered unexpected instruction:"); 7261638Srgrimes n->dump(2); 7271638Srgrimes warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]); 7281638Srgrimes} 7291638Srgrimes#endif 7301638Srgrimes 7311638Srgrimes 7321638Srgrimesvoid emit_form3_mem_reg(CodeBuffer &cbuf, const MachNode* n, int primary, int tertiary, 7331638Srgrimes int src1_enc, int disp32, int src2_enc, int dst_enc) { 7341638Srgrimes 7351638Srgrimes#ifdef ASSERT 7361638Srgrimes // The following code implements the +VerifyOops feature. 7371638Srgrimes // It verifies oop values which are loaded into or stored out of 7381638Srgrimes // the current method activation. +VerifyOops complements techniques 7391638Srgrimes // like ScavengeALot, because it eagerly inspects oops in transit, 7401638Srgrimes // as they enter or leave the stack, as opposed to ScavengeALot, 7411638Srgrimes // which inspects oops "at rest", in the stack or heap, at safepoints. 7421638Srgrimes // For this reason, +VerifyOops can sometimes detect bugs very close 7431638Srgrimes // to their point of creation. It can also serve as a cross-check 7441638Srgrimes // on the validity of oop maps, when used toegether with ScavengeALot. 7451638Srgrimes 7461638Srgrimes // It would be good to verify oops at other points, especially 7471638Srgrimes // when an oop is used as a base pointer for a load or store. 7481638Srgrimes // This is presently difficult, because it is hard to know when 7491638Srgrimes // a base address is biased or not. (If we had such information, 7501638Srgrimes // it would be easy and useful to make a two-argument version of 7511638Srgrimes // verify_oop which unbiases the base, and performs verification.) 7521638Srgrimes 7531638Srgrimes assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary"); 7541638Srgrimes bool is_verified_oop_base = false; 7551638Srgrimes bool is_verified_oop_load = false; 7561638Srgrimes bool is_verified_oop_store = false; 7571638Srgrimes int tmp_enc = -1; 7581638Srgrimes if (VerifyOops && src1_enc != R_SP_enc) { 7591638Srgrimes // classify the op, mainly for an assert check 7601638Srgrimes int st_op = 0, ld_op = 0; 7611638Srgrimes switch (primary) { 7621638Srgrimes case Assembler::stb_op3: st_op = Op_StoreB; break; 7631638Srgrimes case Assembler::sth_op3: st_op = Op_StoreC; break; 7641638Srgrimes case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0 7651638Srgrimes case Assembler::stw_op3: st_op = Op_StoreI; break; 7661638Srgrimes case Assembler::std_op3: st_op = Op_StoreL; break; 7671638Srgrimes case Assembler::stf_op3: st_op = Op_StoreF; break; 7681638Srgrimes case Assembler::stdf_op3: st_op = Op_StoreD; break; 7691638Srgrimes 7701638Srgrimes case Assembler::ldsb_op3: ld_op = Op_LoadB; break; 7711638Srgrimes case Assembler::lduh_op3: ld_op = Op_LoadUS; break; 7721638Srgrimes case Assembler::ldsh_op3: ld_op = Op_LoadS; break; 7731638Srgrimes case Assembler::ldx_op3: // may become LoadP or stay LoadI 7741638Srgrimes case Assembler::ldsw_op3: // may become LoadP or stay LoadI 7751638Srgrimes case Assembler::lduw_op3: ld_op = Op_LoadI; break; 7761638Srgrimes case Assembler::ldd_op3: ld_op = Op_LoadL; break; 7771638Srgrimes case Assembler::ldf_op3: ld_op = Op_LoadF; break; 7781638Srgrimes case Assembler::lddf_op3: ld_op = Op_LoadD; break; 7791638Srgrimes case Assembler::ldub_op3: ld_op = Op_LoadB; break; 7801638Srgrimes case Assembler::prefetch_op3: ld_op = Op_LoadI; break; 7811638Srgrimes 7821638Srgrimes default: ShouldNotReachHere(); 7831638Srgrimes } 7841638Srgrimes if (tertiary == REGP_OP) { 7851638Srgrimes if (st_op == Op_StoreI) st_op = Op_StoreP; 7861638Srgrimes else if (ld_op == Op_LoadI) ld_op = Op_LoadP; 7871638Srgrimes else ShouldNotReachHere(); 7881638Srgrimes if (st_op) { 7891638Srgrimes // a store 7901638Srgrimes // inputs are (0:control, 1:memory, 2:address, 3:value) 7911638Srgrimes Node* n2 = n->in(3); 7921638Srgrimes if (n2 != NULL) { 7931638Srgrimes const Type* t = n2->bottom_type(); 7941638Srgrimes is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 7951638Srgrimes } 7961638Srgrimes } else { 7971638Srgrimes // a load 7981638Srgrimes const Type* t = n->bottom_type(); 7991638Srgrimes is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false; 8001638Srgrimes } 8011638Srgrimes } 8021638Srgrimes 8031638Srgrimes if (ld_op) { 8041638Srgrimes // a Load 8051638Srgrimes // inputs are (0:control, 1:memory, 2:address) 8061638Srgrimes if (!(n->ideal_Opcode()==ld_op) && // Following are special cases 8071638Srgrimes !(n->ideal_Opcode()==Op_LoadLLocked && ld_op==Op_LoadI) && 8081638Srgrimes !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) && 8091638Srgrimes !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) && 8101638Srgrimes !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) && 8111638Srgrimes !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) && 8121638Srgrimes !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) && 8131638Srgrimes !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) && 8141638Srgrimes !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) && 8151638Srgrimes !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) && 8161638Srgrimes !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) && 8171638Srgrimes !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) && 8181638Srgrimes !(n->ideal_Opcode()==Op_PrefetchRead && ld_op==Op_LoadI) && 8191638Srgrimes !(n->ideal_Opcode()==Op_PrefetchWrite && ld_op==Op_LoadI) && 8201638Srgrimes !(n->ideal_Opcode()==Op_Load2I && ld_op==Op_LoadD) && 8211638Srgrimes !(n->ideal_Opcode()==Op_Load4C && ld_op==Op_LoadD) && 8221638Srgrimes !(n->ideal_Opcode()==Op_Load4S && ld_op==Op_LoadD) && 8231638Srgrimes !(n->ideal_Opcode()==Op_Load8B && ld_op==Op_LoadD) && 8241638Srgrimes !(n->rule() == loadUB_rule)) { 8251638Srgrimes verify_oops_warning(n, n->ideal_Opcode(), ld_op); 8261638Srgrimes } 8271638Srgrimes } else if (st_op) { 8281638Srgrimes // a Store 8291638Srgrimes // inputs are (0:control, 1:memory, 2:address, 3:value) 8301638Srgrimes if (!(n->ideal_Opcode()==st_op) && // Following are special cases 8311638Srgrimes !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) && 8321638Srgrimes !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) && 8331638Srgrimes !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) && 8341638Srgrimes !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) && 8351638Srgrimes !(n->ideal_Opcode()==Op_Store2I && st_op==Op_StoreD) && 8361638Srgrimes !(n->ideal_Opcode()==Op_Store4C && st_op==Op_StoreD) && 8371638Srgrimes !(n->ideal_Opcode()==Op_Store8B && st_op==Op_StoreD) && 8381638Srgrimes !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) { 8391638Srgrimes verify_oops_warning(n, n->ideal_Opcode(), st_op); 8401638Srgrimes } 8411638Srgrimes } 8421638Srgrimes 8431638Srgrimes if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) { 8441638Srgrimes Node* addr = n->in(2); 8451638Srgrimes if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) { 8461638Srgrimes const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr? 8471638Srgrimes if (atype != NULL) { 8481638Srgrimes intptr_t offset = get_offset_from_base(n, atype, disp32); 8491638Srgrimes intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32); 8501638Srgrimes if (offset != offset_2) { 8511638Srgrimes get_offset_from_base(n, atype, disp32); 8521638Srgrimes get_offset_from_base_2(n, atype, disp32); 8531638Srgrimes } 8541638Srgrimes assert(offset == offset_2, "different offsets"); 8551638Srgrimes if (offset == disp32) { 8561638Srgrimes // we now know that src1 is a true oop pointer 8571638Srgrimes is_verified_oop_base = true; 8581638Srgrimes if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) { 8591638Srgrimes if( primary == Assembler::ldd_op3 ) { 8601638Srgrimes is_verified_oop_base = false; // Cannot 'ldd' into O7 8611638Srgrimes } else { 8621638Srgrimes tmp_enc = dst_enc; 8631638Srgrimes dst_enc = R_O7_enc; // Load into O7; preserve source oop 8641638Srgrimes assert(src1_enc != dst_enc, ""); 8651638Srgrimes } 8661638Srgrimes } 8671638Srgrimes } 8681638Srgrimes if (st_op && (( offset == oopDesc::klass_offset_in_bytes()) 8691638Srgrimes || offset == oopDesc::mark_offset_in_bytes())) { 8701638Srgrimes // loading the mark should not be allowed either, but 8711638Srgrimes // we don't check this since it conflicts with InlineObjectHash 8721638Srgrimes // usage of LoadINode to get the mark. We could keep the 8731638Srgrimes // check if we create a new LoadMarkNode 8741638Srgrimes // but do not verify the object before its header is initialized 8751638Srgrimes ShouldNotReachHere(); 8761638Srgrimes } 8771638Srgrimes } 8781638Srgrimes } 8791638Srgrimes } 8801638Srgrimes } 8811638Srgrimes#endif 8821638Srgrimes 8831638Srgrimes uint instr; 8841638Srgrimes instr = (Assembler::ldst_op << 30) 8851638Srgrimes | (dst_enc << 25) 8861638Srgrimes | (primary << 19) 8871638Srgrimes | (src1_enc << 14); 8881638Srgrimes 8891638Srgrimes uint index = src2_enc; 8901638Srgrimes int disp = disp32; 8911638Srgrimes 8921638Srgrimes if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) 8931638Srgrimes disp += STACK_BIAS; 8941638Srgrimes 8951638Srgrimes // We should have a compiler bailout here rather than a guarantee. 8961638Srgrimes // Better yet would be some mechanism to handle variable-size matches correctly. 8971638Srgrimes guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" ); 8981638Srgrimes 8991638Srgrimes if( disp == 0 ) { 9001638Srgrimes // use reg-reg form 9011638Srgrimes // bit 13 is already zero 9021638Srgrimes instr |= index; 9031638Srgrimes } else { 9041638Srgrimes // use reg-imm form 9051638Srgrimes instr |= 0x00002000; // set bit 13 to one 9061638Srgrimes instr |= disp & 0x1FFF; 9071638Srgrimes } 9081638Srgrimes 9091638Srgrimes cbuf.insts()->emit_int32(instr); 9101638Srgrimes 9111638Srgrimes#ifdef ASSERT 9121638Srgrimes { 9131638Srgrimes MacroAssembler _masm(&cbuf); 9141638Srgrimes if (is_verified_oop_base) { 9151638Srgrimes __ verify_oop(reg_to_register_object(src1_enc)); 9161638Srgrimes } 9171638Srgrimes if (is_verified_oop_store) { 9181638Srgrimes __ verify_oop(reg_to_register_object(dst_enc)); 9191638Srgrimes } 9201638Srgrimes if (tmp_enc != -1) { 9211638Srgrimes __ mov(O7, reg_to_register_object(tmp_enc)); 9221638Srgrimes } 9231638Srgrimes if (is_verified_oop_load) { 9241638Srgrimes __ verify_oop(reg_to_register_object(dst_enc)); 9251638Srgrimes } 9261638Srgrimes } 9271638Srgrimes#endif 9281638Srgrimes} 9291638Srgrimes 9301638Srgrimesvoid emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false, bool force_far_call = false) { 9311638Srgrimes // The method which records debug information at every safepoint 9321638Srgrimes // expects the call to be the first instruction in the snippet as 9331638Srgrimes // it creates a PcDesc structure which tracks the offset of a call 9341638Srgrimes // from the start of the codeBlob. This offset is computed as 9351638Srgrimes // code_end() - code_begin() of the code which has been emitted 9361638Srgrimes // so far. 9371638Srgrimes // In this particular case we have skirted around the problem by 9381638Srgrimes // putting the "mov" instruction in the delay slot but the problem 9391638Srgrimes // may bite us again at some other point and a cleaner/generic 9401638Srgrimes // solution using relocations would be needed. 9411638Srgrimes MacroAssembler _masm(&cbuf); 9421638Srgrimes __ set_inst_mark(); 9431638Srgrimes 9441638Srgrimes // We flush the current window just so that there is a valid stack copy 9451638Srgrimes // the fact that the current window becomes active again instantly is 9461638Srgrimes // not a problem there is nothing live in it. 9471638Srgrimes 9481638Srgrimes#ifdef ASSERT 9491638Srgrimes int startpos = __ offset(); 9501638Srgrimes#endif /* ASSERT */ 9511638Srgrimes 9521638Srgrimes#ifdef _LP64 9531638Srgrimes // Calls to the runtime or native may not be reachable from compiled code, 9541638Srgrimes // so we generate the far call sequence on 64 bit sparc. 9551638Srgrimes // This code sequence is relocatable to any address, even on LP64. 9561638Srgrimes if ( force_far_call ) { 9571638Srgrimes __ relocate(rtype); 9581638Srgrimes AddressLiteral dest(entry_point); 9591638Srgrimes __ jumpl_to(dest, O7, O7); 9601638Srgrimes } 9611638Srgrimes else 9621638Srgrimes#endif 9631638Srgrimes { 9641638Srgrimes __ call((address)entry_point, rtype); 9651638Srgrimes } 9661638Srgrimes 9671638Srgrimes if (preserve_g2) __ delayed()->mov(G2, L7); 9681638Srgrimes else __ delayed()->nop(); 9691638Srgrimes 9701638Srgrimes if (preserve_g2) __ mov(L7, G2); 9711638Srgrimes 9721638Srgrimes#ifdef ASSERT 9731638Srgrimes if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) { 9741638Srgrimes#ifdef _LP64 9751638Srgrimes // Trash argument dump slots. 9761638Srgrimes __ set(0xb0b8ac0db0b8ac0d, G1); 9771638Srgrimes __ mov(G1, G5); 9781638Srgrimes __ stx(G1, SP, STACK_BIAS + 0x80); 9791638Srgrimes __ stx(G1, SP, STACK_BIAS + 0x88); 9801638Srgrimes __ stx(G1, SP, STACK_BIAS + 0x90); 9811638Srgrimes __ stx(G1, SP, STACK_BIAS + 0x98); 9821638Srgrimes __ stx(G1, SP, STACK_BIAS + 0xA0); 9831638Srgrimes __ stx(G1, SP, STACK_BIAS + 0xA8); 9841638Srgrimes#else // _LP64 9851638Srgrimes // this is also a native call, so smash the first 7 stack locations, 9861638Srgrimes // and the various registers 9871638Srgrimes 9881638Srgrimes // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset], 9891638Srgrimes // while [SP+0x44..0x58] are the argument dump slots. 9901638Srgrimes __ set((intptr_t)0xbaadf00d, G1); 9911638Srgrimes __ mov(G1, G5); 9921638Srgrimes __ sllx(G1, 32, G1); 9931638Srgrimes __ or3(G1, G5, G1); 9941638Srgrimes __ mov(G1, G5); 9951638Srgrimes __ stx(G1, SP, 0x40); 9961638Srgrimes __ stx(G1, SP, 0x48); 9971638Srgrimes __ stx(G1, SP, 0x50); 9981638Srgrimes __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot 9991638Srgrimes#endif // _LP64 10001638Srgrimes } 10011638Srgrimes#endif /*ASSERT*/ 10021638Srgrimes} 10031638Srgrimes 10041638Srgrimes//============================================================================= 10051638Srgrimes// REQUIRED FUNCTIONALITY for encoding 10061638Srgrimesvoid emit_lo(CodeBuffer &cbuf, int val) { } 10071638Srgrimesvoid emit_hi(CodeBuffer &cbuf, int val) { } 10081638Srgrimes 10091638Srgrimes 10101638Srgrimes//============================================================================= 10111638Srgrimes 10121638Srgrimes#ifndef PRODUCT 10131638Srgrimesvoid MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 10141638Srgrimes Compile* C = ra_->C; 10151638Srgrimes 10161638Srgrimes for (int i = 0; i < OptoPrologueNops; i++) { 10171638Srgrimes st->print_cr("NOP"); st->print("\t"); 10181638Srgrimes } 10191638Srgrimes 10201638Srgrimes if( VerifyThread ) { 10211638Srgrimes st->print_cr("Verify_Thread"); st->print("\t"); 10221638Srgrimes } 10231638Srgrimes 10241638Srgrimes size_t framesize = C->frame_slots() << LogBytesPerInt; 10251638Srgrimes 10261638Srgrimes // Calls to C2R adapters often do not accept exceptional returns. 10271638Srgrimes // We require that their callers must bang for them. But be careful, because 10281638Srgrimes // some VM calls (such as call site linkage) can use several kilobytes of 10291638Srgrimes // stack. But the stack safety zone should account for that. 10301638Srgrimes // See bugs 4446381, 4468289, 4497237. 10311638Srgrimes if (C->need_stack_bang(framesize)) { 10321638Srgrimes st->print_cr("! stack bang"); st->print("\t"); 10331638Srgrimes } 10341638Srgrimes 10351638Srgrimes if (Assembler::is_simm13(-framesize)) { 10361638Srgrimes st->print ("SAVE R_SP,-%d,R_SP",framesize); 10371638Srgrimes } else { 10381638Srgrimes st->print_cr("SETHI R_SP,hi%%(-%d),R_G3",framesize); st->print("\t"); 10391638Srgrimes st->print_cr("ADD R_G3,lo%%(-%d),R_G3",framesize); st->print("\t"); 10401638Srgrimes st->print ("SAVE R_SP,R_G3,R_SP"); 10411638Srgrimes } 10421638Srgrimes 10431638Srgrimes} 10441638Srgrimes#endif 10451638Srgrimes 10461638Srgrimesvoid MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 10471638Srgrimes Compile* C = ra_->C; 10481638Srgrimes MacroAssembler _masm(&cbuf); 10491638Srgrimes 10501638Srgrimes for (int i = 0; i < OptoPrologueNops; i++) { 10511638Srgrimes __ nop(); 10521638Srgrimes } 10531638Srgrimes 10541638Srgrimes __ verify_thread(); 10551638Srgrimes 10561638Srgrimes size_t framesize = C->frame_slots() << LogBytesPerInt; 10571638Srgrimes assert(framesize >= 16*wordSize, "must have room for reg. save area"); 10581638Srgrimes assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment"); 10591638Srgrimes 10601638Srgrimes // Calls to C2R adapters often do not accept exceptional returns. 10611638Srgrimes // We require that their callers must bang for them. But be careful, because 10621638Srgrimes // some VM calls (such as call site linkage) can use several kilobytes of 10631638Srgrimes // stack. But the stack safety zone should account for that. 10641638Srgrimes // See bugs 4446381, 4468289, 4497237. 10651638Srgrimes if (C->need_stack_bang(framesize)) { 10661638Srgrimes __ generate_stack_overflow_check(framesize); 10671638Srgrimes } 10681638Srgrimes 10691638Srgrimes if (Assembler::is_simm13(-framesize)) { 10701638Srgrimes __ save(SP, -framesize, SP); 10711638Srgrimes } else { 10721638Srgrimes __ sethi(-framesize & ~0x3ff, G3); 10731638Srgrimes __ add(G3, -framesize & 0x3ff, G3); 10741638Srgrimes __ save(SP, G3, SP); 10751638Srgrimes } 10761638Srgrimes C->set_frame_complete( __ offset() ); 10771638Srgrimes} 10781638Srgrimes 10791638Srgrimesuint MachPrologNode::size(PhaseRegAlloc *ra_) const { 10801638Srgrimes return MachNode::size(ra_); 10811638Srgrimes} 10821638Srgrimes 10831638Srgrimesint MachPrologNode::reloc() const { 10841638Srgrimes return 10; // a large enough number 10851638Srgrimes} 10861638Srgrimes 10871638Srgrimes//============================================================================= 10881638Srgrimes#ifndef PRODUCT 10891638Srgrimesvoid MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 10901638Srgrimes Compile* C = ra_->C; 10911638Srgrimes 10921638Srgrimes if( do_polling() && ra_->C->is_method_compilation() ) { 10931638Srgrimes st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t"); 10941638Srgrimes#ifdef _LP64 10951638Srgrimes st->print("LDX [L0],G0\t!Poll for Safepointing\n\t"); 10961638Srgrimes#else 10971638Srgrimes st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t"); 10981638Srgrimes#endif 10991638Srgrimes } 11001638Srgrimes 11011638Srgrimes if( do_polling() ) 11021638Srgrimes st->print("RET\n\t"); 11031638Srgrimes 11041638Srgrimes st->print("RESTORE"); 11051638Srgrimes} 11061638Srgrimes#endif 11071638Srgrimes 11081638Srgrimesvoid MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 11091638Srgrimes MacroAssembler _masm(&cbuf); 11101638Srgrimes Compile* C = ra_->C; 11111638Srgrimes 11121638Srgrimes __ verify_thread(); 11131638Srgrimes 11141638Srgrimes // If this does safepoint polling, then do it here 11151638Srgrimes if( do_polling() && ra_->C->is_method_compilation() ) { 11161638Srgrimes AddressLiteral polling_page(os::get_polling_page()); 11171638Srgrimes __ sethi(polling_page, L0); 11181638Srgrimes __ relocate(relocInfo::poll_return_type); 11191638Srgrimes __ ld_ptr( L0, 0, G0 ); 11201638Srgrimes } 11211638Srgrimes 11221638Srgrimes // If this is a return, then stuff the restore in the delay slot 11231638Srgrimes if( do_polling() ) { 11241638Srgrimes __ ret(); 11251638Srgrimes __ delayed()->restore(); 11261638Srgrimes } else { 11271638Srgrimes __ restore(); 11281638Srgrimes } 11291638Srgrimes} 11301638Srgrimes 11311638Srgrimesuint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 11321638Srgrimes return MachNode::size(ra_); 11331638Srgrimes} 11341638Srgrimes 11351638Srgrimesint MachEpilogNode::reloc() const { 11361638Srgrimes return 16; // a large enough number 11371638Srgrimes} 11381638Srgrimes 11391638Srgrimesconst Pipeline * MachEpilogNode::pipeline() const { 11401638Srgrimes return MachNode::pipeline_class(); 11411638Srgrimes} 11421638Srgrimes 11431638Srgrimesint MachEpilogNode::safepoint_offset() const { 11441638Srgrimes assert( do_polling(), "no return for this epilog node"); 11451638Srgrimes return MacroAssembler::size_of_sethi(os::get_polling_page()); 11461638Srgrimes} 11471638Srgrimes 11481638Srgrimes//============================================================================= 11491638Srgrimes 11501638Srgrimes// Figure out which register class each belongs in: rc_int, rc_float, rc_stack 11511638Srgrimesenum RC { rc_bad, rc_int, rc_float, rc_stack }; 11521638Srgrimesstatic enum RC rc_class( OptoReg::Name reg ) { 11531638Srgrimes if( !OptoReg::is_valid(reg) ) return rc_bad; 11541638Srgrimes if (OptoReg::is_stack(reg)) return rc_stack; 11551638Srgrimes VMReg r = OptoReg::as_VMReg(reg); 11561638Srgrimes if (r->is_Register()) return rc_int; 11571638Srgrimes assert(r->is_FloatRegister(), "must be"); 11581638Srgrimes return rc_float; 11591638Srgrimes} 11601638Srgrimes 11611638Srgrimesstatic int impl_helper( const MachNode *mach, CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) { 11621638Srgrimes if( cbuf ) { 11631638Srgrimes // Better yet would be some mechanism to handle variable-size matches correctly 11641638Srgrimes if (!Assembler::is_simm13(offset + STACK_BIAS)) { 11651638Srgrimes ra_->C->record_method_not_compilable("unable to handle large constant offsets"); 11661638Srgrimes } else { 11671638Srgrimes emit_form3_mem_reg(*cbuf, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]); 11681638Srgrimes } 11691638Srgrimes } 11701638Srgrimes#ifndef PRODUCT 11711638Srgrimes else if( !do_size ) { 11721638Srgrimes if( size != 0 ) st->print("\n\t"); 11731638Srgrimes if( is_load ) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg)); 11741638Srgrimes else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset); 11751638Srgrimes } 11761638Srgrimes#endif 11771638Srgrimes return size+4; 11781638Srgrimes} 11791638Srgrimes 11801638Srgrimesstatic int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) { 11811638Srgrimes if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] ); 11821638Srgrimes#ifndef PRODUCT 11831638Srgrimes else if( !do_size ) { 11841638Srgrimes if( size != 0 ) st->print("\n\t"); 11851638Srgrimes st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst)); 11861638Srgrimes } 11871638Srgrimes#endif 11881638Srgrimes return size+4; 11891638Srgrimes} 11901638Srgrimes 11911638Srgrimesuint MachSpillCopyNode::implementation( CodeBuffer *cbuf, 11921638Srgrimes PhaseRegAlloc *ra_, 11931638Srgrimes bool do_size, 11941638Srgrimes outputStream* st ) const { 11951638Srgrimes // Get registers to move 11961638Srgrimes OptoReg::Name src_second = ra_->get_reg_second(in(1)); 11971638Srgrimes OptoReg::Name src_first = ra_->get_reg_first(in(1)); 11981638Srgrimes OptoReg::Name dst_second = ra_->get_reg_second(this ); 11991638Srgrimes OptoReg::Name dst_first = ra_->get_reg_first(this ); 12001638Srgrimes 12011638Srgrimes enum RC src_second_rc = rc_class(src_second); 12021638Srgrimes enum RC src_first_rc = rc_class(src_first); 12031638Srgrimes enum RC dst_second_rc = rc_class(dst_second); 12041638Srgrimes enum RC dst_first_rc = rc_class(dst_first); 12051638Srgrimes 12061638Srgrimes assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" ); 12071638Srgrimes 12081638Srgrimes // Generate spill code! 12091638Srgrimes int size = 0; 12101638Srgrimes 12111638Srgrimes if( src_first == dst_first && src_second == dst_second ) 12121638Srgrimes return size; // Self copy, no move 12131638Srgrimes 12141638Srgrimes // -------------------------------------- 12151638Srgrimes // Check for mem-mem move. Load into unused float registers and fall into 12161638Srgrimes // the float-store case. 12171638Srgrimes if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) { 12181638Srgrimes int offset = ra_->reg2offset(src_first); 12191638Srgrimes // Further check for aligned-adjacent pair, so we can use a double load 12201638Srgrimes if( (src_first&1)==0 && src_first+1 == src_second ) { 12211638Srgrimes src_second = OptoReg::Name(R_F31_num); 12221638Srgrimes src_second_rc = rc_float; 12231638Srgrimes size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st); 12241638Srgrimes } else { 12251638Srgrimes size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st); 12261638Srgrimes } 12271638Srgrimes src_first = OptoReg::Name(R_F30_num); 12281638Srgrimes src_first_rc = rc_float; 12291638Srgrimes } 12301638Srgrimes 12311638Srgrimes if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) { 12321638Srgrimes int offset = ra_->reg2offset(src_second); 12331638Srgrimes size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st); 12341638Srgrimes src_second = OptoReg::Name(R_F31_num); 12351638Srgrimes src_second_rc = rc_float; 12361638Srgrimes } 12371638Srgrimes 12381638Srgrimes // -------------------------------------- 12391638Srgrimes // Check for float->int copy; requires a trip through memory 12401638Srgrimes if( src_first_rc == rc_float && dst_first_rc == rc_int ) { 12411638Srgrimes int offset = frame::register_save_words*wordSize; 12421638Srgrimes if( cbuf ) { 12431638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 ); 12441638Srgrimes impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 12451638Srgrimes impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 12461638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 ); 12471638Srgrimes } 12481638Srgrimes#ifndef PRODUCT 12491638Srgrimes else if( !do_size ) { 12501638Srgrimes if( size != 0 ) st->print("\n\t"); 12511638Srgrimes st->print( "SUB R_SP,16,R_SP\n"); 12521638Srgrimes impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 12531638Srgrimes impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 12541638Srgrimes st->print("\tADD R_SP,16,R_SP\n"); 12551638Srgrimes } 12561638Srgrimes#endif 12571638Srgrimes size += 16; 12581638Srgrimes } 12591638Srgrimes 12601638Srgrimes // -------------------------------------- 12611638Srgrimes // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations. 12621638Srgrimes // In such cases, I have to do the big-endian swap. For aligned targets, the 12631638Srgrimes // hardware does the flop for me. Doubles are always aligned, so no problem 12641638Srgrimes // there. Misaligned sources only come from native-long-returns (handled 12651638Srgrimes // special below). 12661638Srgrimes#ifndef _LP64 12671638Srgrimes if( src_first_rc == rc_int && // source is already big-endian 12681638Srgrimes src_second_rc != rc_bad && // 64-bit move 12691638Srgrimes ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst 12701638Srgrimes assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" ); 12711638Srgrimes // Do the big-endian flop. 12721638Srgrimes OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ; 12731638Srgrimes enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc; 12741638Srgrimes } 12751638Srgrimes#endif 12761638Srgrimes 12771638Srgrimes // -------------------------------------- 12781638Srgrimes // Check for integer reg-reg copy 12791638Srgrimes if( src_first_rc == rc_int && dst_first_rc == rc_int ) { 12801638Srgrimes#ifndef _LP64 12811638Srgrimes if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case 12821638Srgrimes // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 12831638Srgrimes // as stored in memory. On a big-endian machine like SPARC, this means that the _second 12841638Srgrimes // operand contains the least significant word of the 64-bit value and vice versa. 12851638Srgrimes OptoReg::Name tmp = OptoReg::Name(R_O7_num); 12861638Srgrimes assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" ); 12871638Srgrimes // Shift O0 left in-place, zero-extend O1, then OR them into the dst 12881638Srgrimes if( cbuf ) { 12891638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 ); 12901638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 ); 12911638Srgrimes emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] ); 12921638Srgrimes#ifndef PRODUCT 12931638Srgrimes } else if( !do_size ) { 12941638Srgrimes if( size != 0 ) st->print("\n\t"); 12951638Srgrimes st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp)); 12961638Srgrimes st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second)); 12971638Srgrimes st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first)); 12981638Srgrimes#endif 12991638Srgrimes } 13001638Srgrimes return size+12; 13011638Srgrimes } 13021638Srgrimes else if( dst_first == R_I0_num && dst_second == R_I1_num ) { 13031638Srgrimes // returning a long value in I0/I1 13041638Srgrimes // a SpillCopy must be able to target a return instruction's reg_class 13051638Srgrimes // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value 13061638Srgrimes // as stored in memory. On a big-endian machine like SPARC, this means that the _second 13071638Srgrimes // operand contains the least significant word of the 64-bit value and vice versa. 13081638Srgrimes OptoReg::Name tdest = dst_first; 13091638Srgrimes 13101638Srgrimes if (src_first == dst_first) { 13111638Srgrimes tdest = OptoReg::Name(R_O7_num); 13121638Srgrimes size += 4; 13131638Srgrimes } 13141638Srgrimes 13151638Srgrimes if( cbuf ) { 13161638Srgrimes assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg"); 13171638Srgrimes // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1 13181638Srgrimes // ShrL_reg_imm6 13191638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 ); 13201638Srgrimes // ShrR_reg_imm6 src, 0, dst 13211638Srgrimes emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 ); 13221638Srgrimes if (tdest != dst_first) { 13231638Srgrimes emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] ); 1324 } 1325 } 1326#ifndef PRODUCT 1327 else if( !do_size ) { 1328 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!! 1329 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest)); 1330 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second)); 1331 if (tdest != dst_first) { 1332 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first)); 1333 } 1334 } 1335#endif // PRODUCT 1336 return size+8; 1337 } 1338#endif // !_LP64 1339 // Else normal reg-reg copy 1340 assert( src_second != dst_first, "smashed second before evacuating it" ); 1341 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st); 1342 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" ); 1343 // This moves an aligned adjacent pair. 1344 // See if we are done. 1345 if( src_first+1 == src_second && dst_first+1 == dst_second ) 1346 return size; 1347 } 1348 1349 // Check for integer store 1350 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) { 1351 int offset = ra_->reg2offset(dst_first); 1352 // Further check for aligned-adjacent pair, so we can use a double store 1353 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1354 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st); 1355 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st); 1356 } 1357 1358 // Check for integer load 1359 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) { 1360 int offset = ra_->reg2offset(src_first); 1361 // Further check for aligned-adjacent pair, so we can use a double load 1362 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1363 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st); 1364 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st); 1365 } 1366 1367 // Check for float reg-reg copy 1368 if( src_first_rc == rc_float && dst_first_rc == rc_float ) { 1369 // Further check for aligned-adjacent pair, so we can use a double move 1370 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1371 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st); 1372 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st); 1373 } 1374 1375 // Check for float store 1376 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) { 1377 int offset = ra_->reg2offset(dst_first); 1378 // Further check for aligned-adjacent pair, so we can use a double store 1379 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1380 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st); 1381 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st); 1382 } 1383 1384 // Check for float load 1385 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) { 1386 int offset = ra_->reg2offset(src_first); 1387 // Further check for aligned-adjacent pair, so we can use a double load 1388 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second ) 1389 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st); 1390 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st); 1391 } 1392 1393 // -------------------------------------------------------------------- 1394 // Check for hi bits still needing moving. Only happens for misaligned 1395 // arguments to native calls. 1396 if( src_second == dst_second ) 1397 return size; // Self copy; no move 1398 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" ); 1399 1400#ifndef _LP64 1401 // In the LP64 build, all registers can be moved as aligned/adjacent 1402 // pairs, so there's never any need to move the high bits separately. 1403 // The 32-bit builds have to deal with the 32-bit ABI which can force 1404 // all sorts of silly alignment problems. 1405 1406 // Check for integer reg-reg copy. Hi bits are stuck up in the top 1407 // 32-bits of a 64-bit register, but are needed in low bits of another 1408 // register (else it's a hi-bits-to-hi-bits copy which should have 1409 // happened already as part of a 64-bit move) 1410 if( src_second_rc == rc_int && dst_second_rc == rc_int ) { 1411 assert( (src_second&1)==1, "its the evil O0/O1 native return case" ); 1412 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" ); 1413 // Shift src_second down to dst_second's low bits. 1414 if( cbuf ) { 1415 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1416#ifndef PRODUCT 1417 } else if( !do_size ) { 1418 if( size != 0 ) st->print("\n\t"); 1419 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second)); 1420#endif 1421 } 1422 return size+4; 1423 } 1424 1425 // Check for high word integer store. Must down-shift the hi bits 1426 // into a temp register, then fall into the case of storing int bits. 1427 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) { 1428 // Shift src_second down to dst_second's low bits. 1429 if( cbuf ) { 1430 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 ); 1431#ifndef PRODUCT 1432 } else if( !do_size ) { 1433 if( size != 0 ) st->print("\n\t"); 1434 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num)); 1435#endif 1436 } 1437 size+=4; 1438 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num! 1439 } 1440 1441 // Check for high word integer load 1442 if( dst_second_rc == rc_int && src_second_rc == rc_stack ) 1443 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st); 1444 1445 // Check for high word integer store 1446 if( src_second_rc == rc_int && dst_second_rc == rc_stack ) 1447 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st); 1448 1449 // Check for high word float store 1450 if( src_second_rc == rc_float && dst_second_rc == rc_stack ) 1451 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st); 1452 1453#endif // !_LP64 1454 1455 Unimplemented(); 1456} 1457 1458#ifndef PRODUCT 1459void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1460 implementation( NULL, ra_, false, st ); 1461} 1462#endif 1463 1464void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1465 implementation( &cbuf, ra_, false, NULL ); 1466} 1467 1468uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1469 return implementation( NULL, ra_, true, NULL ); 1470} 1471 1472//============================================================================= 1473#ifndef PRODUCT 1474void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const { 1475 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count); 1476} 1477#endif 1478 1479void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const { 1480 MacroAssembler _masm(&cbuf); 1481 for(int i = 0; i < _count; i += 1) { 1482 __ nop(); 1483 } 1484} 1485 1486uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1487 return 4 * _count; 1488} 1489 1490 1491//============================================================================= 1492#ifndef PRODUCT 1493void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1494 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1495 int reg = ra_->get_reg_first(this); 1496 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]); 1497} 1498#endif 1499 1500void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1501 MacroAssembler _masm(&cbuf); 1502 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS; 1503 int reg = ra_->get_encode(this); 1504 1505 if (Assembler::is_simm13(offset)) { 1506 __ add(SP, offset, reg_to_register_object(reg)); 1507 } else { 1508 __ set(offset, O7); 1509 __ add(SP, O7, reg_to_register_object(reg)); 1510 } 1511} 1512 1513uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1514 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_) 1515 assert(ra_ == ra_->C->regalloc(), "sanity"); 1516 return ra_->C->scratch_emit_size(this); 1517} 1518 1519//============================================================================= 1520 1521// emit call stub, compiled java to interpretor 1522void emit_java_to_interp(CodeBuffer &cbuf ) { 1523 1524 // Stub is fixed up when the corresponding call is converted from calling 1525 // compiled code to calling interpreted code. 1526 // set (empty), G5 1527 // jmp -1 1528 1529 address mark = cbuf.insts_mark(); // get mark within main instrs section 1530 1531 MacroAssembler _masm(&cbuf); 1532 1533 address base = 1534 __ start_a_stub(Compile::MAX_stubs_size); 1535 if (base == NULL) return; // CodeBuffer::expand failed 1536 1537 // static stub relocation stores the instruction address of the call 1538 __ relocate(static_stub_Relocation::spec(mark)); 1539 1540 __ set_oop(NULL, reg_to_register_object(Matcher::inline_cache_reg_encode())); 1541 1542 __ set_inst_mark(); 1543 AddressLiteral addrlit(-1); 1544 __ JUMP(addrlit, G3, 0); 1545 1546 __ delayed()->nop(); 1547 1548 // Update current stubs pointer and restore code_end. 1549 __ end_a_stub(); 1550} 1551 1552// size of call stub, compiled java to interpretor 1553uint size_java_to_interp() { 1554 // This doesn't need to be accurate but it must be larger or equal to 1555 // the real size of the stub. 1556 return (NativeMovConstReg::instruction_size + // sethi/setlo; 1557 NativeJump::instruction_size + // sethi; jmp; nop 1558 (TraceJumps ? 20 * BytesPerInstWord : 0) ); 1559} 1560// relocation entries for call stub, compiled java to interpretor 1561uint reloc_java_to_interp() { 1562 return 10; // 4 in emit_java_to_interp + 1 in Java_Static_Call 1563} 1564 1565 1566//============================================================================= 1567#ifndef PRODUCT 1568void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const { 1569 st->print_cr("\nUEP:"); 1570#ifdef _LP64 1571 if (UseCompressedOops) { 1572 assert(Universe::heap() != NULL, "java heap should be initialized"); 1573 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass"); 1574 st->print_cr("\tSLL R_G5,3,R_G5"); 1575 if (Universe::narrow_oop_base() != NULL) 1576 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5"); 1577 } else { 1578 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1579 } 1580 st->print_cr("\tCMP R_G5,R_G3" ); 1581 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1582#else // _LP64 1583 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check"); 1584 st->print_cr("\tCMP R_G5,R_G3" ); 1585 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2"); 1586#endif // _LP64 1587} 1588#endif 1589 1590void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1591 MacroAssembler _masm(&cbuf); 1592 Label L; 1593 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 1594 Register temp_reg = G3; 1595 assert( G5_ic_reg != temp_reg, "conflicting registers" ); 1596 1597 // Load klass from receiver 1598 __ load_klass(O0, temp_reg); 1599 // Compare against expected klass 1600 __ cmp(temp_reg, G5_ic_reg); 1601 // Branch to miss code, checks xcc or icc depending 1602 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2); 1603} 1604 1605uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1606 return MachNode::size(ra_); 1607} 1608 1609 1610//============================================================================= 1611 1612uint size_exception_handler() { 1613 if (TraceJumps) { 1614 return (400); // just a guess 1615 } 1616 return ( NativeJump::instruction_size ); // sethi;jmp;nop 1617} 1618 1619uint size_deopt_handler() { 1620 if (TraceJumps) { 1621 return (400); // just a guess 1622 } 1623 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore 1624} 1625 1626// Emit exception handler code. 1627int emit_exception_handler(CodeBuffer& cbuf) { 1628 Register temp_reg = G3; 1629 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point()); 1630 MacroAssembler _masm(&cbuf); 1631 1632 address base = 1633 __ start_a_stub(size_exception_handler()); 1634 if (base == NULL) return 0; // CodeBuffer::expand failed 1635 1636 int offset = __ offset(); 1637 1638 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp 1639 __ delayed()->nop(); 1640 1641 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow"); 1642 1643 __ end_a_stub(); 1644 1645 return offset; 1646} 1647 1648int emit_deopt_handler(CodeBuffer& cbuf) { 1649 // Can't use any of the current frame's registers as we may have deopted 1650 // at a poll and everything (including G3) can be live. 1651 Register temp_reg = L0; 1652 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 1653 MacroAssembler _masm(&cbuf); 1654 1655 address base = 1656 __ start_a_stub(size_deopt_handler()); 1657 if (base == NULL) return 0; // CodeBuffer::expand failed 1658 1659 int offset = __ offset(); 1660 __ save_frame(0); 1661 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp 1662 __ delayed()->restore(); 1663 1664 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow"); 1665 1666 __ end_a_stub(); 1667 return offset; 1668 1669} 1670 1671// Given a register encoding, produce a Integer Register object 1672static Register reg_to_register_object(int register_encoding) { 1673 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding"); 1674 return as_Register(register_encoding); 1675} 1676 1677// Given a register encoding, produce a single-precision Float Register object 1678static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) { 1679 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding"); 1680 return as_SingleFloatRegister(register_encoding); 1681} 1682 1683// Given a register encoding, produce a double-precision Float Register object 1684static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) { 1685 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding"); 1686 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding"); 1687 return as_DoubleFloatRegister(register_encoding); 1688} 1689 1690const bool Matcher::match_rule_supported(int opcode) { 1691 if (!has_match_rule(opcode)) 1692 return false; 1693 1694 switch (opcode) { 1695 case Op_CountLeadingZerosI: 1696 case Op_CountLeadingZerosL: 1697 case Op_CountTrailingZerosI: 1698 case Op_CountTrailingZerosL: 1699 if (!UsePopCountInstruction) 1700 return false; 1701 break; 1702 } 1703 1704 return true; // Per default match rules are supported. 1705} 1706 1707int Matcher::regnum_to_fpu_offset(int regnum) { 1708 return regnum - 32; // The FP registers are in the second chunk 1709} 1710 1711#ifdef ASSERT 1712address last_rethrow = NULL; // debugging aid for Rethrow encoding 1713#endif 1714 1715// Vector width in bytes 1716const uint Matcher::vector_width_in_bytes(void) { 1717 return 8; 1718} 1719 1720// Vector ideal reg 1721const uint Matcher::vector_ideal_reg(void) { 1722 return Op_RegD; 1723} 1724 1725// USII supports fxtof through the whole range of number, USIII doesn't 1726const bool Matcher::convL2FSupported(void) { 1727 return VM_Version::has_fast_fxtof(); 1728} 1729 1730// Is this branch offset short enough that a short branch can be used? 1731// 1732// NOTE: If the platform does not provide any short branch variants, then 1733// this method should return false for offset 0. 1734bool Matcher::is_short_branch_offset(int rule, int offset) { 1735 return false; 1736} 1737 1738const bool Matcher::isSimpleConstant64(jlong value) { 1739 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?. 1740 // Depends on optimizations in MacroAssembler::setx. 1741 int hi = (int)(value >> 32); 1742 int lo = (int)(value & ~0); 1743 return (hi == 0) || (hi == -1) || (lo == 0); 1744} 1745 1746// No scaling for the parameter the ClearArray node. 1747const bool Matcher::init_array_count_is_in_bytes = true; 1748 1749// Threshold size for cleararray. 1750const int Matcher::init_array_short_size = 8 * BytesPerLong; 1751 1752// Should the Matcher clone shifts on addressing modes, expecting them to 1753// be subsumed into complex addressing expressions or compute them into 1754// registers? True for Intel but false for most RISCs 1755const bool Matcher::clone_shift_expressions = false; 1756 1757bool Matcher::narrow_oop_use_complex_address() { 1758 NOT_LP64(ShouldNotCallThis()); 1759 assert(UseCompressedOops, "only for compressed oops code"); 1760 return false; 1761} 1762 1763// Is it better to copy float constants, or load them directly from memory? 1764// Intel can load a float constant from a direct address, requiring no 1765// extra registers. Most RISCs will have to materialize an address into a 1766// register first, so they would do better to copy the constant from stack. 1767const bool Matcher::rematerialize_float_constants = false; 1768 1769// If CPU can load and store mis-aligned doubles directly then no fixup is 1770// needed. Else we split the double into 2 integer pieces and move it 1771// piece-by-piece. Only happens when passing doubles into C code as the 1772// Java calling convention forces doubles to be aligned. 1773#ifdef _LP64 1774const bool Matcher::misaligned_doubles_ok = true; 1775#else 1776const bool Matcher::misaligned_doubles_ok = false; 1777#endif 1778 1779// No-op on SPARC. 1780void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 1781} 1782 1783// Advertise here if the CPU requires explicit rounding operations 1784// to implement the UseStrictFP mode. 1785const bool Matcher::strict_fp_requires_explicit_rounding = false; 1786 1787// Are floats conerted to double when stored to stack during deoptimization? 1788// Sparc does not handle callee-save floats. 1789bool Matcher::float_in_double() { return false; } 1790 1791// Do ints take an entire long register or just half? 1792// Note that we if-def off of _LP64. 1793// The relevant question is how the int is callee-saved. In _LP64 1794// the whole long is written but de-opt'ing will have to extract 1795// the relevant 32 bits, in not-_LP64 only the low 32 bits is written. 1796#ifdef _LP64 1797const bool Matcher::int_in_long = true; 1798#else 1799const bool Matcher::int_in_long = false; 1800#endif 1801 1802// Return whether or not this register is ever used as an argument. This 1803// function is used on startup to build the trampoline stubs in generateOptoStub. 1804// Registers not mentioned will be killed by the VM call in the trampoline, and 1805// arguments in those registers not be available to the callee. 1806bool Matcher::can_be_java_arg( int reg ) { 1807 // Standard sparc 6 args in registers 1808 if( reg == R_I0_num || 1809 reg == R_I1_num || 1810 reg == R_I2_num || 1811 reg == R_I3_num || 1812 reg == R_I4_num || 1813 reg == R_I5_num ) return true; 1814#ifdef _LP64 1815 // 64-bit builds can pass 64-bit pointers and longs in 1816 // the high I registers 1817 if( reg == R_I0H_num || 1818 reg == R_I1H_num || 1819 reg == R_I2H_num || 1820 reg == R_I3H_num || 1821 reg == R_I4H_num || 1822 reg == R_I5H_num ) return true; 1823 1824 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) { 1825 return true; 1826 } 1827 1828#else 1829 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4. 1830 // Longs cannot be passed in O regs, because O regs become I regs 1831 // after a 'save' and I regs get their high bits chopped off on 1832 // interrupt. 1833 if( reg == R_G1H_num || reg == R_G1_num ) return true; 1834 if( reg == R_G4H_num || reg == R_G4_num ) return true; 1835#endif 1836 // A few float args in registers 1837 if( reg >= R_F0_num && reg <= R_F7_num ) return true; 1838 1839 return false; 1840} 1841 1842bool Matcher::is_spillable_arg( int reg ) { 1843 return can_be_java_arg(reg); 1844} 1845 1846// Register for DIVI projection of divmodI 1847RegMask Matcher::divI_proj_mask() { 1848 ShouldNotReachHere(); 1849 return RegMask(); 1850} 1851 1852// Register for MODI projection of divmodI 1853RegMask Matcher::modI_proj_mask() { 1854 ShouldNotReachHere(); 1855 return RegMask(); 1856} 1857 1858// Register for DIVL projection of divmodL 1859RegMask Matcher::divL_proj_mask() { 1860 ShouldNotReachHere(); 1861 return RegMask(); 1862} 1863 1864// Register for MODL projection of divmodL 1865RegMask Matcher::modL_proj_mask() { 1866 ShouldNotReachHere(); 1867 return RegMask(); 1868} 1869 1870const RegMask Matcher::method_handle_invoke_SP_save_mask() { 1871 return L7_REGP_mask; 1872} 1873 1874%} 1875 1876 1877// The intptr_t operand types, defined by textual substitution. 1878// (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.) 1879#ifdef _LP64 1880#define immX immL 1881#define immX13 immL13 1882#define immX13m7 immL13m7 1883#define iRegX iRegL 1884#define g1RegX g1RegL 1885#else 1886#define immX immI 1887#define immX13 immI13 1888#define immX13m7 immI13m7 1889#define iRegX iRegI 1890#define g1RegX g1RegI 1891#endif 1892 1893//----------ENCODING BLOCK----------------------------------------------------- 1894// This block specifies the encoding classes used by the compiler to output 1895// byte streams. Encoding classes are parameterized macros used by 1896// Machine Instruction Nodes in order to generate the bit encoding of the 1897// instruction. Operands specify their base encoding interface with the 1898// interface keyword. There are currently supported four interfaces, 1899// REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 1900// operand to generate a function which returns its register number when 1901// queried. CONST_INTER causes an operand to generate a function which 1902// returns the value of the constant when queried. MEMORY_INTER causes an 1903// operand to generate four functions which return the Base Register, the 1904// Index Register, the Scale Value, and the Offset Value of the operand when 1905// queried. COND_INTER causes an operand to generate six functions which 1906// return the encoding code (ie - encoding bits for the instruction) 1907// associated with each basic boolean condition for a conditional instruction. 1908// 1909// Instructions specify two basic values for encoding. Again, a function 1910// is available to check if the constant displacement is an oop. They use the 1911// ins_encode keyword to specify their encoding classes (which must be 1912// a sequence of enc_class names, and their parameters, specified in 1913// the encoding block), and they use the 1914// opcode keyword to specify, in order, their primary, secondary, and 1915// tertiary opcode. Only the opcode sections which a particular instruction 1916// needs for encoding need to be specified. 1917encode %{ 1918 enc_class enc_untested %{ 1919#ifdef ASSERT 1920 MacroAssembler _masm(&cbuf); 1921 __ untested("encoding"); 1922#endif 1923 %} 1924 1925 enc_class form3_mem_reg( memory mem, iRegI dst ) %{ 1926 emit_form3_mem_reg(cbuf, this, $primary, $tertiary, 1927 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1928 %} 1929 1930 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{ 1931 emit_form3_mem_reg(cbuf, this, $primary, -1, 1932 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg); 1933 %} 1934 1935 enc_class form3_mem_prefetch_read( memory mem ) %{ 1936 emit_form3_mem_reg(cbuf, this, $primary, -1, 1937 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/); 1938 %} 1939 1940 enc_class form3_mem_prefetch_write( memory mem ) %{ 1941 emit_form3_mem_reg(cbuf, this, $primary, -1, 1942 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/); 1943 %} 1944 1945 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{ 1946 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1947 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1948 guarantee($mem$$index == R_G0_enc, "double index?"); 1949 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc ); 1950 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg ); 1951 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 ); 1952 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc ); 1953 %} 1954 1955 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{ 1956 assert( Assembler::is_simm13($mem$$disp ), "need disp and disp+4" ); 1957 assert( Assembler::is_simm13($mem$$disp+4), "need disp and disp+4" ); 1958 guarantee($mem$$index == R_G0_enc, "double index?"); 1959 // Load long with 2 instructions 1960 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 ); 1961 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 ); 1962 %} 1963 1964 //%%% form3_mem_plus_4_reg is a hack--get rid of it 1965 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{ 1966 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4"); 1967 emit_form3_mem_reg(cbuf, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg); 1968 %} 1969 1970 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{ 1971 // Encode a reg-reg copy. If it is useless, then empty encoding. 1972 if( $rs2$$reg != $rd$$reg ) 1973 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg ); 1974 %} 1975 1976 // Target lo half of long 1977 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{ 1978 // Encode a reg-reg copy. If it is useless, then empty encoding. 1979 if( $rs2$$reg != LONG_LO_REG($rd$$reg) ) 1980 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg ); 1981 %} 1982 1983 // Source lo half of long 1984 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{ 1985 // Encode a reg-reg copy. If it is useless, then empty encoding. 1986 if( LONG_LO_REG($rs2$$reg) != $rd$$reg ) 1987 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) ); 1988 %} 1989 1990 // Target hi half of long 1991 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{ 1992 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 ); 1993 %} 1994 1995 // Source lo half of long, and leave it sign extended. 1996 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{ 1997 // Sign extend low half 1998 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 ); 1999 %} 2000 2001 // Source hi half of long, and leave it sign extended. 2002 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{ 2003 // Shift high half to low half 2004 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 ); 2005 %} 2006 2007 // Source hi half of long 2008 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{ 2009 // Encode a reg-reg copy. If it is useless, then empty encoding. 2010 if( LONG_HI_REG($rs2$$reg) != $rd$$reg ) 2011 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) ); 2012 %} 2013 2014 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{ 2015 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg ); 2016 %} 2017 2018 enc_class enc_to_bool( iRegI src, iRegI dst ) %{ 2019 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg ); 2020 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 ); 2021 %} 2022 2023 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{ 2024 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg ); 2025 // clear if nothing else is happening 2026 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 ); 2027 // blt,a,pn done 2028 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 ); 2029 // mov dst,-1 in delay slot 2030 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2031 %} 2032 2033 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{ 2034 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F ); 2035 %} 2036 2037 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{ 2038 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 ); 2039 %} 2040 2041 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{ 2042 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg ); 2043 %} 2044 2045 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{ 2046 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant ); 2047 %} 2048 2049 enc_class move_return_pc_to_o1() %{ 2050 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset ); 2051 %} 2052 2053#ifdef _LP64 2054 /* %%% merge with enc_to_bool */ 2055 enc_class enc_convP2B( iRegI dst, iRegP src ) %{ 2056 MacroAssembler _masm(&cbuf); 2057 2058 Register src_reg = reg_to_register_object($src$$reg); 2059 Register dst_reg = reg_to_register_object($dst$$reg); 2060 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg); 2061 %} 2062#endif 2063 2064 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{ 2065 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))) 2066 MacroAssembler _masm(&cbuf); 2067 2068 Register p_reg = reg_to_register_object($p$$reg); 2069 Register q_reg = reg_to_register_object($q$$reg); 2070 Register y_reg = reg_to_register_object($y$$reg); 2071 Register tmp_reg = reg_to_register_object($tmp$$reg); 2072 2073 __ subcc( p_reg, q_reg, p_reg ); 2074 __ add ( p_reg, y_reg, tmp_reg ); 2075 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg ); 2076 %} 2077 2078 enc_class form_d2i_helper(regD src, regF dst) %{ 2079 // fcmp %fcc0,$src,$src 2080 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2081 // branch %fcc0 not-nan, predict taken 2082 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2083 // fdtoi $src,$dst 2084 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg ); 2085 // fitos $dst,$dst (if nan) 2086 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2087 // clear $dst (if nan) 2088 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2089 // carry on here... 2090 %} 2091 2092 enc_class form_d2l_helper(regD src, regD dst) %{ 2093 // fcmp %fcc0,$src,$src check for NAN 2094 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg ); 2095 // branch %fcc0 not-nan, predict taken 2096 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2097 // fdtox $src,$dst convert in delay slot 2098 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg ); 2099 // fxtod $dst,$dst (if nan) 2100 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2101 // clear $dst (if nan) 2102 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2103 // carry on here... 2104 %} 2105 2106 enc_class form_f2i_helper(regF src, regF dst) %{ 2107 // fcmps %fcc0,$src,$src 2108 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2109 // branch %fcc0 not-nan, predict taken 2110 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2111 // fstoi $src,$dst 2112 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg ); 2113 // fitos $dst,$dst (if nan) 2114 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg ); 2115 // clear $dst (if nan) 2116 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg ); 2117 // carry on here... 2118 %} 2119 2120 enc_class form_f2l_helper(regF src, regD dst) %{ 2121 // fcmps %fcc0,$src,$src 2122 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg ); 2123 // branch %fcc0 not-nan, predict taken 2124 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 ); 2125 // fstox $src,$dst 2126 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg ); 2127 // fxtod $dst,$dst (if nan) 2128 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg ); 2129 // clear $dst (if nan) 2130 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg ); 2131 // carry on here... 2132 %} 2133 2134 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2135 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2136 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2137 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2138 2139 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %} 2140 2141 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %} 2142 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %} 2143 2144 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{ 2145 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2146 %} 2147 2148 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{ 2149 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2150 %} 2151 2152 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{ 2153 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2154 %} 2155 2156 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{ 2157 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg ); 2158 %} 2159 2160 enc_class form3_convI2F(regF rs2, regF rd) %{ 2161 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg); 2162 %} 2163 2164 // Encloding class for traceable jumps 2165 enc_class form_jmpl(g3RegP dest) %{ 2166 emit_jmpl(cbuf, $dest$$reg); 2167 %} 2168 2169 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{ 2170 emit_jmpl_set_exception_pc(cbuf, $dest$$reg); 2171 %} 2172 2173 enc_class form2_nop() %{ 2174 emit_nop(cbuf); 2175 %} 2176 2177 enc_class form2_illtrap() %{ 2178 emit_illtrap(cbuf); 2179 %} 2180 2181 2182 // Compare longs and convert into -1, 0, 1. 2183 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{ 2184 // CMP $src1,$src2 2185 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg ); 2186 // blt,a,pn done 2187 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 ); 2188 // mov dst,-1 in delay slot 2189 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 ); 2190 // bgt,a,pn done 2191 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 ); 2192 // mov dst,1 in delay slot 2193 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 ); 2194 // CLR $dst 2195 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 ); 2196 %} 2197 2198 enc_class enc_PartialSubtypeCheck() %{ 2199 MacroAssembler _masm(&cbuf); 2200 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type); 2201 __ delayed()->nop(); 2202 %} 2203 2204 enc_class enc_bp( Label labl, cmpOp cmp, flagsReg cc ) %{ 2205 MacroAssembler _masm(&cbuf); 2206 Label &L = *($labl$$label); 2207 Assembler::Predict predict_taken = 2208 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2209 2210 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, L); 2211 __ delayed()->nop(); 2212 %} 2213 2214 enc_class enc_bpl( Label labl, cmpOp cmp, flagsRegL cc ) %{ 2215 MacroAssembler _masm(&cbuf); 2216 Label &L = *($labl$$label); 2217 Assembler::Predict predict_taken = 2218 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2219 2220 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, L); 2221 __ delayed()->nop(); 2222 %} 2223 2224 enc_class enc_bpx( Label labl, cmpOp cmp, flagsRegP cc ) %{ 2225 MacroAssembler _masm(&cbuf); 2226 Label &L = *($labl$$label); 2227 Assembler::Predict predict_taken = 2228 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2229 2230 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, L); 2231 __ delayed()->nop(); 2232 %} 2233 2234 enc_class enc_fbp( Label labl, cmpOpF cmp, flagsRegF cc ) %{ 2235 MacroAssembler _masm(&cbuf); 2236 Label &L = *($labl$$label); 2237 Assembler::Predict predict_taken = 2238 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2239 2240 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($cc$$reg), predict_taken, L); 2241 __ delayed()->nop(); 2242 %} 2243 2244 enc_class jump_enc( iRegX switch_val, o7RegI table) %{ 2245 MacroAssembler _masm(&cbuf); 2246 2247 Register switch_reg = as_Register($switch_val$$reg); 2248 Register table_reg = O7; 2249 2250 address table_base = __ address_table_constant(_index2label); 2251 RelocationHolder rspec = internal_word_Relocation::spec(table_base); 2252 2253 // Move table address into a register. 2254 __ set(table_base, table_reg, rspec); 2255 2256 // Jump to base address + switch value 2257 __ ld_ptr(table_reg, switch_reg, table_reg); 2258 __ jmp(table_reg, G0); 2259 __ delayed()->nop(); 2260 2261 %} 2262 2263 enc_class enc_ba( Label labl ) %{ 2264 MacroAssembler _masm(&cbuf); 2265 Label &L = *($labl$$label); 2266 __ ba(false, L); 2267 __ delayed()->nop(); 2268 %} 2269 2270 enc_class enc_bpr( Label labl, cmpOp_reg cmp, iRegI op1 ) %{ 2271 MacroAssembler _masm(&cbuf); 2272 Label &L = *$labl$$label; 2273 Assembler::Predict predict_taken = 2274 cbuf.is_backward_branch(L) ? Assembler::pt : Assembler::pn; 2275 2276 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), L); 2277 __ delayed()->nop(); 2278 %} 2279 2280 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{ 2281 int op = (Assembler::arith_op << 30) | 2282 ($dst$$reg << 25) | 2283 (Assembler::movcc_op3 << 19) | 2284 (1 << 18) | // cc2 bit for 'icc' 2285 ($cmp$$cmpcode << 14) | 2286 (0 << 13) | // select register move 2287 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc' 2288 ($src$$reg << 0); 2289 cbuf.insts()->emit_int32(op); 2290 %} 2291 2292 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{ 2293 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2294 int op = (Assembler::arith_op << 30) | 2295 ($dst$$reg << 25) | 2296 (Assembler::movcc_op3 << 19) | 2297 (1 << 18) | // cc2 bit for 'icc' 2298 ($cmp$$cmpcode << 14) | 2299 (1 << 13) | // select immediate move 2300 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' 2301 (simm11 << 0); 2302 cbuf.insts()->emit_int32(op); 2303 %} 2304 2305 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{ 2306 int op = (Assembler::arith_op << 30) | 2307 ($dst$$reg << 25) | 2308 (Assembler::movcc_op3 << 19) | 2309 (0 << 18) | // cc2 bit for 'fccX' 2310 ($cmp$$cmpcode << 14) | 2311 (0 << 13) | // select register move 2312 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2313 ($src$$reg << 0); 2314 cbuf.insts()->emit_int32(op); 2315 %} 2316 2317 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{ 2318 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits 2319 int op = (Assembler::arith_op << 30) | 2320 ($dst$$reg << 25) | 2321 (Assembler::movcc_op3 << 19) | 2322 (0 << 18) | // cc2 bit for 'fccX' 2323 ($cmp$$cmpcode << 14) | 2324 (1 << 13) | // select immediate move 2325 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3 2326 (simm11 << 0); 2327 cbuf.insts()->emit_int32(op); 2328 %} 2329 2330 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{ 2331 int op = (Assembler::arith_op << 30) | 2332 ($dst$$reg << 25) | 2333 (Assembler::fpop2_op3 << 19) | 2334 (0 << 18) | 2335 ($cmp$$cmpcode << 14) | 2336 (1 << 13) | // select register move 2337 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc' 2338 ($primary << 5) | // select single, double or quad 2339 ($src$$reg << 0); 2340 cbuf.insts()->emit_int32(op); 2341 %} 2342 2343 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{ 2344 int op = (Assembler::arith_op << 30) | 2345 ($dst$$reg << 25) | 2346 (Assembler::fpop2_op3 << 19) | 2347 (0 << 18) | 2348 ($cmp$$cmpcode << 14) | 2349 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX' 2350 ($primary << 5) | // select single, double or quad 2351 ($src$$reg << 0); 2352 cbuf.insts()->emit_int32(op); 2353 %} 2354 2355 // Used by the MIN/MAX encodings. Same as a CMOV, but 2356 // the condition comes from opcode-field instead of an argument. 2357 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{ 2358 int op = (Assembler::arith_op << 30) | 2359 ($dst$$reg << 25) | 2360 (Assembler::movcc_op3 << 19) | 2361 (1 << 18) | // cc2 bit for 'icc' 2362 ($primary << 14) | 2363 (0 << 13) | // select register move 2364 (0 << 11) | // cc1, cc0 bits for 'icc' 2365 ($src$$reg << 0); 2366 cbuf.insts()->emit_int32(op); 2367 %} 2368 2369 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{ 2370 int op = (Assembler::arith_op << 30) | 2371 ($dst$$reg << 25) | 2372 (Assembler::movcc_op3 << 19) | 2373 (6 << 16) | // cc2 bit for 'xcc' 2374 ($primary << 14) | 2375 (0 << 13) | // select register move 2376 (0 << 11) | // cc1, cc0 bits for 'icc' 2377 ($src$$reg << 0); 2378 cbuf.insts()->emit_int32(op); 2379 %} 2380 2381 // Utility encoding for loading a 64 bit Pointer into a register 2382 // The 64 bit pointer is stored in the generated code stream 2383 enc_class SetPtr( immP src, iRegP rd ) %{ 2384 Register dest = reg_to_register_object($rd$$reg); 2385 MacroAssembler _masm(&cbuf); 2386 // [RGV] This next line should be generated from ADLC 2387 if ( _opnds[1]->constant_is_oop() ) { 2388 intptr_t val = $src$$constant; 2389 __ set_oop_constant((jobject)val, dest); 2390 } else { // non-oop pointers, e.g. card mark base, heap top 2391 __ set($src$$constant, dest); 2392 } 2393 %} 2394 2395 enc_class Set13( immI13 src, iRegI rd ) %{ 2396 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant ); 2397 %} 2398 2399 enc_class SetHi22( immI src, iRegI rd ) %{ 2400 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant ); 2401 %} 2402 2403 enc_class Set32( immI src, iRegI rd ) %{ 2404 MacroAssembler _masm(&cbuf); 2405 __ set($src$$constant, reg_to_register_object($rd$$reg)); 2406 %} 2407 2408 enc_class SetNull( iRegI rd ) %{ 2409 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0 ); 2410 %} 2411 2412 enc_class call_epilog %{ 2413 if( VerifyStackAtCalls ) { 2414 MacroAssembler _masm(&cbuf); 2415 int framesize = ra_->C->frame_slots() << LogBytesPerInt; 2416 Register temp_reg = G3; 2417 __ add(SP, framesize, temp_reg); 2418 __ cmp(temp_reg, FP); 2419 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc); 2420 } 2421 %} 2422 2423 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value 2424 // to G1 so the register allocator will not have to deal with the misaligned register 2425 // pair. 2426 enc_class adjust_long_from_native_call %{ 2427#ifndef _LP64 2428 if (returns_long()) { 2429 // sllx O0,32,O0 2430 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 ); 2431 // srl O1,0,O1 2432 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 ); 2433 // or O0,O1,G1 2434 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc ); 2435 } 2436#endif 2437 %} 2438 2439 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime 2440 // CALL directly to the runtime 2441 // The user of this is responsible for ensuring that R_L7 is empty (killed). 2442 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type, 2443 /*preserve_g2=*/true, /*force far call*/true); 2444 %} 2445 2446 enc_class preserve_SP %{ 2447 MacroAssembler _masm(&cbuf); 2448 __ mov(SP, L7_mh_SP_save); 2449 %} 2450 2451 enc_class restore_SP %{ 2452 MacroAssembler _masm(&cbuf); 2453 __ mov(L7_mh_SP_save, SP); 2454 %} 2455 2456 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL 2457 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2458 // who we intended to call. 2459 if ( !_method ) { 2460 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type); 2461 } else if (_optimized_virtual) { 2462 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type); 2463 } else { 2464 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type); 2465 } 2466 if( _method ) { // Emit stub for static call 2467 emit_java_to_interp(cbuf); 2468 } 2469 %} 2470 2471 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL 2472 MacroAssembler _masm(&cbuf); 2473 __ set_inst_mark(); 2474 int vtable_index = this->_vtable_index; 2475 // MachCallDynamicJavaNode::ret_addr_offset uses this same test 2476 if (vtable_index < 0) { 2477 // must be invalid_vtable_index, not nonvirtual_vtable_index 2478 assert(vtable_index == methodOopDesc::invalid_vtable_index, "correct sentinel value"); 2479 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2480 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()"); 2481 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub"); 2482 // !!!!! 2483 // Generate "set 0x01, R_G5", placeholder instruction to load oop-info 2484 // emit_call_dynamic_prologue( cbuf ); 2485 __ set_oop((jobject)Universe::non_oop_word(), G5_ic_reg); 2486 2487 address virtual_call_oop_addr = __ inst_mark(); 2488 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine 2489 // who we intended to call. 2490 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr)); 2491 emit_call_reloc(cbuf, $meth$$method, relocInfo::none); 2492 } else { 2493 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 2494 // Just go thru the vtable 2495 // get receiver klass (receiver already checked for non-null) 2496 // If we end up going thru a c2i adapter interpreter expects method in G5 2497 int off = __ offset(); 2498 __ load_klass(O0, G3_scratch); 2499 int klass_load_size; 2500 if (UseCompressedOops) { 2501 assert(Universe::heap() != NULL, "java heap should be initialized"); 2502 if (Universe::narrow_oop_base() == NULL) 2503 klass_load_size = 2*BytesPerInstWord; 2504 else 2505 klass_load_size = 3*BytesPerInstWord; 2506 } else { 2507 klass_load_size = 1*BytesPerInstWord; 2508 } 2509 int entry_offset = instanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size(); 2510 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes(); 2511 if( __ is_simm13(v_off) ) { 2512 __ ld_ptr(G3, v_off, G5_method); 2513 } else { 2514 // Generate 2 instructions 2515 __ Assembler::sethi(v_off & ~0x3ff, G5_method); 2516 __ or3(G5_method, v_off & 0x3ff, G5_method); 2517 // ld_ptr, set_hi, set 2518 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord, 2519 "Unexpected instruction size(s)"); 2520 __ ld_ptr(G3, G5_method, G5_method); 2521 } 2522 // NOTE: for vtable dispatches, the vtable entry will never be null. 2523 // However it may very well end up in handle_wrong_method if the 2524 // method is abstract for the particular class. 2525 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 2526 // jump to target (either compiled code or c2iadapter) 2527 __ jmpl(G3_scratch, G0, O7); 2528 __ delayed()->nop(); 2529 } 2530 %} 2531 2532 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL 2533 MacroAssembler _masm(&cbuf); 2534 2535 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode()); 2536 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because 2537 // we might be calling a C2I adapter which needs it. 2538 2539 assert(temp_reg != G5_ic_reg, "conflicting registers"); 2540 // Load nmethod 2541 __ ld_ptr(G5_ic_reg, in_bytes(methodOopDesc::from_compiled_offset()), temp_reg); 2542 2543 // CALL to compiled java, indirect the contents of G3 2544 __ set_inst_mark(); 2545 __ callr(temp_reg, G0); 2546 __ delayed()->nop(); 2547 %} 2548 2549enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{ 2550 MacroAssembler _masm(&cbuf); 2551 Register Rdividend = reg_to_register_object($src1$$reg); 2552 Register Rdivisor = reg_to_register_object($src2$$reg); 2553 Register Rresult = reg_to_register_object($dst$$reg); 2554 2555 __ sra(Rdivisor, 0, Rdivisor); 2556 __ sra(Rdividend, 0, Rdividend); 2557 __ sdivx(Rdividend, Rdivisor, Rresult); 2558%} 2559 2560enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{ 2561 MacroAssembler _masm(&cbuf); 2562 2563 Register Rdividend = reg_to_register_object($src1$$reg); 2564 int divisor = $imm$$constant; 2565 Register Rresult = reg_to_register_object($dst$$reg); 2566 2567 __ sra(Rdividend, 0, Rdividend); 2568 __ sdivx(Rdividend, divisor, Rresult); 2569%} 2570 2571enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{ 2572 MacroAssembler _masm(&cbuf); 2573 Register Rsrc1 = reg_to_register_object($src1$$reg); 2574 Register Rsrc2 = reg_to_register_object($src2$$reg); 2575 Register Rdst = reg_to_register_object($dst$$reg); 2576 2577 __ sra( Rsrc1, 0, Rsrc1 ); 2578 __ sra( Rsrc2, 0, Rsrc2 ); 2579 __ mulx( Rsrc1, Rsrc2, Rdst ); 2580 __ srlx( Rdst, 32, Rdst ); 2581%} 2582 2583enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{ 2584 MacroAssembler _masm(&cbuf); 2585 Register Rdividend = reg_to_register_object($src1$$reg); 2586 Register Rdivisor = reg_to_register_object($src2$$reg); 2587 Register Rresult = reg_to_register_object($dst$$reg); 2588 Register Rscratch = reg_to_register_object($scratch$$reg); 2589 2590 assert(Rdividend != Rscratch, ""); 2591 assert(Rdivisor != Rscratch, ""); 2592 2593 __ sra(Rdividend, 0, Rdividend); 2594 __ sra(Rdivisor, 0, Rdivisor); 2595 __ sdivx(Rdividend, Rdivisor, Rscratch); 2596 __ mulx(Rscratch, Rdivisor, Rscratch); 2597 __ sub(Rdividend, Rscratch, Rresult); 2598%} 2599 2600enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{ 2601 MacroAssembler _masm(&cbuf); 2602 2603 Register Rdividend = reg_to_register_object($src1$$reg); 2604 int divisor = $imm$$constant; 2605 Register Rresult = reg_to_register_object($dst$$reg); 2606 Register Rscratch = reg_to_register_object($scratch$$reg); 2607 2608 assert(Rdividend != Rscratch, ""); 2609 2610 __ sra(Rdividend, 0, Rdividend); 2611 __ sdivx(Rdividend, divisor, Rscratch); 2612 __ mulx(Rscratch, divisor, Rscratch); 2613 __ sub(Rdividend, Rscratch, Rresult); 2614%} 2615 2616enc_class fabss (sflt_reg dst, sflt_reg src) %{ 2617 MacroAssembler _masm(&cbuf); 2618 2619 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2620 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2621 2622 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst); 2623%} 2624 2625enc_class fabsd (dflt_reg dst, dflt_reg src) %{ 2626 MacroAssembler _masm(&cbuf); 2627 2628 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2629 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2630 2631 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst); 2632%} 2633 2634enc_class fnegd (dflt_reg dst, dflt_reg src) %{ 2635 MacroAssembler _masm(&cbuf); 2636 2637 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2638 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2639 2640 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst); 2641%} 2642 2643enc_class fsqrts (sflt_reg dst, sflt_reg src) %{ 2644 MacroAssembler _masm(&cbuf); 2645 2646 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2647 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2648 2649 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst); 2650%} 2651 2652enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{ 2653 MacroAssembler _masm(&cbuf); 2654 2655 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2656 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2657 2658 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst); 2659%} 2660 2661enc_class fmovs (dflt_reg dst, dflt_reg src) %{ 2662 MacroAssembler _masm(&cbuf); 2663 2664 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg); 2665 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg); 2666 2667 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst); 2668%} 2669 2670enc_class fmovd (dflt_reg dst, dflt_reg src) %{ 2671 MacroAssembler _masm(&cbuf); 2672 2673 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg); 2674 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg); 2675 2676 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst); 2677%} 2678 2679enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2680 MacroAssembler _masm(&cbuf); 2681 2682 Register Roop = reg_to_register_object($oop$$reg); 2683 Register Rbox = reg_to_register_object($box$$reg); 2684 Register Rscratch = reg_to_register_object($scratch$$reg); 2685 Register Rmark = reg_to_register_object($scratch2$$reg); 2686 2687 assert(Roop != Rscratch, ""); 2688 assert(Roop != Rmark, ""); 2689 assert(Rbox != Rscratch, ""); 2690 assert(Rbox != Rmark, ""); 2691 2692 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining); 2693%} 2694 2695enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{ 2696 MacroAssembler _masm(&cbuf); 2697 2698 Register Roop = reg_to_register_object($oop$$reg); 2699 Register Rbox = reg_to_register_object($box$$reg); 2700 Register Rscratch = reg_to_register_object($scratch$$reg); 2701 Register Rmark = reg_to_register_object($scratch2$$reg); 2702 2703 assert(Roop != Rscratch, ""); 2704 assert(Roop != Rmark, ""); 2705 assert(Rbox != Rscratch, ""); 2706 assert(Rbox != Rmark, ""); 2707 2708 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining); 2709 %} 2710 2711 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{ 2712 MacroAssembler _masm(&cbuf); 2713 Register Rmem = reg_to_register_object($mem$$reg); 2714 Register Rold = reg_to_register_object($old$$reg); 2715 Register Rnew = reg_to_register_object($new$$reg); 2716 2717 // casx_under_lock picks 1 of 3 encodings: 2718 // For 32-bit pointers you get a 32-bit CAS 2719 // For 64-bit pointers you get a 64-bit CASX 2720 __ casn(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold 2721 __ cmp( Rold, Rnew ); 2722 %} 2723 2724 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{ 2725 Register Rmem = reg_to_register_object($mem$$reg); 2726 Register Rold = reg_to_register_object($old$$reg); 2727 Register Rnew = reg_to_register_object($new$$reg); 2728 2729 MacroAssembler _masm(&cbuf); 2730 __ mov(Rnew, O7); 2731 __ casx(Rmem, Rold, O7); 2732 __ cmp( Rold, O7 ); 2733 %} 2734 2735 // raw int cas, used for compareAndSwap 2736 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{ 2737 Register Rmem = reg_to_register_object($mem$$reg); 2738 Register Rold = reg_to_register_object($old$$reg); 2739 Register Rnew = reg_to_register_object($new$$reg); 2740 2741 MacroAssembler _masm(&cbuf); 2742 __ mov(Rnew, O7); 2743 __ cas(Rmem, Rold, O7); 2744 __ cmp( Rold, O7 ); 2745 %} 2746 2747 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{ 2748 Register Rres = reg_to_register_object($res$$reg); 2749 2750 MacroAssembler _masm(&cbuf); 2751 __ mov(1, Rres); 2752 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres ); 2753 %} 2754 2755 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{ 2756 Register Rres = reg_to_register_object($res$$reg); 2757 2758 MacroAssembler _masm(&cbuf); 2759 __ mov(1, Rres); 2760 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres ); 2761 %} 2762 2763 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{ 2764 MacroAssembler _masm(&cbuf); 2765 Register Rdst = reg_to_register_object($dst$$reg); 2766 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg) 2767 : reg_to_DoubleFloatRegister_object($src1$$reg); 2768 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg) 2769 : reg_to_DoubleFloatRegister_object($src2$$reg); 2770 2771 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1) 2772 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst); 2773 %} 2774 2775 enc_class LdImmL (immL src, iRegL dst, o7RegL tmp) %{ // Load Immediate 2776 MacroAssembler _masm(&cbuf); 2777 Register dest = reg_to_register_object($dst$$reg); 2778 Register temp = reg_to_register_object($tmp$$reg); 2779 __ set64( $src$$constant, dest, temp ); 2780 %} 2781 2782 enc_class LdReplImmI(immI src, regD dst, o7RegP tmp, int count, int width) %{ 2783 // Load a constant replicated "count" times with width "width" 2784 int bit_width = $width$$constant * 8; 2785 jlong elt_val = $src$$constant; 2786 elt_val &= (((jlong)1) << bit_width) - 1; // mask off sign bits 2787 jlong val = elt_val; 2788 for (int i = 0; i < $count$$constant - 1; i++) { 2789 val <<= bit_width; 2790 val |= elt_val; 2791 } 2792 jdouble dval = *(jdouble*)&val; // coerce to double type 2793 MacroAssembler _masm(&cbuf); 2794 address double_address = __ double_constant(dval); 2795 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 2796 AddressLiteral addrlit(double_address, rspec); 2797 2798 __ sethi(addrlit, $tmp$$Register); 2799 // XXX This is a quick fix for 6833573. 2800 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 2801 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 2802 %} 2803 2804 // Compiler ensures base is doubleword aligned and cnt is count of doublewords 2805 enc_class enc_Clear_Array(iRegX cnt, iRegP base, iRegX temp) %{ 2806 MacroAssembler _masm(&cbuf); 2807 Register nof_bytes_arg = reg_to_register_object($cnt$$reg); 2808 Register nof_bytes_tmp = reg_to_register_object($temp$$reg); 2809 Register base_pointer_arg = reg_to_register_object($base$$reg); 2810 2811 Label loop; 2812 __ mov(nof_bytes_arg, nof_bytes_tmp); 2813 2814 // Loop and clear, walking backwards through the array. 2815 // nof_bytes_tmp (if >0) is always the number of bytes to zero 2816 __ bind(loop); 2817 __ deccc(nof_bytes_tmp, 8); 2818 __ br(Assembler::greaterEqual, true, Assembler::pt, loop); 2819 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp); 2820 // %%%% this mini-loop must not cross a cache boundary! 2821 %} 2822 2823 2824 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{ 2825 Label Ldone, Lloop; 2826 MacroAssembler _masm(&cbuf); 2827 2828 Register str1_reg = reg_to_register_object($str1$$reg); 2829 Register str2_reg = reg_to_register_object($str2$$reg); 2830 Register cnt1_reg = reg_to_register_object($cnt1$$reg); 2831 Register cnt2_reg = reg_to_register_object($cnt2$$reg); 2832 Register result_reg = reg_to_register_object($result$$reg); 2833 2834 assert(result_reg != str1_reg && 2835 result_reg != str2_reg && 2836 result_reg != cnt1_reg && 2837 result_reg != cnt2_reg , 2838 "need different registers"); 2839 2840 // Compute the minimum of the string lengths(str1_reg) and the 2841 // difference of the string lengths (stack) 2842 2843 // See if the lengths are different, and calculate min in str1_reg. 2844 // Stash diff in O7 in case we need it for a tie-breaker. 2845 Label Lskip; 2846 __ subcc(cnt1_reg, cnt2_reg, O7); 2847 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2848 __ br(Assembler::greater, true, Assembler::pt, Lskip); 2849 // cnt2 is shorter, so use its count: 2850 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit 2851 __ bind(Lskip); 2852 2853 // reallocate cnt1_reg, cnt2_reg, result_reg 2854 // Note: limit_reg holds the string length pre-scaled by 2 2855 Register limit_reg = cnt1_reg; 2856 Register chr2_reg = cnt2_reg; 2857 Register chr1_reg = result_reg; 2858 // str{12} are the base pointers 2859 2860 // Is the minimum length zero? 2861 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity 2862 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2863 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2864 2865 // Load first characters 2866 __ lduh(str1_reg, 0, chr1_reg); 2867 __ lduh(str2_reg, 0, chr2_reg); 2868 2869 // Compare first characters 2870 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2871 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2872 assert(chr1_reg == result_reg, "result must be pre-placed"); 2873 __ delayed()->nop(); 2874 2875 { 2876 // Check after comparing first character to see if strings are equivalent 2877 Label LSkip2; 2878 // Check if the strings start at same location 2879 __ cmp(str1_reg, str2_reg); 2880 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2); 2881 __ delayed()->nop(); 2882 2883 // Check if the length difference is zero (in O7) 2884 __ cmp(G0, O7); 2885 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2886 __ delayed()->mov(G0, result_reg); // result is zero 2887 2888 // Strings might not be equal 2889 __ bind(LSkip2); 2890 } 2891 2892 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg); 2893 __ br(Assembler::equal, true, Assembler::pn, Ldone); 2894 __ delayed()->mov(O7, result_reg); // result is difference in lengths 2895 2896 // Shift str1_reg and str2_reg to the end of the arrays, negate limit 2897 __ add(str1_reg, limit_reg, str1_reg); 2898 __ add(str2_reg, limit_reg, str2_reg); 2899 __ neg(chr1_reg, limit_reg); // limit = -(limit-2) 2900 2901 // Compare the rest of the characters 2902 __ lduh(str1_reg, limit_reg, chr1_reg); 2903 __ bind(Lloop); 2904 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2905 __ lduh(str2_reg, limit_reg, chr2_reg); 2906 __ subcc(chr1_reg, chr2_reg, chr1_reg); 2907 __ br(Assembler::notZero, false, Assembler::pt, Ldone); 2908 assert(chr1_reg == result_reg, "result must be pre-placed"); 2909 __ delayed()->inccc(limit_reg, sizeof(jchar)); 2910 // annul LDUH if branch is not taken to prevent access past end of string 2911 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 2912 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2913 2914 // If strings are equal up to min length, return the length difference. 2915 __ mov(O7, result_reg); 2916 2917 // Otherwise, return the difference between the first mismatched chars. 2918 __ bind(Ldone); 2919 %} 2920 2921enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{ 2922 Label Lword_loop, Lpost_word, Lchar, Lchar_loop, Ldone; 2923 MacroAssembler _masm(&cbuf); 2924 2925 Register str1_reg = reg_to_register_object($str1$$reg); 2926 Register str2_reg = reg_to_register_object($str2$$reg); 2927 Register cnt_reg = reg_to_register_object($cnt$$reg); 2928 Register tmp1_reg = O7; 2929 Register result_reg = reg_to_register_object($result$$reg); 2930 2931 assert(result_reg != str1_reg && 2932 result_reg != str2_reg && 2933 result_reg != cnt_reg && 2934 result_reg != tmp1_reg , 2935 "need different registers"); 2936 2937 __ cmp(str1_reg, str2_reg); //same char[] ? 2938 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 2939 __ delayed()->add(G0, 1, result_reg); 2940 2941 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, cnt_reg, Ldone); 2942 __ delayed()->add(G0, 1, result_reg); // count == 0 2943 2944 //rename registers 2945 Register limit_reg = cnt_reg; 2946 Register chr1_reg = result_reg; 2947 Register chr2_reg = tmp1_reg; 2948 2949 //check for alignment and position the pointers to the ends 2950 __ or3(str1_reg, str2_reg, chr1_reg); 2951 __ andcc(chr1_reg, 0x3, chr1_reg); 2952 // notZero means at least one not 4-byte aligned. 2953 // We could optimize the case when both arrays are not aligned 2954 // but it is not frequent case and it requires additional checks. 2955 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare 2956 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count 2957 2958 // Compare char[] arrays aligned to 4 bytes. 2959 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg, 2960 chr1_reg, chr2_reg, Ldone); 2961 __ ba(false,Ldone); 2962 __ delayed()->add(G0, 1, result_reg); 2963 2964 // char by char compare 2965 __ bind(Lchar); 2966 __ add(str1_reg, limit_reg, str1_reg); 2967 __ add(str2_reg, limit_reg, str2_reg); 2968 __ neg(limit_reg); //negate count 2969 2970 __ lduh(str1_reg, limit_reg, chr1_reg); 2971 // Lchar_loop 2972 __ bind(Lchar_loop); 2973 __ lduh(str2_reg, limit_reg, chr2_reg); 2974 __ cmp(chr1_reg, chr2_reg); 2975 __ br(Assembler::notEqual, true, Assembler::pt, Ldone); 2976 __ delayed()->mov(G0, result_reg); //not equal 2977 __ inccc(limit_reg, sizeof(jchar)); 2978 // annul LDUH if branch is not taken to prevent access past end of string 2979 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop); 2980 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted 2981 2982 __ add(G0, 1, result_reg); //equal 2983 2984 __ bind(Ldone); 2985 %} 2986 2987enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{ 2988 Label Lvector, Ldone, Lloop; 2989 MacroAssembler _masm(&cbuf); 2990 2991 Register ary1_reg = reg_to_register_object($ary1$$reg); 2992 Register ary2_reg = reg_to_register_object($ary2$$reg); 2993 Register tmp1_reg = reg_to_register_object($tmp1$$reg); 2994 Register tmp2_reg = O7; 2995 Register result_reg = reg_to_register_object($result$$reg); 2996 2997 int length_offset = arrayOopDesc::length_offset_in_bytes(); 2998 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR); 2999 3000 // return true if the same array 3001 __ cmp(ary1_reg, ary2_reg); 3002 __ brx(Assembler::equal, true, Assembler::pn, Ldone); 3003 __ delayed()->add(G0, 1, result_reg); // equal 3004 3005 __ br_null(ary1_reg, true, Assembler::pn, Ldone); 3006 __ delayed()->mov(G0, result_reg); // not equal 3007 3008 __ br_null(ary2_reg, true, Assembler::pn, Ldone); 3009 __ delayed()->mov(G0, result_reg); // not equal 3010 3011 //load the lengths of arrays 3012 __ ld(Address(ary1_reg, length_offset), tmp1_reg); 3013 __ ld(Address(ary2_reg, length_offset), tmp2_reg); 3014 3015 // return false if the two arrays are not equal length 3016 __ cmp(tmp1_reg, tmp2_reg); 3017 __ br(Assembler::notEqual, true, Assembler::pn, Ldone); 3018 __ delayed()->mov(G0, result_reg); // not equal 3019 3020 __ br_on_reg_cond(Assembler::rc_z, true, Assembler::pn, tmp1_reg, Ldone); 3021 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal 3022 3023 // load array addresses 3024 __ add(ary1_reg, base_offset, ary1_reg); 3025 __ add(ary2_reg, base_offset, ary2_reg); 3026 3027 // renaming registers 3028 Register chr1_reg = result_reg; // for characters in ary1 3029 Register chr2_reg = tmp2_reg; // for characters in ary2 3030 Register limit_reg = tmp1_reg; // length 3031 3032 // set byte count 3033 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); 3034 3035 // Compare char[] arrays aligned to 4 bytes. 3036 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg, 3037 chr1_reg, chr2_reg, Ldone); 3038 __ add(G0, 1, result_reg); // equals 3039 3040 __ bind(Ldone); 3041 %} 3042 3043 enc_class enc_rethrow() %{ 3044 cbuf.set_insts_mark(); 3045 Register temp_reg = G3; 3046 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub()); 3047 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg"); 3048 MacroAssembler _masm(&cbuf); 3049#ifdef ASSERT 3050 __ save_frame(0); 3051 AddressLiteral last_rethrow_addrlit(&last_rethrow); 3052 __ sethi(last_rethrow_addrlit, L1); 3053 Address addr(L1, last_rethrow_addrlit.low10()); 3054 __ get_pc(L2); 3055 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to 3056 __ st_ptr(L2, addr); 3057 __ restore(); 3058#endif 3059 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp 3060 __ delayed()->nop(); 3061 %} 3062 3063 enc_class emit_mem_nop() %{ 3064 // Generates the instruction LDUXA [o6,g0],#0x82,g0 3065 cbuf.insts()->emit_int32((unsigned int) 0xc0839040); 3066 %} 3067 3068 enc_class emit_fadd_nop() %{ 3069 // Generates the instruction FMOVS f31,f31 3070 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f); 3071 %} 3072 3073 enc_class emit_br_nop() %{ 3074 // Generates the instruction BPN,PN . 3075 cbuf.insts()->emit_int32((unsigned int) 0x00400000); 3076 %} 3077 3078 enc_class enc_membar_acquire %{ 3079 MacroAssembler _masm(&cbuf); 3080 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) ); 3081 %} 3082 3083 enc_class enc_membar_release %{ 3084 MacroAssembler _masm(&cbuf); 3085 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) ); 3086 %} 3087 3088 enc_class enc_membar_volatile %{ 3089 MacroAssembler _masm(&cbuf); 3090 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3091 %} 3092 3093 enc_class enc_repl8b( iRegI src, iRegL dst ) %{ 3094 MacroAssembler _masm(&cbuf); 3095 Register src_reg = reg_to_register_object($src$$reg); 3096 Register dst_reg = reg_to_register_object($dst$$reg); 3097 __ sllx(src_reg, 56, dst_reg); 3098 __ srlx(dst_reg, 8, O7); 3099 __ or3 (dst_reg, O7, dst_reg); 3100 __ srlx(dst_reg, 16, O7); 3101 __ or3 (dst_reg, O7, dst_reg); 3102 __ srlx(dst_reg, 32, O7); 3103 __ or3 (dst_reg, O7, dst_reg); 3104 %} 3105 3106 enc_class enc_repl4b( iRegI src, iRegL dst ) %{ 3107 MacroAssembler _masm(&cbuf); 3108 Register src_reg = reg_to_register_object($src$$reg); 3109 Register dst_reg = reg_to_register_object($dst$$reg); 3110 __ sll(src_reg, 24, dst_reg); 3111 __ srl(dst_reg, 8, O7); 3112 __ or3(dst_reg, O7, dst_reg); 3113 __ srl(dst_reg, 16, O7); 3114 __ or3(dst_reg, O7, dst_reg); 3115 %} 3116 3117 enc_class enc_repl4s( iRegI src, iRegL dst ) %{ 3118 MacroAssembler _masm(&cbuf); 3119 Register src_reg = reg_to_register_object($src$$reg); 3120 Register dst_reg = reg_to_register_object($dst$$reg); 3121 __ sllx(src_reg, 48, dst_reg); 3122 __ srlx(dst_reg, 16, O7); 3123 __ or3 (dst_reg, O7, dst_reg); 3124 __ srlx(dst_reg, 32, O7); 3125 __ or3 (dst_reg, O7, dst_reg); 3126 %} 3127 3128 enc_class enc_repl2i( iRegI src, iRegL dst ) %{ 3129 MacroAssembler _masm(&cbuf); 3130 Register src_reg = reg_to_register_object($src$$reg); 3131 Register dst_reg = reg_to_register_object($dst$$reg); 3132 __ sllx(src_reg, 32, dst_reg); 3133 __ srlx(dst_reg, 32, O7); 3134 __ or3 (dst_reg, O7, dst_reg); 3135 %} 3136 3137%} 3138 3139//----------FRAME-------------------------------------------------------------- 3140// Definition of frame structure and management information. 3141// 3142// S T A C K L A Y O U T Allocators stack-slot number 3143// | (to get allocators register number 3144// G Owned by | | v add VMRegImpl::stack0) 3145// r CALLER | | 3146// o | +--------+ pad to even-align allocators stack-slot 3147// w V | pad0 | numbers; owned by CALLER 3148// t -----------+--------+----> Matcher::_in_arg_limit, unaligned 3149// h ^ | in | 5 3150// | | args | 4 Holes in incoming args owned by SELF 3151// | | | | 3 3152// | | +--------+ 3153// V | | old out| Empty on Intel, window on Sparc 3154// | old |preserve| Must be even aligned. 3155// | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned 3156// | | in | 3 area for Intel ret address 3157// Owned by |preserve| Empty on Sparc. 3158// SELF +--------+ 3159// | | pad2 | 2 pad to align old SP 3160// | +--------+ 1 3161// | | locks | 0 3162// | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned 3163// | | pad1 | 11 pad to align new SP 3164// | +--------+ 3165// | | | 10 3166// | | spills | 9 spills 3167// V | | 8 (pad0 slot for callee) 3168// -----------+--------+----> Matcher::_out_arg_limit, unaligned 3169// ^ | out | 7 3170// | | args | 6 Holes in outgoing args owned by CALLEE 3171// Owned by +--------+ 3172// CALLEE | new out| 6 Empty on Intel, window on Sparc 3173// | new |preserve| Must be even-aligned. 3174// | SP-+--------+----> Matcher::_new_SP, even aligned 3175// | | | 3176// 3177// Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is 3178// known from SELF's arguments and the Java calling convention. 3179// Region 6-7 is determined per call site. 3180// Note 2: If the calling convention leaves holes in the incoming argument 3181// area, those holes are owned by SELF. Holes in the outgoing area 3182// are owned by the CALLEE. Holes should not be nessecary in the 3183// incoming area, as the Java calling convention is completely under 3184// the control of the AD file. Doubles can be sorted and packed to 3185// avoid holes. Holes in the outgoing arguments may be nessecary for 3186// varargs C calling conventions. 3187// Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is 3188// even aligned with pad0 as needed. 3189// Region 6 is even aligned. Region 6-7 is NOT even aligned; 3190// region 6-11 is even aligned; it may be padded out more so that 3191// the region from SP to FP meets the minimum stack alignment. 3192 3193frame %{ 3194 // What direction does stack grow in (assumed to be same for native & Java) 3195 stack_direction(TOWARDS_LOW); 3196 3197 // These two registers define part of the calling convention 3198 // between compiled code and the interpreter. 3199 inline_cache_reg(R_G5); // Inline Cache Register or methodOop for I2C 3200 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter 3201 3202 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset] 3203 cisc_spilling_operand_name(indOffset); 3204 3205 // Number of stack slots consumed by a Monitor enter 3206#ifdef _LP64 3207 sync_stack_slots(2); 3208#else 3209 sync_stack_slots(1); 3210#endif 3211 3212 // Compiled code's Frame Pointer 3213 frame_pointer(R_SP); 3214 3215 // Stack alignment requirement 3216 stack_alignment(StackAlignmentInBytes); 3217 // LP64: Alignment size in bytes (128-bit -> 16 bytes) 3218 // !LP64: Alignment size in bytes (64-bit -> 8 bytes) 3219 3220 // Number of stack slots between incoming argument block and the start of 3221 // a new frame. The PROLOG must add this many slots to the stack. The 3222 // EPILOG must remove this many slots. 3223 in_preserve_stack_slots(0); 3224 3225 // Number of outgoing stack slots killed above the out_preserve_stack_slots 3226 // for calls to C. Supports the var-args backing area for register parms. 3227 // ADLC doesn't support parsing expressions, so I folded the math by hand. 3228#ifdef _LP64 3229 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word 3230 varargs_C_out_slots_killed(12); 3231#else 3232 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word 3233 varargs_C_out_slots_killed( 7); 3234#endif 3235 3236 // The after-PROLOG location of the return address. Location of 3237 // return address specifies a type (REG or STACK) and a number 3238 // representing the register number (i.e. - use a register name) or 3239 // stack slot. 3240 return_addr(REG R_I7); // Ret Addr is in register I7 3241 3242 // Body of function which returns an OptoRegs array locating 3243 // arguments either in registers or in stack slots for calling 3244 // java 3245 calling_convention %{ 3246 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing); 3247 3248 %} 3249 3250 // Body of function which returns an OptoRegs array locating 3251 // arguments either in registers or in stack slots for callin 3252 // C. 3253 c_calling_convention %{ 3254 // This is obviously always outgoing 3255 (void) SharedRuntime::c_calling_convention(sig_bt, regs, length); 3256 %} 3257 3258 // Location of native (C/C++) and interpreter return values. This is specified to 3259 // be the same as Java. In the 32-bit VM, long values are actually returned from 3260 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying 3261 // to and from the register pairs is done by the appropriate call and epilog 3262 // opcodes. This simplifies the register allocator. 3263 c_return_value %{ 3264 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3265#ifdef _LP64 3266 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3267 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3268 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3269 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3270#else // !_LP64 3271 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3272 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3273 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3274 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num }; 3275#endif 3276 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3277 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3278 %} 3279 3280 // Location of compiled Java return values. Same as C 3281 return_value %{ 3282 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" ); 3283#ifdef _LP64 3284 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num }; 3285 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num}; 3286 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num }; 3287 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num}; 3288#else // !_LP64 3289 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num }; 3290 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3291 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num }; 3292 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num}; 3293#endif 3294 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg], 3295 (is_outgoing?lo_out:lo_in)[ideal_reg] ); 3296 %} 3297 3298%} 3299 3300 3301//----------ATTRIBUTES--------------------------------------------------------- 3302//----------Operand Attributes------------------------------------------------- 3303op_attrib op_cost(1); // Required cost attribute 3304 3305//----------Instruction Attributes--------------------------------------------- 3306ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute 3307ins_attrib ins_size(32); // Required size attribute (in bits) 3308ins_attrib ins_pc_relative(0); // Required PC Relative flag 3309ins_attrib ins_short_branch(0); // Required flag: is this instruction a 3310 // non-matching short branch variant of some 3311 // long branch? 3312 3313//----------OPERANDS----------------------------------------------------------- 3314// Operand definitions must precede instruction definitions for correct parsing 3315// in the ADLC because operands constitute user defined types which are used in 3316// instruction definitions. 3317 3318//----------Simple Operands---------------------------------------------------- 3319// Immediate Operands 3320// Integer Immediate: 32-bit 3321operand immI() %{ 3322 match(ConI); 3323 3324 op_cost(0); 3325 // formats are generated automatically for constants and base registers 3326 format %{ %} 3327 interface(CONST_INTER); 3328%} 3329 3330// Integer Immediate: 8-bit 3331operand immI8() %{ 3332 predicate(Assembler::is_simm(n->get_int(), 8)); 3333 match(ConI); 3334 op_cost(0); 3335 format %{ %} 3336 interface(CONST_INTER); 3337%} 3338 3339// Integer Immediate: 13-bit 3340operand immI13() %{ 3341 predicate(Assembler::is_simm13(n->get_int())); 3342 match(ConI); 3343 op_cost(0); 3344 3345 format %{ %} 3346 interface(CONST_INTER); 3347%} 3348 3349// Integer Immediate: 13-bit minus 7 3350operand immI13m7() %{ 3351 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095)); 3352 match(ConI); 3353 op_cost(0); 3354 3355 format %{ %} 3356 interface(CONST_INTER); 3357%} 3358 3359// Integer Immediate: 16-bit 3360operand immI16() %{ 3361 predicate(Assembler::is_simm(n->get_int(), 16)); 3362 match(ConI); 3363 op_cost(0); 3364 format %{ %} 3365 interface(CONST_INTER); 3366%} 3367 3368// Unsigned (positive) Integer Immediate: 13-bit 3369operand immU13() %{ 3370 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int())); 3371 match(ConI); 3372 op_cost(0); 3373 3374 format %{ %} 3375 interface(CONST_INTER); 3376%} 3377 3378// Integer Immediate: 6-bit 3379operand immU6() %{ 3380 predicate(n->get_int() >= 0 && n->get_int() <= 63); 3381 match(ConI); 3382 op_cost(0); 3383 format %{ %} 3384 interface(CONST_INTER); 3385%} 3386 3387// Integer Immediate: 11-bit 3388operand immI11() %{ 3389 predicate(Assembler::is_simm(n->get_int(),11)); 3390 match(ConI); 3391 op_cost(0); 3392 format %{ %} 3393 interface(CONST_INTER); 3394%} 3395 3396// Integer Immediate: 0-bit 3397operand immI0() %{ 3398 predicate(n->get_int() == 0); 3399 match(ConI); 3400 op_cost(0); 3401 3402 format %{ %} 3403 interface(CONST_INTER); 3404%} 3405 3406// Integer Immediate: the value 10 3407operand immI10() %{ 3408 predicate(n->get_int() == 10); 3409 match(ConI); 3410 op_cost(0); 3411 3412 format %{ %} 3413 interface(CONST_INTER); 3414%} 3415 3416// Integer Immediate: the values 0-31 3417operand immU5() %{ 3418 predicate(n->get_int() >= 0 && n->get_int() <= 31); 3419 match(ConI); 3420 op_cost(0); 3421 3422 format %{ %} 3423 interface(CONST_INTER); 3424%} 3425 3426// Integer Immediate: the values 1-31 3427operand immI_1_31() %{ 3428 predicate(n->get_int() >= 1 && n->get_int() <= 31); 3429 match(ConI); 3430 op_cost(0); 3431 3432 format %{ %} 3433 interface(CONST_INTER); 3434%} 3435 3436// Integer Immediate: the values 32-63 3437operand immI_32_63() %{ 3438 predicate(n->get_int() >= 32 && n->get_int() <= 63); 3439 match(ConI); 3440 op_cost(0); 3441 3442 format %{ %} 3443 interface(CONST_INTER); 3444%} 3445 3446// Immediates for special shifts (sign extend) 3447 3448// Integer Immediate: the value 16 3449operand immI_16() %{ 3450 predicate(n->get_int() == 16); 3451 match(ConI); 3452 op_cost(0); 3453 3454 format %{ %} 3455 interface(CONST_INTER); 3456%} 3457 3458// Integer Immediate: the value 24 3459operand immI_24() %{ 3460 predicate(n->get_int() == 24); 3461 match(ConI); 3462 op_cost(0); 3463 3464 format %{ %} 3465 interface(CONST_INTER); 3466%} 3467 3468// Integer Immediate: the value 255 3469operand immI_255() %{ 3470 predicate( n->get_int() == 255 ); 3471 match(ConI); 3472 op_cost(0); 3473 3474 format %{ %} 3475 interface(CONST_INTER); 3476%} 3477 3478// Integer Immediate: the value 65535 3479operand immI_65535() %{ 3480 predicate(n->get_int() == 65535); 3481 match(ConI); 3482 op_cost(0); 3483 3484 format %{ %} 3485 interface(CONST_INTER); 3486%} 3487 3488// Long Immediate: the value FF 3489operand immL_FF() %{ 3490 predicate( n->get_long() == 0xFFL ); 3491 match(ConL); 3492 op_cost(0); 3493 3494 format %{ %} 3495 interface(CONST_INTER); 3496%} 3497 3498// Long Immediate: the value FFFF 3499operand immL_FFFF() %{ 3500 predicate( n->get_long() == 0xFFFFL ); 3501 match(ConL); 3502 op_cost(0); 3503 3504 format %{ %} 3505 interface(CONST_INTER); 3506%} 3507 3508// Pointer Immediate: 32 or 64-bit 3509operand immP() %{ 3510 match(ConP); 3511 3512 op_cost(5); 3513 // formats are generated automatically for constants and base registers 3514 format %{ %} 3515 interface(CONST_INTER); 3516%} 3517 3518operand immP13() %{ 3519 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095)); 3520 match(ConP); 3521 op_cost(0); 3522 3523 format %{ %} 3524 interface(CONST_INTER); 3525%} 3526 3527operand immP0() %{ 3528 predicate(n->get_ptr() == 0); 3529 match(ConP); 3530 op_cost(0); 3531 3532 format %{ %} 3533 interface(CONST_INTER); 3534%} 3535 3536operand immP_poll() %{ 3537 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page()); 3538 match(ConP); 3539 3540 // formats are generated automatically for constants and base registers 3541 format %{ %} 3542 interface(CONST_INTER); 3543%} 3544 3545// Pointer Immediate 3546operand immN() 3547%{ 3548 match(ConN); 3549 3550 op_cost(10); 3551 format %{ %} 3552 interface(CONST_INTER); 3553%} 3554 3555// NULL Pointer Immediate 3556operand immN0() 3557%{ 3558 predicate(n->get_narrowcon() == 0); 3559 match(ConN); 3560 3561 op_cost(0); 3562 format %{ %} 3563 interface(CONST_INTER); 3564%} 3565 3566operand immL() %{ 3567 match(ConL); 3568 op_cost(40); 3569 // formats are generated automatically for constants and base registers 3570 format %{ %} 3571 interface(CONST_INTER); 3572%} 3573 3574operand immL0() %{ 3575 predicate(n->get_long() == 0L); 3576 match(ConL); 3577 op_cost(0); 3578 // formats are generated automatically for constants and base registers 3579 format %{ %} 3580 interface(CONST_INTER); 3581%} 3582 3583// Long Immediate: 13-bit 3584operand immL13() %{ 3585 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L)); 3586 match(ConL); 3587 op_cost(0); 3588 3589 format %{ %} 3590 interface(CONST_INTER); 3591%} 3592 3593// Long Immediate: 13-bit minus 7 3594operand immL13m7() %{ 3595 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L)); 3596 match(ConL); 3597 op_cost(0); 3598 3599 format %{ %} 3600 interface(CONST_INTER); 3601%} 3602 3603// Long Immediate: low 32-bit mask 3604operand immL_32bits() %{ 3605 predicate(n->get_long() == 0xFFFFFFFFL); 3606 match(ConL); 3607 op_cost(0); 3608 3609 format %{ %} 3610 interface(CONST_INTER); 3611%} 3612 3613// Double Immediate 3614operand immD() %{ 3615 match(ConD); 3616 3617 op_cost(40); 3618 format %{ %} 3619 interface(CONST_INTER); 3620%} 3621 3622operand immD0() %{ 3623#ifdef _LP64 3624 // on 64-bit architectures this comparision is faster 3625 predicate(jlong_cast(n->getd()) == 0); 3626#else 3627 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO)); 3628#endif 3629 match(ConD); 3630 3631 op_cost(0); 3632 format %{ %} 3633 interface(CONST_INTER); 3634%} 3635 3636// Float Immediate 3637operand immF() %{ 3638 match(ConF); 3639 3640 op_cost(20); 3641 format %{ %} 3642 interface(CONST_INTER); 3643%} 3644 3645// Float Immediate: 0 3646operand immF0() %{ 3647 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO)); 3648 match(ConF); 3649 3650 op_cost(0); 3651 format %{ %} 3652 interface(CONST_INTER); 3653%} 3654 3655// Integer Register Operands 3656// Integer Register 3657operand iRegI() %{ 3658 constraint(ALLOC_IN_RC(int_reg)); 3659 match(RegI); 3660 3661 match(notemp_iRegI); 3662 match(g1RegI); 3663 match(o0RegI); 3664 match(iRegIsafe); 3665 3666 format %{ %} 3667 interface(REG_INTER); 3668%} 3669 3670operand notemp_iRegI() %{ 3671 constraint(ALLOC_IN_RC(notemp_int_reg)); 3672 match(RegI); 3673 3674 match(o0RegI); 3675 3676 format %{ %} 3677 interface(REG_INTER); 3678%} 3679 3680operand o0RegI() %{ 3681 constraint(ALLOC_IN_RC(o0_regI)); 3682 match(iRegI); 3683 3684 format %{ %} 3685 interface(REG_INTER); 3686%} 3687 3688// Pointer Register 3689operand iRegP() %{ 3690 constraint(ALLOC_IN_RC(ptr_reg)); 3691 match(RegP); 3692 3693 match(lock_ptr_RegP); 3694 match(g1RegP); 3695 match(g2RegP); 3696 match(g3RegP); 3697 match(g4RegP); 3698 match(i0RegP); 3699 match(o0RegP); 3700 match(o1RegP); 3701 match(l7RegP); 3702 3703 format %{ %} 3704 interface(REG_INTER); 3705%} 3706 3707operand sp_ptr_RegP() %{ 3708 constraint(ALLOC_IN_RC(sp_ptr_reg)); 3709 match(RegP); 3710 match(iRegP); 3711 3712 format %{ %} 3713 interface(REG_INTER); 3714%} 3715 3716operand lock_ptr_RegP() %{ 3717 constraint(ALLOC_IN_RC(lock_ptr_reg)); 3718 match(RegP); 3719 match(i0RegP); 3720 match(o0RegP); 3721 match(o1RegP); 3722 match(l7RegP); 3723 3724 format %{ %} 3725 interface(REG_INTER); 3726%} 3727 3728operand g1RegP() %{ 3729 constraint(ALLOC_IN_RC(g1_regP)); 3730 match(iRegP); 3731 3732 format %{ %} 3733 interface(REG_INTER); 3734%} 3735 3736operand g2RegP() %{ 3737 constraint(ALLOC_IN_RC(g2_regP)); 3738 match(iRegP); 3739 3740 format %{ %} 3741 interface(REG_INTER); 3742%} 3743 3744operand g3RegP() %{ 3745 constraint(ALLOC_IN_RC(g3_regP)); 3746 match(iRegP); 3747 3748 format %{ %} 3749 interface(REG_INTER); 3750%} 3751 3752operand g1RegI() %{ 3753 constraint(ALLOC_IN_RC(g1_regI)); 3754 match(iRegI); 3755 3756 format %{ %} 3757 interface(REG_INTER); 3758%} 3759 3760operand g3RegI() %{ 3761 constraint(ALLOC_IN_RC(g3_regI)); 3762 match(iRegI); 3763 3764 format %{ %} 3765 interface(REG_INTER); 3766%} 3767 3768operand g4RegI() %{ 3769 constraint(ALLOC_IN_RC(g4_regI)); 3770 match(iRegI); 3771 3772 format %{ %} 3773 interface(REG_INTER); 3774%} 3775 3776operand g4RegP() %{ 3777 constraint(ALLOC_IN_RC(g4_regP)); 3778 match(iRegP); 3779 3780 format %{ %} 3781 interface(REG_INTER); 3782%} 3783 3784operand i0RegP() %{ 3785 constraint(ALLOC_IN_RC(i0_regP)); 3786 match(iRegP); 3787 3788 format %{ %} 3789 interface(REG_INTER); 3790%} 3791 3792operand o0RegP() %{ 3793 constraint(ALLOC_IN_RC(o0_regP)); 3794 match(iRegP); 3795 3796 format %{ %} 3797 interface(REG_INTER); 3798%} 3799 3800operand o1RegP() %{ 3801 constraint(ALLOC_IN_RC(o1_regP)); 3802 match(iRegP); 3803 3804 format %{ %} 3805 interface(REG_INTER); 3806%} 3807 3808operand o2RegP() %{ 3809 constraint(ALLOC_IN_RC(o2_regP)); 3810 match(iRegP); 3811 3812 format %{ %} 3813 interface(REG_INTER); 3814%} 3815 3816operand o7RegP() %{ 3817 constraint(ALLOC_IN_RC(o7_regP)); 3818 match(iRegP); 3819 3820 format %{ %} 3821 interface(REG_INTER); 3822%} 3823 3824operand l7RegP() %{ 3825 constraint(ALLOC_IN_RC(l7_regP)); 3826 match(iRegP); 3827 3828 format %{ %} 3829 interface(REG_INTER); 3830%} 3831 3832operand o7RegI() %{ 3833 constraint(ALLOC_IN_RC(o7_regI)); 3834 match(iRegI); 3835 3836 format %{ %} 3837 interface(REG_INTER); 3838%} 3839 3840operand iRegN() %{ 3841 constraint(ALLOC_IN_RC(int_reg)); 3842 match(RegN); 3843 3844 format %{ %} 3845 interface(REG_INTER); 3846%} 3847 3848// Long Register 3849operand iRegL() %{ 3850 constraint(ALLOC_IN_RC(long_reg)); 3851 match(RegL); 3852 3853 format %{ %} 3854 interface(REG_INTER); 3855%} 3856 3857operand o2RegL() %{ 3858 constraint(ALLOC_IN_RC(o2_regL)); 3859 match(iRegL); 3860 3861 format %{ %} 3862 interface(REG_INTER); 3863%} 3864 3865operand o7RegL() %{ 3866 constraint(ALLOC_IN_RC(o7_regL)); 3867 match(iRegL); 3868 3869 format %{ %} 3870 interface(REG_INTER); 3871%} 3872 3873operand g1RegL() %{ 3874 constraint(ALLOC_IN_RC(g1_regL)); 3875 match(iRegL); 3876 3877 format %{ %} 3878 interface(REG_INTER); 3879%} 3880 3881operand g3RegL() %{ 3882 constraint(ALLOC_IN_RC(g3_regL)); 3883 match(iRegL); 3884 3885 format %{ %} 3886 interface(REG_INTER); 3887%} 3888 3889// Int Register safe 3890// This is 64bit safe 3891operand iRegIsafe() %{ 3892 constraint(ALLOC_IN_RC(long_reg)); 3893 3894 match(iRegI); 3895 3896 format %{ %} 3897 interface(REG_INTER); 3898%} 3899 3900// Condition Code Flag Register 3901operand flagsReg() %{ 3902 constraint(ALLOC_IN_RC(int_flags)); 3903 match(RegFlags); 3904 3905 format %{ "ccr" %} // both ICC and XCC 3906 interface(REG_INTER); 3907%} 3908 3909// Condition Code Register, unsigned comparisons. 3910operand flagsRegU() %{ 3911 constraint(ALLOC_IN_RC(int_flags)); 3912 match(RegFlags); 3913 3914 format %{ "icc_U" %} 3915 interface(REG_INTER); 3916%} 3917 3918// Condition Code Register, pointer comparisons. 3919operand flagsRegP() %{ 3920 constraint(ALLOC_IN_RC(int_flags)); 3921 match(RegFlags); 3922 3923#ifdef _LP64 3924 format %{ "xcc_P" %} 3925#else 3926 format %{ "icc_P" %} 3927#endif 3928 interface(REG_INTER); 3929%} 3930 3931// Condition Code Register, long comparisons. 3932operand flagsRegL() %{ 3933 constraint(ALLOC_IN_RC(int_flags)); 3934 match(RegFlags); 3935 3936 format %{ "xcc_L" %} 3937 interface(REG_INTER); 3938%} 3939 3940// Condition Code Register, floating comparisons, unordered same as "less". 3941operand flagsRegF() %{ 3942 constraint(ALLOC_IN_RC(float_flags)); 3943 match(RegFlags); 3944 match(flagsRegF0); 3945 3946 format %{ %} 3947 interface(REG_INTER); 3948%} 3949 3950operand flagsRegF0() %{ 3951 constraint(ALLOC_IN_RC(float_flag0)); 3952 match(RegFlags); 3953 3954 format %{ %} 3955 interface(REG_INTER); 3956%} 3957 3958 3959// Condition Code Flag Register used by long compare 3960operand flagsReg_long_LTGE() %{ 3961 constraint(ALLOC_IN_RC(int_flags)); 3962 match(RegFlags); 3963 format %{ "icc_LTGE" %} 3964 interface(REG_INTER); 3965%} 3966operand flagsReg_long_EQNE() %{ 3967 constraint(ALLOC_IN_RC(int_flags)); 3968 match(RegFlags); 3969 format %{ "icc_EQNE" %} 3970 interface(REG_INTER); 3971%} 3972operand flagsReg_long_LEGT() %{ 3973 constraint(ALLOC_IN_RC(int_flags)); 3974 match(RegFlags); 3975 format %{ "icc_LEGT" %} 3976 interface(REG_INTER); 3977%} 3978 3979 3980operand regD() %{ 3981 constraint(ALLOC_IN_RC(dflt_reg)); 3982 match(RegD); 3983 3984 match(regD_low); 3985 3986 format %{ %} 3987 interface(REG_INTER); 3988%} 3989 3990operand regF() %{ 3991 constraint(ALLOC_IN_RC(sflt_reg)); 3992 match(RegF); 3993 3994 format %{ %} 3995 interface(REG_INTER); 3996%} 3997 3998operand regD_low() %{ 3999 constraint(ALLOC_IN_RC(dflt_low_reg)); 4000 match(regD); 4001 4002 format %{ %} 4003 interface(REG_INTER); 4004%} 4005 4006// Special Registers 4007 4008// Method Register 4009operand inline_cache_regP(iRegP reg) %{ 4010 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1 4011 match(reg); 4012 format %{ %} 4013 interface(REG_INTER); 4014%} 4015 4016operand interpreter_method_oop_regP(iRegP reg) %{ 4017 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1 4018 match(reg); 4019 format %{ %} 4020 interface(REG_INTER); 4021%} 4022 4023 4024//----------Complex Operands--------------------------------------------------- 4025// Indirect Memory Reference 4026operand indirect(sp_ptr_RegP reg) %{ 4027 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4028 match(reg); 4029 4030 op_cost(100); 4031 format %{ "[$reg]" %} 4032 interface(MEMORY_INTER) %{ 4033 base($reg); 4034 index(0x0); 4035 scale(0x0); 4036 disp(0x0); 4037 %} 4038%} 4039 4040// Indirect with simm13 Offset 4041operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{ 4042 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4043 match(AddP reg offset); 4044 4045 op_cost(100); 4046 format %{ "[$reg + $offset]" %} 4047 interface(MEMORY_INTER) %{ 4048 base($reg); 4049 index(0x0); 4050 scale(0x0); 4051 disp($offset); 4052 %} 4053%} 4054 4055// Indirect with simm13 Offset minus 7 4056operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{ 4057 constraint(ALLOC_IN_RC(sp_ptr_reg)); 4058 match(AddP reg offset); 4059 4060 op_cost(100); 4061 format %{ "[$reg + $offset]" %} 4062 interface(MEMORY_INTER) %{ 4063 base($reg); 4064 index(0x0); 4065 scale(0x0); 4066 disp($offset); 4067 %} 4068%} 4069 4070// Note: Intel has a swapped version also, like this: 4071//operand indOffsetX(iRegI reg, immP offset) %{ 4072// constraint(ALLOC_IN_RC(int_reg)); 4073// match(AddP offset reg); 4074// 4075// op_cost(100); 4076// format %{ "[$reg + $offset]" %} 4077// interface(MEMORY_INTER) %{ 4078// base($reg); 4079// index(0x0); 4080// scale(0x0); 4081// disp($offset); 4082// %} 4083//%} 4084//// However, it doesn't make sense for SPARC, since 4085// we have no particularly good way to embed oops in 4086// single instructions. 4087 4088// Indirect with Register Index 4089operand indIndex(iRegP addr, iRegX index) %{ 4090 constraint(ALLOC_IN_RC(ptr_reg)); 4091 match(AddP addr index); 4092 4093 op_cost(100); 4094 format %{ "[$addr + $index]" %} 4095 interface(MEMORY_INTER) %{ 4096 base($addr); 4097 index($index); 4098 scale(0x0); 4099 disp(0x0); 4100 %} 4101%} 4102 4103//----------Special Memory Operands-------------------------------------------- 4104// Stack Slot Operand - This operand is used for loading and storing temporary 4105// values on the stack where a match requires a value to 4106// flow through memory. 4107operand stackSlotI(sRegI reg) %{ 4108 constraint(ALLOC_IN_RC(stack_slots)); 4109 op_cost(100); 4110 //match(RegI); 4111 format %{ "[$reg]" %} 4112 interface(MEMORY_INTER) %{ 4113 base(0xE); // R_SP 4114 index(0x0); 4115 scale(0x0); 4116 disp($reg); // Stack Offset 4117 %} 4118%} 4119 4120operand stackSlotP(sRegP reg) %{ 4121 constraint(ALLOC_IN_RC(stack_slots)); 4122 op_cost(100); 4123 //match(RegP); 4124 format %{ "[$reg]" %} 4125 interface(MEMORY_INTER) %{ 4126 base(0xE); // R_SP 4127 index(0x0); 4128 scale(0x0); 4129 disp($reg); // Stack Offset 4130 %} 4131%} 4132 4133operand stackSlotF(sRegF reg) %{ 4134 constraint(ALLOC_IN_RC(stack_slots)); 4135 op_cost(100); 4136 //match(RegF); 4137 format %{ "[$reg]" %} 4138 interface(MEMORY_INTER) %{ 4139 base(0xE); // R_SP 4140 index(0x0); 4141 scale(0x0); 4142 disp($reg); // Stack Offset 4143 %} 4144%} 4145operand stackSlotD(sRegD reg) %{ 4146 constraint(ALLOC_IN_RC(stack_slots)); 4147 op_cost(100); 4148 //match(RegD); 4149 format %{ "[$reg]" %} 4150 interface(MEMORY_INTER) %{ 4151 base(0xE); // R_SP 4152 index(0x0); 4153 scale(0x0); 4154 disp($reg); // Stack Offset 4155 %} 4156%} 4157operand stackSlotL(sRegL reg) %{ 4158 constraint(ALLOC_IN_RC(stack_slots)); 4159 op_cost(100); 4160 //match(RegL); 4161 format %{ "[$reg]" %} 4162 interface(MEMORY_INTER) %{ 4163 base(0xE); // R_SP 4164 index(0x0); 4165 scale(0x0); 4166 disp($reg); // Stack Offset 4167 %} 4168%} 4169 4170// Operands for expressing Control Flow 4171// NOTE: Label is a predefined operand which should not be redefined in 4172// the AD file. It is generically handled within the ADLC. 4173 4174//----------Conditional Branch Operands---------------------------------------- 4175// Comparison Op - This is the operation of the comparison, and is limited to 4176// the following set of codes: 4177// L (<), LE (<=), G (>), GE (>=), E (==), NE (!=) 4178// 4179// Other attributes of the comparison, such as unsignedness, are specified 4180// by the comparison instruction that sets a condition code flags register. 4181// That result is represented by a flags operand whose subtype is appropriate 4182// to the unsignedness (etc.) of the comparison. 4183// 4184// Later, the instruction which matches both the Comparison Op (a Bool) and 4185// the flags (produced by the Cmp) specifies the coding of the comparison op 4186// by matching a specific subtype of Bool operand below, such as cmpOpU. 4187 4188operand cmpOp() %{ 4189 match(Bool); 4190 4191 format %{ "" %} 4192 interface(COND_INTER) %{ 4193 equal(0x1); 4194 not_equal(0x9); 4195 less(0x3); 4196 greater_equal(0xB); 4197 less_equal(0x2); 4198 greater(0xA); 4199 %} 4200%} 4201 4202// Comparison Op, unsigned 4203operand cmpOpU() %{ 4204 match(Bool); 4205 4206 format %{ "u" %} 4207 interface(COND_INTER) %{ 4208 equal(0x1); 4209 not_equal(0x9); 4210 less(0x5); 4211 greater_equal(0xD); 4212 less_equal(0x4); 4213 greater(0xC); 4214 %} 4215%} 4216 4217// Comparison Op, pointer (same as unsigned) 4218operand cmpOpP() %{ 4219 match(Bool); 4220 4221 format %{ "p" %} 4222 interface(COND_INTER) %{ 4223 equal(0x1); 4224 not_equal(0x9); 4225 less(0x5); 4226 greater_equal(0xD); 4227 less_equal(0x4); 4228 greater(0xC); 4229 %} 4230%} 4231 4232// Comparison Op, branch-register encoding 4233operand cmpOp_reg() %{ 4234 match(Bool); 4235 4236 format %{ "" %} 4237 interface(COND_INTER) %{ 4238 equal (0x1); 4239 not_equal (0x5); 4240 less (0x3); 4241 greater_equal(0x7); 4242 less_equal (0x2); 4243 greater (0x6); 4244 %} 4245%} 4246 4247// Comparison Code, floating, unordered same as less 4248operand cmpOpF() %{ 4249 match(Bool); 4250 4251 format %{ "fl" %} 4252 interface(COND_INTER) %{ 4253 equal(0x9); 4254 not_equal(0x1); 4255 less(0x3); 4256 greater_equal(0xB); 4257 less_equal(0xE); 4258 greater(0x6); 4259 %} 4260%} 4261 4262// Used by long compare 4263operand cmpOp_commute() %{ 4264 match(Bool); 4265 4266 format %{ "" %} 4267 interface(COND_INTER) %{ 4268 equal(0x1); 4269 not_equal(0x9); 4270 less(0xA); 4271 greater_equal(0x2); 4272 less_equal(0xB); 4273 greater(0x3); 4274 %} 4275%} 4276 4277//----------OPERAND CLASSES---------------------------------------------------- 4278// Operand Classes are groups of operands that are used to simplify 4279// instruction definitions by not requiring the AD writer to specify separate 4280// instructions for every form of operand when the instruction accepts 4281// multiple operand types with the same basic encoding and format. The classic 4282// case of this is memory operands. 4283opclass memory( indirect, indOffset13, indIndex ); 4284opclass indIndexMemory( indIndex ); 4285 4286//----------PIPELINE----------------------------------------------------------- 4287pipeline %{ 4288 4289//----------ATTRIBUTES--------------------------------------------------------- 4290attributes %{ 4291 fixed_size_instructions; // Fixed size instructions 4292 branch_has_delay_slot; // Branch has delay slot following 4293 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle 4294 instruction_unit_size = 4; // An instruction is 4 bytes long 4295 instruction_fetch_unit_size = 16; // The processor fetches one line 4296 instruction_fetch_units = 1; // of 16 bytes 4297 4298 // List of nop instructions 4299 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR ); 4300%} 4301 4302//----------RESOURCES---------------------------------------------------------- 4303// Resources are the functional units available to the machine 4304resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1); 4305 4306//----------PIPELINE DESCRIPTION----------------------------------------------- 4307// Pipeline Description specifies the stages in the machine's pipeline 4308 4309pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D); 4310 4311//----------PIPELINE CLASSES--------------------------------------------------- 4312// Pipeline Classes describe the stages in which input and output are 4313// referenced by the hardware pipeline. 4314 4315// Integer ALU reg-reg operation 4316pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4317 single_instruction; 4318 dst : E(write); 4319 src1 : R(read); 4320 src2 : R(read); 4321 IALU : R; 4322%} 4323 4324// Integer ALU reg-reg long operation 4325pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 4326 instruction_count(2); 4327 dst : E(write); 4328 src1 : R(read); 4329 src2 : R(read); 4330 IALU : R; 4331 IALU : R; 4332%} 4333 4334// Integer ALU reg-reg long dependent operation 4335pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{ 4336 instruction_count(1); multiple_bundles; 4337 dst : E(write); 4338 src1 : R(read); 4339 src2 : R(read); 4340 cr : E(write); 4341 IALU : R(2); 4342%} 4343 4344// Integer ALU reg-imm operaion 4345pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4346 single_instruction; 4347 dst : E(write); 4348 src1 : R(read); 4349 IALU : R; 4350%} 4351 4352// Integer ALU reg-reg operation with condition code 4353pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{ 4354 single_instruction; 4355 dst : E(write); 4356 cr : E(write); 4357 src1 : R(read); 4358 src2 : R(read); 4359 IALU : R; 4360%} 4361 4362// Integer ALU reg-imm operation with condition code 4363pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{ 4364 single_instruction; 4365 dst : E(write); 4366 cr : E(write); 4367 src1 : R(read); 4368 IALU : R; 4369%} 4370 4371// Integer ALU zero-reg operation 4372pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 4373 single_instruction; 4374 dst : E(write); 4375 src2 : R(read); 4376 IALU : R; 4377%} 4378 4379// Integer ALU zero-reg operation with condition code only 4380pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{ 4381 single_instruction; 4382 cr : E(write); 4383 src : R(read); 4384 IALU : R; 4385%} 4386 4387// Integer ALU reg-reg operation with condition code only 4388pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4389 single_instruction; 4390 cr : E(write); 4391 src1 : R(read); 4392 src2 : R(read); 4393 IALU : R; 4394%} 4395 4396// Integer ALU reg-imm operation with condition code only 4397pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4398 single_instruction; 4399 cr : E(write); 4400 src1 : R(read); 4401 IALU : R; 4402%} 4403 4404// Integer ALU reg-reg-zero operation with condition code only 4405pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{ 4406 single_instruction; 4407 cr : E(write); 4408 src1 : R(read); 4409 src2 : R(read); 4410 IALU : R; 4411%} 4412 4413// Integer ALU reg-imm-zero operation with condition code only 4414pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{ 4415 single_instruction; 4416 cr : E(write); 4417 src1 : R(read); 4418 IALU : R; 4419%} 4420 4421// Integer ALU reg-reg operation with condition code, src1 modified 4422pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{ 4423 single_instruction; 4424 cr : E(write); 4425 src1 : E(write); 4426 src1 : R(read); 4427 src2 : R(read); 4428 IALU : R; 4429%} 4430 4431// Integer ALU reg-imm operation with condition code, src1 modified 4432pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{ 4433 single_instruction; 4434 cr : E(write); 4435 src1 : E(write); 4436 src1 : R(read); 4437 IALU : R; 4438%} 4439 4440pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{ 4441 multiple_bundles; 4442 dst : E(write)+4; 4443 cr : E(write); 4444 src1 : R(read); 4445 src2 : R(read); 4446 IALU : R(3); 4447 BR : R(2); 4448%} 4449 4450// Integer ALU operation 4451pipe_class ialu_none(iRegI dst) %{ 4452 single_instruction; 4453 dst : E(write); 4454 IALU : R; 4455%} 4456 4457// Integer ALU reg operation 4458pipe_class ialu_reg(iRegI dst, iRegI src) %{ 4459 single_instruction; may_have_no_code; 4460 dst : E(write); 4461 src : R(read); 4462 IALU : R; 4463%} 4464 4465// Integer ALU reg conditional operation 4466// This instruction has a 1 cycle stall, and cannot execute 4467// in the same cycle as the instruction setting the condition 4468// code. We kludge this by pretending to read the condition code 4469// 1 cycle earlier, and by marking the functional units as busy 4470// for 2 cycles with the result available 1 cycle later than 4471// is really the case. 4472pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{ 4473 single_instruction; 4474 op2_out : C(write); 4475 op1 : R(read); 4476 cr : R(read); // This is really E, with a 1 cycle stall 4477 BR : R(2); 4478 MS : R(2); 4479%} 4480 4481#ifdef _LP64 4482pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{ 4483 instruction_count(1); multiple_bundles; 4484 dst : C(write)+1; 4485 src : R(read)+1; 4486 IALU : R(1); 4487 BR : E(2); 4488 MS : E(2); 4489%} 4490#endif 4491 4492// Integer ALU reg operation 4493pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{ 4494 single_instruction; may_have_no_code; 4495 dst : E(write); 4496 src : R(read); 4497 IALU : R; 4498%} 4499pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{ 4500 single_instruction; may_have_no_code; 4501 dst : E(write); 4502 src : R(read); 4503 IALU : R; 4504%} 4505 4506// Two integer ALU reg operations 4507pipe_class ialu_reg_2(iRegL dst, iRegL src) %{ 4508 instruction_count(2); 4509 dst : E(write); 4510 src : R(read); 4511 A0 : R; 4512 A1 : R; 4513%} 4514 4515// Two integer ALU reg operations 4516pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{ 4517 instruction_count(2); may_have_no_code; 4518 dst : E(write); 4519 src : R(read); 4520 A0 : R; 4521 A1 : R; 4522%} 4523 4524// Integer ALU imm operation 4525pipe_class ialu_imm(iRegI dst, immI13 src) %{ 4526 single_instruction; 4527 dst : E(write); 4528 IALU : R; 4529%} 4530 4531// Integer ALU reg-reg with carry operation 4532pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{ 4533 single_instruction; 4534 dst : E(write); 4535 src1 : R(read); 4536 src2 : R(read); 4537 IALU : R; 4538%} 4539 4540// Integer ALU cc operation 4541pipe_class ialu_cc(iRegI dst, flagsReg cc) %{ 4542 single_instruction; 4543 dst : E(write); 4544 cc : R(read); 4545 IALU : R; 4546%} 4547 4548// Integer ALU cc / second IALU operation 4549pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{ 4550 instruction_count(1); multiple_bundles; 4551 dst : E(write)+1; 4552 src : R(read); 4553 IALU : R; 4554%} 4555 4556// Integer ALU cc / second IALU operation 4557pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{ 4558 instruction_count(1); multiple_bundles; 4559 dst : E(write)+1; 4560 p : R(read); 4561 q : R(read); 4562 IALU : R; 4563%} 4564 4565// Integer ALU hi-lo-reg operation 4566pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{ 4567 instruction_count(1); multiple_bundles; 4568 dst : E(write)+1; 4569 IALU : R(2); 4570%} 4571 4572// Float ALU hi-lo-reg operation (with temp) 4573pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{ 4574 instruction_count(1); multiple_bundles; 4575 dst : E(write)+1; 4576 IALU : R(2); 4577%} 4578 4579// Long Constant 4580pipe_class loadConL( iRegL dst, immL src ) %{ 4581 instruction_count(2); multiple_bundles; 4582 dst : E(write)+1; 4583 IALU : R(2); 4584 IALU : R(2); 4585%} 4586 4587// Pointer Constant 4588pipe_class loadConP( iRegP dst, immP src ) %{ 4589 instruction_count(0); multiple_bundles; 4590 fixed_latency(6); 4591%} 4592 4593// Polling Address 4594pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{ 4595#ifdef _LP64 4596 instruction_count(0); multiple_bundles; 4597 fixed_latency(6); 4598#else 4599 dst : E(write); 4600 IALU : R; 4601#endif 4602%} 4603 4604// Long Constant small 4605pipe_class loadConLlo( iRegL dst, immL src ) %{ 4606 instruction_count(2); 4607 dst : E(write); 4608 IALU : R; 4609 IALU : R; 4610%} 4611 4612// [PHH] This is wrong for 64-bit. See LdImmF/D. 4613pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{ 4614 instruction_count(1); multiple_bundles; 4615 src : R(read); 4616 dst : M(write)+1; 4617 IALU : R; 4618 MS : E; 4619%} 4620 4621// Integer ALU nop operation 4622pipe_class ialu_nop() %{ 4623 single_instruction; 4624 IALU : R; 4625%} 4626 4627// Integer ALU nop operation 4628pipe_class ialu_nop_A0() %{ 4629 single_instruction; 4630 A0 : R; 4631%} 4632 4633// Integer ALU nop operation 4634pipe_class ialu_nop_A1() %{ 4635 single_instruction; 4636 A1 : R; 4637%} 4638 4639// Integer Multiply reg-reg operation 4640pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 4641 single_instruction; 4642 dst : E(write); 4643 src1 : R(read); 4644 src2 : R(read); 4645 MS : R(5); 4646%} 4647 4648// Integer Multiply reg-imm operation 4649pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{ 4650 single_instruction; 4651 dst : E(write); 4652 src1 : R(read); 4653 MS : R(5); 4654%} 4655 4656pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4657 single_instruction; 4658 dst : E(write)+4; 4659 src1 : R(read); 4660 src2 : R(read); 4661 MS : R(6); 4662%} 4663 4664pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4665 single_instruction; 4666 dst : E(write)+4; 4667 src1 : R(read); 4668 MS : R(6); 4669%} 4670 4671// Integer Divide reg-reg 4672pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{ 4673 instruction_count(1); multiple_bundles; 4674 dst : E(write); 4675 temp : E(write); 4676 src1 : R(read); 4677 src2 : R(read); 4678 temp : R(read); 4679 MS : R(38); 4680%} 4681 4682// Integer Divide reg-imm 4683pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{ 4684 instruction_count(1); multiple_bundles; 4685 dst : E(write); 4686 temp : E(write); 4687 src1 : R(read); 4688 temp : R(read); 4689 MS : R(38); 4690%} 4691 4692// Long Divide 4693pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 4694 dst : E(write)+71; 4695 src1 : R(read); 4696 src2 : R(read)+1; 4697 MS : R(70); 4698%} 4699 4700pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{ 4701 dst : E(write)+71; 4702 src1 : R(read); 4703 MS : R(70); 4704%} 4705 4706// Floating Point Add Float 4707pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{ 4708 single_instruction; 4709 dst : X(write); 4710 src1 : E(read); 4711 src2 : E(read); 4712 FA : R; 4713%} 4714 4715// Floating Point Add Double 4716pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{ 4717 single_instruction; 4718 dst : X(write); 4719 src1 : E(read); 4720 src2 : E(read); 4721 FA : R; 4722%} 4723 4724// Floating Point Conditional Move based on integer flags 4725pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{ 4726 single_instruction; 4727 dst : X(write); 4728 src : E(read); 4729 cr : R(read); 4730 FA : R(2); 4731 BR : R(2); 4732%} 4733 4734// Floating Point Conditional Move based on integer flags 4735pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{ 4736 single_instruction; 4737 dst : X(write); 4738 src : E(read); 4739 cr : R(read); 4740 FA : R(2); 4741 BR : R(2); 4742%} 4743 4744// Floating Point Multiply Float 4745pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{ 4746 single_instruction; 4747 dst : X(write); 4748 src1 : E(read); 4749 src2 : E(read); 4750 FM : R; 4751%} 4752 4753// Floating Point Multiply Double 4754pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{ 4755 single_instruction; 4756 dst : X(write); 4757 src1 : E(read); 4758 src2 : E(read); 4759 FM : R; 4760%} 4761 4762// Floating Point Divide Float 4763pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{ 4764 single_instruction; 4765 dst : X(write); 4766 src1 : E(read); 4767 src2 : E(read); 4768 FM : R; 4769 FDIV : C(14); 4770%} 4771 4772// Floating Point Divide Double 4773pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{ 4774 single_instruction; 4775 dst : X(write); 4776 src1 : E(read); 4777 src2 : E(read); 4778 FM : R; 4779 FDIV : C(17); 4780%} 4781 4782// Floating Point Move/Negate/Abs Float 4783pipe_class faddF_reg(regF dst, regF src) %{ 4784 single_instruction; 4785 dst : W(write); 4786 src : E(read); 4787 FA : R(1); 4788%} 4789 4790// Floating Point Move/Negate/Abs Double 4791pipe_class faddD_reg(regD dst, regD src) %{ 4792 single_instruction; 4793 dst : W(write); 4794 src : E(read); 4795 FA : R; 4796%} 4797 4798// Floating Point Convert F->D 4799pipe_class fcvtF2D(regD dst, regF src) %{ 4800 single_instruction; 4801 dst : X(write); 4802 src : E(read); 4803 FA : R; 4804%} 4805 4806// Floating Point Convert I->D 4807pipe_class fcvtI2D(regD dst, regF src) %{ 4808 single_instruction; 4809 dst : X(write); 4810 src : E(read); 4811 FA : R; 4812%} 4813 4814// Floating Point Convert LHi->D 4815pipe_class fcvtLHi2D(regD dst, regD src) %{ 4816 single_instruction; 4817 dst : X(write); 4818 src : E(read); 4819 FA : R; 4820%} 4821 4822// Floating Point Convert L->D 4823pipe_class fcvtL2D(regD dst, regF src) %{ 4824 single_instruction; 4825 dst : X(write); 4826 src : E(read); 4827 FA : R; 4828%} 4829 4830// Floating Point Convert L->F 4831pipe_class fcvtL2F(regD dst, regF src) %{ 4832 single_instruction; 4833 dst : X(write); 4834 src : E(read); 4835 FA : R; 4836%} 4837 4838// Floating Point Convert D->F 4839pipe_class fcvtD2F(regD dst, regF src) %{ 4840 single_instruction; 4841 dst : X(write); 4842 src : E(read); 4843 FA : R; 4844%} 4845 4846// Floating Point Convert I->L 4847pipe_class fcvtI2L(regD dst, regF src) %{ 4848 single_instruction; 4849 dst : X(write); 4850 src : E(read); 4851 FA : R; 4852%} 4853 4854// Floating Point Convert D->F 4855pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{ 4856 instruction_count(1); multiple_bundles; 4857 dst : X(write)+6; 4858 src : E(read); 4859 FA : R; 4860%} 4861 4862// Floating Point Convert D->L 4863pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{ 4864 instruction_count(1); multiple_bundles; 4865 dst : X(write)+6; 4866 src : E(read); 4867 FA : R; 4868%} 4869 4870// Floating Point Convert F->I 4871pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{ 4872 instruction_count(1); multiple_bundles; 4873 dst : X(write)+6; 4874 src : E(read); 4875 FA : R; 4876%} 4877 4878// Floating Point Convert F->L 4879pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{ 4880 instruction_count(1); multiple_bundles; 4881 dst : X(write)+6; 4882 src : E(read); 4883 FA : R; 4884%} 4885 4886// Floating Point Convert I->F 4887pipe_class fcvtI2F(regF dst, regF src) %{ 4888 single_instruction; 4889 dst : X(write); 4890 src : E(read); 4891 FA : R; 4892%} 4893 4894// Floating Point Compare 4895pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{ 4896 single_instruction; 4897 cr : X(write); 4898 src1 : E(read); 4899 src2 : E(read); 4900 FA : R; 4901%} 4902 4903// Floating Point Compare 4904pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{ 4905 single_instruction; 4906 cr : X(write); 4907 src1 : E(read); 4908 src2 : E(read); 4909 FA : R; 4910%} 4911 4912// Floating Add Nop 4913pipe_class fadd_nop() %{ 4914 single_instruction; 4915 FA : R; 4916%} 4917 4918// Integer Store to Memory 4919pipe_class istore_mem_reg(memory mem, iRegI src) %{ 4920 single_instruction; 4921 mem : R(read); 4922 src : C(read); 4923 MS : R; 4924%} 4925 4926// Integer Store to Memory 4927pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{ 4928 single_instruction; 4929 mem : R(read); 4930 src : C(read); 4931 MS : R; 4932%} 4933 4934// Integer Store Zero to Memory 4935pipe_class istore_mem_zero(memory mem, immI0 src) %{ 4936 single_instruction; 4937 mem : R(read); 4938 MS : R; 4939%} 4940 4941// Special Stack Slot Store 4942pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{ 4943 single_instruction; 4944 stkSlot : R(read); 4945 src : C(read); 4946 MS : R; 4947%} 4948 4949// Special Stack Slot Store 4950pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{ 4951 instruction_count(2); multiple_bundles; 4952 stkSlot : R(read); 4953 src : C(read); 4954 MS : R(2); 4955%} 4956 4957// Float Store 4958pipe_class fstoreF_mem_reg(memory mem, RegF src) %{ 4959 single_instruction; 4960 mem : R(read); 4961 src : C(read); 4962 MS : R; 4963%} 4964 4965// Float Store 4966pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{ 4967 single_instruction; 4968 mem : R(read); 4969 MS : R; 4970%} 4971 4972// Double Store 4973pipe_class fstoreD_mem_reg(memory mem, RegD src) %{ 4974 instruction_count(1); 4975 mem : R(read); 4976 src : C(read); 4977 MS : R; 4978%} 4979 4980// Double Store 4981pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{ 4982 single_instruction; 4983 mem : R(read); 4984 MS : R; 4985%} 4986 4987// Special Stack Slot Float Store 4988pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{ 4989 single_instruction; 4990 stkSlot : R(read); 4991 src : C(read); 4992 MS : R; 4993%} 4994 4995// Special Stack Slot Double Store 4996pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{ 4997 single_instruction; 4998 stkSlot : R(read); 4999 src : C(read); 5000 MS : R; 5001%} 5002 5003// Integer Load (when sign bit propagation not needed) 5004pipe_class iload_mem(iRegI dst, memory mem) %{ 5005 single_instruction; 5006 mem : R(read); 5007 dst : C(write); 5008 MS : R; 5009%} 5010 5011// Integer Load from stack operand 5012pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{ 5013 single_instruction; 5014 mem : R(read); 5015 dst : C(write); 5016 MS : R; 5017%} 5018 5019// Integer Load (when sign bit propagation or masking is needed) 5020pipe_class iload_mask_mem(iRegI dst, memory mem) %{ 5021 single_instruction; 5022 mem : R(read); 5023 dst : M(write); 5024 MS : R; 5025%} 5026 5027// Float Load 5028pipe_class floadF_mem(regF dst, memory mem) %{ 5029 single_instruction; 5030 mem : R(read); 5031 dst : M(write); 5032 MS : R; 5033%} 5034 5035// Float Load 5036pipe_class floadD_mem(regD dst, memory mem) %{ 5037 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case 5038 mem : R(read); 5039 dst : M(write); 5040 MS : R; 5041%} 5042 5043// Float Load 5044pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{ 5045 single_instruction; 5046 stkSlot : R(read); 5047 dst : M(write); 5048 MS : R; 5049%} 5050 5051// Float Load 5052pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{ 5053 single_instruction; 5054 stkSlot : R(read); 5055 dst : M(write); 5056 MS : R; 5057%} 5058 5059// Memory Nop 5060pipe_class mem_nop() %{ 5061 single_instruction; 5062 MS : R; 5063%} 5064 5065pipe_class sethi(iRegP dst, immI src) %{ 5066 single_instruction; 5067 dst : E(write); 5068 IALU : R; 5069%} 5070 5071pipe_class loadPollP(iRegP poll) %{ 5072 single_instruction; 5073 poll : R(read); 5074 MS : R; 5075%} 5076 5077pipe_class br(Universe br, label labl) %{ 5078 single_instruction_with_delay_slot; 5079 BR : R; 5080%} 5081 5082pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{ 5083 single_instruction_with_delay_slot; 5084 cr : E(read); 5085 BR : R; 5086%} 5087 5088pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{ 5089 single_instruction_with_delay_slot; 5090 op1 : E(read); 5091 BR : R; 5092 MS : R; 5093%} 5094 5095pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{ 5096 single_instruction_with_delay_slot; 5097 cr : E(read); 5098 BR : R; 5099%} 5100 5101pipe_class br_nop() %{ 5102 single_instruction; 5103 BR : R; 5104%} 5105 5106pipe_class simple_call(method meth) %{ 5107 instruction_count(2); multiple_bundles; force_serialization; 5108 fixed_latency(100); 5109 BR : R(1); 5110 MS : R(1); 5111 A0 : R(1); 5112%} 5113 5114pipe_class compiled_call(method meth) %{ 5115 instruction_count(1); multiple_bundles; force_serialization; 5116 fixed_latency(100); 5117 MS : R(1); 5118%} 5119 5120pipe_class call(method meth) %{ 5121 instruction_count(0); multiple_bundles; force_serialization; 5122 fixed_latency(100); 5123%} 5124 5125pipe_class tail_call(Universe ignore, label labl) %{ 5126 single_instruction; has_delay_slot; 5127 fixed_latency(100); 5128 BR : R(1); 5129 MS : R(1); 5130%} 5131 5132pipe_class ret(Universe ignore) %{ 5133 single_instruction; has_delay_slot; 5134 BR : R(1); 5135 MS : R(1); 5136%} 5137 5138pipe_class ret_poll(g3RegP poll) %{ 5139 instruction_count(3); has_delay_slot; 5140 poll : E(read); 5141 MS : R; 5142%} 5143 5144// The real do-nothing guy 5145pipe_class empty( ) %{ 5146 instruction_count(0); 5147%} 5148 5149pipe_class long_memory_op() %{ 5150 instruction_count(0); multiple_bundles; force_serialization; 5151 fixed_latency(25); 5152 MS : R(1); 5153%} 5154 5155// Check-cast 5156pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{ 5157 array : R(read); 5158 match : R(read); 5159 IALU : R(2); 5160 BR : R(2); 5161 MS : R; 5162%} 5163 5164// Convert FPU flags into +1,0,-1 5165pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{ 5166 src1 : E(read); 5167 src2 : E(read); 5168 dst : E(write); 5169 FA : R; 5170 MS : R(2); 5171 BR : R(2); 5172%} 5173 5174// Compare for p < q, and conditionally add y 5175pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{ 5176 p : E(read); 5177 q : E(read); 5178 y : E(read); 5179 IALU : R(3) 5180%} 5181 5182// Perform a compare, then move conditionally in a branch delay slot. 5183pipe_class min_max( iRegI src2, iRegI srcdst ) %{ 5184 src2 : E(read); 5185 srcdst : E(read); 5186 IALU : R; 5187 BR : R; 5188%} 5189 5190// Define the class for the Nop node 5191define %{ 5192 MachNop = ialu_nop; 5193%} 5194 5195%} 5196 5197//----------INSTRUCTIONS------------------------------------------------------- 5198 5199//------------Special Stack Slot instructions - no match rules----------------- 5200instruct stkI_to_regF(regF dst, stackSlotI src) %{ 5201 // No match rule to avoid chain rule match. 5202 effect(DEF dst, USE src); 5203 ins_cost(MEMORY_REF_COST); 5204 size(4); 5205 format %{ "LDF $src,$dst\t! stkI to regF" %} 5206 opcode(Assembler::ldf_op3); 5207 ins_encode(simple_form3_mem_reg(src, dst)); 5208 ins_pipe(floadF_stk); 5209%} 5210 5211instruct stkL_to_regD(regD dst, stackSlotL src) %{ 5212 // No match rule to avoid chain rule match. 5213 effect(DEF dst, USE src); 5214 ins_cost(MEMORY_REF_COST); 5215 size(4); 5216 format %{ "LDDF $src,$dst\t! stkL to regD" %} 5217 opcode(Assembler::lddf_op3); 5218 ins_encode(simple_form3_mem_reg(src, dst)); 5219 ins_pipe(floadD_stk); 5220%} 5221 5222instruct regF_to_stkI(stackSlotI dst, regF src) %{ 5223 // No match rule to avoid chain rule match. 5224 effect(DEF dst, USE src); 5225 ins_cost(MEMORY_REF_COST); 5226 size(4); 5227 format %{ "STF $src,$dst\t! regF to stkI" %} 5228 opcode(Assembler::stf_op3); 5229 ins_encode(simple_form3_mem_reg(dst, src)); 5230 ins_pipe(fstoreF_stk_reg); 5231%} 5232 5233instruct regD_to_stkL(stackSlotL dst, regD src) %{ 5234 // No match rule to avoid chain rule match. 5235 effect(DEF dst, USE src); 5236 ins_cost(MEMORY_REF_COST); 5237 size(4); 5238 format %{ "STDF $src,$dst\t! regD to stkL" %} 5239 opcode(Assembler::stdf_op3); 5240 ins_encode(simple_form3_mem_reg(dst, src)); 5241 ins_pipe(fstoreD_stk_reg); 5242%} 5243 5244instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{ 5245 effect(DEF dst, USE src); 5246 ins_cost(MEMORY_REF_COST*2); 5247 size(8); 5248 format %{ "STW $src,$dst.hi\t! long\n\t" 5249 "STW R_G0,$dst.lo" %} 5250 opcode(Assembler::stw_op3); 5251 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0)); 5252 ins_pipe(lstoreI_stk_reg); 5253%} 5254 5255instruct regL_to_stkD(stackSlotD dst, iRegL src) %{ 5256 // No match rule to avoid chain rule match. 5257 effect(DEF dst, USE src); 5258 ins_cost(MEMORY_REF_COST); 5259 size(4); 5260 format %{ "STX $src,$dst\t! regL to stkD" %} 5261 opcode(Assembler::stx_op3); 5262 ins_encode(simple_form3_mem_reg( dst, src ) ); 5263 ins_pipe(istore_stk_reg); 5264%} 5265 5266//---------- Chain stack slots between similar types -------- 5267 5268// Load integer from stack slot 5269instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{ 5270 match(Set dst src); 5271 ins_cost(MEMORY_REF_COST); 5272 5273 size(4); 5274 format %{ "LDUW $src,$dst\t!stk" %} 5275 opcode(Assembler::lduw_op3); 5276 ins_encode(simple_form3_mem_reg( src, dst ) ); 5277 ins_pipe(iload_mem); 5278%} 5279 5280// Store integer to stack slot 5281instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{ 5282 match(Set dst src); 5283 ins_cost(MEMORY_REF_COST); 5284 5285 size(4); 5286 format %{ "STW $src,$dst\t!stk" %} 5287 opcode(Assembler::stw_op3); 5288 ins_encode(simple_form3_mem_reg( dst, src ) ); 5289 ins_pipe(istore_mem_reg); 5290%} 5291 5292// Load long from stack slot 5293instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{ 5294 match(Set dst src); 5295 5296 ins_cost(MEMORY_REF_COST); 5297 size(4); 5298 format %{ "LDX $src,$dst\t! long" %} 5299 opcode(Assembler::ldx_op3); 5300 ins_encode(simple_form3_mem_reg( src, dst ) ); 5301 ins_pipe(iload_mem); 5302%} 5303 5304// Store long to stack slot 5305instruct regL_to_stkL(stackSlotL dst, iRegL src) %{ 5306 match(Set dst src); 5307 5308 ins_cost(MEMORY_REF_COST); 5309 size(4); 5310 format %{ "STX $src,$dst\t! long" %} 5311 opcode(Assembler::stx_op3); 5312 ins_encode(simple_form3_mem_reg( dst, src ) ); 5313 ins_pipe(istore_mem_reg); 5314%} 5315 5316#ifdef _LP64 5317// Load pointer from stack slot, 64-bit encoding 5318instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5319 match(Set dst src); 5320 ins_cost(MEMORY_REF_COST); 5321 size(4); 5322 format %{ "LDX $src,$dst\t!ptr" %} 5323 opcode(Assembler::ldx_op3); 5324 ins_encode(simple_form3_mem_reg( src, dst ) ); 5325 ins_pipe(iload_mem); 5326%} 5327 5328// Store pointer to stack slot 5329instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5330 match(Set dst src); 5331 ins_cost(MEMORY_REF_COST); 5332 size(4); 5333 format %{ "STX $src,$dst\t!ptr" %} 5334 opcode(Assembler::stx_op3); 5335 ins_encode(simple_form3_mem_reg( dst, src ) ); 5336 ins_pipe(istore_mem_reg); 5337%} 5338#else // _LP64 5339// Load pointer from stack slot, 32-bit encoding 5340instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{ 5341 match(Set dst src); 5342 ins_cost(MEMORY_REF_COST); 5343 format %{ "LDUW $src,$dst\t!ptr" %} 5344 opcode(Assembler::lduw_op3, Assembler::ldst_op); 5345 ins_encode(simple_form3_mem_reg( src, dst ) ); 5346 ins_pipe(iload_mem); 5347%} 5348 5349// Store pointer to stack slot 5350instruct regP_to_stkP(stackSlotP dst, iRegP src) %{ 5351 match(Set dst src); 5352 ins_cost(MEMORY_REF_COST); 5353 format %{ "STW $src,$dst\t!ptr" %} 5354 opcode(Assembler::stw_op3, Assembler::ldst_op); 5355 ins_encode(simple_form3_mem_reg( dst, src ) ); 5356 ins_pipe(istore_mem_reg); 5357%} 5358#endif // _LP64 5359 5360//------------Special Nop instructions for bundling - no match rules----------- 5361// Nop using the A0 functional unit 5362instruct Nop_A0() %{ 5363 ins_cost(0); 5364 5365 format %{ "NOP ! Alu Pipeline" %} 5366 opcode(Assembler::or_op3, Assembler::arith_op); 5367 ins_encode( form2_nop() ); 5368 ins_pipe(ialu_nop_A0); 5369%} 5370 5371// Nop using the A1 functional unit 5372instruct Nop_A1( ) %{ 5373 ins_cost(0); 5374 5375 format %{ "NOP ! Alu Pipeline" %} 5376 opcode(Assembler::or_op3, Assembler::arith_op); 5377 ins_encode( form2_nop() ); 5378 ins_pipe(ialu_nop_A1); 5379%} 5380 5381// Nop using the memory functional unit 5382instruct Nop_MS( ) %{ 5383 ins_cost(0); 5384 5385 format %{ "NOP ! Memory Pipeline" %} 5386 ins_encode( emit_mem_nop ); 5387 ins_pipe(mem_nop); 5388%} 5389 5390// Nop using the floating add functional unit 5391instruct Nop_FA( ) %{ 5392 ins_cost(0); 5393 5394 format %{ "NOP ! Floating Add Pipeline" %} 5395 ins_encode( emit_fadd_nop ); 5396 ins_pipe(fadd_nop); 5397%} 5398 5399// Nop using the branch functional unit 5400instruct Nop_BR( ) %{ 5401 ins_cost(0); 5402 5403 format %{ "NOP ! Branch Pipeline" %} 5404 ins_encode( emit_br_nop ); 5405 ins_pipe(br_nop); 5406%} 5407 5408//----------Load/Store/Move Instructions--------------------------------------- 5409//----------Load Instructions-------------------------------------------------- 5410// Load Byte (8bit signed) 5411instruct loadB(iRegI dst, memory mem) %{ 5412 match(Set dst (LoadB mem)); 5413 ins_cost(MEMORY_REF_COST); 5414 5415 size(4); 5416 format %{ "LDSB $mem,$dst\t! byte" %} 5417 ins_encode %{ 5418 __ ldsb($mem$$Address, $dst$$Register); 5419 %} 5420 ins_pipe(iload_mask_mem); 5421%} 5422 5423// Load Byte (8bit signed) into a Long Register 5424instruct loadB2L(iRegL dst, memory mem) %{ 5425 match(Set dst (ConvI2L (LoadB mem))); 5426 ins_cost(MEMORY_REF_COST); 5427 5428 size(4); 5429 format %{ "LDSB $mem,$dst\t! byte -> long" %} 5430 ins_encode %{ 5431 __ ldsb($mem$$Address, $dst$$Register); 5432 %} 5433 ins_pipe(iload_mask_mem); 5434%} 5435 5436// Load Unsigned Byte (8bit UNsigned) into an int reg 5437instruct loadUB(iRegI dst, memory mem) %{ 5438 match(Set dst (LoadUB mem)); 5439 ins_cost(MEMORY_REF_COST); 5440 5441 size(4); 5442 format %{ "LDUB $mem,$dst\t! ubyte" %} 5443 ins_encode %{ 5444 __ ldub($mem$$Address, $dst$$Register); 5445 %} 5446 ins_pipe(iload_mem); 5447%} 5448 5449// Load Unsigned Byte (8bit UNsigned) into a Long Register 5450instruct loadUB2L(iRegL dst, memory mem) %{ 5451 match(Set dst (ConvI2L (LoadUB mem))); 5452 ins_cost(MEMORY_REF_COST); 5453 5454 size(4); 5455 format %{ "LDUB $mem,$dst\t! ubyte -> long" %} 5456 ins_encode %{ 5457 __ ldub($mem$$Address, $dst$$Register); 5458 %} 5459 ins_pipe(iload_mem); 5460%} 5461 5462// Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register 5463instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{ 5464 match(Set dst (ConvI2L (AndI (LoadUB mem) mask))); 5465 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5466 5467 size(2*4); 5468 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t" 5469 "AND $dst,$mask,$dst" %} 5470 ins_encode %{ 5471 __ ldub($mem$$Address, $dst$$Register); 5472 __ and3($dst$$Register, $mask$$constant, $dst$$Register); 5473 %} 5474 ins_pipe(iload_mem); 5475%} 5476 5477// Load Short (16bit signed) 5478instruct loadS(iRegI dst, memory mem) %{ 5479 match(Set dst (LoadS mem)); 5480 ins_cost(MEMORY_REF_COST); 5481 5482 size(4); 5483 format %{ "LDSH $mem,$dst\t! short" %} 5484 ins_encode %{ 5485 __ ldsh($mem$$Address, $dst$$Register); 5486 %} 5487 ins_pipe(iload_mask_mem); 5488%} 5489 5490// Load Short (16 bit signed) to Byte (8 bit signed) 5491instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5492 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour)); 5493 ins_cost(MEMORY_REF_COST); 5494 5495 size(4); 5496 5497 format %{ "LDSB $mem+1,$dst\t! short -> byte" %} 5498 ins_encode %{ 5499 __ ldsb($mem$$Address, $dst$$Register, 1); 5500 %} 5501 ins_pipe(iload_mask_mem); 5502%} 5503 5504// Load Short (16bit signed) into a Long Register 5505instruct loadS2L(iRegL dst, memory mem) %{ 5506 match(Set dst (ConvI2L (LoadS mem))); 5507 ins_cost(MEMORY_REF_COST); 5508 5509 size(4); 5510 format %{ "LDSH $mem,$dst\t! short -> long" %} 5511 ins_encode %{ 5512 __ ldsh($mem$$Address, $dst$$Register); 5513 %} 5514 ins_pipe(iload_mask_mem); 5515%} 5516 5517// Load Unsigned Short/Char (16bit UNsigned) 5518instruct loadUS(iRegI dst, memory mem) %{ 5519 match(Set dst (LoadUS mem)); 5520 ins_cost(MEMORY_REF_COST); 5521 5522 size(4); 5523 format %{ "LDUH $mem,$dst\t! ushort/char" %} 5524 ins_encode %{ 5525 __ lduh($mem$$Address, $dst$$Register); 5526 %} 5527 ins_pipe(iload_mem); 5528%} 5529 5530// Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed) 5531instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5532 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour)); 5533 ins_cost(MEMORY_REF_COST); 5534 5535 size(4); 5536 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %} 5537 ins_encode %{ 5538 __ ldsb($mem$$Address, $dst$$Register, 1); 5539 %} 5540 ins_pipe(iload_mask_mem); 5541%} 5542 5543// Load Unsigned Short/Char (16bit UNsigned) into a Long Register 5544instruct loadUS2L(iRegL dst, memory mem) %{ 5545 match(Set dst (ConvI2L (LoadUS mem))); 5546 ins_cost(MEMORY_REF_COST); 5547 5548 size(4); 5549 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %} 5550 ins_encode %{ 5551 __ lduh($mem$$Address, $dst$$Register); 5552 %} 5553 ins_pipe(iload_mem); 5554%} 5555 5556// Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register 5557instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5558 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5559 ins_cost(MEMORY_REF_COST); 5560 5561 size(4); 5562 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %} 5563 ins_encode %{ 5564 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE 5565 %} 5566 ins_pipe(iload_mem); 5567%} 5568 5569// Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register 5570instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5571 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5572 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5573 5574 size(2*4); 5575 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t" 5576 "AND $dst,$mask,$dst" %} 5577 ins_encode %{ 5578 Register Rdst = $dst$$Register; 5579 __ lduh($mem$$Address, Rdst); 5580 __ and3(Rdst, $mask$$constant, Rdst); 5581 %} 5582 ins_pipe(iload_mem); 5583%} 5584 5585// Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register 5586instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{ 5587 match(Set dst (ConvI2L (AndI (LoadUS mem) mask))); 5588 effect(TEMP dst, TEMP tmp); 5589 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5590 5591 size((3+1)*4); // set may use two instructions. 5592 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t" 5593 "SET $mask,$tmp\n\t" 5594 "AND $dst,$tmp,$dst" %} 5595 ins_encode %{ 5596 Register Rdst = $dst$$Register; 5597 Register Rtmp = $tmp$$Register; 5598 __ lduh($mem$$Address, Rdst); 5599 __ set($mask$$constant, Rtmp); 5600 __ and3(Rdst, Rtmp, Rdst); 5601 %} 5602 ins_pipe(iload_mem); 5603%} 5604 5605// Load Integer 5606instruct loadI(iRegI dst, memory mem) %{ 5607 match(Set dst (LoadI mem)); 5608 ins_cost(MEMORY_REF_COST); 5609 5610 size(4); 5611 format %{ "LDUW $mem,$dst\t! int" %} 5612 ins_encode %{ 5613 __ lduw($mem$$Address, $dst$$Register); 5614 %} 5615 ins_pipe(iload_mem); 5616%} 5617 5618// Load Integer to Byte (8 bit signed) 5619instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{ 5620 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour)); 5621 ins_cost(MEMORY_REF_COST); 5622 5623 size(4); 5624 5625 format %{ "LDSB $mem+3,$dst\t! int -> byte" %} 5626 ins_encode %{ 5627 __ ldsb($mem$$Address, $dst$$Register, 3); 5628 %} 5629 ins_pipe(iload_mask_mem); 5630%} 5631 5632// Load Integer to Unsigned Byte (8 bit UNsigned) 5633instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{ 5634 match(Set dst (AndI (LoadI mem) mask)); 5635 ins_cost(MEMORY_REF_COST); 5636 5637 size(4); 5638 5639 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %} 5640 ins_encode %{ 5641 __ ldub($mem$$Address, $dst$$Register, 3); 5642 %} 5643 ins_pipe(iload_mask_mem); 5644%} 5645 5646// Load Integer to Short (16 bit signed) 5647instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{ 5648 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen)); 5649 ins_cost(MEMORY_REF_COST); 5650 5651 size(4); 5652 5653 format %{ "LDSH $mem+2,$dst\t! int -> short" %} 5654 ins_encode %{ 5655 __ ldsh($mem$$Address, $dst$$Register, 2); 5656 %} 5657 ins_pipe(iload_mask_mem); 5658%} 5659 5660// Load Integer to Unsigned Short (16 bit UNsigned) 5661instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{ 5662 match(Set dst (AndI (LoadI mem) mask)); 5663 ins_cost(MEMORY_REF_COST); 5664 5665 size(4); 5666 5667 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %} 5668 ins_encode %{ 5669 __ lduh($mem$$Address, $dst$$Register, 2); 5670 %} 5671 ins_pipe(iload_mask_mem); 5672%} 5673 5674// Load Integer into a Long Register 5675instruct loadI2L(iRegL dst, memory mem) %{ 5676 match(Set dst (ConvI2L (LoadI mem))); 5677 ins_cost(MEMORY_REF_COST); 5678 5679 size(4); 5680 format %{ "LDSW $mem,$dst\t! int -> long" %} 5681 ins_encode %{ 5682 __ ldsw($mem$$Address, $dst$$Register); 5683 %} 5684 ins_pipe(iload_mask_mem); 5685%} 5686 5687// Load Integer with mask 0xFF into a Long Register 5688instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{ 5689 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5690 ins_cost(MEMORY_REF_COST); 5691 5692 size(4); 5693 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %} 5694 ins_encode %{ 5695 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE 5696 %} 5697 ins_pipe(iload_mem); 5698%} 5699 5700// Load Integer with mask 0xFFFF into a Long Register 5701instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{ 5702 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5703 ins_cost(MEMORY_REF_COST); 5704 5705 size(4); 5706 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %} 5707 ins_encode %{ 5708 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE 5709 %} 5710 ins_pipe(iload_mem); 5711%} 5712 5713// Load Integer with a 13-bit mask into a Long Register 5714instruct loadI2L_immI13(iRegL dst, memory mem, immI13 mask) %{ 5715 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5716 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5717 5718 size(2*4); 5719 format %{ "LDUW $mem,$dst\t! int & 13-bit mask -> long\n\t" 5720 "AND $dst,$mask,$dst" %} 5721 ins_encode %{ 5722 Register Rdst = $dst$$Register; 5723 __ lduw($mem$$Address, Rdst); 5724 __ and3(Rdst, $mask$$constant, Rdst); 5725 %} 5726 ins_pipe(iload_mem); 5727%} 5728 5729// Load Integer with a 32-bit mask into a Long Register 5730instruct loadI2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{ 5731 match(Set dst (ConvI2L (AndI (LoadI mem) mask))); 5732 effect(TEMP dst, TEMP tmp); 5733 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST); 5734 5735 size((3+1)*4); // set may use two instructions. 5736 format %{ "LDUW $mem,$dst\t! int & 32-bit mask -> long\n\t" 5737 "SET $mask,$tmp\n\t" 5738 "AND $dst,$tmp,$dst" %} 5739 ins_encode %{ 5740 Register Rdst = $dst$$Register; 5741 Register Rtmp = $tmp$$Register; 5742 __ lduw($mem$$Address, Rdst); 5743 __ set($mask$$constant, Rtmp); 5744 __ and3(Rdst, Rtmp, Rdst); 5745 %} 5746 ins_pipe(iload_mem); 5747%} 5748 5749// Load Unsigned Integer into a Long Register 5750instruct loadUI2L(iRegL dst, memory mem) %{ 5751 match(Set dst (LoadUI2L mem)); 5752 ins_cost(MEMORY_REF_COST); 5753 5754 size(4); 5755 format %{ "LDUW $mem,$dst\t! uint -> long" %} 5756 ins_encode %{ 5757 __ lduw($mem$$Address, $dst$$Register); 5758 %} 5759 ins_pipe(iload_mem); 5760%} 5761 5762// Load Long - aligned 5763instruct loadL(iRegL dst, memory mem ) %{ 5764 match(Set dst (LoadL mem)); 5765 ins_cost(MEMORY_REF_COST); 5766 5767 size(4); 5768 format %{ "LDX $mem,$dst\t! long" %} 5769 ins_encode %{ 5770 __ ldx($mem$$Address, $dst$$Register); 5771 %} 5772 ins_pipe(iload_mem); 5773%} 5774 5775// Load Long - UNaligned 5776instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{ 5777 match(Set dst (LoadL_unaligned mem)); 5778 effect(KILL tmp); 5779 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5780 size(16); 5781 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n" 5782 "\tLDUW $mem ,$dst\n" 5783 "\tSLLX #32, $dst, $dst\n" 5784 "\tOR $dst, R_O7, $dst" %} 5785 opcode(Assembler::lduw_op3); 5786 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst )); 5787 ins_pipe(iload_mem); 5788%} 5789 5790// Load Aligned Packed Byte into a Double Register 5791instruct loadA8B(regD dst, memory mem) %{ 5792 match(Set dst (Load8B mem)); 5793 ins_cost(MEMORY_REF_COST); 5794 size(4); 5795 format %{ "LDDF $mem,$dst\t! packed8B" %} 5796 opcode(Assembler::lddf_op3); 5797 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5798 ins_pipe(floadD_mem); 5799%} 5800 5801// Load Aligned Packed Char into a Double Register 5802instruct loadA4C(regD dst, memory mem) %{ 5803 match(Set dst (Load4C mem)); 5804 ins_cost(MEMORY_REF_COST); 5805 size(4); 5806 format %{ "LDDF $mem,$dst\t! packed4C" %} 5807 opcode(Assembler::lddf_op3); 5808 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5809 ins_pipe(floadD_mem); 5810%} 5811 5812// Load Aligned Packed Short into a Double Register 5813instruct loadA4S(regD dst, memory mem) %{ 5814 match(Set dst (Load4S mem)); 5815 ins_cost(MEMORY_REF_COST); 5816 size(4); 5817 format %{ "LDDF $mem,$dst\t! packed4S" %} 5818 opcode(Assembler::lddf_op3); 5819 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5820 ins_pipe(floadD_mem); 5821%} 5822 5823// Load Aligned Packed Int into a Double Register 5824instruct loadA2I(regD dst, memory mem) %{ 5825 match(Set dst (Load2I mem)); 5826 ins_cost(MEMORY_REF_COST); 5827 size(4); 5828 format %{ "LDDF $mem,$dst\t! packed2I" %} 5829 opcode(Assembler::lddf_op3); 5830 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5831 ins_pipe(floadD_mem); 5832%} 5833 5834// Load Range 5835instruct loadRange(iRegI dst, memory mem) %{ 5836 match(Set dst (LoadRange mem)); 5837 ins_cost(MEMORY_REF_COST); 5838 5839 size(4); 5840 format %{ "LDUW $mem,$dst\t! range" %} 5841 opcode(Assembler::lduw_op3); 5842 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5843 ins_pipe(iload_mem); 5844%} 5845 5846// Load Integer into %f register (for fitos/fitod) 5847instruct loadI_freg(regF dst, memory mem) %{ 5848 match(Set dst (LoadI mem)); 5849 ins_cost(MEMORY_REF_COST); 5850 size(4); 5851 5852 format %{ "LDF $mem,$dst\t! for fitos/fitod" %} 5853 opcode(Assembler::ldf_op3); 5854 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5855 ins_pipe(floadF_mem); 5856%} 5857 5858// Load Pointer 5859instruct loadP(iRegP dst, memory mem) %{ 5860 match(Set dst (LoadP mem)); 5861 ins_cost(MEMORY_REF_COST); 5862 size(4); 5863 5864#ifndef _LP64 5865 format %{ "LDUW $mem,$dst\t! ptr" %} 5866 ins_encode %{ 5867 __ lduw($mem$$Address, $dst$$Register); 5868 %} 5869#else 5870 format %{ "LDX $mem,$dst\t! ptr" %} 5871 ins_encode %{ 5872 __ ldx($mem$$Address, $dst$$Register); 5873 %} 5874#endif 5875 ins_pipe(iload_mem); 5876%} 5877 5878// Load Compressed Pointer 5879instruct loadN(iRegN dst, memory mem) %{ 5880 match(Set dst (LoadN mem)); 5881 ins_cost(MEMORY_REF_COST); 5882 size(4); 5883 5884 format %{ "LDUW $mem,$dst\t! compressed ptr" %} 5885 ins_encode %{ 5886 __ lduw($mem$$Address, $dst$$Register); 5887 %} 5888 ins_pipe(iload_mem); 5889%} 5890 5891// Load Klass Pointer 5892instruct loadKlass(iRegP dst, memory mem) %{ 5893 match(Set dst (LoadKlass mem)); 5894 ins_cost(MEMORY_REF_COST); 5895 size(4); 5896 5897#ifndef _LP64 5898 format %{ "LDUW $mem,$dst\t! klass ptr" %} 5899 ins_encode %{ 5900 __ lduw($mem$$Address, $dst$$Register); 5901 %} 5902#else 5903 format %{ "LDX $mem,$dst\t! klass ptr" %} 5904 ins_encode %{ 5905 __ ldx($mem$$Address, $dst$$Register); 5906 %} 5907#endif 5908 ins_pipe(iload_mem); 5909%} 5910 5911// Load narrow Klass Pointer 5912instruct loadNKlass(iRegN dst, memory mem) %{ 5913 match(Set dst (LoadNKlass mem)); 5914 ins_cost(MEMORY_REF_COST); 5915 size(4); 5916 5917 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %} 5918 ins_encode %{ 5919 __ lduw($mem$$Address, $dst$$Register); 5920 %} 5921 ins_pipe(iload_mem); 5922%} 5923 5924// Load Double 5925instruct loadD(regD dst, memory mem) %{ 5926 match(Set dst (LoadD mem)); 5927 ins_cost(MEMORY_REF_COST); 5928 5929 size(4); 5930 format %{ "LDDF $mem,$dst" %} 5931 opcode(Assembler::lddf_op3); 5932 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5933 ins_pipe(floadD_mem); 5934%} 5935 5936// Load Double - UNaligned 5937instruct loadD_unaligned(regD_low dst, memory mem ) %{ 5938 match(Set dst (LoadD_unaligned mem)); 5939 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST); 5940 size(8); 5941 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n" 5942 "\tLDF $mem+4,$dst.lo\t!" %} 5943 opcode(Assembler::ldf_op3); 5944 ins_encode( form3_mem_reg_double_unaligned( mem, dst )); 5945 ins_pipe(iload_mem); 5946%} 5947 5948// Load Float 5949instruct loadF(regF dst, memory mem) %{ 5950 match(Set dst (LoadF mem)); 5951 ins_cost(MEMORY_REF_COST); 5952 5953 size(4); 5954 format %{ "LDF $mem,$dst" %} 5955 opcode(Assembler::ldf_op3); 5956 ins_encode(simple_form3_mem_reg( mem, dst ) ); 5957 ins_pipe(floadF_mem); 5958%} 5959 5960// Load Constant 5961instruct loadConI( iRegI dst, immI src ) %{ 5962 match(Set dst src); 5963 ins_cost(DEFAULT_COST * 3/2); 5964 format %{ "SET $src,$dst" %} 5965 ins_encode( Set32(src, dst) ); 5966 ins_pipe(ialu_hi_lo_reg); 5967%} 5968 5969instruct loadConI13( iRegI dst, immI13 src ) %{ 5970 match(Set dst src); 5971 5972 size(4); 5973 format %{ "MOV $src,$dst" %} 5974 ins_encode( Set13( src, dst ) ); 5975 ins_pipe(ialu_imm); 5976%} 5977 5978instruct loadConP(iRegP dst, immP src) %{ 5979 match(Set dst src); 5980 ins_cost(DEFAULT_COST * 3/2); 5981 format %{ "SET $src,$dst\t!ptr" %} 5982 // This rule does not use "expand" unlike loadConI because then 5983 // the result type is not known to be an Oop. An ADLC 5984 // enhancement will be needed to make that work - not worth it! 5985 5986 ins_encode( SetPtr( src, dst ) ); 5987 ins_pipe(loadConP); 5988 5989%} 5990 5991instruct loadConP0(iRegP dst, immP0 src) %{ 5992 match(Set dst src); 5993 5994 size(4); 5995 format %{ "CLR $dst\t!ptr" %} 5996 ins_encode( SetNull( dst ) ); 5997 ins_pipe(ialu_imm); 5998%} 5999 6000instruct loadConP_poll(iRegP dst, immP_poll src) %{ 6001 match(Set dst src); 6002 ins_cost(DEFAULT_COST); 6003 format %{ "SET $src,$dst\t!ptr" %} 6004 ins_encode %{ 6005 AddressLiteral polling_page(os::get_polling_page()); 6006 __ sethi(polling_page, reg_to_register_object($dst$$reg)); 6007 %} 6008 ins_pipe(loadConP_poll); 6009%} 6010 6011instruct loadConN0(iRegN dst, immN0 src) %{ 6012 match(Set dst src); 6013 6014 size(4); 6015 format %{ "CLR $dst\t! compressed NULL ptr" %} 6016 ins_encode( SetNull( dst ) ); 6017 ins_pipe(ialu_imm); 6018%} 6019 6020instruct loadConN(iRegN dst, immN src) %{ 6021 match(Set dst src); 6022 ins_cost(DEFAULT_COST * 3/2); 6023 format %{ "SET $src,$dst\t! compressed ptr" %} 6024 ins_encode %{ 6025 Register dst = $dst$$Register; 6026 __ set_narrow_oop((jobject)$src$$constant, dst); 6027 %} 6028 ins_pipe(ialu_hi_lo_reg); 6029%} 6030 6031instruct loadConL(iRegL dst, immL src, o7RegL tmp) %{ 6032 // %%% maybe this should work like loadConD 6033 match(Set dst src); 6034 effect(KILL tmp); 6035 ins_cost(DEFAULT_COST * 4); 6036 format %{ "SET64 $src,$dst KILL $tmp\t! long" %} 6037 ins_encode( LdImmL(src, dst, tmp) ); 6038 ins_pipe(loadConL); 6039%} 6040 6041instruct loadConL0( iRegL dst, immL0 src ) %{ 6042 match(Set dst src); 6043 ins_cost(DEFAULT_COST); 6044 size(4); 6045 format %{ "CLR $dst\t! long" %} 6046 ins_encode( Set13( src, dst ) ); 6047 ins_pipe(ialu_imm); 6048%} 6049 6050instruct loadConL13( iRegL dst, immL13 src ) %{ 6051 match(Set dst src); 6052 ins_cost(DEFAULT_COST * 2); 6053 6054 size(4); 6055 format %{ "MOV $src,$dst\t! long" %} 6056 ins_encode( Set13( src, dst ) ); 6057 ins_pipe(ialu_imm); 6058%} 6059 6060instruct loadConF(regF dst, immF src, o7RegP tmp) %{ 6061 match(Set dst src); 6062 effect(KILL tmp); 6063 6064#ifdef _LP64 6065 size(8*4); 6066#else 6067 size(2*4); 6068#endif 6069 6070 format %{ "SETHI hi(&$src),$tmp\t!get float $src from table\n\t" 6071 "LDF [$tmp+lo(&$src)],$dst" %} 6072 ins_encode %{ 6073 address float_address = __ float_constant($src$$constant); 6074 RelocationHolder rspec = internal_word_Relocation::spec(float_address); 6075 AddressLiteral addrlit(float_address, rspec); 6076 6077 __ sethi(addrlit, $tmp$$Register); 6078 __ ldf(FloatRegisterImpl::S, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6079 %} 6080 ins_pipe(loadConFD); 6081%} 6082 6083instruct loadConD(regD dst, immD src, o7RegP tmp) %{ 6084 match(Set dst src); 6085 effect(KILL tmp); 6086 6087#ifdef _LP64 6088 size(8*4); 6089#else 6090 size(2*4); 6091#endif 6092 6093 format %{ "SETHI hi(&$src),$tmp\t!get double $src from table\n\t" 6094 "LDDF [$tmp+lo(&$src)],$dst" %} 6095 ins_encode %{ 6096 address double_address = __ double_constant($src$$constant); 6097 RelocationHolder rspec = internal_word_Relocation::spec(double_address); 6098 AddressLiteral addrlit(double_address, rspec); 6099 6100 __ sethi(addrlit, $tmp$$Register); 6101 // XXX This is a quick fix for 6833573. 6102 //__ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), $dst$$FloatRegister, rspec); 6103 __ ldf(FloatRegisterImpl::D, $tmp$$Register, addrlit.low10(), as_DoubleFloatRegister($dst$$reg), rspec); 6104 %} 6105 ins_pipe(loadConFD); 6106%} 6107 6108// Prefetch instructions. 6109// Must be safe to execute with invalid address (cannot fault). 6110 6111instruct prefetchr( memory mem ) %{ 6112 match( PrefetchRead mem ); 6113 ins_cost(MEMORY_REF_COST); 6114 6115 format %{ "PREFETCH $mem,0\t! Prefetch read-many" %} 6116 opcode(Assembler::prefetch_op3); 6117 ins_encode( form3_mem_prefetch_read( mem ) ); 6118 ins_pipe(iload_mem); 6119%} 6120 6121instruct prefetchw( memory mem ) %{ 6122 predicate(AllocatePrefetchStyle != 3 ); 6123 match( PrefetchWrite mem ); 6124 ins_cost(MEMORY_REF_COST); 6125 6126 format %{ "PREFETCH $mem,2\t! Prefetch write-many (and read)" %} 6127 opcode(Assembler::prefetch_op3); 6128 ins_encode( form3_mem_prefetch_write( mem ) ); 6129 ins_pipe(iload_mem); 6130%} 6131 6132// Use BIS instruction to prefetch. 6133instruct prefetchw_bis( memory mem ) %{ 6134 predicate(AllocatePrefetchStyle == 3); 6135 match( PrefetchWrite mem ); 6136 ins_cost(MEMORY_REF_COST); 6137 6138 format %{ "STXA G0,$mem\t! // Block initializing store" %} 6139 ins_encode %{ 6140 Register base = as_Register($mem$$base); 6141 int disp = $mem$$disp; 6142 if (disp != 0) { 6143 __ add(base, AllocatePrefetchStepSize, base); 6144 } 6145 __ stxa(G0, base, G0, ASI_BLK_INIT_QUAD_LDD_P); 6146 %} 6147 ins_pipe(istore_mem_reg); 6148%} 6149 6150//----------Store Instructions------------------------------------------------- 6151// Store Byte 6152instruct storeB(memory mem, iRegI src) %{ 6153 match(Set mem (StoreB mem src)); 6154 ins_cost(MEMORY_REF_COST); 6155 6156 size(4); 6157 format %{ "STB $src,$mem\t! byte" %} 6158 opcode(Assembler::stb_op3); 6159 ins_encode(simple_form3_mem_reg( mem, src ) ); 6160 ins_pipe(istore_mem_reg); 6161%} 6162 6163instruct storeB0(memory mem, immI0 src) %{ 6164 match(Set mem (StoreB mem src)); 6165 ins_cost(MEMORY_REF_COST); 6166 6167 size(4); 6168 format %{ "STB $src,$mem\t! byte" %} 6169 opcode(Assembler::stb_op3); 6170 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6171 ins_pipe(istore_mem_zero); 6172%} 6173 6174instruct storeCM0(memory mem, immI0 src) %{ 6175 match(Set mem (StoreCM mem src)); 6176 ins_cost(MEMORY_REF_COST); 6177 6178 size(4); 6179 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %} 6180 opcode(Assembler::stb_op3); 6181 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6182 ins_pipe(istore_mem_zero); 6183%} 6184 6185// Store Char/Short 6186instruct storeC(memory mem, iRegI src) %{ 6187 match(Set mem (StoreC mem src)); 6188 ins_cost(MEMORY_REF_COST); 6189 6190 size(4); 6191 format %{ "STH $src,$mem\t! short" %} 6192 opcode(Assembler::sth_op3); 6193 ins_encode(simple_form3_mem_reg( mem, src ) ); 6194 ins_pipe(istore_mem_reg); 6195%} 6196 6197instruct storeC0(memory mem, immI0 src) %{ 6198 match(Set mem (StoreC mem src)); 6199 ins_cost(MEMORY_REF_COST); 6200 6201 size(4); 6202 format %{ "STH $src,$mem\t! short" %} 6203 opcode(Assembler::sth_op3); 6204 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6205 ins_pipe(istore_mem_zero); 6206%} 6207 6208// Store Integer 6209instruct storeI(memory mem, iRegI src) %{ 6210 match(Set mem (StoreI mem src)); 6211 ins_cost(MEMORY_REF_COST); 6212 6213 size(4); 6214 format %{ "STW $src,$mem" %} 6215 opcode(Assembler::stw_op3); 6216 ins_encode(simple_form3_mem_reg( mem, src ) ); 6217 ins_pipe(istore_mem_reg); 6218%} 6219 6220// Store Long 6221instruct storeL(memory mem, iRegL src) %{ 6222 match(Set mem (StoreL mem src)); 6223 ins_cost(MEMORY_REF_COST); 6224 size(4); 6225 format %{ "STX $src,$mem\t! long" %} 6226 opcode(Assembler::stx_op3); 6227 ins_encode(simple_form3_mem_reg( mem, src ) ); 6228 ins_pipe(istore_mem_reg); 6229%} 6230 6231instruct storeI0(memory mem, immI0 src) %{ 6232 match(Set mem (StoreI mem src)); 6233 ins_cost(MEMORY_REF_COST); 6234 6235 size(4); 6236 format %{ "STW $src,$mem" %} 6237 opcode(Assembler::stw_op3); 6238 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6239 ins_pipe(istore_mem_zero); 6240%} 6241 6242instruct storeL0(memory mem, immL0 src) %{ 6243 match(Set mem (StoreL mem src)); 6244 ins_cost(MEMORY_REF_COST); 6245 6246 size(4); 6247 format %{ "STX $src,$mem" %} 6248 opcode(Assembler::stx_op3); 6249 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6250 ins_pipe(istore_mem_zero); 6251%} 6252 6253// Store Integer from float register (used after fstoi) 6254instruct storeI_Freg(memory mem, regF src) %{ 6255 match(Set mem (StoreI mem src)); 6256 ins_cost(MEMORY_REF_COST); 6257 6258 size(4); 6259 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %} 6260 opcode(Assembler::stf_op3); 6261 ins_encode(simple_form3_mem_reg( mem, src ) ); 6262 ins_pipe(fstoreF_mem_reg); 6263%} 6264 6265// Store Pointer 6266instruct storeP(memory dst, sp_ptr_RegP src) %{ 6267 match(Set dst (StoreP dst src)); 6268 ins_cost(MEMORY_REF_COST); 6269 size(4); 6270 6271#ifndef _LP64 6272 format %{ "STW $src,$dst\t! ptr" %} 6273 opcode(Assembler::stw_op3, 0, REGP_OP); 6274#else 6275 format %{ "STX $src,$dst\t! ptr" %} 6276 opcode(Assembler::stx_op3, 0, REGP_OP); 6277#endif 6278 ins_encode( form3_mem_reg( dst, src ) ); 6279 ins_pipe(istore_mem_spORreg); 6280%} 6281 6282instruct storeP0(memory dst, immP0 src) %{ 6283 match(Set dst (StoreP dst src)); 6284 ins_cost(MEMORY_REF_COST); 6285 size(4); 6286 6287#ifndef _LP64 6288 format %{ "STW $src,$dst\t! ptr" %} 6289 opcode(Assembler::stw_op3, 0, REGP_OP); 6290#else 6291 format %{ "STX $src,$dst\t! ptr" %} 6292 opcode(Assembler::stx_op3, 0, REGP_OP); 6293#endif 6294 ins_encode( form3_mem_reg( dst, R_G0 ) ); 6295 ins_pipe(istore_mem_zero); 6296%} 6297 6298// Store Compressed Pointer 6299instruct storeN(memory dst, iRegN src) %{ 6300 match(Set dst (StoreN dst src)); 6301 ins_cost(MEMORY_REF_COST); 6302 size(4); 6303 6304 format %{ "STW $src,$dst\t! compressed ptr" %} 6305 ins_encode %{ 6306 Register base = as_Register($dst$$base); 6307 Register index = as_Register($dst$$index); 6308 Register src = $src$$Register; 6309 if (index != G0) { 6310 __ stw(src, base, index); 6311 } else { 6312 __ stw(src, base, $dst$$disp); 6313 } 6314 %} 6315 ins_pipe(istore_mem_spORreg); 6316%} 6317 6318instruct storeN0(memory dst, immN0 src) %{ 6319 match(Set dst (StoreN dst src)); 6320 ins_cost(MEMORY_REF_COST); 6321 size(4); 6322 6323 format %{ "STW $src,$dst\t! compressed ptr" %} 6324 ins_encode %{ 6325 Register base = as_Register($dst$$base); 6326 Register index = as_Register($dst$$index); 6327 if (index != G0) { 6328 __ stw(0, base, index); 6329 } else { 6330 __ stw(0, base, $dst$$disp); 6331 } 6332 %} 6333 ins_pipe(istore_mem_zero); 6334%} 6335 6336// Store Double 6337instruct storeD( memory mem, regD src) %{ 6338 match(Set mem (StoreD mem src)); 6339 ins_cost(MEMORY_REF_COST); 6340 6341 size(4); 6342 format %{ "STDF $src,$mem" %} 6343 opcode(Assembler::stdf_op3); 6344 ins_encode(simple_form3_mem_reg( mem, src ) ); 6345 ins_pipe(fstoreD_mem_reg); 6346%} 6347 6348instruct storeD0( memory mem, immD0 src) %{ 6349 match(Set mem (StoreD mem src)); 6350 ins_cost(MEMORY_REF_COST); 6351 6352 size(4); 6353 format %{ "STX $src,$mem" %} 6354 opcode(Assembler::stx_op3); 6355 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6356 ins_pipe(fstoreD_mem_zero); 6357%} 6358 6359// Store Float 6360instruct storeF( memory mem, regF src) %{ 6361 match(Set mem (StoreF mem src)); 6362 ins_cost(MEMORY_REF_COST); 6363 6364 size(4); 6365 format %{ "STF $src,$mem" %} 6366 opcode(Assembler::stf_op3); 6367 ins_encode(simple_form3_mem_reg( mem, src ) ); 6368 ins_pipe(fstoreF_mem_reg); 6369%} 6370 6371instruct storeF0( memory mem, immF0 src) %{ 6372 match(Set mem (StoreF mem src)); 6373 ins_cost(MEMORY_REF_COST); 6374 6375 size(4); 6376 format %{ "STW $src,$mem\t! storeF0" %} 6377 opcode(Assembler::stw_op3); 6378 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6379 ins_pipe(fstoreF_mem_zero); 6380%} 6381 6382// Store Aligned Packed Bytes in Double register to memory 6383instruct storeA8B(memory mem, regD src) %{ 6384 match(Set mem (Store8B mem src)); 6385 ins_cost(MEMORY_REF_COST); 6386 size(4); 6387 format %{ "STDF $src,$mem\t! packed8B" %} 6388 opcode(Assembler::stdf_op3); 6389 ins_encode(simple_form3_mem_reg( mem, src ) ); 6390 ins_pipe(fstoreD_mem_reg); 6391%} 6392 6393// Convert oop pointer into compressed form 6394instruct encodeHeapOop(iRegN dst, iRegP src) %{ 6395 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull); 6396 match(Set dst (EncodeP src)); 6397 format %{ "encode_heap_oop $src, $dst" %} 6398 ins_encode %{ 6399 __ encode_heap_oop($src$$Register, $dst$$Register); 6400 %} 6401 ins_pipe(ialu_reg); 6402%} 6403 6404instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{ 6405 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull); 6406 match(Set dst (EncodeP src)); 6407 format %{ "encode_heap_oop_not_null $src, $dst" %} 6408 ins_encode %{ 6409 __ encode_heap_oop_not_null($src$$Register, $dst$$Register); 6410 %} 6411 ins_pipe(ialu_reg); 6412%} 6413 6414instruct decodeHeapOop(iRegP dst, iRegN src) %{ 6415 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6416 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant); 6417 match(Set dst (DecodeN src)); 6418 format %{ "decode_heap_oop $src, $dst" %} 6419 ins_encode %{ 6420 __ decode_heap_oop($src$$Register, $dst$$Register); 6421 %} 6422 ins_pipe(ialu_reg); 6423%} 6424 6425instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{ 6426 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6427 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant); 6428 match(Set dst (DecodeN src)); 6429 format %{ "decode_heap_oop_not_null $src, $dst" %} 6430 ins_encode %{ 6431 __ decode_heap_oop_not_null($src$$Register, $dst$$Register); 6432 %} 6433 ins_pipe(ialu_reg); 6434%} 6435 6436 6437// Store Zero into Aligned Packed Bytes 6438instruct storeA8B0(memory mem, immI0 zero) %{ 6439 match(Set mem (Store8B mem zero)); 6440 ins_cost(MEMORY_REF_COST); 6441 size(4); 6442 format %{ "STX $zero,$mem\t! packed8B" %} 6443 opcode(Assembler::stx_op3); 6444 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6445 ins_pipe(fstoreD_mem_zero); 6446%} 6447 6448// Store Aligned Packed Chars/Shorts in Double register to memory 6449instruct storeA4C(memory mem, regD src) %{ 6450 match(Set mem (Store4C mem src)); 6451 ins_cost(MEMORY_REF_COST); 6452 size(4); 6453 format %{ "STDF $src,$mem\t! packed4C" %} 6454 opcode(Assembler::stdf_op3); 6455 ins_encode(simple_form3_mem_reg( mem, src ) ); 6456 ins_pipe(fstoreD_mem_reg); 6457%} 6458 6459// Store Zero into Aligned Packed Chars/Shorts 6460instruct storeA4C0(memory mem, immI0 zero) %{ 6461 match(Set mem (Store4C mem (Replicate4C zero))); 6462 ins_cost(MEMORY_REF_COST); 6463 size(4); 6464 format %{ "STX $zero,$mem\t! packed4C" %} 6465 opcode(Assembler::stx_op3); 6466 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6467 ins_pipe(fstoreD_mem_zero); 6468%} 6469 6470// Store Aligned Packed Ints in Double register to memory 6471instruct storeA2I(memory mem, regD src) %{ 6472 match(Set mem (Store2I mem src)); 6473 ins_cost(MEMORY_REF_COST); 6474 size(4); 6475 format %{ "STDF $src,$mem\t! packed2I" %} 6476 opcode(Assembler::stdf_op3); 6477 ins_encode(simple_form3_mem_reg( mem, src ) ); 6478 ins_pipe(fstoreD_mem_reg); 6479%} 6480 6481// Store Zero into Aligned Packed Ints 6482instruct storeA2I0(memory mem, immI0 zero) %{ 6483 match(Set mem (Store2I mem zero)); 6484 ins_cost(MEMORY_REF_COST); 6485 size(4); 6486 format %{ "STX $zero,$mem\t! packed2I" %} 6487 opcode(Assembler::stx_op3); 6488 ins_encode(simple_form3_mem_reg( mem, R_G0 ) ); 6489 ins_pipe(fstoreD_mem_zero); 6490%} 6491 6492 6493//----------MemBar Instructions----------------------------------------------- 6494// Memory barrier flavors 6495 6496instruct membar_acquire() %{ 6497 match(MemBarAcquire); 6498 ins_cost(4*MEMORY_REF_COST); 6499 6500 size(0); 6501 format %{ "MEMBAR-acquire" %} 6502 ins_encode( enc_membar_acquire ); 6503 ins_pipe(long_memory_op); 6504%} 6505 6506instruct membar_acquire_lock() %{ 6507 match(MemBarAcquire); 6508 predicate(Matcher::prior_fast_lock(n)); 6509 ins_cost(0); 6510 6511 size(0); 6512 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %} 6513 ins_encode( ); 6514 ins_pipe(empty); 6515%} 6516 6517instruct membar_release() %{ 6518 match(MemBarRelease); 6519 ins_cost(4*MEMORY_REF_COST); 6520 6521 size(0); 6522 format %{ "MEMBAR-release" %} 6523 ins_encode( enc_membar_release ); 6524 ins_pipe(long_memory_op); 6525%} 6526 6527instruct membar_release_lock() %{ 6528 match(MemBarRelease); 6529 predicate(Matcher::post_fast_unlock(n)); 6530 ins_cost(0); 6531 6532 size(0); 6533 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %} 6534 ins_encode( ); 6535 ins_pipe(empty); 6536%} 6537 6538instruct membar_volatile() %{ 6539 match(MemBarVolatile); 6540 ins_cost(4*MEMORY_REF_COST); 6541 6542 size(4); 6543 format %{ "MEMBAR-volatile" %} 6544 ins_encode( enc_membar_volatile ); 6545 ins_pipe(long_memory_op); 6546%} 6547 6548instruct unnecessary_membar_volatile() %{ 6549 match(MemBarVolatile); 6550 predicate(Matcher::post_store_load_barrier(n)); 6551 ins_cost(0); 6552 6553 size(0); 6554 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %} 6555 ins_encode( ); 6556 ins_pipe(empty); 6557%} 6558 6559//----------Register Move Instructions----------------------------------------- 6560instruct roundDouble_nop(regD dst) %{ 6561 match(Set dst (RoundDouble dst)); 6562 ins_cost(0); 6563 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6564 ins_encode( ); 6565 ins_pipe(empty); 6566%} 6567 6568 6569instruct roundFloat_nop(regF dst) %{ 6570 match(Set dst (RoundFloat dst)); 6571 ins_cost(0); 6572 // SPARC results are already "rounded" (i.e., normal-format IEEE) 6573 ins_encode( ); 6574 ins_pipe(empty); 6575%} 6576 6577 6578// Cast Index to Pointer for unsafe natives 6579instruct castX2P(iRegX src, iRegP dst) %{ 6580 match(Set dst (CastX2P src)); 6581 6582 format %{ "MOV $src,$dst\t! IntX->Ptr" %} 6583 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6584 ins_pipe(ialu_reg); 6585%} 6586 6587// Cast Pointer to Index for unsafe natives 6588instruct castP2X(iRegP src, iRegX dst) %{ 6589 match(Set dst (CastP2X src)); 6590 6591 format %{ "MOV $src,$dst\t! Ptr->IntX" %} 6592 ins_encode( form3_g0_rs2_rd_move( src, dst ) ); 6593 ins_pipe(ialu_reg); 6594%} 6595 6596instruct stfSSD(stackSlotD stkSlot, regD src) %{ 6597 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6598 match(Set stkSlot src); // chain rule 6599 ins_cost(MEMORY_REF_COST); 6600 format %{ "STDF $src,$stkSlot\t!stk" %} 6601 opcode(Assembler::stdf_op3); 6602 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6603 ins_pipe(fstoreD_stk_reg); 6604%} 6605 6606instruct ldfSSD(regD dst, stackSlotD stkSlot) %{ 6607 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6608 match(Set dst stkSlot); // chain rule 6609 ins_cost(MEMORY_REF_COST); 6610 format %{ "LDDF $stkSlot,$dst\t!stk" %} 6611 opcode(Assembler::lddf_op3); 6612 ins_encode(simple_form3_mem_reg(stkSlot, dst)); 6613 ins_pipe(floadD_stk); 6614%} 6615 6616instruct stfSSF(stackSlotF stkSlot, regF src) %{ 6617 // %%%% TO DO: Tell the coalescer that this kind of node is a copy! 6618 match(Set stkSlot src); // chain rule 6619 ins_cost(MEMORY_REF_COST); 6620 format %{ "STF $src,$stkSlot\t!stk" %} 6621 opcode(Assembler::stf_op3); 6622 ins_encode(simple_form3_mem_reg(stkSlot, src)); 6623 ins_pipe(fstoreF_stk_reg); 6624%} 6625 6626//----------Conditional Move--------------------------------------------------- 6627// Conditional move 6628instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{ 6629 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6630 ins_cost(150); 6631 format %{ "MOV$cmp $pcc,$src,$dst" %} 6632 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6633 ins_pipe(ialu_reg); 6634%} 6635 6636instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{ 6637 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src))); 6638 ins_cost(140); 6639 format %{ "MOV$cmp $pcc,$src,$dst" %} 6640 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6641 ins_pipe(ialu_imm); 6642%} 6643 6644instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{ 6645 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6646 ins_cost(150); 6647 size(4); 6648 format %{ "MOV$cmp $icc,$src,$dst" %} 6649 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6650 ins_pipe(ialu_reg); 6651%} 6652 6653instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{ 6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6655 ins_cost(140); 6656 size(4); 6657 format %{ "MOV$cmp $icc,$src,$dst" %} 6658 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6659 ins_pipe(ialu_imm); 6660%} 6661 6662instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{ 6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6664 ins_cost(150); 6665 size(4); 6666 format %{ "MOV$cmp $icc,$src,$dst" %} 6667 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6668 ins_pipe(ialu_reg); 6669%} 6670 6671instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{ 6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src))); 6673 ins_cost(140); 6674 size(4); 6675 format %{ "MOV$cmp $icc,$src,$dst" %} 6676 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6677 ins_pipe(ialu_imm); 6678%} 6679 6680instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{ 6681 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6682 ins_cost(150); 6683 size(4); 6684 format %{ "MOV$cmp $fcc,$src,$dst" %} 6685 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6686 ins_pipe(ialu_reg); 6687%} 6688 6689instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{ 6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src))); 6691 ins_cost(140); 6692 size(4); 6693 format %{ "MOV$cmp $fcc,$src,$dst" %} 6694 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6695 ins_pipe(ialu_imm); 6696%} 6697 6698// Conditional move for RegN. Only cmov(reg,reg). 6699instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{ 6700 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src))); 6701 ins_cost(150); 6702 format %{ "MOV$cmp $pcc,$src,$dst" %} 6703 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6704 ins_pipe(ialu_reg); 6705%} 6706 6707// This instruction also works with CmpN so we don't need cmovNN_reg. 6708instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{ 6709 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6710 ins_cost(150); 6711 size(4); 6712 format %{ "MOV$cmp $icc,$src,$dst" %} 6713 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6714 ins_pipe(ialu_reg); 6715%} 6716 6717// This instruction also works with CmpN so we don't need cmovNN_reg. 6718instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{ 6719 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src))); 6720 ins_cost(150); 6721 size(4); 6722 format %{ "MOV$cmp $icc,$src,$dst" %} 6723 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6724 ins_pipe(ialu_reg); 6725%} 6726 6727instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{ 6728 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src))); 6729 ins_cost(150); 6730 size(4); 6731 format %{ "MOV$cmp $fcc,$src,$dst" %} 6732 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6733 ins_pipe(ialu_reg); 6734%} 6735 6736// Conditional move 6737instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{ 6738 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6739 ins_cost(150); 6740 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6741 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6742 ins_pipe(ialu_reg); 6743%} 6744 6745instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{ 6746 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src))); 6747 ins_cost(140); 6748 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %} 6749 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6750 ins_pipe(ialu_imm); 6751%} 6752 6753// This instruction also works with CmpN so we don't need cmovPN_reg. 6754instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{ 6755 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6756 ins_cost(150); 6757 6758 size(4); 6759 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6760 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6761 ins_pipe(ialu_reg); 6762%} 6763 6764instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{ 6765 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6766 ins_cost(150); 6767 6768 size(4); 6769 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6770 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6771 ins_pipe(ialu_reg); 6772%} 6773 6774instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{ 6775 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6776 ins_cost(140); 6777 6778 size(4); 6779 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6780 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6781 ins_pipe(ialu_imm); 6782%} 6783 6784instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{ 6785 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src))); 6786 ins_cost(140); 6787 6788 size(4); 6789 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %} 6790 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) ); 6791 ins_pipe(ialu_imm); 6792%} 6793 6794instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{ 6795 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6796 ins_cost(150); 6797 size(4); 6798 format %{ "MOV$cmp $fcc,$src,$dst" %} 6799 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6800 ins_pipe(ialu_imm); 6801%} 6802 6803instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{ 6804 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src))); 6805 ins_cost(140); 6806 size(4); 6807 format %{ "MOV$cmp $fcc,$src,$dst" %} 6808 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) ); 6809 ins_pipe(ialu_imm); 6810%} 6811 6812// Conditional move 6813instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{ 6814 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src))); 6815 ins_cost(150); 6816 opcode(0x101); 6817 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6818 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6819 ins_pipe(int_conditional_float_move); 6820%} 6821 6822instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{ 6823 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6824 ins_cost(150); 6825 6826 size(4); 6827 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6828 opcode(0x101); 6829 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6830 ins_pipe(int_conditional_float_move); 6831%} 6832 6833instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{ 6834 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src))); 6835 ins_cost(150); 6836 6837 size(4); 6838 format %{ "FMOVS$cmp $icc,$src,$dst" %} 6839 opcode(0x101); 6840 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6841 ins_pipe(int_conditional_float_move); 6842%} 6843 6844// Conditional move, 6845instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{ 6846 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src))); 6847 ins_cost(150); 6848 size(4); 6849 format %{ "FMOVF$cmp $fcc,$src,$dst" %} 6850 opcode(0x1); 6851 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6852 ins_pipe(int_conditional_double_move); 6853%} 6854 6855// Conditional move 6856instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{ 6857 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src))); 6858 ins_cost(150); 6859 size(4); 6860 opcode(0x102); 6861 format %{ "FMOVD$cmp $pcc,$src,$dst" %} 6862 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6863 ins_pipe(int_conditional_double_move); 6864%} 6865 6866instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{ 6867 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6868 ins_cost(150); 6869 6870 size(4); 6871 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6872 opcode(0x102); 6873 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6874 ins_pipe(int_conditional_double_move); 6875%} 6876 6877instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{ 6878 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src))); 6879 ins_cost(150); 6880 6881 size(4); 6882 format %{ "FMOVD$cmp $icc,$src,$dst" %} 6883 opcode(0x102); 6884 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) ); 6885 ins_pipe(int_conditional_double_move); 6886%} 6887 6888// Conditional move, 6889instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{ 6890 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src))); 6891 ins_cost(150); 6892 size(4); 6893 format %{ "FMOVD$cmp $fcc,$src,$dst" %} 6894 opcode(0x2); 6895 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) ); 6896 ins_pipe(int_conditional_double_move); 6897%} 6898 6899// Conditional move 6900instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{ 6901 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6902 ins_cost(150); 6903 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6904 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) ); 6905 ins_pipe(ialu_reg); 6906%} 6907 6908instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{ 6909 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src))); 6910 ins_cost(140); 6911 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %} 6912 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) ); 6913 ins_pipe(ialu_imm); 6914%} 6915 6916instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{ 6917 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6918 ins_cost(150); 6919 6920 size(4); 6921 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6923 ins_pipe(ialu_reg); 6924%} 6925 6926 6927instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{ 6928 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src))); 6929 ins_cost(150); 6930 6931 size(4); 6932 format %{ "MOV$cmp $icc,$src,$dst\t! long" %} 6933 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) ); 6934 ins_pipe(ialu_reg); 6935%} 6936 6937 6938instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{ 6939 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src))); 6940 ins_cost(150); 6941 6942 size(4); 6943 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %} 6944 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) ); 6945 ins_pipe(ialu_reg); 6946%} 6947 6948 6949 6950//----------OS and Locking Instructions---------------------------------------- 6951 6952// This name is KNOWN by the ADLC and cannot be changed. 6953// The ADLC forces a 'TypeRawPtr::BOTTOM' output type 6954// for this guy. 6955instruct tlsLoadP(g2RegP dst) %{ 6956 match(Set dst (ThreadLocal)); 6957 6958 size(0); 6959 ins_cost(0); 6960 format %{ "# TLS is in G2" %} 6961 ins_encode( /*empty encoding*/ ); 6962 ins_pipe(ialu_none); 6963%} 6964 6965instruct checkCastPP( iRegP dst ) %{ 6966 match(Set dst (CheckCastPP dst)); 6967 6968 size(0); 6969 format %{ "# checkcastPP of $dst" %} 6970 ins_encode( /*empty encoding*/ ); 6971 ins_pipe(empty); 6972%} 6973 6974 6975instruct castPP( iRegP dst ) %{ 6976 match(Set dst (CastPP dst)); 6977 format %{ "# castPP of $dst" %} 6978 ins_encode( /*empty encoding*/ ); 6979 ins_pipe(empty); 6980%} 6981 6982instruct castII( iRegI dst ) %{ 6983 match(Set dst (CastII dst)); 6984 format %{ "# castII of $dst" %} 6985 ins_encode( /*empty encoding*/ ); 6986 ins_cost(0); 6987 ins_pipe(empty); 6988%} 6989 6990//----------Arithmetic Instructions-------------------------------------------- 6991// Addition Instructions 6992// Register Addition 6993instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 6994 match(Set dst (AddI src1 src2)); 6995 6996 size(4); 6997 format %{ "ADD $src1,$src2,$dst" %} 6998 ins_encode %{ 6999 __ add($src1$$Register, $src2$$Register, $dst$$Register); 7000 %} 7001 ins_pipe(ialu_reg_reg); 7002%} 7003 7004// Immediate Addition 7005instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7006 match(Set dst (AddI src1 src2)); 7007 7008 size(4); 7009 format %{ "ADD $src1,$src2,$dst" %} 7010 opcode(Assembler::add_op3, Assembler::arith_op); 7011 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7012 ins_pipe(ialu_reg_imm); 7013%} 7014 7015// Pointer Register Addition 7016instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{ 7017 match(Set dst (AddP src1 src2)); 7018 7019 size(4); 7020 format %{ "ADD $src1,$src2,$dst" %} 7021 opcode(Assembler::add_op3, Assembler::arith_op); 7022 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7023 ins_pipe(ialu_reg_reg); 7024%} 7025 7026// Pointer Immediate Addition 7027instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{ 7028 match(Set dst (AddP src1 src2)); 7029 7030 size(4); 7031 format %{ "ADD $src1,$src2,$dst" %} 7032 opcode(Assembler::add_op3, Assembler::arith_op); 7033 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7034 ins_pipe(ialu_reg_imm); 7035%} 7036 7037// Long Addition 7038instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7039 match(Set dst (AddL src1 src2)); 7040 7041 size(4); 7042 format %{ "ADD $src1,$src2,$dst\t! long" %} 7043 opcode(Assembler::add_op3, Assembler::arith_op); 7044 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7045 ins_pipe(ialu_reg_reg); 7046%} 7047 7048instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7049 match(Set dst (AddL src1 con)); 7050 7051 size(4); 7052 format %{ "ADD $src1,$con,$dst" %} 7053 opcode(Assembler::add_op3, Assembler::arith_op); 7054 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7055 ins_pipe(ialu_reg_imm); 7056%} 7057 7058//----------Conditional_store-------------------------------------------------- 7059// Conditional-store of the updated heap-top. 7060// Used during allocation of the shared heap. 7061// Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7062 7063// LoadP-locked. Same as a regular pointer load when used with a compare-swap 7064instruct loadPLocked(iRegP dst, memory mem) %{ 7065 match(Set dst (LoadPLocked mem)); 7066 ins_cost(MEMORY_REF_COST); 7067 7068#ifndef _LP64 7069 size(4); 7070 format %{ "LDUW $mem,$dst\t! ptr" %} 7071 opcode(Assembler::lduw_op3, 0, REGP_OP); 7072#else 7073 format %{ "LDX $mem,$dst\t! ptr" %} 7074 opcode(Assembler::ldx_op3, 0, REGP_OP); 7075#endif 7076 ins_encode( form3_mem_reg( mem, dst ) ); 7077 ins_pipe(iload_mem); 7078%} 7079 7080// LoadL-locked. Same as a regular long load when used with a compare-swap 7081instruct loadLLocked(iRegL dst, memory mem) %{ 7082 match(Set dst (LoadLLocked mem)); 7083 ins_cost(MEMORY_REF_COST); 7084 size(4); 7085 format %{ "LDX $mem,$dst\t! long" %} 7086 opcode(Assembler::ldx_op3); 7087 ins_encode(simple_form3_mem_reg( mem, dst ) ); 7088 ins_pipe(iload_mem); 7089%} 7090 7091instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{ 7092 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval))); 7093 effect( KILL newval ); 7094 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t" 7095 "CMP R_G3,$oldval\t\t! See if we made progress" %} 7096 ins_encode( enc_cas(heap_top_ptr,oldval,newval) ); 7097 ins_pipe( long_memory_op ); 7098%} 7099 7100// Conditional-store of an int value. 7101instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{ 7102 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval))); 7103 effect( KILL newval ); 7104 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7105 "CMP $oldval,$newval\t\t! See if we made progress" %} 7106 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7107 ins_pipe( long_memory_op ); 7108%} 7109 7110// Conditional-store of a long value. 7111instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{ 7112 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval))); 7113 effect( KILL newval ); 7114 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t" 7115 "CMP $oldval,$newval\t\t! See if we made progress" %} 7116 ins_encode( enc_cas(mem_ptr,oldval,newval) ); 7117 ins_pipe( long_memory_op ); 7118%} 7119 7120// No flag versions for CompareAndSwap{P,I,L} because matcher can't match them 7121 7122instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7123 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval))); 7124 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7125 format %{ 7126 "MOV $newval,O7\n\t" 7127 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7128 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7129 "MOV 1,$res\n\t" 7130 "MOVne xcc,R_G0,$res" 7131 %} 7132 ins_encode( enc_casx(mem_ptr, oldval, newval), 7133 enc_lflags_ne_to_boolean(res) ); 7134 ins_pipe( long_memory_op ); 7135%} 7136 7137 7138instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7139 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval))); 7140 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7141 format %{ 7142 "MOV $newval,O7\n\t" 7143 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7144 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7145 "MOV 1,$res\n\t" 7146 "MOVne icc,R_G0,$res" 7147 %} 7148 ins_encode( enc_casi(mem_ptr, oldval, newval), 7149 enc_iflags_ne_to_boolean(res) ); 7150 ins_pipe( long_memory_op ); 7151%} 7152 7153instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7154 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval))); 7155 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7156 format %{ 7157 "MOV $newval,O7\n\t" 7158 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7159 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7160 "MOV 1,$res\n\t" 7161 "MOVne xcc,R_G0,$res" 7162 %} 7163#ifdef _LP64 7164 ins_encode( enc_casx(mem_ptr, oldval, newval), 7165 enc_lflags_ne_to_boolean(res) ); 7166#else 7167 ins_encode( enc_casi(mem_ptr, oldval, newval), 7168 enc_iflags_ne_to_boolean(res) ); 7169#endif 7170 ins_pipe( long_memory_op ); 7171%} 7172 7173instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{ 7174 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval))); 7175 effect( USE mem_ptr, KILL ccr, KILL tmp1); 7176 format %{ 7177 "MOV $newval,O7\n\t" 7178 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t" 7179 "CMP $oldval,O7\t\t! See if we made progress\n\t" 7180 "MOV 1,$res\n\t" 7181 "MOVne icc,R_G0,$res" 7182 %} 7183 ins_encode( enc_casi(mem_ptr, oldval, newval), 7184 enc_iflags_ne_to_boolean(res) ); 7185 ins_pipe( long_memory_op ); 7186%} 7187 7188//--------------------- 7189// Subtraction Instructions 7190// Register Subtraction 7191instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7192 match(Set dst (SubI src1 src2)); 7193 7194 size(4); 7195 format %{ "SUB $src1,$src2,$dst" %} 7196 opcode(Assembler::sub_op3, Assembler::arith_op); 7197 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7198 ins_pipe(ialu_reg_reg); 7199%} 7200 7201// Immediate Subtraction 7202instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7203 match(Set dst (SubI src1 src2)); 7204 7205 size(4); 7206 format %{ "SUB $src1,$src2,$dst" %} 7207 opcode(Assembler::sub_op3, Assembler::arith_op); 7208 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7209 ins_pipe(ialu_reg_imm); 7210%} 7211 7212instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{ 7213 match(Set dst (SubI zero src2)); 7214 7215 size(4); 7216 format %{ "NEG $src2,$dst" %} 7217 opcode(Assembler::sub_op3, Assembler::arith_op); 7218 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7219 ins_pipe(ialu_zero_reg); 7220%} 7221 7222// Long subtraction 7223instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7224 match(Set dst (SubL src1 src2)); 7225 7226 size(4); 7227 format %{ "SUB $src1,$src2,$dst\t! long" %} 7228 opcode(Assembler::sub_op3, Assembler::arith_op); 7229 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7230 ins_pipe(ialu_reg_reg); 7231%} 7232 7233// Immediate Subtraction 7234instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7235 match(Set dst (SubL src1 con)); 7236 7237 size(4); 7238 format %{ "SUB $src1,$con,$dst\t! long" %} 7239 opcode(Assembler::sub_op3, Assembler::arith_op); 7240 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7241 ins_pipe(ialu_reg_imm); 7242%} 7243 7244// Long negation 7245instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{ 7246 match(Set dst (SubL zero src2)); 7247 7248 size(4); 7249 format %{ "NEG $src2,$dst\t! long" %} 7250 opcode(Assembler::sub_op3, Assembler::arith_op); 7251 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) ); 7252 ins_pipe(ialu_zero_reg); 7253%} 7254 7255// Multiplication Instructions 7256// Integer Multiplication 7257// Register Multiplication 7258instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7259 match(Set dst (MulI src1 src2)); 7260 7261 size(4); 7262 format %{ "MULX $src1,$src2,$dst" %} 7263 opcode(Assembler::mulx_op3, Assembler::arith_op); 7264 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7265 ins_pipe(imul_reg_reg); 7266%} 7267 7268// Immediate Multiplication 7269instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7270 match(Set dst (MulI src1 src2)); 7271 7272 size(4); 7273 format %{ "MULX $src1,$src2,$dst" %} 7274 opcode(Assembler::mulx_op3, Assembler::arith_op); 7275 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7276 ins_pipe(imul_reg_imm); 7277%} 7278 7279instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7280 match(Set dst (MulL src1 src2)); 7281 ins_cost(DEFAULT_COST * 5); 7282 size(4); 7283 format %{ "MULX $src1,$src2,$dst\t! long" %} 7284 opcode(Assembler::mulx_op3, Assembler::arith_op); 7285 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7286 ins_pipe(mulL_reg_reg); 7287%} 7288 7289// Immediate Multiplication 7290instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7291 match(Set dst (MulL src1 src2)); 7292 ins_cost(DEFAULT_COST * 5); 7293 size(4); 7294 format %{ "MULX $src1,$src2,$dst" %} 7295 opcode(Assembler::mulx_op3, Assembler::arith_op); 7296 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7297 ins_pipe(mulL_reg_imm); 7298%} 7299 7300// Integer Division 7301// Register Division 7302instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{ 7303 match(Set dst (DivI src1 src2)); 7304 ins_cost((2+71)*DEFAULT_COST); 7305 7306 format %{ "SRA $src2,0,$src2\n\t" 7307 "SRA $src1,0,$src1\n\t" 7308 "SDIVX $src1,$src2,$dst" %} 7309 ins_encode( idiv_reg( src1, src2, dst ) ); 7310 ins_pipe(sdiv_reg_reg); 7311%} 7312 7313// Immediate Division 7314instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{ 7315 match(Set dst (DivI src1 src2)); 7316 ins_cost((2+71)*DEFAULT_COST); 7317 7318 format %{ "SRA $src1,0,$src1\n\t" 7319 "SDIVX $src1,$src2,$dst" %} 7320 ins_encode( idiv_imm( src1, src2, dst ) ); 7321 ins_pipe(sdiv_reg_imm); 7322%} 7323 7324//----------Div-By-10-Expansion------------------------------------------------ 7325// Extract hi bits of a 32x32->64 bit multiply. 7326// Expand rule only, not matched 7327instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{ 7328 effect( DEF dst, USE src1, USE src2 ); 7329 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t" 7330 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %} 7331 ins_encode( enc_mul_hi(dst,src1,src2)); 7332 ins_pipe(sdiv_reg_reg); 7333%} 7334 7335// Magic constant, reciprocal of 10 7336instruct loadConI_x66666667(iRegIsafe dst) %{ 7337 effect( DEF dst ); 7338 7339 size(8); 7340 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %} 7341 ins_encode( Set32(0x66666667, dst) ); 7342 ins_pipe(ialu_hi_lo_reg); 7343%} 7344 7345// Register Shift Right Arithmetic Long by 32-63 7346instruct sra_31( iRegI dst, iRegI src ) %{ 7347 effect( DEF dst, USE src ); 7348 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %} 7349 ins_encode( form3_rs1_rd_copysign_hi(src,dst) ); 7350 ins_pipe(ialu_reg_reg); 7351%} 7352 7353// Arithmetic Shift Right by 8-bit immediate 7354instruct sra_reg_2( iRegI dst, iRegI src ) %{ 7355 effect( DEF dst, USE src ); 7356 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %} 7357 opcode(Assembler::sra_op3, Assembler::arith_op); 7358 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) ); 7359 ins_pipe(ialu_reg_imm); 7360%} 7361 7362// Integer DIV with 10 7363instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{ 7364 match(Set dst (DivI src div)); 7365 ins_cost((6+6)*DEFAULT_COST); 7366 expand %{ 7367 iRegIsafe tmp1; // Killed temps; 7368 iRegIsafe tmp2; // Killed temps; 7369 iRegI tmp3; // Killed temps; 7370 iRegI tmp4; // Killed temps; 7371 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1 7372 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2 7373 sra_31( tmp3, src ); // SRA src,31 -> tmp3 7374 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4 7375 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst 7376 %} 7377%} 7378 7379// Register Long Division 7380instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7381 match(Set dst (DivL src1 src2)); 7382 ins_cost(DEFAULT_COST*71); 7383 size(4); 7384 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7385 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7386 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7387 ins_pipe(divL_reg_reg); 7388%} 7389 7390// Register Long Division 7391instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7392 match(Set dst (DivL src1 src2)); 7393 ins_cost(DEFAULT_COST*71); 7394 size(4); 7395 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7396 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7397 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7398 ins_pipe(divL_reg_imm); 7399%} 7400 7401// Integer Remainder 7402// Register Remainder 7403instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{ 7404 match(Set dst (ModI src1 src2)); 7405 effect( KILL ccr, KILL temp); 7406 7407 format %{ "SREM $src1,$src2,$dst" %} 7408 ins_encode( irem_reg(src1, src2, dst, temp) ); 7409 ins_pipe(sdiv_reg_reg); 7410%} 7411 7412// Immediate Remainder 7413instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{ 7414 match(Set dst (ModI src1 src2)); 7415 effect( KILL ccr, KILL temp); 7416 7417 format %{ "SREM $src1,$src2,$dst" %} 7418 ins_encode( irem_imm(src1, src2, dst, temp) ); 7419 ins_pipe(sdiv_reg_imm); 7420%} 7421 7422// Register Long Remainder 7423instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7424 effect(DEF dst, USE src1, USE src2); 7425 size(4); 7426 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7427 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7428 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7429 ins_pipe(divL_reg_reg); 7430%} 7431 7432// Register Long Division 7433instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7434 effect(DEF dst, USE src1, USE src2); 7435 size(4); 7436 format %{ "SDIVX $src1,$src2,$dst\t! long" %} 7437 opcode(Assembler::sdivx_op3, Assembler::arith_op); 7438 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7439 ins_pipe(divL_reg_imm); 7440%} 7441 7442instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7443 effect(DEF dst, USE src1, USE src2); 7444 size(4); 7445 format %{ "MULX $src1,$src2,$dst\t! long" %} 7446 opcode(Assembler::mulx_op3, Assembler::arith_op); 7447 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7448 ins_pipe(mulL_reg_reg); 7449%} 7450 7451// Immediate Multiplication 7452instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{ 7453 effect(DEF dst, USE src1, USE src2); 7454 size(4); 7455 format %{ "MULX $src1,$src2,$dst" %} 7456 opcode(Assembler::mulx_op3, Assembler::arith_op); 7457 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7458 ins_pipe(mulL_reg_imm); 7459%} 7460 7461instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{ 7462 effect(DEF dst, USE src1, USE src2); 7463 size(4); 7464 format %{ "SUB $src1,$src2,$dst\t! long" %} 7465 opcode(Assembler::sub_op3, Assembler::arith_op); 7466 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7467 ins_pipe(ialu_reg_reg); 7468%} 7469 7470instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{ 7471 effect(DEF dst, USE src1, USE src2); 7472 size(4); 7473 format %{ "SUB $src1,$src2,$dst\t! long" %} 7474 opcode(Assembler::sub_op3, Assembler::arith_op); 7475 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7476 ins_pipe(ialu_reg_reg); 7477%} 7478 7479// Register Long Remainder 7480instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7481 match(Set dst (ModL src1 src2)); 7482 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7483 expand %{ 7484 iRegL tmp1; 7485 iRegL tmp2; 7486 divL_reg_reg_1(tmp1, src1, src2); 7487 mulL_reg_reg_1(tmp2, tmp1, src2); 7488 subL_reg_reg_1(dst, src1, tmp2); 7489 %} 7490%} 7491 7492// Register Long Remainder 7493instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{ 7494 match(Set dst (ModL src1 src2)); 7495 ins_cost(DEFAULT_COST*(71 + 6 + 1)); 7496 expand %{ 7497 iRegL tmp1; 7498 iRegL tmp2; 7499 divL_reg_imm13_1(tmp1, src1, src2); 7500 mulL_reg_imm13_1(tmp2, tmp1, src2); 7501 subL_reg_reg_2 (dst, src1, tmp2); 7502 %} 7503%} 7504 7505// Integer Shift Instructions 7506// Register Shift Left 7507instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7508 match(Set dst (LShiftI src1 src2)); 7509 7510 size(4); 7511 format %{ "SLL $src1,$src2,$dst" %} 7512 opcode(Assembler::sll_op3, Assembler::arith_op); 7513 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7514 ins_pipe(ialu_reg_reg); 7515%} 7516 7517// Register Shift Left Immediate 7518instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7519 match(Set dst (LShiftI src1 src2)); 7520 7521 size(4); 7522 format %{ "SLL $src1,$src2,$dst" %} 7523 opcode(Assembler::sll_op3, Assembler::arith_op); 7524 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7525 ins_pipe(ialu_reg_imm); 7526%} 7527 7528// Register Shift Left 7529instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7530 match(Set dst (LShiftL src1 src2)); 7531 7532 size(4); 7533 format %{ "SLLX $src1,$src2,$dst" %} 7534 opcode(Assembler::sllx_op3, Assembler::arith_op); 7535 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7536 ins_pipe(ialu_reg_reg); 7537%} 7538 7539// Register Shift Left Immediate 7540instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7541 match(Set dst (LShiftL src1 src2)); 7542 7543 size(4); 7544 format %{ "SLLX $src1,$src2,$dst" %} 7545 opcode(Assembler::sllx_op3, Assembler::arith_op); 7546 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7547 ins_pipe(ialu_reg_imm); 7548%} 7549 7550// Register Arithmetic Shift Right 7551instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7552 match(Set dst (RShiftI src1 src2)); 7553 size(4); 7554 format %{ "SRA $src1,$src2,$dst" %} 7555 opcode(Assembler::sra_op3, Assembler::arith_op); 7556 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7557 ins_pipe(ialu_reg_reg); 7558%} 7559 7560// Register Arithmetic Shift Right Immediate 7561instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7562 match(Set dst (RShiftI src1 src2)); 7563 7564 size(4); 7565 format %{ "SRA $src1,$src2,$dst" %} 7566 opcode(Assembler::sra_op3, Assembler::arith_op); 7567 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7568 ins_pipe(ialu_reg_imm); 7569%} 7570 7571// Register Shift Right Arithmatic Long 7572instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7573 match(Set dst (RShiftL src1 src2)); 7574 7575 size(4); 7576 format %{ "SRAX $src1,$src2,$dst" %} 7577 opcode(Assembler::srax_op3, Assembler::arith_op); 7578 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7579 ins_pipe(ialu_reg_reg); 7580%} 7581 7582// Register Shift Left Immediate 7583instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7584 match(Set dst (RShiftL src1 src2)); 7585 7586 size(4); 7587 format %{ "SRAX $src1,$src2,$dst" %} 7588 opcode(Assembler::srax_op3, Assembler::arith_op); 7589 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7590 ins_pipe(ialu_reg_imm); 7591%} 7592 7593// Register Shift Right 7594instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7595 match(Set dst (URShiftI src1 src2)); 7596 7597 size(4); 7598 format %{ "SRL $src1,$src2,$dst" %} 7599 opcode(Assembler::srl_op3, Assembler::arith_op); 7600 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7601 ins_pipe(ialu_reg_reg); 7602%} 7603 7604// Register Shift Right Immediate 7605instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{ 7606 match(Set dst (URShiftI src1 src2)); 7607 7608 size(4); 7609 format %{ "SRL $src1,$src2,$dst" %} 7610 opcode(Assembler::srl_op3, Assembler::arith_op); 7611 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7612 ins_pipe(ialu_reg_imm); 7613%} 7614 7615// Register Shift Right 7616instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{ 7617 match(Set dst (URShiftL src1 src2)); 7618 7619 size(4); 7620 format %{ "SRLX $src1,$src2,$dst" %} 7621 opcode(Assembler::srlx_op3, Assembler::arith_op); 7622 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) ); 7623 ins_pipe(ialu_reg_reg); 7624%} 7625 7626// Register Shift Right Immediate 7627instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{ 7628 match(Set dst (URShiftL src1 src2)); 7629 7630 size(4); 7631 format %{ "SRLX $src1,$src2,$dst" %} 7632 opcode(Assembler::srlx_op3, Assembler::arith_op); 7633 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7634 ins_pipe(ialu_reg_imm); 7635%} 7636 7637// Register Shift Right Immediate with a CastP2X 7638#ifdef _LP64 7639instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{ 7640 match(Set dst (URShiftL (CastP2X src1) src2)); 7641 size(4); 7642 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %} 7643 opcode(Assembler::srlx_op3, Assembler::arith_op); 7644 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) ); 7645 ins_pipe(ialu_reg_imm); 7646%} 7647#else 7648instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{ 7649 match(Set dst (URShiftI (CastP2X src1) src2)); 7650 size(4); 7651 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %} 7652 opcode(Assembler::srl_op3, Assembler::arith_op); 7653 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) ); 7654 ins_pipe(ialu_reg_imm); 7655%} 7656#endif 7657 7658 7659//----------Floating Point Arithmetic Instructions----------------------------- 7660 7661// Add float single precision 7662instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 7663 match(Set dst (AddF src1 src2)); 7664 7665 size(4); 7666 format %{ "FADDS $src1,$src2,$dst" %} 7667 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf); 7668 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7669 ins_pipe(faddF_reg_reg); 7670%} 7671 7672// Add float double precision 7673instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 7674 match(Set dst (AddD src1 src2)); 7675 7676 size(4); 7677 format %{ "FADDD $src1,$src2,$dst" %} 7678 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 7679 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7680 ins_pipe(faddD_reg_reg); 7681%} 7682 7683// Sub float single precision 7684instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 7685 match(Set dst (SubF src1 src2)); 7686 7687 size(4); 7688 format %{ "FSUBS $src1,$src2,$dst" %} 7689 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf); 7690 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7691 ins_pipe(faddF_reg_reg); 7692%} 7693 7694// Sub float double precision 7695instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 7696 match(Set dst (SubD src1 src2)); 7697 7698 size(4); 7699 format %{ "FSUBD $src1,$src2,$dst" %} 7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 7701 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7702 ins_pipe(faddD_reg_reg); 7703%} 7704 7705// Mul float single precision 7706instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 7707 match(Set dst (MulF src1 src2)); 7708 7709 size(4); 7710 format %{ "FMULS $src1,$src2,$dst" %} 7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf); 7712 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7713 ins_pipe(fmulF_reg_reg); 7714%} 7715 7716// Mul float double precision 7717instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 7718 match(Set dst (MulD src1 src2)); 7719 7720 size(4); 7721 format %{ "FMULD $src1,$src2,$dst" %} 7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 7723 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7724 ins_pipe(fmulD_reg_reg); 7725%} 7726 7727// Div float single precision 7728instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 7729 match(Set dst (DivF src1 src2)); 7730 7731 size(4); 7732 format %{ "FDIVS $src1,$src2,$dst" %} 7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf); 7734 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst)); 7735 ins_pipe(fdivF_reg_reg); 7736%} 7737 7738// Div float double precision 7739instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 7740 match(Set dst (DivD src1 src2)); 7741 7742 size(4); 7743 format %{ "FDIVD $src1,$src2,$dst" %} 7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf); 7745 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 7746 ins_pipe(fdivD_reg_reg); 7747%} 7748 7749// Absolute float double precision 7750instruct absD_reg(regD dst, regD src) %{ 7751 match(Set dst (AbsD src)); 7752 7753 format %{ "FABSd $src,$dst" %} 7754 ins_encode(fabsd(dst, src)); 7755 ins_pipe(faddD_reg); 7756%} 7757 7758// Absolute float single precision 7759instruct absF_reg(regF dst, regF src) %{ 7760 match(Set dst (AbsF src)); 7761 7762 format %{ "FABSs $src,$dst" %} 7763 ins_encode(fabss(dst, src)); 7764 ins_pipe(faddF_reg); 7765%} 7766 7767instruct negF_reg(regF dst, regF src) %{ 7768 match(Set dst (NegF src)); 7769 7770 size(4); 7771 format %{ "FNEGs $src,$dst" %} 7772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf); 7773 ins_encode(form3_opf_rs2F_rdF(src, dst)); 7774 ins_pipe(faddF_reg); 7775%} 7776 7777instruct negD_reg(regD dst, regD src) %{ 7778 match(Set dst (NegD src)); 7779 7780 format %{ "FNEGd $src,$dst" %} 7781 ins_encode(fnegd(dst, src)); 7782 ins_pipe(faddD_reg); 7783%} 7784 7785// Sqrt float double precision 7786instruct sqrtF_reg_reg(regF dst, regF src) %{ 7787 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 7788 7789 size(4); 7790 format %{ "FSQRTS $src,$dst" %} 7791 ins_encode(fsqrts(dst, src)); 7792 ins_pipe(fdivF_reg_reg); 7793%} 7794 7795// Sqrt float double precision 7796instruct sqrtD_reg_reg(regD dst, regD src) %{ 7797 match(Set dst (SqrtD src)); 7798 7799 size(4); 7800 format %{ "FSQRTD $src,$dst" %} 7801 ins_encode(fsqrtd(dst, src)); 7802 ins_pipe(fdivD_reg_reg); 7803%} 7804 7805//----------Logical Instructions----------------------------------------------- 7806// And Instructions 7807// Register And 7808instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7809 match(Set dst (AndI src1 src2)); 7810 7811 size(4); 7812 format %{ "AND $src1,$src2,$dst" %} 7813 opcode(Assembler::and_op3, Assembler::arith_op); 7814 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7815 ins_pipe(ialu_reg_reg); 7816%} 7817 7818// Immediate And 7819instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7820 match(Set dst (AndI src1 src2)); 7821 7822 size(4); 7823 format %{ "AND $src1,$src2,$dst" %} 7824 opcode(Assembler::and_op3, Assembler::arith_op); 7825 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7826 ins_pipe(ialu_reg_imm); 7827%} 7828 7829// Register And Long 7830instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7831 match(Set dst (AndL src1 src2)); 7832 7833 ins_cost(DEFAULT_COST); 7834 size(4); 7835 format %{ "AND $src1,$src2,$dst\t! long" %} 7836 opcode(Assembler::and_op3, Assembler::arith_op); 7837 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7838 ins_pipe(ialu_reg_reg); 7839%} 7840 7841instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7842 match(Set dst (AndL src1 con)); 7843 7844 ins_cost(DEFAULT_COST); 7845 size(4); 7846 format %{ "AND $src1,$con,$dst\t! long" %} 7847 opcode(Assembler::and_op3, Assembler::arith_op); 7848 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7849 ins_pipe(ialu_reg_imm); 7850%} 7851 7852// Or Instructions 7853// Register Or 7854instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7855 match(Set dst (OrI src1 src2)); 7856 7857 size(4); 7858 format %{ "OR $src1,$src2,$dst" %} 7859 opcode(Assembler::or_op3, Assembler::arith_op); 7860 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7861 ins_pipe(ialu_reg_reg); 7862%} 7863 7864// Immediate Or 7865instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7866 match(Set dst (OrI src1 src2)); 7867 7868 size(4); 7869 format %{ "OR $src1,$src2,$dst" %} 7870 opcode(Assembler::or_op3, Assembler::arith_op); 7871 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7872 ins_pipe(ialu_reg_imm); 7873%} 7874 7875// Register Or Long 7876instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7877 match(Set dst (OrL src1 src2)); 7878 7879 ins_cost(DEFAULT_COST); 7880 size(4); 7881 format %{ "OR $src1,$src2,$dst\t! long" %} 7882 opcode(Assembler::or_op3, Assembler::arith_op); 7883 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7884 ins_pipe(ialu_reg_reg); 7885%} 7886 7887instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7888 match(Set dst (OrL src1 con)); 7889 ins_cost(DEFAULT_COST*2); 7890 7891 ins_cost(DEFAULT_COST); 7892 size(4); 7893 format %{ "OR $src1,$con,$dst\t! long" %} 7894 opcode(Assembler::or_op3, Assembler::arith_op); 7895 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7896 ins_pipe(ialu_reg_imm); 7897%} 7898 7899#ifndef _LP64 7900 7901// Use sp_ptr_RegP to match G2 (TLS register) without spilling. 7902instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{ 7903 match(Set dst (OrI src1 (CastP2X src2))); 7904 7905 size(4); 7906 format %{ "OR $src1,$src2,$dst" %} 7907 opcode(Assembler::or_op3, Assembler::arith_op); 7908 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7909 ins_pipe(ialu_reg_reg); 7910%} 7911 7912#else 7913 7914instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{ 7915 match(Set dst (OrL src1 (CastP2X src2))); 7916 7917 ins_cost(DEFAULT_COST); 7918 size(4); 7919 format %{ "OR $src1,$src2,$dst\t! long" %} 7920 opcode(Assembler::or_op3, Assembler::arith_op); 7921 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7922 ins_pipe(ialu_reg_reg); 7923%} 7924 7925#endif 7926 7927// Xor Instructions 7928// Register Xor 7929instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{ 7930 match(Set dst (XorI src1 src2)); 7931 7932 size(4); 7933 format %{ "XOR $src1,$src2,$dst" %} 7934 opcode(Assembler::xor_op3, Assembler::arith_op); 7935 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7936 ins_pipe(ialu_reg_reg); 7937%} 7938 7939// Immediate Xor 7940instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{ 7941 match(Set dst (XorI src1 src2)); 7942 7943 size(4); 7944 format %{ "XOR $src1,$src2,$dst" %} 7945 opcode(Assembler::xor_op3, Assembler::arith_op); 7946 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) ); 7947 ins_pipe(ialu_reg_imm); 7948%} 7949 7950// Register Xor Long 7951instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{ 7952 match(Set dst (XorL src1 src2)); 7953 7954 ins_cost(DEFAULT_COST); 7955 size(4); 7956 format %{ "XOR $src1,$src2,$dst\t! long" %} 7957 opcode(Assembler::xor_op3, Assembler::arith_op); 7958 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) ); 7959 ins_pipe(ialu_reg_reg); 7960%} 7961 7962instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{ 7963 match(Set dst (XorL src1 con)); 7964 7965 ins_cost(DEFAULT_COST); 7966 size(4); 7967 format %{ "XOR $src1,$con,$dst\t! long" %} 7968 opcode(Assembler::xor_op3, Assembler::arith_op); 7969 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) ); 7970 ins_pipe(ialu_reg_imm); 7971%} 7972 7973//----------Convert to Boolean------------------------------------------------- 7974// Nice hack for 32-bit tests but doesn't work for 7975// 64-bit pointers. 7976instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{ 7977 match(Set dst (Conv2B src)); 7978 effect( KILL ccr ); 7979 ins_cost(DEFAULT_COST*2); 7980 format %{ "CMP R_G0,$src\n\t" 7981 "ADDX R_G0,0,$dst" %} 7982 ins_encode( enc_to_bool( src, dst ) ); 7983 ins_pipe(ialu_reg_ialu); 7984%} 7985 7986#ifndef _LP64 7987instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{ 7988 match(Set dst (Conv2B src)); 7989 effect( KILL ccr ); 7990 ins_cost(DEFAULT_COST*2); 7991 format %{ "CMP R_G0,$src\n\t" 7992 "ADDX R_G0,0,$dst" %} 7993 ins_encode( enc_to_bool( src, dst ) ); 7994 ins_pipe(ialu_reg_ialu); 7995%} 7996#else 7997instruct convP2B( iRegI dst, iRegP src ) %{ 7998 match(Set dst (Conv2B src)); 7999 ins_cost(DEFAULT_COST*2); 8000 format %{ "MOV $src,$dst\n\t" 8001 "MOVRNZ $src,1,$dst" %} 8002 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) ); 8003 ins_pipe(ialu_clr_and_mover); 8004%} 8005#endif 8006 8007instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{ 8008 match(Set dst (CmpLTMask p q)); 8009 effect( KILL ccr ); 8010 ins_cost(DEFAULT_COST*4); 8011 format %{ "CMP $p,$q\n\t" 8012 "MOV #0,$dst\n\t" 8013 "BLT,a .+8\n\t" 8014 "MOV #-1,$dst" %} 8015 ins_encode( enc_ltmask(p,q,dst) ); 8016 ins_pipe(ialu_reg_reg_ialu); 8017%} 8018 8019instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8020 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q))); 8021 effect(KILL ccr, TEMP tmp); 8022 ins_cost(DEFAULT_COST*3); 8023 8024 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8025 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8026 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8027 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8028 ins_pipe( cadd_cmpltmask ); 8029%} 8030 8031instruct cadd_cmpLTMask2( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{ 8032 match(Set p (AddI (SubI p q) (AndI (CmpLTMask p q) y))); 8033 effect( KILL ccr, TEMP tmp); 8034 ins_cost(DEFAULT_COST*3); 8035 8036 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t" 8037 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t" 8038 "MOVl $tmp,$p\t! p' < 0 ? p'+y : p'" %} 8039 ins_encode( enc_cadd_cmpLTMask(p, q, y, tmp) ); 8040 ins_pipe( cadd_cmpltmask ); 8041%} 8042 8043//----------Arithmetic Conversion Instructions--------------------------------- 8044// The conversions operations are all Alpha sorted. Please keep it that way! 8045 8046instruct convD2F_reg(regF dst, regD src) %{ 8047 match(Set dst (ConvD2F src)); 8048 size(4); 8049 format %{ "FDTOS $src,$dst" %} 8050 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf); 8051 ins_encode(form3_opf_rs2D_rdF(src, dst)); 8052 ins_pipe(fcvtD2F); 8053%} 8054 8055 8056// Convert a double to an int in a float register. 8057// If the double is a NAN, stuff a zero in instead. 8058instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{ 8059 effect(DEF dst, USE src, KILL fcc0); 8060 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8061 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8062 "FDTOI $src,$dst\t! convert in delay slot\n\t" 8063 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8064 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8065 "skip:" %} 8066 ins_encode(form_d2i_helper(src,dst)); 8067 ins_pipe(fcvtD2I); 8068%} 8069 8070instruct convD2I_reg(stackSlotI dst, regD src) %{ 8071 match(Set dst (ConvD2I src)); 8072 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8073 expand %{ 8074 regF tmp; 8075 convD2I_helper(tmp, src); 8076 regF_to_stkI(dst, tmp); 8077 %} 8078%} 8079 8080// Convert a double to a long in a double register. 8081// If the double is a NAN, stuff a zero in instead. 8082instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{ 8083 effect(DEF dst, USE src, KILL fcc0); 8084 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t" 8085 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8086 "FDTOX $src,$dst\t! convert in delay slot\n\t" 8087 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8088 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8089 "skip:" %} 8090 ins_encode(form_d2l_helper(src,dst)); 8091 ins_pipe(fcvtD2L); 8092%} 8093 8094 8095// Double to Long conversion 8096instruct convD2L_reg(stackSlotL dst, regD src) %{ 8097 match(Set dst (ConvD2L src)); 8098 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8099 expand %{ 8100 regD tmp; 8101 convD2L_helper(tmp, src); 8102 regD_to_stkL(dst, tmp); 8103 %} 8104%} 8105 8106 8107instruct convF2D_reg(regD dst, regF src) %{ 8108 match(Set dst (ConvF2D src)); 8109 format %{ "FSTOD $src,$dst" %} 8110 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf); 8111 ins_encode(form3_opf_rs2F_rdD(src, dst)); 8112 ins_pipe(fcvtF2D); 8113%} 8114 8115 8116instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{ 8117 effect(DEF dst, USE src, KILL fcc0); 8118 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8119 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8120 "FSTOI $src,$dst\t! convert in delay slot\n\t" 8121 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t" 8122 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n" 8123 "skip:" %} 8124 ins_encode(form_f2i_helper(src,dst)); 8125 ins_pipe(fcvtF2I); 8126%} 8127 8128instruct convF2I_reg(stackSlotI dst, regF src) %{ 8129 match(Set dst (ConvF2I src)); 8130 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8131 expand %{ 8132 regF tmp; 8133 convF2I_helper(tmp, src); 8134 regF_to_stkI(dst, tmp); 8135 %} 8136%} 8137 8138 8139instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{ 8140 effect(DEF dst, USE src, KILL fcc0); 8141 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t" 8142 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t" 8143 "FSTOX $src,$dst\t! convert in delay slot\n\t" 8144 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t" 8145 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n" 8146 "skip:" %} 8147 ins_encode(form_f2l_helper(src,dst)); 8148 ins_pipe(fcvtF2L); 8149%} 8150 8151// Float to Long conversion 8152instruct convF2L_reg(stackSlotL dst, regF src) %{ 8153 match(Set dst (ConvF2L src)); 8154 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST); 8155 expand %{ 8156 regD tmp; 8157 convF2L_helper(tmp, src); 8158 regD_to_stkL(dst, tmp); 8159 %} 8160%} 8161 8162 8163instruct convI2D_helper(regD dst, regF tmp) %{ 8164 effect(USE tmp, DEF dst); 8165 format %{ "FITOD $tmp,$dst" %} 8166 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8167 ins_encode(form3_opf_rs2F_rdD(tmp, dst)); 8168 ins_pipe(fcvtI2D); 8169%} 8170 8171instruct convI2D_reg(stackSlotI src, regD dst) %{ 8172 match(Set dst (ConvI2D src)); 8173 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8174 expand %{ 8175 regF tmp; 8176 stkI_to_regF( tmp, src); 8177 convI2D_helper( dst, tmp); 8178 %} 8179%} 8180 8181instruct convI2D_mem( regD_low dst, memory mem ) %{ 8182 match(Set dst (ConvI2D (LoadI mem))); 8183 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8184 size(8); 8185 format %{ "LDF $mem,$dst\n\t" 8186 "FITOD $dst,$dst" %} 8187 opcode(Assembler::ldf_op3, Assembler::fitod_opf); 8188 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8189 ins_pipe(floadF_mem); 8190%} 8191 8192 8193instruct convI2F_helper(regF dst, regF tmp) %{ 8194 effect(DEF dst, USE tmp); 8195 format %{ "FITOS $tmp,$dst" %} 8196 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf); 8197 ins_encode(form3_opf_rs2F_rdF(tmp, dst)); 8198 ins_pipe(fcvtI2F); 8199%} 8200 8201instruct convI2F_reg( regF dst, stackSlotI src ) %{ 8202 match(Set dst (ConvI2F src)); 8203 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8204 expand %{ 8205 regF tmp; 8206 stkI_to_regF(tmp,src); 8207 convI2F_helper(dst, tmp); 8208 %} 8209%} 8210 8211instruct convI2F_mem( regF dst, memory mem ) %{ 8212 match(Set dst (ConvI2F (LoadI mem))); 8213 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8214 size(8); 8215 format %{ "LDF $mem,$dst\n\t" 8216 "FITOS $dst,$dst" %} 8217 opcode(Assembler::ldf_op3, Assembler::fitos_opf); 8218 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst)); 8219 ins_pipe(floadF_mem); 8220%} 8221 8222 8223instruct convI2L_reg(iRegL dst, iRegI src) %{ 8224 match(Set dst (ConvI2L src)); 8225 size(4); 8226 format %{ "SRA $src,0,$dst\t! int->long" %} 8227 opcode(Assembler::sra_op3, Assembler::arith_op); 8228 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8229 ins_pipe(ialu_reg_reg); 8230%} 8231 8232// Zero-extend convert int to long 8233instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{ 8234 match(Set dst (AndL (ConvI2L src) mask) ); 8235 size(4); 8236 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %} 8237 opcode(Assembler::srl_op3, Assembler::arith_op); 8238 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8239 ins_pipe(ialu_reg_reg); 8240%} 8241 8242// Zero-extend long 8243instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{ 8244 match(Set dst (AndL src mask) ); 8245 size(4); 8246 format %{ "SRL $src,0,$dst\t! zero-extend long" %} 8247 opcode(Assembler::srl_op3, Assembler::arith_op); 8248 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) ); 8249 ins_pipe(ialu_reg_reg); 8250%} 8251 8252instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{ 8253 match(Set dst (MoveF2I src)); 8254 effect(DEF dst, USE src); 8255 ins_cost(MEMORY_REF_COST); 8256 8257 size(4); 8258 format %{ "LDUW $src,$dst\t! MoveF2I" %} 8259 opcode(Assembler::lduw_op3); 8260 ins_encode(simple_form3_mem_reg( src, dst ) ); 8261 ins_pipe(iload_mem); 8262%} 8263 8264instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{ 8265 match(Set dst (MoveI2F src)); 8266 effect(DEF dst, USE src); 8267 ins_cost(MEMORY_REF_COST); 8268 8269 size(4); 8270 format %{ "LDF $src,$dst\t! MoveI2F" %} 8271 opcode(Assembler::ldf_op3); 8272 ins_encode(simple_form3_mem_reg(src, dst)); 8273 ins_pipe(floadF_stk); 8274%} 8275 8276instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{ 8277 match(Set dst (MoveD2L src)); 8278 effect(DEF dst, USE src); 8279 ins_cost(MEMORY_REF_COST); 8280 8281 size(4); 8282 format %{ "LDX $src,$dst\t! MoveD2L" %} 8283 opcode(Assembler::ldx_op3); 8284 ins_encode(simple_form3_mem_reg( src, dst ) ); 8285 ins_pipe(iload_mem); 8286%} 8287 8288instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{ 8289 match(Set dst (MoveL2D src)); 8290 effect(DEF dst, USE src); 8291 ins_cost(MEMORY_REF_COST); 8292 8293 size(4); 8294 format %{ "LDDF $src,$dst\t! MoveL2D" %} 8295 opcode(Assembler::lddf_op3); 8296 ins_encode(simple_form3_mem_reg(src, dst)); 8297 ins_pipe(floadD_stk); 8298%} 8299 8300instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{ 8301 match(Set dst (MoveF2I src)); 8302 effect(DEF dst, USE src); 8303 ins_cost(MEMORY_REF_COST); 8304 8305 size(4); 8306 format %{ "STF $src,$dst\t!MoveF2I" %} 8307 opcode(Assembler::stf_op3); 8308 ins_encode(simple_form3_mem_reg(dst, src)); 8309 ins_pipe(fstoreF_stk_reg); 8310%} 8311 8312instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{ 8313 match(Set dst (MoveI2F src)); 8314 effect(DEF dst, USE src); 8315 ins_cost(MEMORY_REF_COST); 8316 8317 size(4); 8318 format %{ "STW $src,$dst\t!MoveI2F" %} 8319 opcode(Assembler::stw_op3); 8320 ins_encode(simple_form3_mem_reg( dst, src ) ); 8321 ins_pipe(istore_mem_reg); 8322%} 8323 8324instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{ 8325 match(Set dst (MoveD2L src)); 8326 effect(DEF dst, USE src); 8327 ins_cost(MEMORY_REF_COST); 8328 8329 size(4); 8330 format %{ "STDF $src,$dst\t!MoveD2L" %} 8331 opcode(Assembler::stdf_op3); 8332 ins_encode(simple_form3_mem_reg(dst, src)); 8333 ins_pipe(fstoreD_stk_reg); 8334%} 8335 8336instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{ 8337 match(Set dst (MoveL2D src)); 8338 effect(DEF dst, USE src); 8339 ins_cost(MEMORY_REF_COST); 8340 8341 size(4); 8342 format %{ "STX $src,$dst\t!MoveL2D" %} 8343 opcode(Assembler::stx_op3); 8344 ins_encode(simple_form3_mem_reg( dst, src ) ); 8345 ins_pipe(istore_mem_reg); 8346%} 8347 8348 8349//----------- 8350// Long to Double conversion using V8 opcodes. 8351// Still useful because cheetah traps and becomes 8352// amazingly slow for some common numbers. 8353 8354// Magic constant, 0x43300000 8355instruct loadConI_x43300000(iRegI dst) %{ 8356 effect(DEF dst); 8357 size(4); 8358 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %} 8359 ins_encode(SetHi22(0x43300000, dst)); 8360 ins_pipe(ialu_none); 8361%} 8362 8363// Magic constant, 0x41f00000 8364instruct loadConI_x41f00000(iRegI dst) %{ 8365 effect(DEF dst); 8366 size(4); 8367 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %} 8368 ins_encode(SetHi22(0x41f00000, dst)); 8369 ins_pipe(ialu_none); 8370%} 8371 8372// Construct a double from two float halves 8373instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{ 8374 effect(DEF dst, USE src1, USE src2); 8375 size(8); 8376 format %{ "FMOVS $src1.hi,$dst.hi\n\t" 8377 "FMOVS $src2.lo,$dst.lo" %} 8378 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf); 8379 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst)); 8380 ins_pipe(faddD_reg_reg); 8381%} 8382 8383// Convert integer in high half of a double register (in the lower half of 8384// the double register file) to double 8385instruct convI2D_regDHi_regD(regD dst, regD_low src) %{ 8386 effect(DEF dst, USE src); 8387 size(4); 8388 format %{ "FITOD $src,$dst" %} 8389 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf); 8390 ins_encode(form3_opf_rs2D_rdD(src, dst)); 8391 ins_pipe(fcvtLHi2D); 8392%} 8393 8394// Add float double precision 8395instruct addD_regD_regD(regD dst, regD src1, regD src2) %{ 8396 effect(DEF dst, USE src1, USE src2); 8397 size(4); 8398 format %{ "FADDD $src1,$src2,$dst" %} 8399 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf); 8400 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8401 ins_pipe(faddD_reg_reg); 8402%} 8403 8404// Sub float double precision 8405instruct subD_regD_regD(regD dst, regD src1, regD src2) %{ 8406 effect(DEF dst, USE src1, USE src2); 8407 size(4); 8408 format %{ "FSUBD $src1,$src2,$dst" %} 8409 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf); 8410 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8411 ins_pipe(faddD_reg_reg); 8412%} 8413 8414// Mul float double precision 8415instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{ 8416 effect(DEF dst, USE src1, USE src2); 8417 size(4); 8418 format %{ "FMULD $src1,$src2,$dst" %} 8419 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf); 8420 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst)); 8421 ins_pipe(fmulD_reg_reg); 8422%} 8423 8424instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{ 8425 match(Set dst (ConvL2D src)); 8426 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6); 8427 8428 expand %{ 8429 regD_low tmpsrc; 8430 iRegI ix43300000; 8431 iRegI ix41f00000; 8432 stackSlotL lx43300000; 8433 stackSlotL lx41f00000; 8434 regD_low dx43300000; 8435 regD dx41f00000; 8436 regD tmp1; 8437 regD_low tmp2; 8438 regD tmp3; 8439 regD tmp4; 8440 8441 stkL_to_regD(tmpsrc, src); 8442 8443 loadConI_x43300000(ix43300000); 8444 loadConI_x41f00000(ix41f00000); 8445 regI_to_stkLHi(lx43300000, ix43300000); 8446 regI_to_stkLHi(lx41f00000, ix41f00000); 8447 stkL_to_regD(dx43300000, lx43300000); 8448 stkL_to_regD(dx41f00000, lx41f00000); 8449 8450 convI2D_regDHi_regD(tmp1, tmpsrc); 8451 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc); 8452 subD_regD_regD(tmp3, tmp2, dx43300000); 8453 mulD_regD_regD(tmp4, tmp1, dx41f00000); 8454 addD_regD_regD(dst, tmp3, tmp4); 8455 %} 8456%} 8457 8458// Long to Double conversion using fast fxtof 8459instruct convL2D_helper(regD dst, regD tmp) %{ 8460 effect(DEF dst, USE tmp); 8461 size(4); 8462 format %{ "FXTOD $tmp,$dst" %} 8463 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf); 8464 ins_encode(form3_opf_rs2D_rdD(tmp, dst)); 8465 ins_pipe(fcvtL2D); 8466%} 8467 8468instruct convL2D_reg_fast_fxtof(regD dst, stackSlotL src) %{ 8469 predicate(VM_Version::has_fast_fxtof()); 8470 match(Set dst (ConvL2D src)); 8471 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST); 8472 expand %{ 8473 regD tmp; 8474 stkL_to_regD(tmp, src); 8475 convL2D_helper(dst, tmp); 8476 %} 8477%} 8478 8479//----------- 8480// Long to Float conversion using V8 opcodes. 8481// Still useful because cheetah traps and becomes 8482// amazingly slow for some common numbers. 8483 8484// Long to Float conversion using fast fxtof 8485instruct convL2F_helper(regF dst, regD tmp) %{ 8486 effect(DEF dst, USE tmp); 8487 size(4); 8488 format %{ "FXTOS $tmp,$dst" %} 8489 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf); 8490 ins_encode(form3_opf_rs2D_rdF(tmp, dst)); 8491 ins_pipe(fcvtL2F); 8492%} 8493 8494instruct convL2F_reg_fast_fxtof(regF dst, stackSlotL src) %{ 8495 match(Set dst (ConvL2F src)); 8496 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 8497 expand %{ 8498 regD tmp; 8499 stkL_to_regD(tmp, src); 8500 convL2F_helper(dst, tmp); 8501 %} 8502%} 8503//----------- 8504 8505instruct convL2I_reg(iRegI dst, iRegL src) %{ 8506 match(Set dst (ConvL2I src)); 8507#ifndef _LP64 8508 format %{ "MOV $src.lo,$dst\t! long->int" %} 8509 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) ); 8510 ins_pipe(ialu_move_reg_I_to_L); 8511#else 8512 size(4); 8513 format %{ "SRA $src,R_G0,$dst\t! long->int" %} 8514 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) ); 8515 ins_pipe(ialu_reg); 8516#endif 8517%} 8518 8519// Register Shift Right Immediate 8520instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{ 8521 match(Set dst (ConvL2I (RShiftL src cnt))); 8522 8523 size(4); 8524 format %{ "SRAX $src,$cnt,$dst" %} 8525 opcode(Assembler::srax_op3, Assembler::arith_op); 8526 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) ); 8527 ins_pipe(ialu_reg_imm); 8528%} 8529 8530// Replicate scalar to packed byte values in Double register 8531instruct Repl8B_reg_helper(iRegL dst, iRegI src) %{ 8532 effect(DEF dst, USE src); 8533 format %{ "SLLX $src,56,$dst\n\t" 8534 "SRLX $dst, 8,O7\n\t" 8535 "OR $dst,O7,$dst\n\t" 8536 "SRLX $dst,16,O7\n\t" 8537 "OR $dst,O7,$dst\n\t" 8538 "SRLX $dst,32,O7\n\t" 8539 "OR $dst,O7,$dst\t! replicate8B" %} 8540 ins_encode( enc_repl8b(src, dst)); 8541 ins_pipe(ialu_reg); 8542%} 8543 8544// Replicate scalar to packed byte values in Double register 8545instruct Repl8B_reg(stackSlotD dst, iRegI src) %{ 8546 match(Set dst (Replicate8B src)); 8547 expand %{ 8548 iRegL tmp; 8549 Repl8B_reg_helper(tmp, src); 8550 regL_to_stkD(dst, tmp); 8551 %} 8552%} 8553 8554// Replicate scalar constant to packed byte values in Double register 8555instruct Repl8B_immI(regD dst, immI13 src, o7RegP tmp) %{ 8556 match(Set dst (Replicate8B src)); 8557#ifdef _LP64 8558 size(36); 8559#else 8560 size(8); 8561#endif 8562 format %{ "SETHI hi(&Repl8($src)),$tmp\t!get Repl8B($src) from table\n\t" 8563 "LDDF [$tmp+lo(&Repl8($src))],$dst" %} 8564 ins_encode( LdReplImmI(src, dst, tmp, (8), (1)) ); 8565 ins_pipe(loadConFD); 8566%} 8567 8568// Replicate scalar to packed char values into stack slot 8569instruct Repl4C_reg_helper(iRegL dst, iRegI src) %{ 8570 effect(DEF dst, USE src); 8571 format %{ "SLLX $src,48,$dst\n\t" 8572 "SRLX $dst,16,O7\n\t" 8573 "OR $dst,O7,$dst\n\t" 8574 "SRLX $dst,32,O7\n\t" 8575 "OR $dst,O7,$dst\t! replicate4C" %} 8576 ins_encode( enc_repl4s(src, dst) ); 8577 ins_pipe(ialu_reg); 8578%} 8579 8580// Replicate scalar to packed char values into stack slot 8581instruct Repl4C_reg(stackSlotD dst, iRegI src) %{ 8582 match(Set dst (Replicate4C src)); 8583 expand %{ 8584 iRegL tmp; 8585 Repl4C_reg_helper(tmp, src); 8586 regL_to_stkD(dst, tmp); 8587 %} 8588%} 8589 8590// Replicate scalar constant to packed char values in Double register 8591instruct Repl4C_immI(regD dst, immI src, o7RegP tmp) %{ 8592 match(Set dst (Replicate4C src)); 8593#ifdef _LP64 8594 size(36); 8595#else 8596 size(8); 8597#endif 8598 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4C($src) from table\n\t" 8599 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8600 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8601 ins_pipe(loadConFD); 8602%} 8603 8604// Replicate scalar to packed short values into stack slot 8605instruct Repl4S_reg_helper(iRegL dst, iRegI src) %{ 8606 effect(DEF dst, USE src); 8607 format %{ "SLLX $src,48,$dst\n\t" 8608 "SRLX $dst,16,O7\n\t" 8609 "OR $dst,O7,$dst\n\t" 8610 "SRLX $dst,32,O7\n\t" 8611 "OR $dst,O7,$dst\t! replicate4S" %} 8612 ins_encode( enc_repl4s(src, dst) ); 8613 ins_pipe(ialu_reg); 8614%} 8615 8616// Replicate scalar to packed short values into stack slot 8617instruct Repl4S_reg(stackSlotD dst, iRegI src) %{ 8618 match(Set dst (Replicate4S src)); 8619 expand %{ 8620 iRegL tmp; 8621 Repl4S_reg_helper(tmp, src); 8622 regL_to_stkD(dst, tmp); 8623 %} 8624%} 8625 8626// Replicate scalar constant to packed short values in Double register 8627instruct Repl4S_immI(regD dst, immI src, o7RegP tmp) %{ 8628 match(Set dst (Replicate4S src)); 8629#ifdef _LP64 8630 size(36); 8631#else 8632 size(8); 8633#endif 8634 format %{ "SETHI hi(&Repl4($src)),$tmp\t!get Repl4S($src) from table\n\t" 8635 "LDDF [$tmp+lo(&Repl4($src))],$dst" %} 8636 ins_encode( LdReplImmI(src, dst, tmp, (4), (2)) ); 8637 ins_pipe(loadConFD); 8638%} 8639 8640// Replicate scalar to packed int values in Double register 8641instruct Repl2I_reg_helper(iRegL dst, iRegI src) %{ 8642 effect(DEF dst, USE src); 8643 format %{ "SLLX $src,32,$dst\n\t" 8644 "SRLX $dst,32,O7\n\t" 8645 "OR $dst,O7,$dst\t! replicate2I" %} 8646 ins_encode( enc_repl2i(src, dst)); 8647 ins_pipe(ialu_reg); 8648%} 8649 8650// Replicate scalar to packed int values in Double register 8651instruct Repl2I_reg(stackSlotD dst, iRegI src) %{ 8652 match(Set dst (Replicate2I src)); 8653 expand %{ 8654 iRegL tmp; 8655 Repl2I_reg_helper(tmp, src); 8656 regL_to_stkD(dst, tmp); 8657 %} 8658%} 8659 8660// Replicate scalar zero constant to packed int values in Double register 8661instruct Repl2I_immI(regD dst, immI src, o7RegP tmp) %{ 8662 match(Set dst (Replicate2I src)); 8663#ifdef _LP64 8664 size(36); 8665#else 8666 size(8); 8667#endif 8668 format %{ "SETHI hi(&Repl2($src)),$tmp\t!get Repl2I($src) from table\n\t" 8669 "LDDF [$tmp+lo(&Repl2($src))],$dst" %} 8670 ins_encode( LdReplImmI(src, dst, tmp, (2), (4)) ); 8671 ins_pipe(loadConFD); 8672%} 8673 8674//----------Control Flow Instructions------------------------------------------ 8675// Compare Instructions 8676// Compare Integers 8677instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{ 8678 match(Set icc (CmpI op1 op2)); 8679 effect( DEF icc, USE op1, USE op2 ); 8680 8681 size(4); 8682 format %{ "CMP $op1,$op2" %} 8683 opcode(Assembler::subcc_op3, Assembler::arith_op); 8684 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8685 ins_pipe(ialu_cconly_reg_reg); 8686%} 8687 8688instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{ 8689 match(Set icc (CmpU op1 op2)); 8690 8691 size(4); 8692 format %{ "CMP $op1,$op2\t! unsigned" %} 8693 opcode(Assembler::subcc_op3, Assembler::arith_op); 8694 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8695 ins_pipe(ialu_cconly_reg_reg); 8696%} 8697 8698instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{ 8699 match(Set icc (CmpI op1 op2)); 8700 effect( DEF icc, USE op1 ); 8701 8702 size(4); 8703 format %{ "CMP $op1,$op2" %} 8704 opcode(Assembler::subcc_op3, Assembler::arith_op); 8705 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8706 ins_pipe(ialu_cconly_reg_imm); 8707%} 8708 8709instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{ 8710 match(Set icc (CmpI (AndI op1 op2) zero)); 8711 8712 size(4); 8713 format %{ "BTST $op2,$op1" %} 8714 opcode(Assembler::andcc_op3, Assembler::arith_op); 8715 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8716 ins_pipe(ialu_cconly_reg_reg_zero); 8717%} 8718 8719instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{ 8720 match(Set icc (CmpI (AndI op1 op2) zero)); 8721 8722 size(4); 8723 format %{ "BTST $op2,$op1" %} 8724 opcode(Assembler::andcc_op3, Assembler::arith_op); 8725 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8726 ins_pipe(ialu_cconly_reg_imm_zero); 8727%} 8728 8729instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{ 8730 match(Set xcc (CmpL op1 op2)); 8731 effect( DEF xcc, USE op1, USE op2 ); 8732 8733 size(4); 8734 format %{ "CMP $op1,$op2\t\t! long" %} 8735 opcode(Assembler::subcc_op3, Assembler::arith_op); 8736 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8737 ins_pipe(ialu_cconly_reg_reg); 8738%} 8739 8740instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{ 8741 match(Set xcc (CmpL op1 con)); 8742 effect( DEF xcc, USE op1, USE con ); 8743 8744 size(4); 8745 format %{ "CMP $op1,$con\t\t! long" %} 8746 opcode(Assembler::subcc_op3, Assembler::arith_op); 8747 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8748 ins_pipe(ialu_cconly_reg_reg); 8749%} 8750 8751instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{ 8752 match(Set xcc (CmpL (AndL op1 op2) zero)); 8753 effect( DEF xcc, USE op1, USE op2 ); 8754 8755 size(4); 8756 format %{ "BTST $op1,$op2\t\t! long" %} 8757 opcode(Assembler::andcc_op3, Assembler::arith_op); 8758 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8759 ins_pipe(ialu_cconly_reg_reg); 8760%} 8761 8762// useful for checking the alignment of a pointer: 8763instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{ 8764 match(Set xcc (CmpL (AndL op1 con) zero)); 8765 effect( DEF xcc, USE op1, USE con ); 8766 8767 size(4); 8768 format %{ "BTST $op1,$con\t\t! long" %} 8769 opcode(Assembler::andcc_op3, Assembler::arith_op); 8770 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) ); 8771 ins_pipe(ialu_cconly_reg_reg); 8772%} 8773 8774instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU13 op2 ) %{ 8775 match(Set icc (CmpU op1 op2)); 8776 8777 size(4); 8778 format %{ "CMP $op1,$op2\t! unsigned" %} 8779 opcode(Assembler::subcc_op3, Assembler::arith_op); 8780 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8781 ins_pipe(ialu_cconly_reg_imm); 8782%} 8783 8784// Compare Pointers 8785instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{ 8786 match(Set pcc (CmpP op1 op2)); 8787 8788 size(4); 8789 format %{ "CMP $op1,$op2\t! ptr" %} 8790 opcode(Assembler::subcc_op3, Assembler::arith_op); 8791 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8792 ins_pipe(ialu_cconly_reg_reg); 8793%} 8794 8795instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{ 8796 match(Set pcc (CmpP op1 op2)); 8797 8798 size(4); 8799 format %{ "CMP $op1,$op2\t! ptr" %} 8800 opcode(Assembler::subcc_op3, Assembler::arith_op); 8801 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8802 ins_pipe(ialu_cconly_reg_imm); 8803%} 8804 8805// Compare Narrow oops 8806instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{ 8807 match(Set icc (CmpN op1 op2)); 8808 8809 size(4); 8810 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8811 opcode(Assembler::subcc_op3, Assembler::arith_op); 8812 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) ); 8813 ins_pipe(ialu_cconly_reg_reg); 8814%} 8815 8816instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{ 8817 match(Set icc (CmpN op1 op2)); 8818 8819 size(4); 8820 format %{ "CMP $op1,$op2\t! compressed ptr" %} 8821 opcode(Assembler::subcc_op3, Assembler::arith_op); 8822 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) ); 8823 ins_pipe(ialu_cconly_reg_imm); 8824%} 8825 8826//----------Max and Min-------------------------------------------------------- 8827// Min Instructions 8828// Conditional move for min 8829instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8830 effect( USE_DEF op2, USE op1, USE icc ); 8831 8832 size(4); 8833 format %{ "MOVlt icc,$op1,$op2\t! min" %} 8834 opcode(Assembler::less); 8835 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8836 ins_pipe(ialu_reg_flags); 8837%} 8838 8839// Min Register with Register. 8840instruct minI_eReg(iRegI op1, iRegI op2) %{ 8841 match(Set op2 (MinI op1 op2)); 8842 ins_cost(DEFAULT_COST*2); 8843 expand %{ 8844 flagsReg icc; 8845 compI_iReg(icc,op1,op2); 8846 cmovI_reg_lt(op2,op1,icc); 8847 %} 8848%} 8849 8850// Max Instructions 8851// Conditional move for max 8852instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{ 8853 effect( USE_DEF op2, USE op1, USE icc ); 8854 format %{ "MOVgt icc,$op1,$op2\t! max" %} 8855 opcode(Assembler::greater); 8856 ins_encode( enc_cmov_reg_minmax(op2,op1) ); 8857 ins_pipe(ialu_reg_flags); 8858%} 8859 8860// Max Register with Register 8861instruct maxI_eReg(iRegI op1, iRegI op2) %{ 8862 match(Set op2 (MaxI op1 op2)); 8863 ins_cost(DEFAULT_COST*2); 8864 expand %{ 8865 flagsReg icc; 8866 compI_iReg(icc,op1,op2); 8867 cmovI_reg_gt(op2,op1,icc); 8868 %} 8869%} 8870 8871 8872//----------Float Compares---------------------------------------------------- 8873// Compare floating, generate condition code 8874instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{ 8875 match(Set fcc (CmpF src1 src2)); 8876 8877 size(4); 8878 format %{ "FCMPs $fcc,$src1,$src2" %} 8879 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf); 8880 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) ); 8881 ins_pipe(faddF_fcc_reg_reg_zero); 8882%} 8883 8884instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{ 8885 match(Set fcc (CmpD src1 src2)); 8886 8887 size(4); 8888 format %{ "FCMPd $fcc,$src1,$src2" %} 8889 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf); 8890 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) ); 8891 ins_pipe(faddD_fcc_reg_reg_zero); 8892%} 8893 8894 8895// Compare floating, generate -1,0,1 8896instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{ 8897 match(Set dst (CmpF3 src1 src2)); 8898 effect(KILL fcc0); 8899 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8900 format %{ "fcmpl $dst,$src1,$src2" %} 8901 // Primary = float 8902 opcode( true ); 8903 ins_encode( floating_cmp( dst, src1, src2 ) ); 8904 ins_pipe( floating_cmp ); 8905%} 8906 8907instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{ 8908 match(Set dst (CmpD3 src1 src2)); 8909 effect(KILL fcc0); 8910 ins_cost(DEFAULT_COST*3+BRANCH_COST*3); 8911 format %{ "dcmpl $dst,$src1,$src2" %} 8912 // Primary = double (not float) 8913 opcode( false ); 8914 ins_encode( floating_cmp( dst, src1, src2 ) ); 8915 ins_pipe( floating_cmp ); 8916%} 8917 8918//----------Branches--------------------------------------------------------- 8919// Jump 8920// (compare 'operand indIndex' and 'instruct addP_reg_reg' above) 8921instruct jumpXtnd(iRegX switch_val, o7RegI table) %{ 8922 match(Jump switch_val); 8923 8924 ins_cost(350); 8925 8926 format %{ "SETHI [hi(table_base)],O7\n\t" 8927 "ADD O7, lo(table_base), O7\n\t" 8928 "LD [O7+$switch_val], O7\n\t" 8929 "JUMP O7" 8930 %} 8931 ins_encode( jump_enc( switch_val, table) ); 8932 ins_pc_relative(1); 8933 ins_pipe(ialu_reg_reg); 8934%} 8935 8936// Direct Branch. Use V8 version with longer range. 8937instruct branch(label labl) %{ 8938 match(Goto); 8939 effect(USE labl); 8940 8941 size(8); 8942 ins_cost(BRANCH_COST); 8943 format %{ "BA $labl" %} 8944 // Prim = bits 24-22, Secnd = bits 31-30, Tert = cond 8945 opcode(Assembler::br_op2, Assembler::branch_op, Assembler::always); 8946 ins_encode( enc_ba( labl ) ); 8947 ins_pc_relative(1); 8948 ins_pipe(br); 8949%} 8950 8951// Conditional Direct Branch 8952instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{ 8953 match(If cmp icc); 8954 effect(USE labl); 8955 8956 size(8); 8957 ins_cost(BRANCH_COST); 8958 format %{ "BP$cmp $icc,$labl" %} 8959 // Prim = bits 24-22, Secnd = bits 31-30 8960 ins_encode( enc_bp( labl, cmp, icc ) ); 8961 ins_pc_relative(1); 8962 ins_pipe(br_cc); 8963%} 8964 8965// Branch-on-register tests all 64 bits. We assume that values 8966// in 64-bit registers always remains zero or sign extended 8967// unless our code munges the high bits. Interrupts can chop 8968// the high order bits to zero or sign at any time. 8969instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{ 8970 match(If cmp (CmpI op1 zero)); 8971 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8972 effect(USE labl); 8973 8974 size(8); 8975 ins_cost(BRANCH_COST); 8976 format %{ "BR$cmp $op1,$labl" %} 8977 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8978 ins_pc_relative(1); 8979 ins_pipe(br_reg); 8980%} 8981 8982instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{ 8983 match(If cmp (CmpP op1 null)); 8984 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8985 effect(USE labl); 8986 8987 size(8); 8988 ins_cost(BRANCH_COST); 8989 format %{ "BR$cmp $op1,$labl" %} 8990 ins_encode( enc_bpr( labl, cmp, op1 ) ); 8991 ins_pc_relative(1); 8992 ins_pipe(br_reg); 8993%} 8994 8995instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{ 8996 match(If cmp (CmpL op1 zero)); 8997 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf)); 8998 effect(USE labl); 8999 9000 size(8); 9001 ins_cost(BRANCH_COST); 9002 format %{ "BR$cmp $op1,$labl" %} 9003 ins_encode( enc_bpr( labl, cmp, op1 ) ); 9004 ins_pc_relative(1); 9005 ins_pipe(br_reg); 9006%} 9007 9008instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9009 match(If cmp icc); 9010 effect(USE labl); 9011 9012 format %{ "BP$cmp $icc,$labl" %} 9013 // Prim = bits 24-22, Secnd = bits 31-30 9014 ins_encode( enc_bp( labl, cmp, icc ) ); 9015 ins_pc_relative(1); 9016 ins_pipe(br_cc); 9017%} 9018 9019instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{ 9020 match(If cmp pcc); 9021 effect(USE labl); 9022 9023 size(8); 9024 ins_cost(BRANCH_COST); 9025 format %{ "BP$cmp $pcc,$labl" %} 9026 // Prim = bits 24-22, Secnd = bits 31-30 9027 ins_encode( enc_bpx( labl, cmp, pcc ) ); 9028 ins_pc_relative(1); 9029 ins_pipe(br_cc); 9030%} 9031 9032instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{ 9033 match(If cmp fcc); 9034 effect(USE labl); 9035 9036 size(8); 9037 ins_cost(BRANCH_COST); 9038 format %{ "FBP$cmp $fcc,$labl" %} 9039 // Prim = bits 24-22, Secnd = bits 31-30 9040 ins_encode( enc_fbp( labl, cmp, fcc ) ); 9041 ins_pc_relative(1); 9042 ins_pipe(br_fcc); 9043%} 9044 9045instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{ 9046 match(CountedLoopEnd cmp icc); 9047 effect(USE labl); 9048 9049 size(8); 9050 ins_cost(BRANCH_COST); 9051 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9052 // Prim = bits 24-22, Secnd = bits 31-30 9053 ins_encode( enc_bp( labl, cmp, icc ) ); 9054 ins_pc_relative(1); 9055 ins_pipe(br_cc); 9056%} 9057 9058instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{ 9059 match(CountedLoopEnd cmp icc); 9060 effect(USE labl); 9061 9062 size(8); 9063 ins_cost(BRANCH_COST); 9064 format %{ "BP$cmp $icc,$labl\t! Loop end" %} 9065 // Prim = bits 24-22, Secnd = bits 31-30 9066 ins_encode( enc_bp( labl, cmp, icc ) ); 9067 ins_pc_relative(1); 9068 ins_pipe(br_cc); 9069%} 9070 9071// ============================================================================ 9072// Long Compare 9073// 9074// Currently we hold longs in 2 registers. Comparing such values efficiently 9075// is tricky. The flavor of compare used depends on whether we are testing 9076// for LT, LE, or EQ. For a simple LT test we can check just the sign bit. 9077// The GE test is the negated LT test. The LE test can be had by commuting 9078// the operands (yielding a GE test) and then negating; negate again for the 9079// GT test. The EQ test is done by ORcc'ing the high and low halves, and the 9080// NE test is negated from that. 9081 9082// Due to a shortcoming in the ADLC, it mixes up expressions like: 9083// (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the 9084// difference between 'Y' and '0L'. The tree-matches for the CmpI sections 9085// are collapsed internally in the ADLC's dfa-gen code. The match for 9086// (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the 9087// foo match ends up with the wrong leaf. One fix is to not match both 9088// reg-reg and reg-zero forms of long-compare. This is unfortunate because 9089// both forms beat the trinary form of long-compare and both are very useful 9090// on Intel which has so few registers. 9091 9092instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{ 9093 match(If cmp xcc); 9094 effect(USE labl); 9095 9096 size(8); 9097 ins_cost(BRANCH_COST); 9098 format %{ "BP$cmp $xcc,$labl" %} 9099 // Prim = bits 24-22, Secnd = bits 31-30 9100 ins_encode( enc_bpl( labl, cmp, xcc ) ); 9101 ins_pc_relative(1); 9102 ins_pipe(br_cc); 9103%} 9104 9105// Manifest a CmpL3 result in an integer register. Very painful. 9106// This is the test to avoid. 9107instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{ 9108 match(Set dst (CmpL3 src1 src2) ); 9109 effect( KILL ccr ); 9110 ins_cost(6*DEFAULT_COST); 9111 size(24); 9112 format %{ "CMP $src1,$src2\t\t! long\n" 9113 "\tBLT,a,pn done\n" 9114 "\tMOV -1,$dst\t! delay slot\n" 9115 "\tBGT,a,pn done\n" 9116 "\tMOV 1,$dst\t! delay slot\n" 9117 "\tCLR $dst\n" 9118 "done:" %} 9119 ins_encode( cmpl_flag(src1,src2,dst) ); 9120 ins_pipe(cmpL_reg); 9121%} 9122 9123// Conditional move 9124instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{ 9125 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9126 ins_cost(150); 9127 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9128 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9129 ins_pipe(ialu_reg); 9130%} 9131 9132instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{ 9133 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src))); 9134 ins_cost(140); 9135 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %} 9136 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9137 ins_pipe(ialu_imm); 9138%} 9139 9140instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{ 9141 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9142 ins_cost(150); 9143 format %{ "MOV$cmp $xcc,$src,$dst" %} 9144 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9145 ins_pipe(ialu_reg); 9146%} 9147 9148instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{ 9149 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src))); 9150 ins_cost(140); 9151 format %{ "MOV$cmp $xcc,$src,$dst" %} 9152 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9153 ins_pipe(ialu_imm); 9154%} 9155 9156instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{ 9157 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src))); 9158 ins_cost(150); 9159 format %{ "MOV$cmp $xcc,$src,$dst" %} 9160 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9161 ins_pipe(ialu_reg); 9162%} 9163 9164instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{ 9165 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9166 ins_cost(150); 9167 format %{ "MOV$cmp $xcc,$src,$dst" %} 9168 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) ); 9169 ins_pipe(ialu_reg); 9170%} 9171 9172instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{ 9173 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src))); 9174 ins_cost(140); 9175 format %{ "MOV$cmp $xcc,$src,$dst" %} 9176 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) ); 9177 ins_pipe(ialu_imm); 9178%} 9179 9180instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{ 9181 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src))); 9182 ins_cost(150); 9183 opcode(0x101); 9184 format %{ "FMOVS$cmp $xcc,$src,$dst" %} 9185 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9186 ins_pipe(int_conditional_float_move); 9187%} 9188 9189instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{ 9190 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src))); 9191 ins_cost(150); 9192 opcode(0x102); 9193 format %{ "FMOVD$cmp $xcc,$src,$dst" %} 9194 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) ); 9195 ins_pipe(int_conditional_float_move); 9196%} 9197 9198// ============================================================================ 9199// Safepoint Instruction 9200instruct safePoint_poll(iRegP poll) %{ 9201 match(SafePoint poll); 9202 effect(USE poll); 9203 9204 size(4); 9205#ifdef _LP64 9206 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %} 9207#else 9208 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %} 9209#endif 9210 ins_encode %{ 9211 __ relocate(relocInfo::poll_type); 9212 __ ld_ptr($poll$$Register, 0, G0); 9213 %} 9214 ins_pipe(loadPollP); 9215%} 9216 9217// ============================================================================ 9218// Call Instructions 9219// Call Java Static Instruction 9220instruct CallStaticJavaDirect( method meth ) %{ 9221 match(CallStaticJava); 9222 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9223 effect(USE meth); 9224 9225 size(8); 9226 ins_cost(CALL_COST); 9227 format %{ "CALL,static ; NOP ==> " %} 9228 ins_encode( Java_Static_Call( meth ), call_epilog ); 9229 ins_pc_relative(1); 9230 ins_pipe(simple_call); 9231%} 9232 9233// Call Java Static Instruction (method handle version) 9234instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{ 9235 match(CallStaticJava); 9236 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke()); 9237 effect(USE meth, KILL l7_mh_SP_save); 9238 9239 size(8); 9240 ins_cost(CALL_COST); 9241 format %{ "CALL,static/MethodHandle" %} 9242 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog); 9243 ins_pc_relative(1); 9244 ins_pipe(simple_call); 9245%} 9246 9247// Call Java Dynamic Instruction 9248instruct CallDynamicJavaDirect( method meth ) %{ 9249 match(CallDynamicJava); 9250 effect(USE meth); 9251 9252 ins_cost(CALL_COST); 9253 format %{ "SET (empty),R_G5\n\t" 9254 "CALL,dynamic ; NOP ==> " %} 9255 ins_encode( Java_Dynamic_Call( meth ), call_epilog ); 9256 ins_pc_relative(1); 9257 ins_pipe(call); 9258%} 9259 9260// Call Runtime Instruction 9261instruct CallRuntimeDirect(method meth, l7RegP l7) %{ 9262 match(CallRuntime); 9263 effect(USE meth, KILL l7); 9264 ins_cost(CALL_COST); 9265 format %{ "CALL,runtime" %} 9266 ins_encode( Java_To_Runtime( meth ), 9267 call_epilog, adjust_long_from_native_call ); 9268 ins_pc_relative(1); 9269 ins_pipe(simple_call); 9270%} 9271 9272// Call runtime without safepoint - same as CallRuntime 9273instruct CallLeafDirect(method meth, l7RegP l7) %{ 9274 match(CallLeaf); 9275 effect(USE meth, KILL l7); 9276 ins_cost(CALL_COST); 9277 format %{ "CALL,runtime leaf" %} 9278 ins_encode( Java_To_Runtime( meth ), 9279 call_epilog, 9280 adjust_long_from_native_call ); 9281 ins_pc_relative(1); 9282 ins_pipe(simple_call); 9283%} 9284 9285// Call runtime without safepoint - same as CallLeaf 9286instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{ 9287 match(CallLeafNoFP); 9288 effect(USE meth, KILL l7); 9289 ins_cost(CALL_COST); 9290 format %{ "CALL,runtime leaf nofp" %} 9291 ins_encode( Java_To_Runtime( meth ), 9292 call_epilog, 9293 adjust_long_from_native_call ); 9294 ins_pc_relative(1); 9295 ins_pipe(simple_call); 9296%} 9297 9298// Tail Call; Jump from runtime stub to Java code. 9299// Also known as an 'interprocedural jump'. 9300// Target of jump will eventually return to caller. 9301// TailJump below removes the return address. 9302instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{ 9303 match(TailCall jump_target method_oop ); 9304 9305 ins_cost(CALL_COST); 9306 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %} 9307 ins_encode(form_jmpl(jump_target)); 9308 ins_pipe(tail_call); 9309%} 9310 9311 9312// Return Instruction 9313instruct Ret() %{ 9314 match(Return); 9315 9316 // The epilogue node did the ret already. 9317 size(0); 9318 format %{ "! return" %} 9319 ins_encode(); 9320 ins_pipe(empty); 9321%} 9322 9323 9324// Tail Jump; remove the return address; jump to target. 9325// TailCall above leaves the return address around. 9326// TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 9327// ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 9328// "restore" before this instruction (in Epilogue), we need to materialize it 9329// in %i0. 9330instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{ 9331 match( TailJump jump_target ex_oop ); 9332 ins_cost(CALL_COST); 9333 format %{ "! discard R_O7\n\t" 9334 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %} 9335 ins_encode(form_jmpl_set_exception_pc(jump_target)); 9336 // opcode(Assembler::jmpl_op3, Assembler::arith_op); 9337 // The hack duplicates the exception oop into G3, so that CreateEx can use it there. 9338 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() ); 9339 ins_pipe(tail_call); 9340%} 9341 9342// Create exception oop: created by stack-crawling runtime code. 9343// Created exception is now available to this handler, and is setup 9344// just prior to jumping to this handler. No code emitted. 9345instruct CreateException( o0RegP ex_oop ) 9346%{ 9347 match(Set ex_oop (CreateEx)); 9348 ins_cost(0); 9349 9350 size(0); 9351 // use the following format syntax 9352 format %{ "! exception oop is in R_O0; no code emitted" %} 9353 ins_encode(); 9354 ins_pipe(empty); 9355%} 9356 9357 9358// Rethrow exception: 9359// The exception oop will come in the first argument position. 9360// Then JUMP (not call) to the rethrow stub code. 9361instruct RethrowException() 9362%{ 9363 match(Rethrow); 9364 ins_cost(CALL_COST); 9365 9366 // use the following format syntax 9367 format %{ "Jmp rethrow_stub" %} 9368 ins_encode(enc_rethrow); 9369 ins_pipe(tail_call); 9370%} 9371 9372 9373// Die now 9374instruct ShouldNotReachHere( ) 9375%{ 9376 match(Halt); 9377 ins_cost(CALL_COST); 9378 9379 size(4); 9380 // Use the following format syntax 9381 format %{ "ILLTRAP ; ShouldNotReachHere" %} 9382 ins_encode( form2_illtrap() ); 9383 ins_pipe(tail_call); 9384%} 9385 9386// ============================================================================ 9387// The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 9388// array for an instance of the superklass. Set a hidden internal cache on a 9389// hit (cache is checked with exposed code in gen_subtype_check()). Return 9390// not zero for a miss or zero for a hit. The encoding ALSO sets flags. 9391instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{ 9392 match(Set index (PartialSubtypeCheck sub super)); 9393 effect( KILL pcc, KILL o7 ); 9394 ins_cost(DEFAULT_COST*10); 9395 format %{ "CALL PartialSubtypeCheck\n\tNOP" %} 9396 ins_encode( enc_PartialSubtypeCheck() ); 9397 ins_pipe(partial_subtype_check_pipe); 9398%} 9399 9400instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{ 9401 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero)); 9402 effect( KILL idx, KILL o7 ); 9403 ins_cost(DEFAULT_COST*10); 9404 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %} 9405 ins_encode( enc_PartialSubtypeCheck() ); 9406 ins_pipe(partial_subtype_check_pipe); 9407%} 9408 9409 9410// ============================================================================ 9411// inlined locking and unlocking 9412 9413instruct cmpFastLock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9414 match(Set pcc (FastLock object box)); 9415 9416 effect(KILL scratch, TEMP scratch2); 9417 ins_cost(100); 9418 9419 size(4*112); // conservative overestimation ... 9420 format %{ "FASTLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9421 ins_encode( Fast_Lock(object, box, scratch, scratch2) ); 9422 ins_pipe(long_memory_op); 9423%} 9424 9425 9426instruct cmpFastUnlock(flagsRegP pcc, iRegP object, iRegP box, iRegP scratch2, o7RegP scratch ) %{ 9427 match(Set pcc (FastUnlock object box)); 9428 effect(KILL scratch, TEMP scratch2); 9429 ins_cost(100); 9430 9431 size(4*120); // conservative overestimation ... 9432 format %{ "FASTUNLOCK $object, $box; KILL $scratch, $scratch2, $box" %} 9433 ins_encode( Fast_Unlock(object, box, scratch, scratch2) ); 9434 ins_pipe(long_memory_op); 9435%} 9436 9437// Count and Base registers are fixed because the allocator cannot 9438// kill unknown registers. The encodings are generic. 9439instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{ 9440 match(Set dummy (ClearArray cnt base)); 9441 effect(TEMP temp, KILL ccr); 9442 ins_cost(300); 9443 format %{ "MOV $cnt,$temp\n" 9444 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n" 9445 " BRge loop\t\t! Clearing loop\n" 9446 " STX G0,[$base+$temp]\t! delay slot" %} 9447 ins_encode( enc_Clear_Array(cnt, base, temp) ); 9448 ins_pipe(long_memory_op); 9449%} 9450 9451instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result, 9452 o7RegI tmp, flagsReg ccr) %{ 9453 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 9454 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp); 9455 ins_cost(300); 9456 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %} 9457 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) ); 9458 ins_pipe(long_memory_op); 9459%} 9460 9461instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result, 9462 o7RegI tmp, flagsReg ccr) %{ 9463 match(Set result (StrEquals (Binary str1 str2) cnt)); 9464 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr); 9465 ins_cost(300); 9466 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %} 9467 ins_encode( enc_String_Equals(str1, str2, cnt, result) ); 9468 ins_pipe(long_memory_op); 9469%} 9470 9471instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result, 9472 o7RegI tmp2, flagsReg ccr) %{ 9473 match(Set result (AryEq ary1 ary2)); 9474 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr); 9475 ins_cost(300); 9476 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %} 9477 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result)); 9478 ins_pipe(long_memory_op); 9479%} 9480 9481 9482//---------- Zeros Count Instructions ------------------------------------------ 9483 9484instruct countLeadingZerosI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{ 9485 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9486 match(Set dst (CountLeadingZerosI src)); 9487 effect(TEMP dst, TEMP tmp, KILL cr); 9488 9489 // x |= (x >> 1); 9490 // x |= (x >> 2); 9491 // x |= (x >> 4); 9492 // x |= (x >> 8); 9493 // x |= (x >> 16); 9494 // return (WORDBITS - popc(x)); 9495 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t" 9496 "SRL $src,0,$dst\t! 32-bit zero extend\n\t" 9497 "OR $dst,$tmp,$dst\n\t" 9498 "SRL $dst,2,$tmp\n\t" 9499 "OR $dst,$tmp,$dst\n\t" 9500 "SRL $dst,4,$tmp\n\t" 9501 "OR $dst,$tmp,$dst\n\t" 9502 "SRL $dst,8,$tmp\n\t" 9503 "OR $dst,$tmp,$dst\n\t" 9504 "SRL $dst,16,$tmp\n\t" 9505 "OR $dst,$tmp,$dst\n\t" 9506 "POPC $dst,$dst\n\t" 9507 "MOV 32,$tmp\n\t" 9508 "SUB $tmp,$dst,$dst" %} 9509 ins_encode %{ 9510 Register Rdst = $dst$$Register; 9511 Register Rsrc = $src$$Register; 9512 Register Rtmp = $tmp$$Register; 9513 __ srl(Rsrc, 1, Rtmp); 9514 __ srl(Rsrc, 0, Rdst); 9515 __ or3(Rdst, Rtmp, Rdst); 9516 __ srl(Rdst, 2, Rtmp); 9517 __ or3(Rdst, Rtmp, Rdst); 9518 __ srl(Rdst, 4, Rtmp); 9519 __ or3(Rdst, Rtmp, Rdst); 9520 __ srl(Rdst, 8, Rtmp); 9521 __ or3(Rdst, Rtmp, Rdst); 9522 __ srl(Rdst, 16, Rtmp); 9523 __ or3(Rdst, Rtmp, Rdst); 9524 __ popc(Rdst, Rdst); 9525 __ mov(BitsPerInt, Rtmp); 9526 __ sub(Rtmp, Rdst, Rdst); 9527 %} 9528 ins_pipe(ialu_reg); 9529%} 9530 9531instruct countLeadingZerosL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{ 9532 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9533 match(Set dst (CountLeadingZerosL src)); 9534 effect(TEMP dst, TEMP tmp, KILL cr); 9535 9536 // x |= (x >> 1); 9537 // x |= (x >> 2); 9538 // x |= (x >> 4); 9539 // x |= (x >> 8); 9540 // x |= (x >> 16); 9541 // x |= (x >> 32); 9542 // return (WORDBITS - popc(x)); 9543 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t" 9544 "OR $src,$tmp,$dst\n\t" 9545 "SRLX $dst,2,$tmp\n\t" 9546 "OR $dst,$tmp,$dst\n\t" 9547 "SRLX $dst,4,$tmp\n\t" 9548 "OR $dst,$tmp,$dst\n\t" 9549 "SRLX $dst,8,$tmp\n\t" 9550 "OR $dst,$tmp,$dst\n\t" 9551 "SRLX $dst,16,$tmp\n\t" 9552 "OR $dst,$tmp,$dst\n\t" 9553 "SRLX $dst,32,$tmp\n\t" 9554 "OR $dst,$tmp,$dst\n\t" 9555 "POPC $dst,$dst\n\t" 9556 "MOV 64,$tmp\n\t" 9557 "SUB $tmp,$dst,$dst" %} 9558 ins_encode %{ 9559 Register Rdst = $dst$$Register; 9560 Register Rsrc = $src$$Register; 9561 Register Rtmp = $tmp$$Register; 9562 __ srlx(Rsrc, 1, Rtmp); 9563 __ or3(Rsrc, Rtmp, Rdst); 9564 __ srlx(Rdst, 2, Rtmp); 9565 __ or3(Rdst, Rtmp, Rdst); 9566 __ srlx(Rdst, 4, Rtmp); 9567 __ or3(Rdst, Rtmp, Rdst); 9568 __ srlx(Rdst, 8, Rtmp); 9569 __ or3(Rdst, Rtmp, Rdst); 9570 __ srlx(Rdst, 16, Rtmp); 9571 __ or3(Rdst, Rtmp, Rdst); 9572 __ srlx(Rdst, 32, Rtmp); 9573 __ or3(Rdst, Rtmp, Rdst); 9574 __ popc(Rdst, Rdst); 9575 __ mov(BitsPerLong, Rtmp); 9576 __ sub(Rtmp, Rdst, Rdst); 9577 %} 9578 ins_pipe(ialu_reg); 9579%} 9580 9581instruct countTrailingZerosI(iRegI dst, iRegI src, flagsReg cr) %{ 9582 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9583 match(Set dst (CountTrailingZerosI src)); 9584 effect(TEMP dst, KILL cr); 9585 9586 // return popc(~x & (x - 1)); 9587 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t" 9588 "ANDN $dst,$src,$dst\n\t" 9589 "SRL $dst,R_G0,$dst\n\t" 9590 "POPC $dst,$dst" %} 9591 ins_encode %{ 9592 Register Rdst = $dst$$Register; 9593 Register Rsrc = $src$$Register; 9594 __ sub(Rsrc, 1, Rdst); 9595 __ andn(Rdst, Rsrc, Rdst); 9596 __ srl(Rdst, G0, Rdst); 9597 __ popc(Rdst, Rdst); 9598 %} 9599 ins_pipe(ialu_reg); 9600%} 9601 9602instruct countTrailingZerosL(iRegI dst, iRegL src, flagsReg cr) %{ 9603 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported 9604 match(Set dst (CountTrailingZerosL src)); 9605 effect(TEMP dst, KILL cr); 9606 9607 // return popc(~x & (x - 1)); 9608 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t" 9609 "ANDN $dst,$src,$dst\n\t" 9610 "POPC $dst,$dst" %} 9611 ins_encode %{ 9612 Register Rdst = $dst$$Register; 9613 Register Rsrc = $src$$Register; 9614 __ sub(Rsrc, 1, Rdst); 9615 __ andn(Rdst, Rsrc, Rdst); 9616 __ popc(Rdst, Rdst); 9617 %} 9618 ins_pipe(ialu_reg); 9619%} 9620 9621 9622//---------- Population Count Instructions ------------------------------------- 9623 9624instruct popCountI(iRegI dst, iRegI src) %{ 9625 predicate(UsePopCountInstruction); 9626 match(Set dst (PopCountI src)); 9627 9628 format %{ "POPC $src, $dst" %} 9629 ins_encode %{ 9630 __ popc($src$$Register, $dst$$Register); 9631 %} 9632 ins_pipe(ialu_reg); 9633%} 9634 9635// Note: Long.bitCount(long) returns an int. 9636instruct popCountL(iRegI dst, iRegL src) %{ 9637 predicate(UsePopCountInstruction); 9638 match(Set dst (PopCountL src)); 9639 9640 format %{ "POPC $src, $dst" %} 9641 ins_encode %{ 9642 __ popc($src$$Register, $dst$$Register); 9643 %} 9644 ins_pipe(ialu_reg); 9645%} 9646 9647 9648// ============================================================================ 9649//------------Bytes reverse-------------------------------------------------- 9650 9651instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{ 9652 match(Set dst (ReverseBytesI src)); 9653 9654 // Op cost is artificially doubled to make sure that load or store 9655 // instructions are preferred over this one which requires a spill 9656 // onto a stack slot. 9657 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9658 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9659 9660 ins_encode %{ 9661 __ set($src$$disp + STACK_BIAS, O7); 9662 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9663 %} 9664 ins_pipe( iload_mem ); 9665%} 9666 9667instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{ 9668 match(Set dst (ReverseBytesL src)); 9669 9670 // Op cost is artificially doubled to make sure that load or store 9671 // instructions are preferred over this one which requires a spill 9672 // onto a stack slot. 9673 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9674 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9675 9676 ins_encode %{ 9677 __ set($src$$disp + STACK_BIAS, O7); 9678 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9679 %} 9680 ins_pipe( iload_mem ); 9681%} 9682 9683instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{ 9684 match(Set dst (ReverseBytesUS src)); 9685 9686 // Op cost is artificially doubled to make sure that load or store 9687 // instructions are preferred over this one which requires a spill 9688 // onto a stack slot. 9689 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9690 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %} 9691 9692 ins_encode %{ 9693 // the value was spilled as an int so bias the load 9694 __ set($src$$disp + STACK_BIAS + 2, O7); 9695 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9696 %} 9697 ins_pipe( iload_mem ); 9698%} 9699 9700instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{ 9701 match(Set dst (ReverseBytesS src)); 9702 9703 // Op cost is artificially doubled to make sure that load or store 9704 // instructions are preferred over this one which requires a spill 9705 // onto a stack slot. 9706 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST); 9707 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %} 9708 9709 ins_encode %{ 9710 // the value was spilled as an int so bias the load 9711 __ set($src$$disp + STACK_BIAS + 2, O7); 9712 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9713 %} 9714 ins_pipe( iload_mem ); 9715%} 9716 9717// Load Integer reversed byte order 9718instruct loadI_reversed(iRegI dst, indIndexMemory src) %{ 9719 match(Set dst (ReverseBytesI (LoadI src))); 9720 9721 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 9722 size(4); 9723 format %{ "LDUWA $src, $dst\t!asi=primary_little" %} 9724 9725 ins_encode %{ 9726 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9727 %} 9728 ins_pipe(iload_mem); 9729%} 9730 9731// Load Long - aligned and reversed 9732instruct loadL_reversed(iRegL dst, indIndexMemory src) %{ 9733 match(Set dst (ReverseBytesL (LoadL src))); 9734 9735 ins_cost(MEMORY_REF_COST); 9736 size(4); 9737 format %{ "LDXA $src, $dst\t!asi=primary_little" %} 9738 9739 ins_encode %{ 9740 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9741 %} 9742 ins_pipe(iload_mem); 9743%} 9744 9745// Load unsigned short / char reversed byte order 9746instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{ 9747 match(Set dst (ReverseBytesUS (LoadUS src))); 9748 9749 ins_cost(MEMORY_REF_COST); 9750 size(4); 9751 format %{ "LDUHA $src, $dst\t!asi=primary_little" %} 9752 9753 ins_encode %{ 9754 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9755 %} 9756 ins_pipe(iload_mem); 9757%} 9758 9759// Load short reversed byte order 9760instruct loadS_reversed(iRegI dst, indIndexMemory src) %{ 9761 match(Set dst (ReverseBytesS (LoadS src))); 9762 9763 ins_cost(MEMORY_REF_COST); 9764 size(4); 9765 format %{ "LDSHA $src, $dst\t!asi=primary_little" %} 9766 9767 ins_encode %{ 9768 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register); 9769 %} 9770 ins_pipe(iload_mem); 9771%} 9772 9773// Store Integer reversed byte order 9774instruct storeI_reversed(indIndexMemory dst, iRegI src) %{ 9775 match(Set dst (StoreI dst (ReverseBytesI src))); 9776 9777 ins_cost(MEMORY_REF_COST); 9778 size(4); 9779 format %{ "STWA $src, $dst\t!asi=primary_little" %} 9780 9781 ins_encode %{ 9782 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9783 %} 9784 ins_pipe(istore_mem_reg); 9785%} 9786 9787// Store Long reversed byte order 9788instruct storeL_reversed(indIndexMemory dst, iRegL src) %{ 9789 match(Set dst (StoreL dst (ReverseBytesL src))); 9790 9791 ins_cost(MEMORY_REF_COST); 9792 size(4); 9793 format %{ "STXA $src, $dst\t!asi=primary_little" %} 9794 9795 ins_encode %{ 9796 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9797 %} 9798 ins_pipe(istore_mem_reg); 9799%} 9800 9801// Store unsighed short/char reversed byte order 9802instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{ 9803 match(Set dst (StoreC dst (ReverseBytesUS src))); 9804 9805 ins_cost(MEMORY_REF_COST); 9806 size(4); 9807 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9808 9809 ins_encode %{ 9810 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9811 %} 9812 ins_pipe(istore_mem_reg); 9813%} 9814 9815// Store short reversed byte order 9816instruct storeS_reversed(indIndexMemory dst, iRegI src) %{ 9817 match(Set dst (StoreC dst (ReverseBytesS src))); 9818 9819 ins_cost(MEMORY_REF_COST); 9820 size(4); 9821 format %{ "STHA $src, $dst\t!asi=primary_little" %} 9822 9823 ins_encode %{ 9824 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE); 9825 %} 9826 ins_pipe(istore_mem_reg); 9827%} 9828 9829//----------PEEPHOLE RULES----------------------------------------------------- 9830// These must follow all instruction definitions as they use the names 9831// defined in the instructions definitions. 9832// 9833// peepmatch ( root_instr_name [preceding_instruction]* ); 9834// 9835// peepconstraint %{ 9836// (instruction_number.operand_name relational_op instruction_number.operand_name 9837// [, ...] ); 9838// // instruction numbers are zero-based using left to right order in peepmatch 9839// 9840// peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 9841// // provide an instruction_number.operand_name for each operand that appears 9842// // in the replacement instruction's match rule 9843// 9844// ---------VM FLAGS--------------------------------------------------------- 9845// 9846// All peephole optimizations can be turned off using -XX:-OptoPeephole 9847// 9848// Each peephole rule is given an identifying number starting with zero and 9849// increasing by one in the order seen by the parser. An individual peephole 9850// can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 9851// on the command-line. 9852// 9853// ---------CURRENT LIMITATIONS---------------------------------------------- 9854// 9855// Only match adjacent instructions in same basic block 9856// Only equality constraints 9857// Only constraints between operands, not (0.dest_reg == EAX_enc) 9858// Only one replacement instruction 9859// 9860// ---------EXAMPLE---------------------------------------------------------- 9861// 9862// // pertinent parts of existing instructions in architecture description 9863// instruct movI(eRegI dst, eRegI src) %{ 9864// match(Set dst (CopyI src)); 9865// %} 9866// 9867// instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 9868// match(Set dst (AddI dst src)); 9869// effect(KILL cr); 9870// %} 9871// 9872// // Change (inc mov) to lea 9873// peephole %{ 9874// // increment preceeded by register-register move 9875// peepmatch ( incI_eReg movI ); 9876// // require that the destination register of the increment 9877// // match the destination register of the move 9878// peepconstraint ( 0.dst == 1.dst ); 9879// // construct a replacement instruction that sets 9880// // the destination to ( move's source register + one ) 9881// peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) ); 9882// %} 9883// 9884 9885// // Change load of spilled value to only a spill 9886// instruct storeI(memory mem, eRegI src) %{ 9887// match(Set mem (StoreI mem src)); 9888// %} 9889// 9890// instruct loadI(eRegI dst, memory mem) %{ 9891// match(Set dst (LoadI mem)); 9892// %} 9893// 9894// peephole %{ 9895// peepmatch ( loadI storeI ); 9896// peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 9897// peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 9898// %} 9899 9900//----------SMARTSPILL RULES--------------------------------------------------- 9901// These must follow all instruction definitions as they use the names 9902// defined in the instructions definitions. 9903// 9904// SPARC will probably not have any of these rules due to RISC instruction set. 9905 9906//----------PIPELINE----------------------------------------------------------- 9907// Rules which define the behavior of the target architectures pipeline. 9908