c1_LIRAssembler_sparc.cpp revision 3602:da91efe96a93
1/* 2 * Copyright (c) 2000, 2012, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "c1/c1_Compilation.hpp" 27#include "c1/c1_LIRAssembler.hpp" 28#include "c1/c1_MacroAssembler.hpp" 29#include "c1/c1_Runtime1.hpp" 30#include "c1/c1_ValueStack.hpp" 31#include "ci/ciArrayKlass.hpp" 32#include "ci/ciInstance.hpp" 33#include "gc_interface/collectedHeap.hpp" 34#include "memory/barrierSet.hpp" 35#include "memory/cardTableModRefBS.hpp" 36#include "nativeInst_sparc.hpp" 37#include "oops/objArrayKlass.hpp" 38#include "runtime/sharedRuntime.hpp" 39 40#define __ _masm-> 41 42 43//------------------------------------------------------------ 44 45 46bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 47 if (opr->is_constant()) { 48 LIR_Const* constant = opr->as_constant_ptr(); 49 switch (constant->type()) { 50 case T_INT: { 51 jint value = constant->as_jint(); 52 return Assembler::is_simm13(value); 53 } 54 55 default: 56 return false; 57 } 58 } 59 return false; 60} 61 62 63bool LIR_Assembler::is_single_instruction(LIR_Op* op) { 64 switch (op->code()) { 65 case lir_null_check: 66 return true; 67 68 69 case lir_add: 70 case lir_ushr: 71 case lir_shr: 72 case lir_shl: 73 // integer shifts and adds are always one instruction 74 return op->result_opr()->is_single_cpu(); 75 76 77 case lir_move: { 78 LIR_Op1* op1 = op->as_Op1(); 79 LIR_Opr src = op1->in_opr(); 80 LIR_Opr dst = op1->result_opr(); 81 82 if (src == dst) { 83 NEEDS_CLEANUP; 84 // this works around a problem where moves with the same src and dst 85 // end up in the delay slot and then the assembler swallows the mov 86 // since it has no effect and then it complains because the delay slot 87 // is empty. returning false stops the optimizer from putting this in 88 // the delay slot 89 return false; 90 } 91 92 // don't put moves involving oops into the delay slot since the VerifyOops code 93 // will make it much larger than a single instruction. 94 if (VerifyOops) { 95 return false; 96 } 97 98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || 99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { 100 return false; 101 } 102 103 if (UseCompressedOops) { 104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; 105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; 106 } 107 108 if (dst->is_register()) { 109 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { 110 return !PatchALot; 111 } else if (src->is_single_stack()) { 112 return true; 113 } 114 } 115 116 if (src->is_register()) { 117 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { 118 return !PatchALot; 119 } else if (dst->is_single_stack()) { 120 return true; 121 } 122 } 123 124 if (dst->is_register() && 125 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || 126 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { 127 return true; 128 } 129 130 return false; 131 } 132 133 default: 134 return false; 135 } 136 ShouldNotReachHere(); 137} 138 139 140LIR_Opr LIR_Assembler::receiverOpr() { 141 return FrameMap::O0_oop_opr; 142} 143 144 145LIR_Opr LIR_Assembler::osrBufferPointer() { 146 return FrameMap::I0_opr; 147} 148 149 150int LIR_Assembler::initial_frame_size_in_bytes() { 151 return in_bytes(frame_map()->framesize_in_bytes()); 152} 153 154 155// inline cache check: the inline cached class is in G5_inline_cache_reg(G5); 156// we fetch the class of the receiver (O0) and compare it with the cached class. 157// If they do not match we jump to slow case. 158int LIR_Assembler::check_icache() { 159 int offset = __ offset(); 160 __ inline_cache_check(O0, G5_inline_cache_reg); 161 return offset; 162} 163 164 165void LIR_Assembler::osr_entry() { 166 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 167 // 168 // 1. Create a new compiled activation. 169 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 170 // at the osr_bci; it is not initialized. 171 // 3. Jump to the continuation address in compiled code to resume execution. 172 173 // OSR entry point 174 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 175 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 176 ValueStack* entry_state = osr_entry->end()->state(); 177 int number_of_locks = entry_state->locks_size(); 178 179 // Create a frame for the compiled activation. 180 __ build_frame(initial_frame_size_in_bytes()); 181 182 // OSR buffer is 183 // 184 // locals[nlocals-1..0] 185 // monitors[number_of_locks-1..0] 186 // 187 // locals is a direct copy of the interpreter frame so in the osr buffer 188 // so first slot in the local array is the last local from the interpreter 189 // and last slot is local[0] (receiver) from the interpreter 190 // 191 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 192 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 193 // in the interpreter frame (the method lock if a sync method) 194 195 // Initialize monitors in the compiled activation. 196 // I0: pointer to osr buffer 197 // 198 // All other registers are dead at this point and the locals will be 199 // copied into place by code emitted in the IR. 200 201 Register OSR_buf = osrBufferPointer()->as_register(); 202 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 203 int monitor_offset = BytesPerWord * method()->max_locals() + 204 (2 * BytesPerWord) * (number_of_locks - 1); 205 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 206 // the OSR buffer using 2 word entries: first the lock and then 207 // the oop. 208 for (int i = 0; i < number_of_locks; i++) { 209 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 210#ifdef ASSERT 211 // verify the interpreter's monitor has a non-null object 212 { 213 Label L; 214 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 215 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L); 216 __ stop("locked object is NULL"); 217 __ bind(L); 218 } 219#endif // ASSERT 220 // Copy the lock field into the compiled activation. 221 __ ld_ptr(OSR_buf, slot_offset + 0, O7); 222 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); 223 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 224 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); 225 } 226 } 227} 228 229 230// Optimized Library calls 231// This is the fast version of java.lang.String.compare; it has not 232// OSR-entry and therefore, we generate a slow version for OSR's 233void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { 234 Register str0 = left->as_register(); 235 Register str1 = right->as_register(); 236 237 Label Ldone; 238 239 Register result = dst->as_register(); 240 { 241 // Get a pointer to the first character of string0 in tmp0 242 // and get string0.length() in str0 243 // Get a pointer to the first character of string1 in tmp1 244 // and get string1.length() in str1 245 // Also, get string0.length()-string1.length() in 246 // o7 and get the condition code set 247 // Note: some instructions have been hoisted for better instruction scheduling 248 249 Register tmp0 = L0; 250 Register tmp1 = L1; 251 Register tmp2 = L2; 252 253 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array 254 if (java_lang_String::has_offset_field()) { 255 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position 256 int count_offset = java_lang_String:: count_offset_in_bytes(); 257 __ load_heap_oop(str0, value_offset, tmp0); 258 __ ld(str0, offset_offset, tmp2); 259 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); 260 __ ld(str0, count_offset, str0); 261 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 262 } else { 263 __ load_heap_oop(str0, value_offset, tmp1); 264 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); 265 __ ld(tmp1, arrayOopDesc::length_offset_in_bytes(), str0); 266 } 267 268 // str1 may be null 269 add_debug_info_for_null_check_here(info); 270 271 if (java_lang_String::has_offset_field()) { 272 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position 273 int count_offset = java_lang_String:: count_offset_in_bytes(); 274 __ load_heap_oop(str1, value_offset, tmp1); 275 __ add(tmp0, tmp2, tmp0); 276 277 __ ld(str1, offset_offset, tmp2); 278 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); 279 __ ld(str1, count_offset, str1); 280 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 281 __ add(tmp1, tmp2, tmp1); 282 } else { 283 __ load_heap_oop(str1, value_offset, tmp2); 284 __ add(tmp2, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); 285 __ ld(tmp2, arrayOopDesc::length_offset_in_bytes(), str1); 286 } 287 __ subcc(str0, str1, O7); 288 } 289 290 { 291 // Compute the minimum of the string lengths, scale it and store it in limit 292 Register count0 = I0; 293 Register count1 = I1; 294 Register limit = L3; 295 296 Label Lskip; 297 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter 298 __ br(Assembler::greater, true, Assembler::pt, Lskip); 299 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter 300 __ bind(Lskip); 301 302 // If either string is empty (or both of them) the result is the difference in lengths 303 __ cmp(limit, 0); 304 __ br(Assembler::equal, true, Assembler::pn, Ldone); 305 __ delayed()->mov(O7, result); // result is difference in lengths 306 } 307 308 { 309 // Neither string is empty 310 Label Lloop; 311 312 Register base0 = L0; 313 Register base1 = L1; 314 Register chr0 = I0; 315 Register chr1 = I1; 316 Register limit = L3; 317 318 // Shift base0 and base1 to the end of the arrays, negate limit 319 __ add(base0, limit, base0); 320 __ add(base1, limit, base1); 321 __ neg(limit); // limit = -min{string0.length(), string1.length()} 322 323 __ lduh(base0, limit, chr0); 324 __ bind(Lloop); 325 __ lduh(base1, limit, chr1); 326 __ subcc(chr0, chr1, chr0); 327 __ br(Assembler::notZero, false, Assembler::pn, Ldone); 328 assert(chr0 == result, "result must be pre-placed"); 329 __ delayed()->inccc(limit, sizeof(jchar)); 330 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 331 __ delayed()->lduh(base0, limit, chr0); 332 } 333 334 // If strings are equal up to min length, return the length difference. 335 __ mov(O7, result); 336 337 // Otherwise, return the difference between the first mismatched chars. 338 __ bind(Ldone); 339} 340 341 342// -------------------------------------------------------------------------------------------- 343 344void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { 345 if (!GenerateSynchronizationCode) return; 346 347 Register obj_reg = obj_opr->as_register(); 348 Register lock_reg = lock_opr->as_register(); 349 350 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 351 Register reg = mon_addr.base(); 352 int offset = mon_addr.disp(); 353 // compute pointer to BasicLock 354 if (mon_addr.is_simm13()) { 355 __ add(reg, offset, lock_reg); 356 } 357 else { 358 __ set(offset, lock_reg); 359 __ add(reg, lock_reg, lock_reg); 360 } 361 // unlock object 362 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); 363 // _slow_case_stubs->append(slow_case); 364 // temporary fix: must be created after exceptionhandler, therefore as call stub 365 _slow_case_stubs->append(slow_case); 366 if (UseFastLocking) { 367 // try inlined fast unlocking first, revert to slow locking if it fails 368 // note: lock_reg points to the displaced header since the displaced header offset is 0! 369 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 370 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 371 } else { 372 // always do slow unlocking 373 // note: the slow unlocking code could be inlined here, however if we use 374 // slow unlocking, speed doesn't matter anyway and this solution is 375 // simpler and requires less duplicated code - additionally, the 376 // slow unlocking code is the same in either case which simplifies 377 // debugging 378 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); 379 __ delayed()->nop(); 380 } 381 // done 382 __ bind(*slow_case->continuation()); 383} 384 385 386int LIR_Assembler::emit_exception_handler() { 387 // if the last instruction is a call (typically to do a throw which 388 // is coming at the end after block reordering) the return address 389 // must still point into the code area in order to avoid assertion 390 // failures when searching for the corresponding bci => add a nop 391 // (was bug 5/14/1999 - gri) 392 __ nop(); 393 394 // generate code for exception handler 395 ciMethod* method = compilation()->method(); 396 397 address handler_base = __ start_a_stub(exception_handler_size); 398 399 if (handler_base == NULL) { 400 // not enough space left for the handler 401 bailout("exception handler overflow"); 402 return -1; 403 } 404 405 int offset = code_offset(); 406 407 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); 408 __ delayed()->nop(); 409 __ should_not_reach_here(); 410 guarantee(code_offset() - offset <= exception_handler_size, "overflow"); 411 __ end_a_stub(); 412 413 return offset; 414} 415 416 417// Emit the code to remove the frame from the stack in the exception 418// unwind path. 419int LIR_Assembler::emit_unwind_handler() { 420#ifndef PRODUCT 421 if (CommentedAssembly) { 422 _masm->block_comment("Unwind handler"); 423 } 424#endif 425 426 int offset = code_offset(); 427 428 // Fetch the exception from TLS and clear out exception related thread state 429 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); 430 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 431 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); 432 433 __ bind(_unwind_handler_entry); 434 __ verify_not_null_oop(O0); 435 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 436 __ mov(O0, I0); // Preserve the exception 437 } 438 439 // Preform needed unlocking 440 MonitorExitStub* stub = NULL; 441 if (method()->is_synchronized()) { 442 monitor_address(0, FrameMap::I1_opr); 443 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); 444 __ unlock_object(I3, I2, I1, *stub->entry()); 445 __ bind(*stub->continuation()); 446 } 447 448 if (compilation()->env()->dtrace_method_probes()) { 449 __ mov(G2_thread, O0); 450 metadata2reg(method()->constant_encoding(), O1); 451 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); 452 __ delayed()->nop(); 453 } 454 455 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 456 __ mov(I0, O0); // Restore the exception 457 } 458 459 // dispatch to the unwind logic 460 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 461 __ delayed()->nop(); 462 463 // Emit the slow path assembly 464 if (stub != NULL) { 465 stub->emit_code(this); 466 } 467 468 return offset; 469} 470 471 472int LIR_Assembler::emit_deopt_handler() { 473 // if the last instruction is a call (typically to do a throw which 474 // is coming at the end after block reordering) the return address 475 // must still point into the code area in order to avoid assertion 476 // failures when searching for the corresponding bci => add a nop 477 // (was bug 5/14/1999 - gri) 478 __ nop(); 479 480 // generate code for deopt handler 481 ciMethod* method = compilation()->method(); 482 address handler_base = __ start_a_stub(deopt_handler_size); 483 if (handler_base == NULL) { 484 // not enough space left for the handler 485 bailout("deopt handler overflow"); 486 return -1; 487 } 488 489 int offset = code_offset(); 490 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 491 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp 492 __ delayed()->nop(); 493 guarantee(code_offset() - offset <= deopt_handler_size, "overflow"); 494 __ end_a_stub(); 495 496 return offset; 497} 498 499 500void LIR_Assembler::jobject2reg(jobject o, Register reg) { 501 if (o == NULL) { 502 __ set(NULL_WORD, reg); 503 } else { 504 int oop_index = __ oop_recorder()->find_index(o); 505 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop"); 506 RelocationHolder rspec = oop_Relocation::spec(oop_index); 507 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created 508 } 509} 510 511 512void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 513 // Allocate a new index in table to hold the object once it's been patched 514 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 515 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_mirror_id, oop_index); 516 517 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); 518 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 519 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 520 // NULL will be dynamically patched later and the patched value may be large. We must 521 // therefore generate the sethi/add as a placeholders 522 __ patchable_set(addrlit, reg); 523 524 patching_epilog(patch, lir_patch_normal, reg, info); 525} 526 527 528void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 529 __ set_metadata_constant(o, reg); 530} 531 532void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 533 // Allocate a new index in table to hold the klass once it's been patched 534 int index = __ oop_recorder()->allocate_metadata_index(NULL); 535 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 536 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index)); 537 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 538 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 539 // NULL will be dynamically patched later and the patched value may be large. We must 540 // therefore generate the sethi/add as a placeholders 541 __ patchable_set(addrlit, reg); 542 543 patching_epilog(patch, lir_patch_normal, reg, info); 544} 545 546void LIR_Assembler::emit_op3(LIR_Op3* op) { 547 Register Rdividend = op->in_opr1()->as_register(); 548 Register Rdivisor = noreg; 549 Register Rscratch = op->in_opr3()->as_register(); 550 Register Rresult = op->result_opr()->as_register(); 551 int divisor = -1; 552 553 if (op->in_opr2()->is_register()) { 554 Rdivisor = op->in_opr2()->as_register(); 555 } else { 556 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); 557 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 558 } 559 560 assert(Rdividend != Rscratch, ""); 561 assert(Rdivisor != Rscratch, ""); 562 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); 563 564 if (Rdivisor == noreg && is_power_of_2(divisor)) { 565 // convert division by a power of two into some shifts and logical operations 566 if (op->code() == lir_idiv) { 567 if (divisor == 2) { 568 __ srl(Rdividend, 31, Rscratch); 569 } else { 570 __ sra(Rdividend, 31, Rscratch); 571 __ and3(Rscratch, divisor - 1, Rscratch); 572 } 573 __ add(Rdividend, Rscratch, Rscratch); 574 __ sra(Rscratch, log2_intptr(divisor), Rresult); 575 return; 576 } else { 577 if (divisor == 2) { 578 __ srl(Rdividend, 31, Rscratch); 579 } else { 580 __ sra(Rdividend, 31, Rscratch); 581 __ and3(Rscratch, divisor - 1,Rscratch); 582 } 583 __ add(Rdividend, Rscratch, Rscratch); 584 __ andn(Rscratch, divisor - 1,Rscratch); 585 __ sub(Rdividend, Rscratch, Rresult); 586 return; 587 } 588 } 589 590 __ sra(Rdividend, 31, Rscratch); 591 __ wry(Rscratch); 592 if (!VM_Version::v9_instructions_work()) { 593 // v9 doesn't require these nops 594 __ nop(); 595 __ nop(); 596 __ nop(); 597 __ nop(); 598 } 599 600 add_debug_info_for_div0_here(op->info()); 601 602 if (Rdivisor != noreg) { 603 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 604 } else { 605 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 606 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 607 } 608 609 Label skip; 610 __ br(Assembler::overflowSet, true, Assembler::pn, skip); 611 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); 612 __ bind(skip); 613 614 if (op->code() == lir_irem) { 615 if (Rdivisor != noreg) { 616 __ smul(Rscratch, Rdivisor, Rscratch); 617 } else { 618 __ smul(Rscratch, divisor, Rscratch); 619 } 620 __ sub(Rdividend, Rscratch, Rresult); 621 } 622} 623 624 625void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 626#ifdef ASSERT 627 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 628 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 629 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 630#endif 631 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 632 633 if (op->cond() == lir_cond_always) { 634 __ br(Assembler::always, false, Assembler::pt, *(op->label())); 635 } else if (op->code() == lir_cond_float_branch) { 636 assert(op->ublock() != NULL, "must have unordered successor"); 637 bool is_unordered = (op->ublock() == op->block()); 638 Assembler::Condition acond; 639 switch (op->cond()) { 640 case lir_cond_equal: acond = Assembler::f_equal; break; 641 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; 642 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; 643 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; 644 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; 645 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; 646 default : ShouldNotReachHere(); 647 }; 648 649 if (!VM_Version::v9_instructions_work()) { 650 __ nop(); 651 } 652 __ fb( acond, false, Assembler::pn, *(op->label())); 653 } else { 654 assert (op->code() == lir_branch, "just checking"); 655 656 Assembler::Condition acond; 657 switch (op->cond()) { 658 case lir_cond_equal: acond = Assembler::equal; break; 659 case lir_cond_notEqual: acond = Assembler::notEqual; break; 660 case lir_cond_less: acond = Assembler::less; break; 661 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 662 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 663 case lir_cond_greater: acond = Assembler::greater; break; 664 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 665 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 666 default: ShouldNotReachHere(); 667 }; 668 669 // sparc has different condition codes for testing 32-bit 670 // vs. 64-bit values. We could always test xcc is we could 671 // guarantee that 32-bit loads always sign extended but that isn't 672 // true and since sign extension isn't free, it would impose a 673 // slight cost. 674#ifdef _LP64 675 if (op->type() == T_INT) { 676 __ br(acond, false, Assembler::pn, *(op->label())); 677 } else 678#endif 679 __ brx(acond, false, Assembler::pn, *(op->label())); 680 } 681 // The peephole pass fills the delay slot 682} 683 684 685void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 686 Bytecodes::Code code = op->bytecode(); 687 LIR_Opr dst = op->result_opr(); 688 689 switch(code) { 690 case Bytecodes::_i2l: { 691 Register rlo = dst->as_register_lo(); 692 Register rhi = dst->as_register_hi(); 693 Register rval = op->in_opr()->as_register(); 694#ifdef _LP64 695 __ sra(rval, 0, rlo); 696#else 697 __ mov(rval, rlo); 698 __ sra(rval, BitsPerInt-1, rhi); 699#endif 700 break; 701 } 702 case Bytecodes::_i2d: 703 case Bytecodes::_i2f: { 704 bool is_double = (code == Bytecodes::_i2d); 705 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 706 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 707 FloatRegister rsrc = op->in_opr()->as_float_reg(); 708 if (rsrc != rdst) { 709 __ fmov(FloatRegisterImpl::S, rsrc, rdst); 710 } 711 __ fitof(w, rdst, rdst); 712 break; 713 } 714 case Bytecodes::_f2i:{ 715 FloatRegister rsrc = op->in_opr()->as_float_reg(); 716 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); 717 Label L; 718 // result must be 0 if value is NaN; test by comparing value to itself 719 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); 720 if (!VM_Version::v9_instructions_work()) { 721 __ nop(); 722 } 723 __ fb(Assembler::f_unordered, true, Assembler::pn, L); 724 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN 725 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); 726 // move integer result from float register to int register 727 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); 728 __ bind (L); 729 break; 730 } 731 case Bytecodes::_l2i: { 732 Register rlo = op->in_opr()->as_register_lo(); 733 Register rhi = op->in_opr()->as_register_hi(); 734 Register rdst = dst->as_register(); 735#ifdef _LP64 736 __ sra(rlo, 0, rdst); 737#else 738 __ mov(rlo, rdst); 739#endif 740 break; 741 } 742 case Bytecodes::_d2f: 743 case Bytecodes::_f2d: { 744 bool is_double = (code == Bytecodes::_f2d); 745 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); 746 LIR_Opr val = op->in_opr(); 747 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); 748 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 749 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; 750 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 751 __ ftof(vw, dw, rval, rdst); 752 break; 753 } 754 case Bytecodes::_i2s: 755 case Bytecodes::_i2b: { 756 Register rval = op->in_opr()->as_register(); 757 Register rdst = dst->as_register(); 758 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); 759 __ sll (rval, shift, rdst); 760 __ sra (rdst, shift, rdst); 761 break; 762 } 763 case Bytecodes::_i2c: { 764 Register rval = op->in_opr()->as_register(); 765 Register rdst = dst->as_register(); 766 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; 767 __ sll (rval, shift, rdst); 768 __ srl (rdst, shift, rdst); 769 break; 770 } 771 772 default: ShouldNotReachHere(); 773 } 774} 775 776 777void LIR_Assembler::align_call(LIR_Code) { 778 // do nothing since all instructions are word aligned on sparc 779} 780 781 782void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 783 __ call(op->addr(), rtype); 784 // The peephole pass fills the delay slot, add_call_info is done in 785 // LIR_Assembler::emit_delay. 786} 787 788 789void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 790 __ ic_call(op->addr(), false); 791 // The peephole pass fills the delay slot, add_call_info is done in 792 // LIR_Assembler::emit_delay. 793} 794 795 796void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 797 add_debug_info_for_null_check_here(op->info()); 798 __ load_klass(O0, G3_scratch); 799 if (Assembler::is_simm13(op->vtable_offset())) { 800 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); 801 } else { 802 // This will generate 2 instructions 803 __ set(op->vtable_offset(), G5_method); 804 // ld_ptr, set_hi, set 805 __ ld_ptr(G3_scratch, G5_method, G5_method); 806 } 807 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch); 808 __ callr(G3_scratch, G0); 809 // the peephole pass fills the delay slot 810} 811 812int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { 813 int store_offset; 814 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 815 assert(!unaligned, "can't handle this"); 816 // for offsets larger than a simm13 we setup the offset in O7 817 __ set(offset, O7); 818 store_offset = store(from_reg, base, O7, type, wide); 819 } else { 820 if (type == T_ARRAY || type == T_OBJECT) { 821 __ verify_oop(from_reg->as_register()); 822 } 823 store_offset = code_offset(); 824 switch (type) { 825 case T_BOOLEAN: // fall through 826 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; 827 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; 828 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; 829 case T_INT : __ stw(from_reg->as_register(), base, offset); break; 830 case T_LONG : 831#ifdef _LP64 832 if (unaligned || PatchALot) { 833 __ srax(from_reg->as_register_lo(), 32, O7); 834 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 835 __ stw(O7, base, offset + hi_word_offset_in_bytes); 836 } else { 837 __ stx(from_reg->as_register_lo(), base, offset); 838 } 839#else 840 assert(Assembler::is_simm13(offset + 4), "must be"); 841 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 842 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); 843#endif 844 break; 845 case T_ADDRESS: 846 __ st_ptr(from_reg->as_register(), base, offset); 847 break; 848 case T_ARRAY : // fall through 849 case T_OBJECT: 850 { 851 if (UseCompressedOops && !wide) { 852 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 853 store_offset = code_offset(); 854 __ stw(G3_scratch, base, offset); 855 } else { 856 __ st_ptr(from_reg->as_register(), base, offset); 857 } 858 break; 859 } 860 861 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; 862 case T_DOUBLE: 863 { 864 FloatRegister reg = from_reg->as_double_reg(); 865 // split unaligned stores 866 if (unaligned || PatchALot) { 867 assert(Assembler::is_simm13(offset + 4), "must be"); 868 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); 869 __ stf(FloatRegisterImpl::S, reg, base, offset); 870 } else { 871 __ stf(FloatRegisterImpl::D, reg, base, offset); 872 } 873 break; 874 } 875 default : ShouldNotReachHere(); 876 } 877 } 878 return store_offset; 879} 880 881 882int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 883 if (type == T_ARRAY || type == T_OBJECT) { 884 __ verify_oop(from_reg->as_register()); 885 } 886 int store_offset = code_offset(); 887 switch (type) { 888 case T_BOOLEAN: // fall through 889 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; 890 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; 891 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; 892 case T_INT : __ stw(from_reg->as_register(), base, disp); break; 893 case T_LONG : 894#ifdef _LP64 895 __ stx(from_reg->as_register_lo(), base, disp); 896#else 897 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); 898 __ std(from_reg->as_register_hi(), base, disp); 899#endif 900 break; 901 case T_ADDRESS: 902 __ st_ptr(from_reg->as_register(), base, disp); 903 break; 904 case T_ARRAY : // fall through 905 case T_OBJECT: 906 { 907 if (UseCompressedOops && !wide) { 908 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 909 store_offset = code_offset(); 910 __ stw(G3_scratch, base, disp); 911 } else { 912 __ st_ptr(from_reg->as_register(), base, disp); 913 } 914 break; 915 } 916 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; 917 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; 918 default : ShouldNotReachHere(); 919 } 920 return store_offset; 921} 922 923 924int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { 925 int load_offset; 926 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 927 assert(base != O7, "destroying register"); 928 assert(!unaligned, "can't handle this"); 929 // for offsets larger than a simm13 we setup the offset in O7 930 __ set(offset, O7); 931 load_offset = load(base, O7, to_reg, type, wide); 932 } else { 933 load_offset = code_offset(); 934 switch(type) { 935 case T_BOOLEAN: // fall through 936 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; 937 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; 938 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; 939 case T_INT : __ ld(base, offset, to_reg->as_register()); break; 940 case T_LONG : 941 if (!unaligned) { 942#ifdef _LP64 943 __ ldx(base, offset, to_reg->as_register_lo()); 944#else 945 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 946 "must be sequential"); 947 __ ldd(base, offset, to_reg->as_register_hi()); 948#endif 949 } else { 950#ifdef _LP64 951 assert(base != to_reg->as_register_lo(), "can't handle this"); 952 assert(O7 != to_reg->as_register_lo(), "can't handle this"); 953 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); 954 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last 955 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); 956 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); 957#else 958 if (base == to_reg->as_register_lo()) { 959 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 960 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 961 } else { 962 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 963 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 964 } 965#endif 966 } 967 break; 968 case T_ADDRESS: __ ld_ptr(base, offset, to_reg->as_register()); break; 969 case T_ARRAY : // fall through 970 case T_OBJECT: 971 { 972 if (UseCompressedOops && !wide) { 973 __ lduw(base, offset, to_reg->as_register()); 974 __ decode_heap_oop(to_reg->as_register()); 975 } else { 976 __ ld_ptr(base, offset, to_reg->as_register()); 977 } 978 break; 979 } 980 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; 981 case T_DOUBLE: 982 { 983 FloatRegister reg = to_reg->as_double_reg(); 984 // split unaligned loads 985 if (unaligned || PatchALot) { 986 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); 987 __ ldf(FloatRegisterImpl::S, base, offset, reg); 988 } else { 989 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); 990 } 991 break; 992 } 993 default : ShouldNotReachHere(); 994 } 995 if (type == T_ARRAY || type == T_OBJECT) { 996 __ verify_oop(to_reg->as_register()); 997 } 998 } 999 return load_offset; 1000} 1001 1002 1003int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 1004 int load_offset = code_offset(); 1005 switch(type) { 1006 case T_BOOLEAN: // fall through 1007 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; 1008 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; 1009 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; 1010 case T_INT : __ ld(base, disp, to_reg->as_register()); break; 1011 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; 1012 case T_ARRAY : // fall through 1013 case T_OBJECT: 1014 { 1015 if (UseCompressedOops && !wide) { 1016 __ lduw(base, disp, to_reg->as_register()); 1017 __ decode_heap_oop(to_reg->as_register()); 1018 } else { 1019 __ ld_ptr(base, disp, to_reg->as_register()); 1020 } 1021 break; 1022 } 1023 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; 1024 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; 1025 case T_LONG : 1026#ifdef _LP64 1027 __ ldx(base, disp, to_reg->as_register_lo()); 1028#else 1029 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 1030 "must be sequential"); 1031 __ ldd(base, disp, to_reg->as_register_hi()); 1032#endif 1033 break; 1034 default : ShouldNotReachHere(); 1035 } 1036 if (type == T_ARRAY || type == T_OBJECT) { 1037 __ verify_oop(to_reg->as_register()); 1038 } 1039 return load_offset; 1040} 1041 1042void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 1043 LIR_Const* c = src->as_constant_ptr(); 1044 switch (c->type()) { 1045 case T_INT: 1046 case T_FLOAT: { 1047 Register src_reg = O7; 1048 int value = c->as_jint_bits(); 1049 if (value == 0) { 1050 src_reg = G0; 1051 } else { 1052 __ set(value, O7); 1053 } 1054 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1055 __ stw(src_reg, addr.base(), addr.disp()); 1056 break; 1057 } 1058 case T_ADDRESS: { 1059 Register src_reg = O7; 1060 int value = c->as_jint_bits(); 1061 if (value == 0) { 1062 src_reg = G0; 1063 } else { 1064 __ set(value, O7); 1065 } 1066 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1067 __ st_ptr(src_reg, addr.base(), addr.disp()); 1068 break; 1069 } 1070 case T_OBJECT: { 1071 Register src_reg = O7; 1072 jobject2reg(c->as_jobject(), src_reg); 1073 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1074 __ st_ptr(src_reg, addr.base(), addr.disp()); 1075 break; 1076 } 1077 case T_LONG: 1078 case T_DOUBLE: { 1079 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1080 1081 Register tmp = O7; 1082 int value_lo = c->as_jint_lo_bits(); 1083 if (value_lo == 0) { 1084 tmp = G0; 1085 } else { 1086 __ set(value_lo, O7); 1087 } 1088 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); 1089 int value_hi = c->as_jint_hi_bits(); 1090 if (value_hi == 0) { 1091 tmp = G0; 1092 } else { 1093 __ set(value_hi, O7); 1094 } 1095 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); 1096 break; 1097 } 1098 default: 1099 Unimplemented(); 1100 } 1101} 1102 1103 1104void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 1105 LIR_Const* c = src->as_constant_ptr(); 1106 LIR_Address* addr = dest->as_address_ptr(); 1107 Register base = addr->base()->as_pointer_register(); 1108 int offset = -1; 1109 1110 switch (c->type()) { 1111 case T_INT: 1112 case T_FLOAT: 1113 case T_ADDRESS: { 1114 LIR_Opr tmp = FrameMap::O7_opr; 1115 int value = c->as_jint_bits(); 1116 if (value == 0) { 1117 tmp = FrameMap::G0_opr; 1118 } else if (Assembler::is_simm13(value)) { 1119 __ set(value, O7); 1120 } 1121 if (addr->index()->is_valid()) { 1122 assert(addr->disp() == 0, "must be zero"); 1123 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1124 } else { 1125 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1126 offset = store(tmp, base, addr->disp(), type, wide, false); 1127 } 1128 break; 1129 } 1130 case T_LONG: 1131 case T_DOUBLE: { 1132 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); 1133 assert(Assembler::is_simm13(addr->disp()) && 1134 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); 1135 1136 LIR_Opr tmp = FrameMap::O7_opr; 1137 int value_lo = c->as_jint_lo_bits(); 1138 if (value_lo == 0) { 1139 tmp = FrameMap::G0_opr; 1140 } else { 1141 __ set(value_lo, O7); 1142 } 1143 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); 1144 int value_hi = c->as_jint_hi_bits(); 1145 if (value_hi == 0) { 1146 tmp = FrameMap::G0_opr; 1147 } else { 1148 __ set(value_hi, O7); 1149 } 1150 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); 1151 break; 1152 } 1153 case T_OBJECT: { 1154 jobject obj = c->as_jobject(); 1155 LIR_Opr tmp; 1156 if (obj == NULL) { 1157 tmp = FrameMap::G0_opr; 1158 } else { 1159 tmp = FrameMap::O7_opr; 1160 jobject2reg(c->as_jobject(), O7); 1161 } 1162 // handle either reg+reg or reg+disp address 1163 if (addr->index()->is_valid()) { 1164 assert(addr->disp() == 0, "must be zero"); 1165 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1166 } else { 1167 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1168 offset = store(tmp, base, addr->disp(), type, wide, false); 1169 } 1170 1171 break; 1172 } 1173 default: 1174 Unimplemented(); 1175 } 1176 if (info != NULL) { 1177 assert(offset != -1, "offset should've been set"); 1178 add_debug_info_for_null_check(offset, info); 1179 } 1180} 1181 1182 1183void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 1184 LIR_Const* c = src->as_constant_ptr(); 1185 LIR_Opr to_reg = dest; 1186 1187 switch (c->type()) { 1188 case T_INT: 1189 case T_ADDRESS: 1190 { 1191 jint con = c->as_jint(); 1192 if (to_reg->is_single_cpu()) { 1193 assert(patch_code == lir_patch_none, "no patching handled here"); 1194 __ set(con, to_reg->as_register()); 1195 } else { 1196 ShouldNotReachHere(); 1197 assert(to_reg->is_single_fpu(), "wrong register kind"); 1198 1199 __ set(con, O7); 1200 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); 1201 __ st(O7, temp_slot); 1202 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); 1203 } 1204 } 1205 break; 1206 1207 case T_LONG: 1208 { 1209 jlong con = c->as_jlong(); 1210 1211 if (to_reg->is_double_cpu()) { 1212#ifdef _LP64 1213 __ set(con, to_reg->as_register_lo()); 1214#else 1215 __ set(low(con), to_reg->as_register_lo()); 1216 __ set(high(con), to_reg->as_register_hi()); 1217#endif 1218#ifdef _LP64 1219 } else if (to_reg->is_single_cpu()) { 1220 __ set(con, to_reg->as_register()); 1221#endif 1222 } else { 1223 ShouldNotReachHere(); 1224 assert(to_reg->is_double_fpu(), "wrong register kind"); 1225 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); 1226 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); 1227 __ set(low(con), O7); 1228 __ st(O7, temp_slot_lo); 1229 __ set(high(con), O7); 1230 __ st(O7, temp_slot_hi); 1231 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); 1232 } 1233 } 1234 break; 1235 1236 case T_OBJECT: 1237 { 1238 if (patch_code == lir_patch_none) { 1239 jobject2reg(c->as_jobject(), to_reg->as_register()); 1240 } else { 1241 jobject2reg_with_patching(to_reg->as_register(), info); 1242 } 1243 } 1244 break; 1245 1246 case T_METADATA: 1247 { 1248 if (patch_code == lir_patch_none) { 1249 metadata2reg(c->as_metadata(), to_reg->as_register()); 1250 } else { 1251 klass2reg_with_patching(to_reg->as_register(), info); 1252 } 1253 } 1254 break; 1255 1256 case T_FLOAT: 1257 { 1258 address const_addr = __ float_constant(c->as_jfloat()); 1259 if (const_addr == NULL) { 1260 bailout("const section overflow"); 1261 break; 1262 } 1263 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1264 AddressLiteral const_addrlit(const_addr, rspec); 1265 if (to_reg->is_single_fpu()) { 1266 __ patchable_sethi(const_addrlit, O7); 1267 __ relocate(rspec); 1268 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); 1269 1270 } else { 1271 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1272 1273 __ set(const_addrlit, O7); 1274 __ ld(O7, 0, to_reg->as_register()); 1275 } 1276 } 1277 break; 1278 1279 case T_DOUBLE: 1280 { 1281 address const_addr = __ double_constant(c->as_jdouble()); 1282 if (const_addr == NULL) { 1283 bailout("const section overflow"); 1284 break; 1285 } 1286 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1287 1288 if (to_reg->is_double_fpu()) { 1289 AddressLiteral const_addrlit(const_addr, rspec); 1290 __ patchable_sethi(const_addrlit, O7); 1291 __ relocate(rspec); 1292 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); 1293 } else { 1294 assert(to_reg->is_double_cpu(), "Must be a long register."); 1295#ifdef _LP64 1296 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); 1297#else 1298 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); 1299 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); 1300#endif 1301 } 1302 1303 } 1304 break; 1305 1306 default: 1307 ShouldNotReachHere(); 1308 } 1309} 1310 1311Address LIR_Assembler::as_Address(LIR_Address* addr) { 1312 Register reg = addr->base()->as_register(); 1313 return Address(reg, addr->disp()); 1314} 1315 1316 1317void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1318 switch (type) { 1319 case T_INT: 1320 case T_FLOAT: { 1321 Register tmp = O7; 1322 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1323 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1324 __ lduw(from.base(), from.disp(), tmp); 1325 __ stw(tmp, to.base(), to.disp()); 1326 break; 1327 } 1328 case T_OBJECT: { 1329 Register tmp = O7; 1330 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1331 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1332 __ ld_ptr(from.base(), from.disp(), tmp); 1333 __ st_ptr(tmp, to.base(), to.disp()); 1334 break; 1335 } 1336 case T_LONG: 1337 case T_DOUBLE: { 1338 Register tmp = O7; 1339 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1340 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1341 __ lduw(from.base(), from.disp(), tmp); 1342 __ stw(tmp, to.base(), to.disp()); 1343 __ lduw(from.base(), from.disp() + 4, tmp); 1344 __ stw(tmp, to.base(), to.disp() + 4); 1345 break; 1346 } 1347 1348 default: 1349 ShouldNotReachHere(); 1350 } 1351} 1352 1353 1354Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1355 Address base = as_Address(addr); 1356 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); 1357} 1358 1359 1360Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1361 Address base = as_Address(addr); 1362 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); 1363} 1364 1365 1366void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1367 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { 1368 1369 LIR_Address* addr = src_opr->as_address_ptr(); 1370 LIR_Opr to_reg = dest; 1371 1372 Register src = addr->base()->as_pointer_register(); 1373 Register disp_reg = noreg; 1374 int disp_value = addr->disp(); 1375 bool needs_patching = (patch_code != lir_patch_none); 1376 1377 if (addr->base()->type() == T_OBJECT) { 1378 __ verify_oop(src); 1379 } 1380 1381 PatchingStub* patch = NULL; 1382 if (needs_patching) { 1383 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1384 assert(!to_reg->is_double_cpu() || 1385 patch_code == lir_patch_none || 1386 patch_code == lir_patch_normal, "patching doesn't match register"); 1387 } 1388 1389 if (addr->index()->is_illegal()) { 1390 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1391 if (needs_patching) { 1392 __ patchable_set(0, O7); 1393 } else { 1394 __ set(disp_value, O7); 1395 } 1396 disp_reg = O7; 1397 } 1398 } else if (unaligned || PatchALot) { 1399 __ add(src, addr->index()->as_register(), O7); 1400 src = O7; 1401 } else { 1402 disp_reg = addr->index()->as_pointer_register(); 1403 assert(disp_value == 0, "can't handle 3 operand addresses"); 1404 } 1405 1406 // remember the offset of the load. The patching_epilog must be done 1407 // before the call to add_debug_info, otherwise the PcDescs don't get 1408 // entered in increasing order. 1409 int offset = code_offset(); 1410 1411 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1412 if (disp_reg == noreg) { 1413 offset = load(src, disp_value, to_reg, type, wide, unaligned); 1414 } else { 1415 assert(!unaligned, "can't handle this"); 1416 offset = load(src, disp_reg, to_reg, type, wide); 1417 } 1418 1419 if (patch != NULL) { 1420 patching_epilog(patch, patch_code, src, info); 1421 } 1422 if (info != NULL) add_debug_info_for_null_check(offset, info); 1423} 1424 1425 1426void LIR_Assembler::prefetchr(LIR_Opr src) { 1427 LIR_Address* addr = src->as_address_ptr(); 1428 Address from_addr = as_Address(addr); 1429 1430 if (VM_Version::has_v9()) { 1431 __ prefetch(from_addr, Assembler::severalReads); 1432 } 1433} 1434 1435 1436void LIR_Assembler::prefetchw(LIR_Opr src) { 1437 LIR_Address* addr = src->as_address_ptr(); 1438 Address from_addr = as_Address(addr); 1439 1440 if (VM_Version::has_v9()) { 1441 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); 1442 } 1443} 1444 1445 1446void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1447 Address addr; 1448 if (src->is_single_word()) { 1449 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1450 } else if (src->is_double_word()) { 1451 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1452 } 1453 1454 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1455 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); 1456} 1457 1458 1459void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1460 Address addr; 1461 if (dest->is_single_word()) { 1462 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1463 } else if (dest->is_double_word()) { 1464 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1465 } 1466 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1467 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); 1468} 1469 1470 1471void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1472 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1473 if (from_reg->is_double_fpu()) { 1474 // double to double moves 1475 assert(to_reg->is_double_fpu(), "should match"); 1476 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); 1477 } else { 1478 // float to float moves 1479 assert(to_reg->is_single_fpu(), "should match"); 1480 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); 1481 } 1482 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1483 if (from_reg->is_double_cpu()) { 1484#ifdef _LP64 1485 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); 1486#else 1487 assert(to_reg->is_double_cpu() && 1488 from_reg->as_register_hi() != to_reg->as_register_lo() && 1489 from_reg->as_register_lo() != to_reg->as_register_hi(), 1490 "should both be long and not overlap"); 1491 // long to long moves 1492 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); 1493 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); 1494#endif 1495#ifdef _LP64 1496 } else if (to_reg->is_double_cpu()) { 1497 // int to int moves 1498 __ mov(from_reg->as_register(), to_reg->as_register_lo()); 1499#endif 1500 } else { 1501 // int to int moves 1502 __ mov(from_reg->as_register(), to_reg->as_register()); 1503 } 1504 } else { 1505 ShouldNotReachHere(); 1506 } 1507 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1508 __ verify_oop(to_reg->as_register()); 1509 } 1510} 1511 1512 1513void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1514 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1515 bool wide, bool unaligned) { 1516 LIR_Address* addr = dest->as_address_ptr(); 1517 1518 Register src = addr->base()->as_pointer_register(); 1519 Register disp_reg = noreg; 1520 int disp_value = addr->disp(); 1521 bool needs_patching = (patch_code != lir_patch_none); 1522 1523 if (addr->base()->is_oop_register()) { 1524 __ verify_oop(src); 1525 } 1526 1527 PatchingStub* patch = NULL; 1528 if (needs_patching) { 1529 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1530 assert(!from_reg->is_double_cpu() || 1531 patch_code == lir_patch_none || 1532 patch_code == lir_patch_normal, "patching doesn't match register"); 1533 } 1534 1535 if (addr->index()->is_illegal()) { 1536 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1537 if (needs_patching) { 1538 __ patchable_set(0, O7); 1539 } else { 1540 __ set(disp_value, O7); 1541 } 1542 disp_reg = O7; 1543 } 1544 } else if (unaligned || PatchALot) { 1545 __ add(src, addr->index()->as_register(), O7); 1546 src = O7; 1547 } else { 1548 disp_reg = addr->index()->as_pointer_register(); 1549 assert(disp_value == 0, "can't handle 3 operand addresses"); 1550 } 1551 1552 // remember the offset of the store. The patching_epilog must be done 1553 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1554 // entered in increasing order. 1555 int offset; 1556 1557 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1558 if (disp_reg == noreg) { 1559 offset = store(from_reg, src, disp_value, type, wide, unaligned); 1560 } else { 1561 assert(!unaligned, "can't handle this"); 1562 offset = store(from_reg, src, disp_reg, type, wide); 1563 } 1564 1565 if (patch != NULL) { 1566 patching_epilog(patch, patch_code, src, info); 1567 } 1568 1569 if (info != NULL) add_debug_info_for_null_check(offset, info); 1570} 1571 1572 1573void LIR_Assembler::return_op(LIR_Opr result) { 1574 // the poll may need a register so just pick one that isn't the return register 1575#if defined(TIERED) && !defined(_LP64) 1576 if (result->type_field() == LIR_OprDesc::long_type) { 1577 // Must move the result to G1 1578 // Must leave proper result in O0,O1 and G1 (TIERED only) 1579 __ sllx(I0, 32, G1); // Shift bits into high G1 1580 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) 1581 __ or3 (I1, G1, G1); // OR 64 bits into G1 1582#ifdef ASSERT 1583 // mangle it so any problems will show up 1584 __ set(0xdeadbeef, I0); 1585 __ set(0xdeadbeef, I1); 1586#endif 1587 } 1588#endif // TIERED 1589 __ set((intptr_t)os::get_polling_page(), L0); 1590 __ relocate(relocInfo::poll_return_type); 1591 __ ld_ptr(L0, 0, G0); 1592 __ ret(); 1593 __ delayed()->restore(); 1594} 1595 1596 1597int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1598 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); 1599 if (info != NULL) { 1600 add_debug_info_for_branch(info); 1601 } else { 1602 __ relocate(relocInfo::poll_type); 1603 } 1604 1605 int offset = __ offset(); 1606 __ ld_ptr(tmp->as_register(), 0, G0); 1607 1608 return offset; 1609} 1610 1611 1612void LIR_Assembler::emit_static_call_stub() { 1613 address call_pc = __ pc(); 1614 address stub = __ start_a_stub(call_stub_size); 1615 if (stub == NULL) { 1616 bailout("static call stub overflow"); 1617 return; 1618 } 1619 1620 int start = __ offset(); 1621 __ relocate(static_stub_Relocation::spec(call_pc)); 1622 1623 __ set_metadata(NULL, G5); 1624 // must be set to -1 at code generation time 1625 AddressLiteral addrlit(-1); 1626 __ jump_to(addrlit, G3); 1627 __ delayed()->nop(); 1628 1629 assert(__ offset() - start <= call_stub_size, "stub too big"); 1630 __ end_a_stub(); 1631} 1632 1633 1634void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1635 if (opr1->is_single_fpu()) { 1636 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1637 } else if (opr1->is_double_fpu()) { 1638 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1639 } else if (opr1->is_single_cpu()) { 1640 if (opr2->is_constant()) { 1641 switch (opr2->as_constant_ptr()->type()) { 1642 case T_INT: 1643 { jint con = opr2->as_constant_ptr()->as_jint(); 1644 if (Assembler::is_simm13(con)) { 1645 __ cmp(opr1->as_register(), con); 1646 } else { 1647 __ set(con, O7); 1648 __ cmp(opr1->as_register(), O7); 1649 } 1650 } 1651 break; 1652 1653 case T_OBJECT: 1654 // there are only equal/notequal comparisions on objects 1655 { jobject con = opr2->as_constant_ptr()->as_jobject(); 1656 if (con == NULL) { 1657 __ cmp(opr1->as_register(), 0); 1658 } else { 1659 jobject2reg(con, O7); 1660 __ cmp(opr1->as_register(), O7); 1661 } 1662 } 1663 break; 1664 1665 default: 1666 ShouldNotReachHere(); 1667 break; 1668 } 1669 } else { 1670 if (opr2->is_address()) { 1671 LIR_Address * addr = opr2->as_address_ptr(); 1672 BasicType type = addr->type(); 1673 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1674 else __ ld(as_Address(addr), O7); 1675 __ cmp(opr1->as_register(), O7); 1676 } else { 1677 __ cmp(opr1->as_register(), opr2->as_register()); 1678 } 1679 } 1680 } else if (opr1->is_double_cpu()) { 1681 Register xlo = opr1->as_register_lo(); 1682 Register xhi = opr1->as_register_hi(); 1683 if (opr2->is_constant() && opr2->as_jlong() == 0) { 1684 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); 1685#ifdef _LP64 1686 __ orcc(xhi, G0, G0); 1687#else 1688 __ orcc(xhi, xlo, G0); 1689#endif 1690 } else if (opr2->is_register()) { 1691 Register ylo = opr2->as_register_lo(); 1692 Register yhi = opr2->as_register_hi(); 1693#ifdef _LP64 1694 __ cmp(xlo, ylo); 1695#else 1696 __ subcc(xlo, ylo, xlo); 1697 __ subccc(xhi, yhi, xhi); 1698 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 1699 __ orcc(xhi, xlo, G0); 1700 } 1701#endif 1702 } else { 1703 ShouldNotReachHere(); 1704 } 1705 } else if (opr1->is_address()) { 1706 LIR_Address * addr = opr1->as_address_ptr(); 1707 BasicType type = addr->type(); 1708 assert (opr2->is_constant(), "Checking"); 1709 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1710 else __ ld(as_Address(addr), O7); 1711 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); 1712 } else { 1713 ShouldNotReachHere(); 1714 } 1715} 1716 1717 1718void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1719 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1720 bool is_unordered_less = (code == lir_ucmp_fd2i); 1721 if (left->is_single_fpu()) { 1722 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1723 } else if (left->is_double_fpu()) { 1724 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1725 } else { 1726 ShouldNotReachHere(); 1727 } 1728 } else if (code == lir_cmp_l2i) { 1729#ifdef _LP64 1730 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); 1731#else 1732 __ lcmp(left->as_register_hi(), left->as_register_lo(), 1733 right->as_register_hi(), right->as_register_lo(), 1734 dst->as_register()); 1735#endif 1736 } else { 1737 ShouldNotReachHere(); 1738 } 1739} 1740 1741 1742void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1743 Assembler::Condition acond; 1744 switch (condition) { 1745 case lir_cond_equal: acond = Assembler::equal; break; 1746 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1747 case lir_cond_less: acond = Assembler::less; break; 1748 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1749 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 1750 case lir_cond_greater: acond = Assembler::greater; break; 1751 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 1752 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 1753 default: ShouldNotReachHere(); 1754 }; 1755 1756 if (opr1->is_constant() && opr1->type() == T_INT) { 1757 Register dest = result->as_register(); 1758 // load up first part of constant before branch 1759 // and do the rest in the delay slot. 1760 if (!Assembler::is_simm13(opr1->as_jint())) { 1761 __ sethi(opr1->as_jint(), dest); 1762 } 1763 } else if (opr1->is_constant()) { 1764 const2reg(opr1, result, lir_patch_none, NULL); 1765 } else if (opr1->is_register()) { 1766 reg2reg(opr1, result); 1767 } else if (opr1->is_stack()) { 1768 stack2reg(opr1, result, result->type()); 1769 } else { 1770 ShouldNotReachHere(); 1771 } 1772 Label skip; 1773#ifdef _LP64 1774 if (type == T_INT) { 1775 __ br(acond, false, Assembler::pt, skip); 1776 } else 1777#endif 1778 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit 1779 if (opr1->is_constant() && opr1->type() == T_INT) { 1780 Register dest = result->as_register(); 1781 if (Assembler::is_simm13(opr1->as_jint())) { 1782 __ delayed()->or3(G0, opr1->as_jint(), dest); 1783 } else { 1784 // the sethi has been done above, so just put in the low 10 bits 1785 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); 1786 } 1787 } else { 1788 // can't do anything useful in the delay slot 1789 __ delayed()->nop(); 1790 } 1791 if (opr2->is_constant()) { 1792 const2reg(opr2, result, lir_patch_none, NULL); 1793 } else if (opr2->is_register()) { 1794 reg2reg(opr2, result); 1795 } else if (opr2->is_stack()) { 1796 stack2reg(opr2, result, result->type()); 1797 } else { 1798 ShouldNotReachHere(); 1799 } 1800 __ bind(skip); 1801} 1802 1803 1804void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1805 assert(info == NULL, "unused on this code path"); 1806 assert(left->is_register(), "wrong items state"); 1807 assert(dest->is_register(), "wrong items state"); 1808 1809 if (right->is_register()) { 1810 if (dest->is_float_kind()) { 1811 1812 FloatRegister lreg, rreg, res; 1813 FloatRegisterImpl::Width w; 1814 if (right->is_single_fpu()) { 1815 w = FloatRegisterImpl::S; 1816 lreg = left->as_float_reg(); 1817 rreg = right->as_float_reg(); 1818 res = dest->as_float_reg(); 1819 } else { 1820 w = FloatRegisterImpl::D; 1821 lreg = left->as_double_reg(); 1822 rreg = right->as_double_reg(); 1823 res = dest->as_double_reg(); 1824 } 1825 1826 switch (code) { 1827 case lir_add: __ fadd(w, lreg, rreg, res); break; 1828 case lir_sub: __ fsub(w, lreg, rreg, res); break; 1829 case lir_mul: // fall through 1830 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; 1831 case lir_div: // fall through 1832 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; 1833 default: ShouldNotReachHere(); 1834 } 1835 1836 } else if (dest->is_double_cpu()) { 1837#ifdef _LP64 1838 Register dst_lo = dest->as_register_lo(); 1839 Register op1_lo = left->as_pointer_register(); 1840 Register op2_lo = right->as_pointer_register(); 1841 1842 switch (code) { 1843 case lir_add: 1844 __ add(op1_lo, op2_lo, dst_lo); 1845 break; 1846 1847 case lir_sub: 1848 __ sub(op1_lo, op2_lo, dst_lo); 1849 break; 1850 1851 default: ShouldNotReachHere(); 1852 } 1853#else 1854 Register op1_lo = left->as_register_lo(); 1855 Register op1_hi = left->as_register_hi(); 1856 Register op2_lo = right->as_register_lo(); 1857 Register op2_hi = right->as_register_hi(); 1858 Register dst_lo = dest->as_register_lo(); 1859 Register dst_hi = dest->as_register_hi(); 1860 1861 switch (code) { 1862 case lir_add: 1863 __ addcc(op1_lo, op2_lo, dst_lo); 1864 __ addc (op1_hi, op2_hi, dst_hi); 1865 break; 1866 1867 case lir_sub: 1868 __ subcc(op1_lo, op2_lo, dst_lo); 1869 __ subc (op1_hi, op2_hi, dst_hi); 1870 break; 1871 1872 default: ShouldNotReachHere(); 1873 } 1874#endif 1875 } else { 1876 assert (right->is_single_cpu(), "Just Checking"); 1877 1878 Register lreg = left->as_register(); 1879 Register res = dest->as_register(); 1880 Register rreg = right->as_register(); 1881 switch (code) { 1882 case lir_add: __ add (lreg, rreg, res); break; 1883 case lir_sub: __ sub (lreg, rreg, res); break; 1884 case lir_mul: __ mult (lreg, rreg, res); break; 1885 default: ShouldNotReachHere(); 1886 } 1887 } 1888 } else { 1889 assert (right->is_constant(), "must be constant"); 1890 1891 if (dest->is_single_cpu()) { 1892 Register lreg = left->as_register(); 1893 Register res = dest->as_register(); 1894 int simm13 = right->as_constant_ptr()->as_jint(); 1895 1896 switch (code) { 1897 case lir_add: __ add (lreg, simm13, res); break; 1898 case lir_sub: __ sub (lreg, simm13, res); break; 1899 case lir_mul: __ mult (lreg, simm13, res); break; 1900 default: ShouldNotReachHere(); 1901 } 1902 } else { 1903 Register lreg = left->as_pointer_register(); 1904 Register res = dest->as_register_lo(); 1905 long con = right->as_constant_ptr()->as_jlong(); 1906 assert(Assembler::is_simm13(con), "must be simm13"); 1907 1908 switch (code) { 1909 case lir_add: __ add (lreg, (int)con, res); break; 1910 case lir_sub: __ sub (lreg, (int)con, res); break; 1911 case lir_mul: __ mult (lreg, (int)con, res); break; 1912 default: ShouldNotReachHere(); 1913 } 1914 } 1915 } 1916} 1917 1918 1919void LIR_Assembler::fpop() { 1920 // do nothing 1921} 1922 1923 1924void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1925 switch (code) { 1926 case lir_sin: 1927 case lir_tan: 1928 case lir_cos: { 1929 assert(thread->is_valid(), "preserve the thread object for performance reasons"); 1930 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); 1931 break; 1932 } 1933 case lir_sqrt: { 1934 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1935 FloatRegister src_reg = value->as_double_reg(); 1936 FloatRegister dst_reg = dest->as_double_reg(); 1937 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); 1938 break; 1939 } 1940 case lir_abs: { 1941 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1942 FloatRegister src_reg = value->as_double_reg(); 1943 FloatRegister dst_reg = dest->as_double_reg(); 1944 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); 1945 break; 1946 } 1947 default: { 1948 ShouldNotReachHere(); 1949 break; 1950 } 1951 } 1952} 1953 1954 1955void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1956 if (right->is_constant()) { 1957 if (dest->is_single_cpu()) { 1958 int simm13 = right->as_constant_ptr()->as_jint(); 1959 switch (code) { 1960 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; 1961 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; 1962 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; 1963 default: ShouldNotReachHere(); 1964 } 1965 } else { 1966 long c = right->as_constant_ptr()->as_jlong(); 1967 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); 1968 int simm13 = (int)c; 1969 switch (code) { 1970 case lir_logic_and: 1971#ifndef _LP64 1972 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); 1973#endif 1974 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1975 break; 1976 1977 case lir_logic_or: 1978#ifndef _LP64 1979 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); 1980#endif 1981 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1982 break; 1983 1984 case lir_logic_xor: 1985#ifndef _LP64 1986 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); 1987#endif 1988 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1989 break; 1990 1991 default: ShouldNotReachHere(); 1992 } 1993 } 1994 } else { 1995 assert(right->is_register(), "right should be in register"); 1996 1997 if (dest->is_single_cpu()) { 1998 switch (code) { 1999 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; 2000 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; 2001 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; 2002 default: ShouldNotReachHere(); 2003 } 2004 } else { 2005#ifdef _LP64 2006 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 2007 left->as_register_lo(); 2008 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 2009 right->as_register_lo(); 2010 2011 switch (code) { 2012 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; 2013 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; 2014 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; 2015 default: ShouldNotReachHere(); 2016 } 2017#else 2018 switch (code) { 2019 case lir_logic_and: 2020 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2021 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2022 break; 2023 2024 case lir_logic_or: 2025 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2026 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2027 break; 2028 2029 case lir_logic_xor: 2030 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2031 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2032 break; 2033 2034 default: ShouldNotReachHere(); 2035 } 2036#endif 2037 } 2038 } 2039} 2040 2041 2042int LIR_Assembler::shift_amount(BasicType t) { 2043 int elem_size = type2aelembytes(t); 2044 switch (elem_size) { 2045 case 1 : return 0; 2046 case 2 : return 1; 2047 case 4 : return 2; 2048 case 8 : return 3; 2049 } 2050 ShouldNotReachHere(); 2051 return -1; 2052} 2053 2054 2055void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2056 assert(exceptionOop->as_register() == Oexception, "should match"); 2057 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); 2058 2059 info->add_register_oop(exceptionOop); 2060 2061 // reuse the debug info from the safepoint poll for the throw op itself 2062 address pc_for_athrow = __ pc(); 2063 int pc_for_athrow_offset = __ offset(); 2064 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 2065 __ set(pc_for_athrow, Oissuing_pc, rspec); 2066 add_call_info(pc_for_athrow_offset, info); // for exception handler 2067 2068 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 2069 __ delayed()->nop(); 2070} 2071 2072 2073void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2074 assert(exceptionOop->as_register() == Oexception, "should match"); 2075 2076 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); 2077 __ delayed()->nop(); 2078} 2079 2080void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2081 Register src = op->src()->as_register(); 2082 Register dst = op->dst()->as_register(); 2083 Register src_pos = op->src_pos()->as_register(); 2084 Register dst_pos = op->dst_pos()->as_register(); 2085 Register length = op->length()->as_register(); 2086 Register tmp = op->tmp()->as_register(); 2087 Register tmp2 = O7; 2088 2089 int flags = op->flags(); 2090 ciArrayKlass* default_type = op->expected_type(); 2091 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2092 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2093 2094#ifdef _LP64 2095 // higher 32bits must be null 2096 __ sra(dst_pos, 0, dst_pos); 2097 __ sra(src_pos, 0, src_pos); 2098 __ sra(length, 0, length); 2099#endif 2100 2101 // set up the arraycopy stub information 2102 ArrayCopyStub* stub = op->stub(); 2103 2104 // always do stub if no type information is available. it's ok if 2105 // the known type isn't loaded since the code sanity checks 2106 // in debug mode and the type isn't required when we know the exact type 2107 // also check that the type is an array type. 2108 if (op->expected_type() == NULL) { 2109 __ mov(src, O0); 2110 __ mov(src_pos, O1); 2111 __ mov(dst, O2); 2112 __ mov(dst_pos, O3); 2113 __ mov(length, O4); 2114 address copyfunc_addr = StubRoutines::generic_arraycopy(); 2115 2116 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 2117 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); 2118 } else { 2119#ifndef PRODUCT 2120 if (PrintC1Statistics) { 2121 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 2122 __ inc_counter(counter, G1, G3); 2123 } 2124#endif 2125 __ call_VM_leaf(tmp, copyfunc_addr); 2126 } 2127 2128 if (copyfunc_addr != NULL) { 2129 __ xor3(O0, -1, tmp); 2130 __ sub(length, tmp, length); 2131 __ add(src_pos, tmp, src_pos); 2132 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 2133 __ delayed()->add(dst_pos, tmp, dst_pos); 2134 } else { 2135 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 2136 __ delayed()->nop(); 2137 } 2138 __ bind(*stub->continuation()); 2139 return; 2140 } 2141 2142 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 2143 2144 // make sure src and dst are non-null and load array length 2145 if (flags & LIR_OpArrayCopy::src_null_check) { 2146 __ tst(src); 2147 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 2148 __ delayed()->nop(); 2149 } 2150 2151 if (flags & LIR_OpArrayCopy::dst_null_check) { 2152 __ tst(dst); 2153 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 2154 __ delayed()->nop(); 2155 } 2156 2157 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2158 // test src_pos register 2159 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry()); 2160 __ delayed()->nop(); 2161 } 2162 2163 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2164 // test dst_pos register 2165 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry()); 2166 __ delayed()->nop(); 2167 } 2168 2169 if (flags & LIR_OpArrayCopy::length_positive_check) { 2170 // make sure length isn't negative 2171 __ cmp_zero_and_br(Assembler::less, length, *stub->entry()); 2172 __ delayed()->nop(); 2173 } 2174 2175 if (flags & LIR_OpArrayCopy::src_range_check) { 2176 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); 2177 __ add(length, src_pos, tmp); 2178 __ cmp(tmp2, tmp); 2179 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2180 __ delayed()->nop(); 2181 } 2182 2183 if (flags & LIR_OpArrayCopy::dst_range_check) { 2184 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); 2185 __ add(length, dst_pos, tmp); 2186 __ cmp(tmp2, tmp); 2187 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2188 __ delayed()->nop(); 2189 } 2190 2191 int shift = shift_amount(basic_type); 2192 2193 if (flags & LIR_OpArrayCopy::type_check) { 2194 // We don't know the array types are compatible 2195 if (basic_type != T_OBJECT) { 2196 // Simple test for basic type arrays 2197 if (UseCompressedKlassPointers) { 2198 // We don't need decode because we just need to compare 2199 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); 2200 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2201 __ cmp(tmp, tmp2); 2202 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2203 } else { 2204 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); 2205 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2206 __ cmp(tmp, tmp2); 2207 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2208 } 2209 __ delayed()->nop(); 2210 } else { 2211 // For object arrays, if src is a sub class of dst then we can 2212 // safely do the copy. 2213 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 2214 2215 Label cont, slow; 2216 assert_different_registers(tmp, tmp2, G3, G1); 2217 2218 __ load_klass(src, G3); 2219 __ load_klass(dst, G1); 2220 2221 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); 2222 2223 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2224 __ delayed()->nop(); 2225 2226 __ cmp(G3, 0); 2227 if (copyfunc_addr != NULL) { // use stub if available 2228 // src is not a sub class of dst so we have to do a 2229 // per-element check. 2230 __ br(Assembler::notEqual, false, Assembler::pt, cont); 2231 __ delayed()->nop(); 2232 2233 __ bind(slow); 2234 2235 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2236 if ((flags & mask) != mask) { 2237 // Check that at least both of them object arrays. 2238 assert(flags & mask, "one of the two should be known to be an object array"); 2239 2240 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2241 __ load_klass(src, tmp); 2242 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2243 __ load_klass(dst, tmp); 2244 } 2245 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2246 2247 __ lduw(tmp, lh_offset, tmp2); 2248 2249 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2250 __ set(objArray_lh, tmp); 2251 __ cmp(tmp, tmp2); 2252 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2253 __ delayed()->nop(); 2254 } 2255 2256 Register src_ptr = O0; 2257 Register dst_ptr = O1; 2258 Register len = O2; 2259 Register chk_off = O3; 2260 Register super_k = O4; 2261 2262 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2263 if (shift == 0) { 2264 __ add(src_ptr, src_pos, src_ptr); 2265 } else { 2266 __ sll(src_pos, shift, tmp); 2267 __ add(src_ptr, tmp, src_ptr); 2268 } 2269 2270 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2271 if (shift == 0) { 2272 __ add(dst_ptr, dst_pos, dst_ptr); 2273 } else { 2274 __ sll(dst_pos, shift, tmp); 2275 __ add(dst_ptr, tmp, dst_ptr); 2276 } 2277 __ mov(length, len); 2278 __ load_klass(dst, tmp); 2279 2280 int ek_offset = in_bytes(objArrayKlass::element_klass_offset()); 2281 __ ld_ptr(tmp, ek_offset, super_k); 2282 2283 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2284 __ lduw(super_k, sco_offset, chk_off); 2285 2286 __ call_VM_leaf(tmp, copyfunc_addr); 2287 2288#ifndef PRODUCT 2289 if (PrintC1Statistics) { 2290 Label failed; 2291 __ br_notnull_short(O0, Assembler::pn, failed); 2292 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); 2293 __ bind(failed); 2294 } 2295#endif 2296 2297 __ br_null(O0, false, Assembler::pt, *stub->continuation()); 2298 __ delayed()->xor3(O0, -1, tmp); 2299 2300#ifndef PRODUCT 2301 if (PrintC1Statistics) { 2302 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); 2303 } 2304#endif 2305 2306 __ sub(length, tmp, length); 2307 __ add(src_pos, tmp, src_pos); 2308 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); 2309 __ delayed()->add(dst_pos, tmp, dst_pos); 2310 2311 __ bind(cont); 2312 } else { 2313 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2314 __ delayed()->nop(); 2315 __ bind(cont); 2316 } 2317 } 2318 } 2319 2320#ifdef ASSERT 2321 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2322 // Sanity check the known type with the incoming class. For the 2323 // primitive case the types must match exactly with src.klass and 2324 // dst.klass each exactly matching the default type. For the 2325 // object array case, if no type check is needed then either the 2326 // dst type is exactly the expected type and the src type is a 2327 // subtype which we can't check or src is the same array as dst 2328 // but not necessarily exactly of type default_type. 2329 Label known_ok, halt; 2330 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2331 if (UseCompressedKlassPointers) { 2332 // tmp holds the default type. It currently comes uncompressed after the 2333 // load of a constant, so encode it. 2334 __ encode_heap_oop(tmp); 2335 // load the raw value of the dst klass, since we will be comparing 2336 // uncompressed values directly. 2337 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2338 if (basic_type != T_OBJECT) { 2339 __ cmp(tmp, tmp2); 2340 __ br(Assembler::notEqual, false, Assembler::pn, halt); 2341 // load the raw value of the src klass. 2342 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); 2343 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2344 } else { 2345 __ cmp(tmp, tmp2); 2346 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2347 __ delayed()->cmp(src, dst); 2348 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2349 __ delayed()->nop(); 2350 } 2351 } else { 2352 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2353 if (basic_type != T_OBJECT) { 2354 __ cmp(tmp, tmp2); 2355 __ brx(Assembler::notEqual, false, Assembler::pn, halt); 2356 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); 2357 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2358 } else { 2359 __ cmp(tmp, tmp2); 2360 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2361 __ delayed()->cmp(src, dst); 2362 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2363 __ delayed()->nop(); 2364 } 2365 } 2366 __ bind(halt); 2367 __ stop("incorrect type information in arraycopy"); 2368 __ bind(known_ok); 2369 } 2370#endif 2371 2372#ifndef PRODUCT 2373 if (PrintC1Statistics) { 2374 address counter = Runtime1::arraycopy_count_address(basic_type); 2375 __ inc_counter(counter, G1, G3); 2376 } 2377#endif 2378 2379 Register src_ptr = O0; 2380 Register dst_ptr = O1; 2381 Register len = O2; 2382 2383 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2384 if (shift == 0) { 2385 __ add(src_ptr, src_pos, src_ptr); 2386 } else { 2387 __ sll(src_pos, shift, tmp); 2388 __ add(src_ptr, tmp, src_ptr); 2389 } 2390 2391 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2392 if (shift == 0) { 2393 __ add(dst_ptr, dst_pos, dst_ptr); 2394 } else { 2395 __ sll(dst_pos, shift, tmp); 2396 __ add(dst_ptr, tmp, dst_ptr); 2397 } 2398 2399 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2400 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2401 const char *name; 2402 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2403 2404 // arraycopy stubs takes a length in number of elements, so don't scale it. 2405 __ mov(length, len); 2406 __ call_VM_leaf(tmp, entry); 2407 2408 __ bind(*stub->continuation()); 2409} 2410 2411 2412void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2413 if (dest->is_single_cpu()) { 2414#ifdef _LP64 2415 if (left->type() == T_OBJECT) { 2416 switch (code) { 2417 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; 2418 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; 2419 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2420 default: ShouldNotReachHere(); 2421 } 2422 } else 2423#endif 2424 switch (code) { 2425 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; 2426 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; 2427 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2428 default: ShouldNotReachHere(); 2429 } 2430 } else { 2431#ifdef _LP64 2432 switch (code) { 2433 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2434 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2435 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2436 default: ShouldNotReachHere(); 2437 } 2438#else 2439 switch (code) { 2440 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2441 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2442 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2443 default: ShouldNotReachHere(); 2444 } 2445#endif 2446 } 2447} 2448 2449 2450void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2451#ifdef _LP64 2452 if (left->type() == T_OBJECT) { 2453 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) 2454 Register l = left->as_register(); 2455 Register d = dest->as_register_lo(); 2456 switch (code) { 2457 case lir_shl: __ sllx (l, count, d); break; 2458 case lir_shr: __ srax (l, count, d); break; 2459 case lir_ushr: __ srlx (l, count, d); break; 2460 default: ShouldNotReachHere(); 2461 } 2462 return; 2463 } 2464#endif 2465 2466 if (dest->is_single_cpu()) { 2467 count = count & 0x1F; // Java spec 2468 switch (code) { 2469 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; 2470 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; 2471 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; 2472 default: ShouldNotReachHere(); 2473 } 2474 } else if (dest->is_double_cpu()) { 2475 count = count & 63; // Java spec 2476 switch (code) { 2477 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2478 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2479 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2480 default: ShouldNotReachHere(); 2481 } 2482 } else { 2483 ShouldNotReachHere(); 2484 } 2485} 2486 2487 2488void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2489 assert(op->tmp1()->as_register() == G1 && 2490 op->tmp2()->as_register() == G3 && 2491 op->tmp3()->as_register() == G4 && 2492 op->obj()->as_register() == O0 && 2493 op->klass()->as_register() == G5, "must be"); 2494 if (op->init_check()) { 2495 __ ldub(op->klass()->as_register(), 2496 in_bytes(InstanceKlass::init_state_offset()), 2497 op->tmp1()->as_register()); 2498 add_debug_info_for_null_check_here(op->stub()->info()); 2499 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2500 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); 2501 __ delayed()->nop(); 2502 } 2503 __ allocate_object(op->obj()->as_register(), 2504 op->tmp1()->as_register(), 2505 op->tmp2()->as_register(), 2506 op->tmp3()->as_register(), 2507 op->header_size(), 2508 op->object_size(), 2509 op->klass()->as_register(), 2510 *op->stub()->entry()); 2511 __ bind(*op->stub()->continuation()); 2512 __ verify_oop(op->obj()->as_register()); 2513} 2514 2515 2516void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2517 assert(op->tmp1()->as_register() == G1 && 2518 op->tmp2()->as_register() == G3 && 2519 op->tmp3()->as_register() == G4 && 2520 op->tmp4()->as_register() == O1 && 2521 op->klass()->as_register() == G5, "must be"); 2522 2523 LP64_ONLY( __ signx(op->len()->as_register()); ) 2524 if (UseSlowPath || 2525 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2526 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2527 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2528 __ delayed()->nop(); 2529 } else { 2530 __ allocate_array(op->obj()->as_register(), 2531 op->len()->as_register(), 2532 op->tmp1()->as_register(), 2533 op->tmp2()->as_register(), 2534 op->tmp3()->as_register(), 2535 arrayOopDesc::header_size(op->type()), 2536 type2aelembytes(op->type()), 2537 op->klass()->as_register(), 2538 *op->stub()->entry()); 2539 } 2540 __ bind(*op->stub()->continuation()); 2541} 2542 2543 2544void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2545 ciMethodData *md, ciProfileData *data, 2546 Register recv, Register tmp1, Label* update_done) { 2547 uint i; 2548 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2549 Label next_test; 2550 // See if the receiver is receiver[n]. 2551 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2552 mdo_offset_bias); 2553 __ ld_ptr(receiver_addr, tmp1); 2554 __ verify_oop(tmp1); 2555 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test); 2556 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2557 mdo_offset_bias); 2558 __ ld_ptr(data_addr, tmp1); 2559 __ add(tmp1, DataLayout::counter_increment, tmp1); 2560 __ st_ptr(tmp1, data_addr); 2561 __ ba(*update_done); 2562 __ delayed()->nop(); 2563 __ bind(next_test); 2564 } 2565 2566 // Didn't find receiver; find next empty slot and fill it in 2567 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2568 Label next_test; 2569 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2570 mdo_offset_bias); 2571 __ ld_ptr(recv_addr, tmp1); 2572 __ br_notnull_short(tmp1, Assembler::pt, next_test); 2573 __ st_ptr(recv, recv_addr); 2574 __ set(DataLayout::counter_increment, tmp1); 2575 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2576 mdo_offset_bias); 2577 __ ba(*update_done); 2578 __ delayed()->nop(); 2579 __ bind(next_test); 2580 } 2581} 2582 2583 2584void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2585 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2586 md = method->method_data_or_null(); 2587 assert(md != NULL, "Sanity"); 2588 data = md->bci_to_data(bci); 2589 assert(data != NULL, "need data for checkcast"); 2590 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2591 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2592 // The offset is large so bias the mdo by the base of the slot so 2593 // that the ld can use simm13s to reference the slots of the data 2594 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2595 } 2596} 2597 2598void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2599 // we always need a stub for the failure case. 2600 CodeStub* stub = op->stub(); 2601 Register obj = op->object()->as_register(); 2602 Register k_RInfo = op->tmp1()->as_register(); 2603 Register klass_RInfo = op->tmp2()->as_register(); 2604 Register dst = op->result_opr()->as_register(); 2605 Register Rtmp1 = op->tmp3()->as_register(); 2606 ciKlass* k = op->klass(); 2607 2608 2609 if (obj == k_RInfo) { 2610 k_RInfo = klass_RInfo; 2611 klass_RInfo = obj; 2612 } 2613 2614 ciMethodData* md; 2615 ciProfileData* data; 2616 int mdo_offset_bias = 0; 2617 if (op->should_profile()) { 2618 ciMethod* method = op->profiled_method(); 2619 assert(method != NULL, "Should have method"); 2620 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2621 2622 Label not_null; 2623 __ br_notnull_short(obj, Assembler::pn, not_null); 2624 Register mdo = k_RInfo; 2625 Register data_val = Rtmp1; 2626 metadata2reg(md->constant_encoding(), mdo); 2627 if (mdo_offset_bias > 0) { 2628 __ set(mdo_offset_bias, data_val); 2629 __ add(mdo, data_val, mdo); 2630 } 2631 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2632 __ ldub(flags_addr, data_val); 2633 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2634 __ stb(data_val, flags_addr); 2635 __ ba(*obj_is_null); 2636 __ delayed()->nop(); 2637 __ bind(not_null); 2638 } else { 2639 __ br_null(obj, false, Assembler::pn, *obj_is_null); 2640 __ delayed()->nop(); 2641 } 2642 2643 Label profile_cast_failure, profile_cast_success; 2644 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2645 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2646 2647 // patching may screw with our temporaries on sparc, 2648 // so let's do it before loading the class 2649 if (k->is_loaded()) { 2650 metadata2reg(k->constant_encoding(), k_RInfo); 2651 } else { 2652 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2653 } 2654 assert(obj != k_RInfo, "must be different"); 2655 2656 // get object class 2657 // not a safepoint as obj null check happens earlier 2658 __ load_klass(obj, klass_RInfo); 2659 if (op->fast_check()) { 2660 assert_different_registers(klass_RInfo, k_RInfo); 2661 __ cmp(k_RInfo, klass_RInfo); 2662 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); 2663 __ delayed()->nop(); 2664 } else { 2665 bool need_slow_path = true; 2666 if (k->is_loaded()) { 2667 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) 2668 need_slow_path = false; 2669 // perform the fast part of the checking logic 2670 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, 2671 (need_slow_path ? success_target : NULL), 2672 failure_target, NULL, 2673 RegisterOrConstant(k->super_check_offset())); 2674 } else { 2675 // perform the fast part of the checking logic 2676 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, 2677 failure_target, NULL); 2678 } 2679 if (need_slow_path) { 2680 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2681 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2682 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2683 __ delayed()->nop(); 2684 __ cmp(G3, 0); 2685 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2686 __ delayed()->nop(); 2687 // Fall through to success case 2688 } 2689 } 2690 2691 if (op->should_profile()) { 2692 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2693 assert_different_registers(obj, mdo, recv, tmp1); 2694 __ bind(profile_cast_success); 2695 metadata2reg(md->constant_encoding(), mdo); 2696 if (mdo_offset_bias > 0) { 2697 __ set(mdo_offset_bias, tmp1); 2698 __ add(mdo, tmp1, mdo); 2699 } 2700 __ load_klass(obj, recv); 2701 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); 2702 // Jump over the failure case 2703 __ ba(*success); 2704 __ delayed()->nop(); 2705 // Cast failure case 2706 __ bind(profile_cast_failure); 2707 metadata2reg(md->constant_encoding(), mdo); 2708 if (mdo_offset_bias > 0) { 2709 __ set(mdo_offset_bias, tmp1); 2710 __ add(mdo, tmp1, mdo); 2711 } 2712 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2713 __ ld_ptr(data_addr, tmp1); 2714 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2715 __ st_ptr(tmp1, data_addr); 2716 __ ba(*failure); 2717 __ delayed()->nop(); 2718 } 2719 __ ba(*success); 2720 __ delayed()->nop(); 2721} 2722 2723void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2724 LIR_Code code = op->code(); 2725 if (code == lir_store_check) { 2726 Register value = op->object()->as_register(); 2727 Register array = op->array()->as_register(); 2728 Register k_RInfo = op->tmp1()->as_register(); 2729 Register klass_RInfo = op->tmp2()->as_register(); 2730 Register Rtmp1 = op->tmp3()->as_register(); 2731 2732 __ verify_oop(value); 2733 CodeStub* stub = op->stub(); 2734 // check if it needs to be profiled 2735 ciMethodData* md; 2736 ciProfileData* data; 2737 int mdo_offset_bias = 0; 2738 if (op->should_profile()) { 2739 ciMethod* method = op->profiled_method(); 2740 assert(method != NULL, "Should have method"); 2741 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2742 } 2743 Label profile_cast_success, profile_cast_failure, done; 2744 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2745 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2746 2747 if (op->should_profile()) { 2748 Label not_null; 2749 __ br_notnull_short(value, Assembler::pn, not_null); 2750 Register mdo = k_RInfo; 2751 Register data_val = Rtmp1; 2752 metadata2reg(md->constant_encoding(), mdo); 2753 if (mdo_offset_bias > 0) { 2754 __ set(mdo_offset_bias, data_val); 2755 __ add(mdo, data_val, mdo); 2756 } 2757 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2758 __ ldub(flags_addr, data_val); 2759 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2760 __ stb(data_val, flags_addr); 2761 __ ba_short(done); 2762 __ bind(not_null); 2763 } else { 2764 __ br_null_short(value, Assembler::pn, done); 2765 } 2766 add_debug_info_for_null_check_here(op->info_for_exception()); 2767 __ load_klass(array, k_RInfo); 2768 __ load_klass(value, klass_RInfo); 2769 2770 // get instance klass 2771 __ ld_ptr(Address(k_RInfo, objArrayKlass::element_klass_offset()), k_RInfo); 2772 // perform the fast part of the checking logic 2773 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); 2774 2775 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2776 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2777 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2778 __ delayed()->nop(); 2779 __ cmp(G3, 0); 2780 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2781 __ delayed()->nop(); 2782 // fall through to the success case 2783 2784 if (op->should_profile()) { 2785 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2786 assert_different_registers(value, mdo, recv, tmp1); 2787 __ bind(profile_cast_success); 2788 metadata2reg(md->constant_encoding(), mdo); 2789 if (mdo_offset_bias > 0) { 2790 __ set(mdo_offset_bias, tmp1); 2791 __ add(mdo, tmp1, mdo); 2792 } 2793 __ load_klass(value, recv); 2794 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2795 __ ba_short(done); 2796 // Cast failure case 2797 __ bind(profile_cast_failure); 2798 metadata2reg(md->constant_encoding(), mdo); 2799 if (mdo_offset_bias > 0) { 2800 __ set(mdo_offset_bias, tmp1); 2801 __ add(mdo, tmp1, mdo); 2802 } 2803 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2804 __ ld_ptr(data_addr, tmp1); 2805 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2806 __ st_ptr(tmp1, data_addr); 2807 __ ba(*stub->entry()); 2808 __ delayed()->nop(); 2809 } 2810 __ bind(done); 2811 } else if (code == lir_checkcast) { 2812 Register obj = op->object()->as_register(); 2813 Register dst = op->result_opr()->as_register(); 2814 Label success; 2815 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2816 __ bind(success); 2817 __ mov(obj, dst); 2818 } else if (code == lir_instanceof) { 2819 Register obj = op->object()->as_register(); 2820 Register dst = op->result_opr()->as_register(); 2821 Label success, failure, done; 2822 emit_typecheck_helper(op, &success, &failure, &failure); 2823 __ bind(failure); 2824 __ set(0, dst); 2825 __ ba_short(done); 2826 __ bind(success); 2827 __ set(1, dst); 2828 __ bind(done); 2829 } else { 2830 ShouldNotReachHere(); 2831 } 2832 2833} 2834 2835 2836void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2837 if (op->code() == lir_cas_long) { 2838 assert(VM_Version::supports_cx8(), "wrong machine"); 2839 Register addr = op->addr()->as_pointer_register(); 2840 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2841 Register cmp_value_hi = op->cmp_value()->as_register_hi(); 2842 Register new_value_lo = op->new_value()->as_register_lo(); 2843 Register new_value_hi = op->new_value()->as_register_hi(); 2844 Register t1 = op->tmp1()->as_register(); 2845 Register t2 = op->tmp2()->as_register(); 2846#ifdef _LP64 2847 __ mov(cmp_value_lo, t1); 2848 __ mov(new_value_lo, t2); 2849 // perform the compare and swap operation 2850 __ casx(addr, t1, t2); 2851 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2852 // overwritten with the original value in "addr" and will be equal to t1. 2853 __ cmp(t1, t2); 2854#else 2855 // move high and low halves of long values into single registers 2856 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg 2857 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half 2858 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value 2859 __ sllx(new_value_hi, 32, t2); 2860 __ srl(new_value_lo, 0, new_value_lo); 2861 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap 2862 // perform the compare and swap operation 2863 __ casx(addr, t1, t2); 2864 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2865 // overwritten with the original value in "addr" and will be equal to t1. 2866 // Produce icc flag for 32bit. 2867 __ sub(t1, t2, t2); 2868 __ srlx(t2, 32, t1); 2869 __ orcc(t2, t1, G0); 2870#endif 2871 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2872 Register addr = op->addr()->as_pointer_register(); 2873 Register cmp_value = op->cmp_value()->as_register(); 2874 Register new_value = op->new_value()->as_register(); 2875 Register t1 = op->tmp1()->as_register(); 2876 Register t2 = op->tmp2()->as_register(); 2877 __ mov(cmp_value, t1); 2878 __ mov(new_value, t2); 2879 if (op->code() == lir_cas_obj) { 2880 if (UseCompressedOops) { 2881 __ encode_heap_oop(t1); 2882 __ encode_heap_oop(t2); 2883 __ cas(addr, t1, t2); 2884 } else { 2885 __ cas_ptr(addr, t1, t2); 2886 } 2887 } else { 2888 __ cas(addr, t1, t2); 2889 } 2890 __ cmp(t1, t2); 2891 } else { 2892 Unimplemented(); 2893 } 2894} 2895 2896void LIR_Assembler::set_24bit_FPU() { 2897 Unimplemented(); 2898} 2899 2900 2901void LIR_Assembler::reset_FPU() { 2902 Unimplemented(); 2903} 2904 2905 2906void LIR_Assembler::breakpoint() { 2907 __ breakpoint_trap(); 2908} 2909 2910 2911void LIR_Assembler::push(LIR_Opr opr) { 2912 Unimplemented(); 2913} 2914 2915 2916void LIR_Assembler::pop(LIR_Opr opr) { 2917 Unimplemented(); 2918} 2919 2920 2921void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2922 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2923 Register dst = dst_opr->as_register(); 2924 Register reg = mon_addr.base(); 2925 int offset = mon_addr.disp(); 2926 // compute pointer to BasicLock 2927 if (mon_addr.is_simm13()) { 2928 __ add(reg, offset, dst); 2929 } else { 2930 __ set(offset, dst); 2931 __ add(dst, reg, dst); 2932 } 2933} 2934 2935 2936void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2937 Register obj = op->obj_opr()->as_register(); 2938 Register hdr = op->hdr_opr()->as_register(); 2939 Register lock = op->lock_opr()->as_register(); 2940 2941 // obj may not be an oop 2942 if (op->code() == lir_lock) { 2943 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2944 if (UseFastLocking) { 2945 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2946 // add debug info for NullPointerException only if one is possible 2947 if (op->info() != NULL) { 2948 add_debug_info_for_null_check_here(op->info()); 2949 } 2950 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2951 } else { 2952 // always do slow locking 2953 // note: the slow locking code could be inlined here, however if we use 2954 // slow locking, speed doesn't matter anyway and this solution is 2955 // simpler and requires less duplicated code - additionally, the 2956 // slow locking code is the same in either case which simplifies 2957 // debugging 2958 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2959 __ delayed()->nop(); 2960 } 2961 } else { 2962 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2963 if (UseFastLocking) { 2964 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2965 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2966 } else { 2967 // always do slow unlocking 2968 // note: the slow unlocking code could be inlined here, however if we use 2969 // slow unlocking, speed doesn't matter anyway and this solution is 2970 // simpler and requires less duplicated code - additionally, the 2971 // slow unlocking code is the same in either case which simplifies 2972 // debugging 2973 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2974 __ delayed()->nop(); 2975 } 2976 } 2977 __ bind(*op->stub()->continuation()); 2978} 2979 2980 2981void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2982 ciMethod* method = op->profiled_method(); 2983 int bci = op->profiled_bci(); 2984 ciMethod* callee = op->profiled_callee(); 2985 2986 // Update counter for all call types 2987 ciMethodData* md = method->method_data_or_null(); 2988 assert(md != NULL, "Sanity"); 2989 ciProfileData* data = md->bci_to_data(bci); 2990 assert(data->is_CounterData(), "need CounterData for calls"); 2991 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2992 Register mdo = op->mdo()->as_register(); 2993#ifdef _LP64 2994 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2995 Register tmp1 = op->tmp1()->as_register_lo(); 2996#else 2997 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2998 Register tmp1 = op->tmp1()->as_register(); 2999#endif 3000 metadata2reg(md->constant_encoding(), mdo); 3001 int mdo_offset_bias = 0; 3002 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + 3003 data->size_in_bytes())) { 3004 // The offset is large so bias the mdo by the base of the slot so 3005 // that the ld can use simm13s to reference the slots of the data 3006 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 3007 __ set(mdo_offset_bias, O7); 3008 __ add(mdo, O7, mdo); 3009 } 3010 3011 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 3012 Bytecodes::Code bc = method->java_code_at_bci(bci); 3013 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 3014 // Perform additional virtual call profiling for invokevirtual and 3015 // invokeinterface bytecodes 3016 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 3017 !callee_is_static && // required for optimized MH invokes 3018 C1ProfileVirtualCalls) { 3019 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 3020 Register recv = op->recv()->as_register(); 3021 assert_different_registers(mdo, tmp1, recv); 3022 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 3023 ciKlass* known_klass = op->known_holder(); 3024 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 3025 // We know the type that will be seen at this call site; we can 3026 // statically update the MethodData* rather than needing to do 3027 // dynamic tests on the receiver type 3028 3029 // NOTE: we should probably put a lock around this search to 3030 // avoid collisions by concurrent compilations 3031 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 3032 uint i; 3033 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3034 ciKlass* receiver = vc_data->receiver(i); 3035 if (known_klass->equals(receiver)) { 3036 Address data_addr(mdo, md->byte_offset_of_slot(data, 3037 VirtualCallData::receiver_count_offset(i)) - 3038 mdo_offset_bias); 3039 __ ld_ptr(data_addr, tmp1); 3040 __ add(tmp1, DataLayout::counter_increment, tmp1); 3041 __ st_ptr(tmp1, data_addr); 3042 return; 3043 } 3044 } 3045 3046 // Receiver type not found in profile data; select an empty slot 3047 3048 // Note that this is less efficient than it should be because it 3049 // always does a write to the receiver part of the 3050 // VirtualCallData rather than just the first time 3051 for (i = 0; i < VirtualCallData::row_limit(); i++) { 3052 ciKlass* receiver = vc_data->receiver(i); 3053 if (receiver == NULL) { 3054 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 3055 mdo_offset_bias); 3056 metadata2reg(known_klass->constant_encoding(), tmp1); 3057 __ st_ptr(tmp1, recv_addr); 3058 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 3059 mdo_offset_bias); 3060 __ ld_ptr(data_addr, tmp1); 3061 __ add(tmp1, DataLayout::counter_increment, tmp1); 3062 __ st_ptr(tmp1, data_addr); 3063 return; 3064 } 3065 } 3066 } else { 3067 __ load_klass(recv, recv); 3068 Label update_done; 3069 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 3070 // Receiver did not match any saved receiver and there is no empty row for it. 3071 // Increment total counter to indicate polymorphic case. 3072 __ ld_ptr(counter_addr, tmp1); 3073 __ add(tmp1, DataLayout::counter_increment, tmp1); 3074 __ st_ptr(tmp1, counter_addr); 3075 3076 __ bind(update_done); 3077 } 3078 } else { 3079 // Static call 3080 __ ld_ptr(counter_addr, tmp1); 3081 __ add(tmp1, DataLayout::counter_increment, tmp1); 3082 __ st_ptr(tmp1, counter_addr); 3083 } 3084} 3085 3086void LIR_Assembler::align_backward_branch_target() { 3087 __ align(OptoLoopAlignment); 3088} 3089 3090 3091void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 3092 // make sure we are expecting a delay 3093 // this has the side effect of clearing the delay state 3094 // so we can use _masm instead of _masm->delayed() to do the 3095 // code generation. 3096 __ delayed(); 3097 3098 // make sure we only emit one instruction 3099 int offset = code_offset(); 3100 op->delay_op()->emit_code(this); 3101#ifdef ASSERT 3102 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { 3103 op->delay_op()->print(); 3104 } 3105 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, 3106 "only one instruction can go in a delay slot"); 3107#endif 3108 3109 // we may also be emitting the call info for the instruction 3110 // which we are the delay slot of. 3111 CodeEmitInfo* call_info = op->call_info(); 3112 if (call_info) { 3113 add_call_info(code_offset(), call_info); 3114 } 3115 3116 if (VerifyStackAtCalls) { 3117 _masm->sub(FP, SP, O7); 3118 _masm->cmp(O7, initial_frame_size_in_bytes()); 3119 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); 3120 } 3121} 3122 3123 3124void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3125 assert(left->is_register(), "can only handle registers"); 3126 3127 if (left->is_single_cpu()) { 3128 __ neg(left->as_register(), dest->as_register()); 3129 } else if (left->is_single_fpu()) { 3130 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); 3131 } else if (left->is_double_fpu()) { 3132 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); 3133 } else { 3134 assert (left->is_double_cpu(), "Must be a long"); 3135 Register Rlow = left->as_register_lo(); 3136 Register Rhi = left->as_register_hi(); 3137#ifdef _LP64 3138 __ sub(G0, Rlow, dest->as_register_lo()); 3139#else 3140 __ subcc(G0, Rlow, dest->as_register_lo()); 3141 __ subc (G0, Rhi, dest->as_register_hi()); 3142#endif 3143 } 3144} 3145 3146 3147void LIR_Assembler::fxch(int i) { 3148 Unimplemented(); 3149} 3150 3151void LIR_Assembler::fld(int i) { 3152 Unimplemented(); 3153} 3154 3155void LIR_Assembler::ffree(int i) { 3156 Unimplemented(); 3157} 3158 3159void LIR_Assembler::rt_call(LIR_Opr result, address dest, 3160 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3161 3162 // if tmp is invalid, then the function being called doesn't destroy the thread 3163 if (tmp->is_valid()) { 3164 __ save_thread(tmp->as_register()); 3165 } 3166 __ call(dest, relocInfo::runtime_call_type); 3167 __ delayed()->nop(); 3168 if (info != NULL) { 3169 add_call_info_here(info); 3170 } 3171 if (tmp->is_valid()) { 3172 __ restore_thread(tmp->as_register()); 3173 } 3174 3175#ifdef ASSERT 3176 __ verify_thread(); 3177#endif // ASSERT 3178} 3179 3180 3181void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3182#ifdef _LP64 3183 ShouldNotReachHere(); 3184#endif 3185 3186 NEEDS_CLEANUP; 3187 if (type == T_LONG) { 3188 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); 3189 3190 // (extended to allow indexed as well as constant displaced for JSR-166) 3191 Register idx = noreg; // contains either constant offset or index 3192 3193 int disp = mem_addr->disp(); 3194 if (mem_addr->index() == LIR_OprFact::illegalOpr) { 3195 if (!Assembler::is_simm13(disp)) { 3196 idx = O7; 3197 __ set(disp, idx); 3198 } 3199 } else { 3200 assert(disp == 0, "not both indexed and disp"); 3201 idx = mem_addr->index()->as_register(); 3202 } 3203 3204 int null_check_offset = -1; 3205 3206 Register base = mem_addr->base()->as_register(); 3207 if (src->is_register() && dest->is_address()) { 3208 // G4 is high half, G5 is low half 3209 if (VM_Version::v9_instructions_work()) { 3210 // clear the top bits of G5, and scale up G4 3211 __ srl (src->as_register_lo(), 0, G5); 3212 __ sllx(src->as_register_hi(), 32, G4); 3213 // combine the two halves into the 64 bits of G4 3214 __ or3(G4, G5, G4); 3215 null_check_offset = __ offset(); 3216 if (idx == noreg) { 3217 __ stx(G4, base, disp); 3218 } else { 3219 __ stx(G4, base, idx); 3220 } 3221 } else { 3222 __ mov (src->as_register_hi(), G4); 3223 __ mov (src->as_register_lo(), G5); 3224 null_check_offset = __ offset(); 3225 if (idx == noreg) { 3226 __ std(G4, base, disp); 3227 } else { 3228 __ std(G4, base, idx); 3229 } 3230 } 3231 } else if (src->is_address() && dest->is_register()) { 3232 null_check_offset = __ offset(); 3233 if (VM_Version::v9_instructions_work()) { 3234 if (idx == noreg) { 3235 __ ldx(base, disp, G5); 3236 } else { 3237 __ ldx(base, idx, G5); 3238 } 3239 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi 3240 __ mov (G5, dest->as_register_lo()); // copy low half into lo 3241 } else { 3242 if (idx == noreg) { 3243 __ ldd(base, disp, G4); 3244 } else { 3245 __ ldd(base, idx, G4); 3246 } 3247 // G4 is high half, G5 is low half 3248 __ mov (G4, dest->as_register_hi()); 3249 __ mov (G5, dest->as_register_lo()); 3250 } 3251 } else { 3252 Unimplemented(); 3253 } 3254 if (info != NULL) { 3255 add_debug_info_for_null_check(null_check_offset, info); 3256 } 3257 3258 } else { 3259 // use normal move for all other volatiles since they don't need 3260 // special handling to remain atomic. 3261 move_op(src, dest, type, lir_patch_none, info, false, false, false); 3262 } 3263} 3264 3265void LIR_Assembler::membar() { 3266 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode 3267 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3268} 3269 3270void LIR_Assembler::membar_acquire() { 3271 // no-op on TSO 3272} 3273 3274void LIR_Assembler::membar_release() { 3275 // no-op on TSO 3276} 3277 3278void LIR_Assembler::membar_loadload() { 3279 // no-op 3280 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3281} 3282 3283void LIR_Assembler::membar_storestore() { 3284 // no-op 3285 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3286} 3287 3288void LIR_Assembler::membar_loadstore() { 3289 // no-op 3290 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3291} 3292 3293void LIR_Assembler::membar_storeload() { 3294 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3295} 3296 3297 3298// Pack two sequential registers containing 32 bit values 3299// into a single 64 bit register. 3300// src and src->successor() are packed into dst 3301// src and dst may be the same register. 3302// Note: src is destroyed 3303void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { 3304 Register rs = src->as_register(); 3305 Register rd = dst->as_register_lo(); 3306 __ sllx(rs, 32, rs); 3307 __ srl(rs->successor(), 0, rs->successor()); 3308 __ or3(rs, rs->successor(), rd); 3309} 3310 3311// Unpack a 64 bit value in a register into 3312// two sequential registers. 3313// src is unpacked into dst and dst->successor() 3314void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { 3315 Register rs = src->as_register_lo(); 3316 Register rd = dst->as_register_hi(); 3317 assert_different_registers(rs, rd, rd->successor()); 3318 __ srlx(rs, 32, rd); 3319 __ srl (rs, 0, rd->successor()); 3320} 3321 3322 3323void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 3324 LIR_Address* addr = addr_opr->as_address_ptr(); 3325 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); 3326 3327 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); 3328} 3329 3330 3331void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3332 assert(result_reg->is_register(), "check"); 3333 __ mov(G2_thread, result_reg->as_register()); 3334} 3335 3336 3337void LIR_Assembler::peephole(LIR_List* lir) { 3338 LIR_OpList* inst = lir->instructions_list(); 3339 for (int i = 0; i < inst->length(); i++) { 3340 LIR_Op* op = inst->at(i); 3341 switch (op->code()) { 3342 case lir_cond_float_branch: 3343 case lir_branch: { 3344 LIR_OpBranch* branch = op->as_OpBranch(); 3345 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); 3346 LIR_Op* delay_op = NULL; 3347 // we'd like to be able to pull following instructions into 3348 // this slot but we don't know enough to do it safely yet so 3349 // only optimize block to block control flow. 3350 if (LIRFillDelaySlots && branch->block()) { 3351 LIR_Op* prev = inst->at(i - 1); 3352 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { 3353 // swap previous instruction into delay slot 3354 inst->at_put(i - 1, op); 3355 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3356#ifndef PRODUCT 3357 if (LIRTracePeephole) { 3358 tty->print_cr("delayed"); 3359 inst->at(i - 1)->print(); 3360 inst->at(i)->print(); 3361 tty->cr(); 3362 } 3363#endif 3364 continue; 3365 } 3366 } 3367 3368 if (!delay_op) { 3369 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); 3370 } 3371 inst->insert_before(i + 1, delay_op); 3372 break; 3373 } 3374 case lir_static_call: 3375 case lir_virtual_call: 3376 case lir_icvirtual_call: 3377 case lir_optvirtual_call: 3378 case lir_dynamic_call: { 3379 LIR_Op* prev = inst->at(i - 1); 3380 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && 3381 (op->code() != lir_virtual_call || 3382 !prev->result_opr()->is_single_cpu() || 3383 prev->result_opr()->as_register() != O0) && 3384 LIR_Assembler::is_single_instruction(prev)) { 3385 // Only moves without info can be put into the delay slot. 3386 // Also don't allow the setup of the receiver in the delay 3387 // slot for vtable calls. 3388 inst->at_put(i - 1, op); 3389 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3390#ifndef PRODUCT 3391 if (LIRTracePeephole) { 3392 tty->print_cr("delayed"); 3393 inst->at(i - 1)->print(); 3394 inst->at(i)->print(); 3395 tty->cr(); 3396 } 3397#endif 3398 } else { 3399 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); 3400 inst->insert_before(i + 1, delay_op); 3401 i++; 3402 } 3403 3404#if defined(TIERED) && !defined(_LP64) 3405 // fixup the return value from G1 to O0/O1 for long returns. 3406 // It's done here instead of in LIRGenerator because there's 3407 // such a mismatch between the single reg and double reg 3408 // calling convention. 3409 LIR_OpJavaCall* callop = op->as_OpJavaCall(); 3410 if (callop->result_opr() == FrameMap::out_long_opr) { 3411 LIR_OpJavaCall* call; 3412 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); 3413 for (int a = 0; a < arguments->length(); a++) { 3414 arguments[a] = callop->arguments()[a]; 3415 } 3416 if (op->code() == lir_virtual_call) { 3417 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, 3418 callop->vtable_offset(), arguments, callop->info()); 3419 } else { 3420 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, 3421 callop->addr(), arguments, callop->info()); 3422 } 3423 inst->at_put(i - 1, call); 3424 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), 3425 T_LONG, lir_patch_none, NULL)); 3426 } 3427#endif 3428 break; 3429 } 3430 } 3431 } 3432} 3433 3434 3435 3436 3437#undef __ 3438