1/* 2 * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25#include "precompiled.hpp" 26#include "c1/c1_Compilation.hpp" 27#include "c1/c1_LIRAssembler.hpp" 28#include "c1/c1_MacroAssembler.hpp" 29#include "c1/c1_Runtime1.hpp" 30#include "c1/c1_ValueStack.hpp" 31#include "ci/ciArrayKlass.hpp" 32#include "ci/ciInstance.hpp" 33#include "gc/shared/barrierSet.hpp" 34#include "gc/shared/cardTableModRefBS.hpp" 35#include "gc/shared/collectedHeap.hpp" 36#include "nativeInst_sparc.hpp" 37#include "oops/objArrayKlass.hpp" 38#include "runtime/sharedRuntime.hpp" 39 40#define __ _masm-> 41 42 43//------------------------------------------------------------ 44 45 46bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 47 if (opr->is_constant()) { 48 LIR_Const* constant = opr->as_constant_ptr(); 49 switch (constant->type()) { 50 case T_INT: { 51 jint value = constant->as_jint(); 52 return Assembler::is_simm13(value); 53 } 54 55 default: 56 return false; 57 } 58 } 59 return false; 60} 61 62 63bool LIR_Assembler::is_single_instruction(LIR_Op* op) { 64 switch (op->code()) { 65 case lir_null_check: 66 return true; 67 68 69 case lir_add: 70 case lir_ushr: 71 case lir_shr: 72 case lir_shl: 73 // integer shifts and adds are always one instruction 74 return op->result_opr()->is_single_cpu(); 75 76 77 case lir_move: { 78 LIR_Op1* op1 = op->as_Op1(); 79 LIR_Opr src = op1->in_opr(); 80 LIR_Opr dst = op1->result_opr(); 81 82 if (src == dst) { 83 NEEDS_CLEANUP; 84 // this works around a problem where moves with the same src and dst 85 // end up in the delay slot and then the assembler swallows the mov 86 // since it has no effect and then it complains because the delay slot 87 // is empty. returning false stops the optimizer from putting this in 88 // the delay slot 89 return false; 90 } 91 92 // don't put moves involving oops into the delay slot since the VerifyOops code 93 // will make it much larger than a single instruction. 94 if (VerifyOops) { 95 return false; 96 } 97 98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || 99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { 100 return false; 101 } 102 103 if (UseCompressedOops) { 104 if (dst->is_address() && !dst->is_stack() && (dst->type() == T_OBJECT || dst->type() == T_ARRAY)) return false; 105 if (src->is_address() && !src->is_stack() && (src->type() == T_OBJECT || src->type() == T_ARRAY)) return false; 106 } 107 108 if (UseCompressedClassPointers) { 109 if (src->is_address() && !src->is_stack() && src->type() == T_ADDRESS && 110 src->as_address_ptr()->disp() == oopDesc::klass_offset_in_bytes()) return false; 111 } 112 113 if (dst->is_register()) { 114 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { 115 return !PatchALot; 116 } else if (src->is_single_stack()) { 117 return true; 118 } 119 } 120 121 if (src->is_register()) { 122 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { 123 return !PatchALot; 124 } else if (dst->is_single_stack()) { 125 return true; 126 } 127 } 128 129 if (dst->is_register() && 130 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || 131 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { 132 return true; 133 } 134 135 return false; 136 } 137 138 default: 139 return false; 140 } 141 ShouldNotReachHere(); 142} 143 144 145LIR_Opr LIR_Assembler::receiverOpr() { 146 return FrameMap::O0_oop_opr; 147} 148 149 150LIR_Opr LIR_Assembler::osrBufferPointer() { 151 return FrameMap::I0_opr; 152} 153 154 155int LIR_Assembler::initial_frame_size_in_bytes() const { 156 return in_bytes(frame_map()->framesize_in_bytes()); 157} 158 159 160// inline cache check: the inline cached class is in G5_inline_cache_reg(G5); 161// we fetch the class of the receiver (O0) and compare it with the cached class. 162// If they do not match we jump to slow case. 163int LIR_Assembler::check_icache() { 164 int offset = __ offset(); 165 __ inline_cache_check(O0, G5_inline_cache_reg); 166 return offset; 167} 168 169 170void LIR_Assembler::osr_entry() { 171 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 172 // 173 // 1. Create a new compiled activation. 174 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 175 // at the osr_bci; it is not initialized. 176 // 3. Jump to the continuation address in compiled code to resume execution. 177 178 // OSR entry point 179 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 180 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 181 ValueStack* entry_state = osr_entry->end()->state(); 182 int number_of_locks = entry_state->locks_size(); 183 184 // Create a frame for the compiled activation. 185 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes()); 186 187 // OSR buffer is 188 // 189 // locals[nlocals-1..0] 190 // monitors[number_of_locks-1..0] 191 // 192 // locals is a direct copy of the interpreter frame so in the osr buffer 193 // so first slot in the local array is the last local from the interpreter 194 // and last slot is local[0] (receiver) from the interpreter 195 // 196 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 197 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 198 // in the interpreter frame (the method lock if a sync method) 199 200 // Initialize monitors in the compiled activation. 201 // I0: pointer to osr buffer 202 // 203 // All other registers are dead at this point and the locals will be 204 // copied into place by code emitted in the IR. 205 206 Register OSR_buf = osrBufferPointer()->as_register(); 207 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 208 int monitor_offset = BytesPerWord * method()->max_locals() + 209 (2 * BytesPerWord) * (number_of_locks - 1); 210 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 211 // the OSR buffer using 2 word entries: first the lock and then 212 // the oop. 213 for (int i = 0; i < number_of_locks; i++) { 214 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 215#ifdef ASSERT 216 // verify the interpreter's monitor has a non-null object 217 { 218 Label L; 219 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 220 __ cmp_and_br_short(O7, G0, Assembler::notEqual, Assembler::pt, L); 221 __ stop("locked object is NULL"); 222 __ bind(L); 223 } 224#endif // ASSERT 225 // Copy the lock field into the compiled activation. 226 __ ld_ptr(OSR_buf, slot_offset + 0, O7); 227 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); 228 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 229 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); 230 } 231 } 232} 233 234 235// -------------------------------------------------------------------------------------------- 236 237void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { 238 if (!GenerateSynchronizationCode) return; 239 240 Register obj_reg = obj_opr->as_register(); 241 Register lock_reg = lock_opr->as_register(); 242 243 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 244 Register reg = mon_addr.base(); 245 int offset = mon_addr.disp(); 246 // compute pointer to BasicLock 247 if (mon_addr.is_simm13()) { 248 __ add(reg, offset, lock_reg); 249 } 250 else { 251 __ set(offset, lock_reg); 252 __ add(reg, lock_reg, lock_reg); 253 } 254 // unlock object 255 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); 256 // _slow_case_stubs->append(slow_case); 257 // temporary fix: must be created after exceptionhandler, therefore as call stub 258 _slow_case_stubs->append(slow_case); 259 if (UseFastLocking) { 260 // try inlined fast unlocking first, revert to slow locking if it fails 261 // note: lock_reg points to the displaced header since the displaced header offset is 0! 262 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 263 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 264 } else { 265 // always do slow unlocking 266 // note: the slow unlocking code could be inlined here, however if we use 267 // slow unlocking, speed doesn't matter anyway and this solution is 268 // simpler and requires less duplicated code - additionally, the 269 // slow unlocking code is the same in either case which simplifies 270 // debugging 271 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); 272 __ delayed()->nop(); 273 } 274 // done 275 __ bind(*slow_case->continuation()); 276} 277 278 279int LIR_Assembler::emit_exception_handler() { 280 // if the last instruction is a call (typically to do a throw which 281 // is coming at the end after block reordering) the return address 282 // must still point into the code area in order to avoid assertion 283 // failures when searching for the corresponding bci => add a nop 284 // (was bug 5/14/1999 - gri) 285 __ nop(); 286 287 // generate code for exception handler 288 ciMethod* method = compilation()->method(); 289 290 address handler_base = __ start_a_stub(exception_handler_size()); 291 292 if (handler_base == NULL) { 293 // not enough space left for the handler 294 bailout("exception handler overflow"); 295 return -1; 296 } 297 298 int offset = code_offset(); 299 300 __ call(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id), relocInfo::runtime_call_type); 301 __ delayed()->nop(); 302 __ should_not_reach_here(); 303 guarantee(code_offset() - offset <= exception_handler_size(), "overflow"); 304 __ end_a_stub(); 305 306 return offset; 307} 308 309 310// Emit the code to remove the frame from the stack in the exception 311// unwind path. 312int LIR_Assembler::emit_unwind_handler() { 313#ifndef PRODUCT 314 if (CommentedAssembly) { 315 _masm->block_comment("Unwind handler"); 316 } 317#endif 318 319 int offset = code_offset(); 320 321 // Fetch the exception from TLS and clear out exception related thread state 322 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); 323 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 324 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); 325 326 __ bind(_unwind_handler_entry); 327 __ verify_not_null_oop(O0); 328 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 329 __ mov(O0, I0); // Preserve the exception 330 } 331 332 // Preform needed unlocking 333 MonitorExitStub* stub = NULL; 334 if (method()->is_synchronized()) { 335 monitor_address(0, FrameMap::I1_opr); 336 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); 337 __ unlock_object(I3, I2, I1, *stub->entry()); 338 __ bind(*stub->continuation()); 339 } 340 341 if (compilation()->env()->dtrace_method_probes()) { 342 __ mov(G2_thread, O0); 343 __ save_thread(I1); // need to preserve thread in G2 across 344 // runtime call 345 metadata2reg(method()->constant_encoding(), O1); 346 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); 347 __ delayed()->nop(); 348 __ restore_thread(I1); 349 } 350 351 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 352 __ mov(I0, O0); // Restore the exception 353 } 354 355 // dispatch to the unwind logic 356 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 357 __ delayed()->nop(); 358 359 // Emit the slow path assembly 360 if (stub != NULL) { 361 stub->emit_code(this); 362 } 363 364 return offset; 365} 366 367 368int LIR_Assembler::emit_deopt_handler() { 369 // if the last instruction is a call (typically to do a throw which 370 // is coming at the end after block reordering) the return address 371 // must still point into the code area in order to avoid assertion 372 // failures when searching for the corresponding bci => add a nop 373 // (was bug 5/14/1999 - gri) 374 __ nop(); 375 376 // generate code for deopt handler 377 ciMethod* method = compilation()->method(); 378 address handler_base = __ start_a_stub(deopt_handler_size()); 379 if (handler_base == NULL) { 380 // not enough space left for the handler 381 bailout("deopt handler overflow"); 382 return -1; 383 } 384 385 int offset = code_offset(); 386 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 387 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp 388 __ delayed()->nop(); 389 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow"); 390 __ end_a_stub(); 391 392 return offset; 393} 394 395 396void LIR_Assembler::jobject2reg(jobject o, Register reg) { 397 if (o == NULL) { 398 __ set(NULL_WORD, reg); 399 } else { 400 int oop_index = __ oop_recorder()->find_index(o); 401 assert(Universe::heap()->is_in_reserved(JNIHandles::resolve(o)), "should be real oop"); 402 RelocationHolder rspec = oop_Relocation::spec(oop_index); 403 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created 404 } 405} 406 407 408void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 409 // Allocate a new index in table to hold the object once it's been patched 410 int oop_index = __ oop_recorder()->allocate_oop_index(NULL); 411 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index); 412 413 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); 414 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 415 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 416 // NULL will be dynamically patched later and the patched value may be large. We must 417 // therefore generate the sethi/add as a placeholders 418 __ patchable_set(addrlit, reg); 419 420 patching_epilog(patch, lir_patch_normal, reg, info); 421} 422 423 424void LIR_Assembler::metadata2reg(Metadata* o, Register reg) { 425 __ set_metadata_constant(o, reg); 426} 427 428void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) { 429 // Allocate a new index in table to hold the klass once it's been patched 430 int index = __ oop_recorder()->allocate_metadata_index(NULL); 431 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index); 432 AddressLiteral addrlit(NULL, metadata_Relocation::spec(index)); 433 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc"); 434 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 435 // NULL will be dynamically patched later and the patched value may be large. We must 436 // therefore generate the sethi/add as a placeholders 437 __ patchable_set(addrlit, reg); 438 439 patching_epilog(patch, lir_patch_normal, reg, info); 440} 441 442void LIR_Assembler::emit_op3(LIR_Op3* op) { 443 switch (op->code()) { 444 case lir_idiv: 445 case lir_irem: // Both idiv & irem are handled after the switch (below). 446 break; 447 case lir_fmaf: 448 __ fmadd(FloatRegisterImpl::S, 449 op->in_opr1()->as_float_reg(), 450 op->in_opr2()->as_float_reg(), 451 op->in_opr3()->as_float_reg(), 452 op->result_opr()->as_float_reg()); 453 return; 454 case lir_fmad: 455 __ fmadd(FloatRegisterImpl::D, 456 op->in_opr1()->as_double_reg(), 457 op->in_opr2()->as_double_reg(), 458 op->in_opr3()->as_double_reg(), 459 op->result_opr()->as_double_reg()); 460 return; 461 default: 462 ShouldNotReachHere(); 463 break; 464 } 465 466 // Handle idiv & irem: 467 468 Register Rdividend = op->in_opr1()->as_register(); 469 Register Rdivisor = noreg; 470 Register Rscratch = op->in_opr3()->as_register(); 471 Register Rresult = op->result_opr()->as_register(); 472 int divisor = -1; 473 474 if (op->in_opr2()->is_register()) { 475 Rdivisor = op->in_opr2()->as_register(); 476 } else { 477 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); 478 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 479 } 480 481 assert(Rdividend != Rscratch, ""); 482 assert(Rdivisor != Rscratch, ""); 483 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); 484 485 if (Rdivisor == noreg && is_power_of_2(divisor)) { 486 // convert division by a power of two into some shifts and logical operations 487 if (op->code() == lir_idiv) { 488 if (divisor == 2) { 489 __ srl(Rdividend, 31, Rscratch); 490 } else { 491 __ sra(Rdividend, 31, Rscratch); 492 __ and3(Rscratch, divisor - 1, Rscratch); 493 } 494 __ add(Rdividend, Rscratch, Rscratch); 495 __ sra(Rscratch, log2_intptr(divisor), Rresult); 496 return; 497 } else { 498 if (divisor == 2) { 499 __ srl(Rdividend, 31, Rscratch); 500 } else { 501 __ sra(Rdividend, 31, Rscratch); 502 __ and3(Rscratch, divisor - 1,Rscratch); 503 } 504 __ add(Rdividend, Rscratch, Rscratch); 505 __ andn(Rscratch, divisor - 1,Rscratch); 506 __ sub(Rdividend, Rscratch, Rresult); 507 return; 508 } 509 } 510 511 __ sra(Rdividend, 31, Rscratch); 512 __ wry(Rscratch); 513 514 add_debug_info_for_div0_here(op->info()); 515 516 if (Rdivisor != noreg) { 517 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 518 } else { 519 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 520 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 521 } 522 523 Label skip; 524 __ br(Assembler::overflowSet, true, Assembler::pn, skip); 525 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); 526 __ bind(skip); 527 528 if (op->code() == lir_irem) { 529 if (Rdivisor != noreg) { 530 __ smul(Rscratch, Rdivisor, Rscratch); 531 } else { 532 __ smul(Rscratch, divisor, Rscratch); 533 } 534 __ sub(Rdividend, Rscratch, Rresult); 535 } 536} 537 538 539void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 540#ifdef ASSERT 541 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 542 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 543 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 544#endif 545 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 546 547 if (op->cond() == lir_cond_always) { 548 __ br(Assembler::always, false, Assembler::pt, *(op->label())); 549 } else if (op->code() == lir_cond_float_branch) { 550 assert(op->ublock() != NULL, "must have unordered successor"); 551 bool is_unordered = (op->ublock() == op->block()); 552 Assembler::Condition acond; 553 switch (op->cond()) { 554 case lir_cond_equal: acond = Assembler::f_equal; break; 555 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; 556 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; 557 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; 558 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; 559 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; 560 default : ShouldNotReachHere(); 561 } 562 __ fb( acond, false, Assembler::pn, *(op->label())); 563 } else { 564 assert (op->code() == lir_branch, "just checking"); 565 566 Assembler::Condition acond; 567 switch (op->cond()) { 568 case lir_cond_equal: acond = Assembler::equal; break; 569 case lir_cond_notEqual: acond = Assembler::notEqual; break; 570 case lir_cond_less: acond = Assembler::less; break; 571 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 572 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 573 case lir_cond_greater: acond = Assembler::greater; break; 574 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 575 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 576 default: ShouldNotReachHere(); 577 }; 578 579 // sparc has different condition codes for testing 32-bit 580 // vs. 64-bit values. We could always test xcc is we could 581 // guarantee that 32-bit loads always sign extended but that isn't 582 // true and since sign extension isn't free, it would impose a 583 // slight cost. 584 if (op->type() == T_INT) { 585 __ br(acond, false, Assembler::pn, *(op->label())); 586 } else 587 __ brx(acond, false, Assembler::pn, *(op->label())); 588 } 589 // The peephole pass fills the delay slot 590} 591 592 593void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 594 Bytecodes::Code code = op->bytecode(); 595 LIR_Opr dst = op->result_opr(); 596 597 switch(code) { 598 case Bytecodes::_i2l: { 599 Register rlo = dst->as_register_lo(); 600 Register rhi = dst->as_register_hi(); 601 Register rval = op->in_opr()->as_register(); 602 __ sra(rval, 0, rlo); 603 break; 604 } 605 case Bytecodes::_i2d: 606 case Bytecodes::_i2f: { 607 bool is_double = (code == Bytecodes::_i2d); 608 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 609 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 610 FloatRegister rsrc = op->in_opr()->as_float_reg(); 611 if (rsrc != rdst) { 612 __ fmov(FloatRegisterImpl::S, rsrc, rdst); 613 } 614 __ fitof(w, rdst, rdst); 615 break; 616 } 617 case Bytecodes::_f2i:{ 618 FloatRegister rsrc = op->in_opr()->as_float_reg(); 619 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); 620 Label L; 621 // result must be 0 if value is NaN; test by comparing value to itself 622 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); 623 __ fb(Assembler::f_unordered, true, Assembler::pn, L); 624 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN 625 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); 626 // move integer result from float register to int register 627 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); 628 __ bind (L); 629 break; 630 } 631 case Bytecodes::_l2i: { 632 Register rlo = op->in_opr()->as_register_lo(); 633 Register rhi = op->in_opr()->as_register_hi(); 634 Register rdst = dst->as_register(); 635 __ sra(rlo, 0, rdst); 636 break; 637 } 638 case Bytecodes::_d2f: 639 case Bytecodes::_f2d: { 640 bool is_double = (code == Bytecodes::_f2d); 641 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); 642 LIR_Opr val = op->in_opr(); 643 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); 644 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 645 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; 646 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 647 __ ftof(vw, dw, rval, rdst); 648 break; 649 } 650 case Bytecodes::_i2s: 651 case Bytecodes::_i2b: { 652 Register rval = op->in_opr()->as_register(); 653 Register rdst = dst->as_register(); 654 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); 655 __ sll (rval, shift, rdst); 656 __ sra (rdst, shift, rdst); 657 break; 658 } 659 case Bytecodes::_i2c: { 660 Register rval = op->in_opr()->as_register(); 661 Register rdst = dst->as_register(); 662 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; 663 __ sll (rval, shift, rdst); 664 __ srl (rdst, shift, rdst); 665 break; 666 } 667 668 default: ShouldNotReachHere(); 669 } 670} 671 672 673void LIR_Assembler::align_call(LIR_Code) { 674 // do nothing since all instructions are word aligned on sparc 675} 676 677 678void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 679 __ call(op->addr(), rtype); 680 // The peephole pass fills the delay slot, add_call_info is done in 681 // LIR_Assembler::emit_delay. 682} 683 684 685void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 686 __ ic_call(op->addr(), false); 687 // The peephole pass fills the delay slot, add_call_info is done in 688 // LIR_Assembler::emit_delay. 689} 690 691 692void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 693 add_debug_info_for_null_check_here(op->info()); 694 __ load_klass(O0, G3_scratch); 695 if (Assembler::is_simm13(op->vtable_offset())) { 696 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); 697 } else { 698 // This will generate 2 instructions 699 __ set(op->vtable_offset(), G5_method); 700 // ld_ptr, set_hi, set 701 __ ld_ptr(G3_scratch, G5_method, G5_method); 702 } 703 __ ld_ptr(G5_method, Method::from_compiled_offset(), G3_scratch); 704 __ callr(G3_scratch, G0); 705 // the peephole pass fills the delay slot 706} 707 708int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) { 709 int store_offset; 710 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 711 assert(base != O7, "destroying register"); 712 assert(!unaligned, "can't handle this"); 713 // for offsets larger than a simm13 we setup the offset in O7 714 __ set(offset, O7); 715 store_offset = store(from_reg, base, O7, type, wide); 716 } else { 717 if (type == T_ARRAY || type == T_OBJECT) { 718 __ verify_oop(from_reg->as_register()); 719 } 720 store_offset = code_offset(); 721 switch (type) { 722 case T_BOOLEAN: // fall through 723 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; 724 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; 725 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; 726 case T_INT : __ stw(from_reg->as_register(), base, offset); break; 727 case T_LONG : 728 if (unaligned || PatchALot) { 729 // Don't use O7 here because it may be equal to 'base' (see LIR_Assembler::reg2mem) 730 assert(G3_scratch != base, "can't handle this"); 731 assert(G3_scratch != from_reg->as_register_lo(), "can't handle this"); 732 __ srax(from_reg->as_register_lo(), 32, G3_scratch); 733 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 734 __ stw(G3_scratch, base, offset + hi_word_offset_in_bytes); 735 } else { 736 __ stx(from_reg->as_register_lo(), base, offset); 737 } 738 break; 739 case T_ADDRESS: 740 case T_METADATA: 741 __ st_ptr(from_reg->as_register(), base, offset); 742 break; 743 case T_ARRAY : // fall through 744 case T_OBJECT: 745 { 746 if (UseCompressedOops && !wide) { 747 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 748 store_offset = code_offset(); 749 __ stw(G3_scratch, base, offset); 750 } else { 751 __ st_ptr(from_reg->as_register(), base, offset); 752 } 753 break; 754 } 755 756 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; 757 case T_DOUBLE: 758 { 759 FloatRegister reg = from_reg->as_double_reg(); 760 // split unaligned stores 761 if (unaligned || PatchALot) { 762 assert(Assembler::is_simm13(offset + 4), "must be"); 763 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); 764 __ stf(FloatRegisterImpl::S, reg, base, offset); 765 } else { 766 __ stf(FloatRegisterImpl::D, reg, base, offset); 767 } 768 break; 769 } 770 default : ShouldNotReachHere(); 771 } 772 } 773 return store_offset; 774} 775 776 777int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) { 778 if (type == T_ARRAY || type == T_OBJECT) { 779 __ verify_oop(from_reg->as_register()); 780 } 781 int store_offset = code_offset(); 782 switch (type) { 783 case T_BOOLEAN: // fall through 784 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; 785 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; 786 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; 787 case T_INT : __ stw(from_reg->as_register(), base, disp); break; 788 case T_LONG : 789 __ stx(from_reg->as_register_lo(), base, disp); 790 break; 791 case T_ADDRESS: 792 __ st_ptr(from_reg->as_register(), base, disp); 793 break; 794 case T_ARRAY : // fall through 795 case T_OBJECT: 796 { 797 if (UseCompressedOops && !wide) { 798 __ encode_heap_oop(from_reg->as_register(), G3_scratch); 799 store_offset = code_offset(); 800 __ stw(G3_scratch, base, disp); 801 } else { 802 __ st_ptr(from_reg->as_register(), base, disp); 803 } 804 break; 805 } 806 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; 807 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; 808 default : ShouldNotReachHere(); 809 } 810 return store_offset; 811} 812 813 814int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) { 815 int load_offset; 816 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 817 assert(base != O7, "destroying register"); 818 assert(!unaligned, "can't handle this"); 819 // for offsets larger than a simm13 we setup the offset in O7 820 __ set(offset, O7); 821 load_offset = load(base, O7, to_reg, type, wide); 822 } else { 823 load_offset = code_offset(); 824 switch(type) { 825 case T_BOOLEAN: // fall through 826 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; 827 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; 828 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; 829 case T_INT : __ ld(base, offset, to_reg->as_register()); break; 830 case T_LONG : 831 if (!unaligned && !PatchALot) { 832 __ ldx(base, offset, to_reg->as_register_lo()); 833 } else { 834 assert(base != to_reg->as_register_lo(), "can't handle this"); 835 assert(O7 != to_reg->as_register_lo(), "can't handle this"); 836 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); 837 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last 838 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); 839 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); 840 } 841 break; 842 case T_METADATA: __ ld_ptr(base, offset, to_reg->as_register()); break; 843 case T_ADDRESS: 844 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) { 845 __ lduw(base, offset, to_reg->as_register()); 846 __ decode_klass_not_null(to_reg->as_register()); 847 } else 848 { 849 __ ld_ptr(base, offset, to_reg->as_register()); 850 } 851 break; 852 case T_ARRAY : // fall through 853 case T_OBJECT: 854 { 855 if (UseCompressedOops && !wide) { 856 __ lduw(base, offset, to_reg->as_register()); 857 __ decode_heap_oop(to_reg->as_register()); 858 } else { 859 __ ld_ptr(base, offset, to_reg->as_register()); 860 } 861 break; 862 } 863 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; 864 case T_DOUBLE: 865 { 866 FloatRegister reg = to_reg->as_double_reg(); 867 // split unaligned loads 868 if (unaligned || PatchALot) { 869 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); 870 __ ldf(FloatRegisterImpl::S, base, offset, reg); 871 } else { 872 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); 873 } 874 break; 875 } 876 default : ShouldNotReachHere(); 877 } 878 if (type == T_ARRAY || type == T_OBJECT) { 879 __ verify_oop(to_reg->as_register()); 880 } 881 } 882 return load_offset; 883} 884 885 886int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) { 887 int load_offset = code_offset(); 888 switch(type) { 889 case T_BOOLEAN: // fall through 890 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; 891 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; 892 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; 893 case T_INT : __ ld(base, disp, to_reg->as_register()); break; 894 case T_ADDRESS: __ ld_ptr(base, disp, to_reg->as_register()); break; 895 case T_ARRAY : // fall through 896 case T_OBJECT: 897 { 898 if (UseCompressedOops && !wide) { 899 __ lduw(base, disp, to_reg->as_register()); 900 __ decode_heap_oop(to_reg->as_register()); 901 } else { 902 __ ld_ptr(base, disp, to_reg->as_register()); 903 } 904 break; 905 } 906 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; 907 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; 908 case T_LONG : 909 __ ldx(base, disp, to_reg->as_register_lo()); 910 break; 911 default : ShouldNotReachHere(); 912 } 913 if (type == T_ARRAY || type == T_OBJECT) { 914 __ verify_oop(to_reg->as_register()); 915 } 916 return load_offset; 917} 918 919void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 920 LIR_Const* c = src->as_constant_ptr(); 921 switch (c->type()) { 922 case T_INT: 923 case T_FLOAT: { 924 Register src_reg = O7; 925 int value = c->as_jint_bits(); 926 if (value == 0) { 927 src_reg = G0; 928 } else { 929 __ set(value, O7); 930 } 931 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 932 __ stw(src_reg, addr.base(), addr.disp()); 933 break; 934 } 935 case T_ADDRESS: { 936 Register src_reg = O7; 937 int value = c->as_jint_bits(); 938 if (value == 0) { 939 src_reg = G0; 940 } else { 941 __ set(value, O7); 942 } 943 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 944 __ st_ptr(src_reg, addr.base(), addr.disp()); 945 break; 946 } 947 case T_OBJECT: { 948 Register src_reg = O7; 949 jobject2reg(c->as_jobject(), src_reg); 950 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 951 __ st_ptr(src_reg, addr.base(), addr.disp()); 952 break; 953 } 954 case T_LONG: 955 case T_DOUBLE: { 956 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 957 958 Register tmp = O7; 959 int value_lo = c->as_jint_lo_bits(); 960 if (value_lo == 0) { 961 tmp = G0; 962 } else { 963 __ set(value_lo, O7); 964 } 965 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); 966 int value_hi = c->as_jint_hi_bits(); 967 if (value_hi == 0) { 968 tmp = G0; 969 } else { 970 __ set(value_hi, O7); 971 } 972 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); 973 break; 974 } 975 default: 976 Unimplemented(); 977 } 978} 979 980 981void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) { 982 LIR_Const* c = src->as_constant_ptr(); 983 LIR_Address* addr = dest->as_address_ptr(); 984 Register base = addr->base()->as_pointer_register(); 985 int offset = -1; 986 987 switch (c->type()) { 988 case T_INT: 989 case T_FLOAT: 990 case T_ADDRESS: { 991 LIR_Opr tmp = FrameMap::O7_opr; 992 int value = c->as_jint_bits(); 993 if (value == 0) { 994 tmp = FrameMap::G0_opr; 995 } else if (Assembler::is_simm13(value)) { 996 __ set(value, O7); 997 } 998 if (addr->index()->is_valid()) { 999 assert(addr->disp() == 0, "must be zero"); 1000 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1001 } else { 1002 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1003 offset = store(tmp, base, addr->disp(), type, wide, false); 1004 } 1005 break; 1006 } 1007 case T_LONG: 1008 case T_DOUBLE: { 1009 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); 1010 assert(Assembler::is_simm13(addr->disp()) && 1011 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); 1012 1013 LIR_Opr tmp = FrameMap::O7_opr; 1014 int value_lo = c->as_jint_lo_bits(); 1015 if (value_lo == 0) { 1016 tmp = FrameMap::G0_opr; 1017 } else { 1018 __ set(value_lo, O7); 1019 } 1020 offset = store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT, wide, false); 1021 int value_hi = c->as_jint_hi_bits(); 1022 if (value_hi == 0) { 1023 tmp = FrameMap::G0_opr; 1024 } else { 1025 __ set(value_hi, O7); 1026 } 1027 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT, wide, false); 1028 break; 1029 } 1030 case T_OBJECT: { 1031 jobject obj = c->as_jobject(); 1032 LIR_Opr tmp; 1033 if (obj == NULL) { 1034 tmp = FrameMap::G0_opr; 1035 } else { 1036 tmp = FrameMap::O7_opr; 1037 jobject2reg(c->as_jobject(), O7); 1038 } 1039 // handle either reg+reg or reg+disp address 1040 if (addr->index()->is_valid()) { 1041 assert(addr->disp() == 0, "must be zero"); 1042 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide); 1043 } else { 1044 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1045 offset = store(tmp, base, addr->disp(), type, wide, false); 1046 } 1047 1048 break; 1049 } 1050 default: 1051 Unimplemented(); 1052 } 1053 if (info != NULL) { 1054 assert(offset != -1, "offset should've been set"); 1055 add_debug_info_for_null_check(offset, info); 1056 } 1057} 1058 1059 1060void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 1061 LIR_Const* c = src->as_constant_ptr(); 1062 LIR_Opr to_reg = dest; 1063 1064 switch (c->type()) { 1065 case T_INT: 1066 case T_ADDRESS: 1067 { 1068 jint con = c->as_jint(); 1069 if (to_reg->is_single_cpu()) { 1070 assert(patch_code == lir_patch_none, "no patching handled here"); 1071 __ set(con, to_reg->as_register()); 1072 } else { 1073 ShouldNotReachHere(); 1074 assert(to_reg->is_single_fpu(), "wrong register kind"); 1075 1076 __ set(con, O7); 1077 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); 1078 __ st(O7, temp_slot); 1079 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); 1080 } 1081 } 1082 break; 1083 1084 case T_LONG: 1085 { 1086 jlong con = c->as_jlong(); 1087 1088 if (to_reg->is_double_cpu()) { 1089 __ set(con, to_reg->as_register_lo()); 1090 } else if (to_reg->is_single_cpu()) { 1091 __ set(con, to_reg->as_register()); 1092 } else { 1093 ShouldNotReachHere(); 1094 assert(to_reg->is_double_fpu(), "wrong register kind"); 1095 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); 1096 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); 1097 __ set(low(con), O7); 1098 __ st(O7, temp_slot_lo); 1099 __ set(high(con), O7); 1100 __ st(O7, temp_slot_hi); 1101 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); 1102 } 1103 } 1104 break; 1105 1106 case T_OBJECT: 1107 { 1108 if (patch_code == lir_patch_none) { 1109 jobject2reg(c->as_jobject(), to_reg->as_register()); 1110 } else { 1111 jobject2reg_with_patching(to_reg->as_register(), info); 1112 } 1113 } 1114 break; 1115 1116 case T_METADATA: 1117 { 1118 if (patch_code == lir_patch_none) { 1119 metadata2reg(c->as_metadata(), to_reg->as_register()); 1120 } else { 1121 klass2reg_with_patching(to_reg->as_register(), info); 1122 } 1123 } 1124 break; 1125 1126 case T_FLOAT: 1127 { 1128 address const_addr = __ float_constant(c->as_jfloat()); 1129 if (const_addr == NULL) { 1130 bailout("const section overflow"); 1131 break; 1132 } 1133 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1134 AddressLiteral const_addrlit(const_addr, rspec); 1135 if (to_reg->is_single_fpu()) { 1136 __ patchable_sethi(const_addrlit, O7); 1137 __ relocate(rspec); 1138 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); 1139 1140 } else { 1141 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1142 1143 __ set(const_addrlit, O7); 1144 __ ld(O7, 0, to_reg->as_register()); 1145 } 1146 } 1147 break; 1148 1149 case T_DOUBLE: 1150 { 1151 address const_addr = __ double_constant(c->as_jdouble()); 1152 if (const_addr == NULL) { 1153 bailout("const section overflow"); 1154 break; 1155 } 1156 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1157 1158 if (to_reg->is_double_fpu()) { 1159 AddressLiteral const_addrlit(const_addr, rspec); 1160 __ patchable_sethi(const_addrlit, O7); 1161 __ relocate(rspec); 1162 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); 1163 } else { 1164 assert(to_reg->is_double_cpu(), "Must be a long register."); 1165 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); 1166 } 1167 1168 } 1169 break; 1170 1171 default: 1172 ShouldNotReachHere(); 1173 } 1174} 1175 1176Address LIR_Assembler::as_Address(LIR_Address* addr) { 1177 Register reg = addr->base()->as_pointer_register(); 1178 LIR_Opr index = addr->index(); 1179 if (index->is_illegal()) { 1180 return Address(reg, addr->disp()); 1181 } else { 1182 assert (addr->disp() == 0, "unsupported address mode"); 1183 return Address(reg, index->as_pointer_register()); 1184 } 1185} 1186 1187 1188void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1189 switch (type) { 1190 case T_INT: 1191 case T_FLOAT: { 1192 Register tmp = O7; 1193 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1194 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1195 __ lduw(from.base(), from.disp(), tmp); 1196 __ stw(tmp, to.base(), to.disp()); 1197 break; 1198 } 1199 case T_OBJECT: { 1200 Register tmp = O7; 1201 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1202 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1203 __ ld_ptr(from.base(), from.disp(), tmp); 1204 __ st_ptr(tmp, to.base(), to.disp()); 1205 break; 1206 } 1207 case T_LONG: 1208 case T_DOUBLE: { 1209 Register tmp = O7; 1210 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1211 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1212 __ lduw(from.base(), from.disp(), tmp); 1213 __ stw(tmp, to.base(), to.disp()); 1214 __ lduw(from.base(), from.disp() + 4, tmp); 1215 __ stw(tmp, to.base(), to.disp() + 4); 1216 break; 1217 } 1218 1219 default: 1220 ShouldNotReachHere(); 1221 } 1222} 1223 1224 1225Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1226 Address base = as_Address(addr); 1227 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); 1228} 1229 1230 1231Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1232 Address base = as_Address(addr); 1233 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); 1234} 1235 1236 1237void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1238 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) { 1239 1240 assert(type != T_METADATA, "load of metadata ptr not supported"); 1241 LIR_Address* addr = src_opr->as_address_ptr(); 1242 LIR_Opr to_reg = dest; 1243 1244 Register src = addr->base()->as_pointer_register(); 1245 Register disp_reg = noreg; 1246 int disp_value = addr->disp(); 1247 bool needs_patching = (patch_code != lir_patch_none); 1248 1249 if (addr->base()->type() == T_OBJECT) { 1250 __ verify_oop(src); 1251 } 1252 1253 PatchingStub* patch = NULL; 1254 if (needs_patching) { 1255 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1256 assert(!to_reg->is_double_cpu() || 1257 patch_code == lir_patch_none || 1258 patch_code == lir_patch_normal, "patching doesn't match register"); 1259 } 1260 1261 if (addr->index()->is_illegal()) { 1262 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1263 if (needs_patching) { 1264 __ patchable_set(0, O7); 1265 } else { 1266 __ set(disp_value, O7); 1267 } 1268 disp_reg = O7; 1269 } 1270 } else if (unaligned || PatchALot) { 1271 __ add(src, addr->index()->as_pointer_register(), O7); 1272 src = O7; 1273 } else { 1274 disp_reg = addr->index()->as_pointer_register(); 1275 assert(disp_value == 0, "can't handle 3 operand addresses"); 1276 } 1277 1278 // remember the offset of the load. The patching_epilog must be done 1279 // before the call to add_debug_info, otherwise the PcDescs don't get 1280 // entered in increasing order. 1281 int offset = code_offset(); 1282 1283 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1284 if (disp_reg == noreg) { 1285 offset = load(src, disp_value, to_reg, type, wide, unaligned); 1286 } else { 1287 assert(!unaligned, "can't handle this"); 1288 offset = load(src, disp_reg, to_reg, type, wide); 1289 } 1290 1291 if (patch != NULL) { 1292 patching_epilog(patch, patch_code, src, info); 1293 } 1294 if (info != NULL) add_debug_info_for_null_check(offset, info); 1295} 1296 1297 1298void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1299 Address addr; 1300 if (src->is_single_word()) { 1301 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1302 } else if (src->is_double_word()) { 1303 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1304 } 1305 1306 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1307 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned); 1308} 1309 1310 1311void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1312 Address addr; 1313 if (dest->is_single_word()) { 1314 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1315 } else if (dest->is_double_word()) { 1316 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1317 } 1318 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1319 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned); 1320} 1321 1322 1323void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1324 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1325 if (from_reg->is_double_fpu()) { 1326 // double to double moves 1327 assert(to_reg->is_double_fpu(), "should match"); 1328 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); 1329 } else { 1330 // float to float moves 1331 assert(to_reg->is_single_fpu(), "should match"); 1332 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); 1333 } 1334 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1335 if (from_reg->is_double_cpu()) { 1336 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); 1337 } else if (to_reg->is_double_cpu()) { 1338 // int to int moves 1339 __ mov(from_reg->as_register(), to_reg->as_register_lo()); 1340 } else { 1341 // int to int moves 1342 __ mov(from_reg->as_register(), to_reg->as_register()); 1343 } 1344 } else { 1345 ShouldNotReachHere(); 1346 } 1347 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1348 __ verify_oop(to_reg->as_register()); 1349 } 1350} 1351 1352 1353void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1354 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1355 bool wide, bool unaligned) { 1356 assert(type != T_METADATA, "store of metadata ptr not supported"); 1357 LIR_Address* addr = dest->as_address_ptr(); 1358 1359 Register src = addr->base()->as_pointer_register(); 1360 Register disp_reg = noreg; 1361 int disp_value = addr->disp(); 1362 bool needs_patching = (patch_code != lir_patch_none); 1363 1364 if (addr->base()->is_oop_register()) { 1365 __ verify_oop(src); 1366 } 1367 1368 PatchingStub* patch = NULL; 1369 if (needs_patching) { 1370 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1371 assert(!from_reg->is_double_cpu() || 1372 patch_code == lir_patch_none || 1373 patch_code == lir_patch_normal, "patching doesn't match register"); 1374 } 1375 1376 if (addr->index()->is_illegal()) { 1377 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1378 if (needs_patching) { 1379 __ patchable_set(0, O7); 1380 } else { 1381 __ set(disp_value, O7); 1382 } 1383 disp_reg = O7; 1384 } 1385 } else if (unaligned || PatchALot) { 1386 __ add(src, addr->index()->as_pointer_register(), O7); 1387 src = O7; 1388 } else { 1389 disp_reg = addr->index()->as_pointer_register(); 1390 assert(disp_value == 0, "can't handle 3 operand addresses"); 1391 } 1392 1393 // remember the offset of the store. The patching_epilog must be done 1394 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1395 // entered in increasing order. 1396 int offset; 1397 1398 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1399 if (disp_reg == noreg) { 1400 offset = store(from_reg, src, disp_value, type, wide, unaligned); 1401 } else { 1402 assert(!unaligned, "can't handle this"); 1403 offset = store(from_reg, src, disp_reg, type, wide); 1404 } 1405 1406 if (patch != NULL) { 1407 patching_epilog(patch, patch_code, src, info); 1408 } 1409 1410 if (info != NULL) add_debug_info_for_null_check(offset, info); 1411} 1412 1413 1414void LIR_Assembler::return_op(LIR_Opr result) { 1415 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) { 1416 __ reserved_stack_check(); 1417 } 1418 __ set((intptr_t)os::get_polling_page(), L0); 1419 __ relocate(relocInfo::poll_return_type); 1420 __ ld_ptr(L0, 0, G0); 1421 __ ret(); 1422 __ delayed()->restore(); 1423} 1424 1425 1426int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1427 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); 1428 if (info != NULL) { 1429 add_debug_info_for_branch(info); 1430 } 1431 int offset = __ offset(); 1432 __ relocate(relocInfo::poll_type); 1433 __ ld_ptr(tmp->as_register(), 0, G0); 1434 return offset; 1435} 1436 1437 1438void LIR_Assembler::emit_static_call_stub() { 1439 address call_pc = __ pc(); 1440 address stub = __ start_a_stub(call_stub_size()); 1441 if (stub == NULL) { 1442 bailout("static call stub overflow"); 1443 return; 1444 } 1445 1446 int start = __ offset(); 1447 __ relocate(static_stub_Relocation::spec(call_pc)); 1448 1449 __ set_metadata(NULL, G5); 1450 // must be set to -1 at code generation time 1451 AddressLiteral addrlit(-1); 1452 __ jump_to(addrlit, G3); 1453 __ delayed()->nop(); 1454 1455 assert(__ offset() - start <= call_stub_size(), "stub too big"); 1456 __ end_a_stub(); 1457} 1458 1459 1460void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1461 if (opr1->is_single_fpu()) { 1462 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1463 } else if (opr1->is_double_fpu()) { 1464 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1465 } else if (opr1->is_single_cpu()) { 1466 if (opr2->is_constant()) { 1467 switch (opr2->as_constant_ptr()->type()) { 1468 case T_INT: 1469 { jint con = opr2->as_constant_ptr()->as_jint(); 1470 if (Assembler::is_simm13(con)) { 1471 __ cmp(opr1->as_register(), con); 1472 } else { 1473 __ set(con, O7); 1474 __ cmp(opr1->as_register(), O7); 1475 } 1476 } 1477 break; 1478 1479 case T_OBJECT: 1480 // there are only equal/notequal comparisions on objects 1481 { jobject con = opr2->as_constant_ptr()->as_jobject(); 1482 if (con == NULL) { 1483 __ cmp(opr1->as_register(), 0); 1484 } else { 1485 jobject2reg(con, O7); 1486 __ cmp(opr1->as_register(), O7); 1487 } 1488 } 1489 break; 1490 1491 default: 1492 ShouldNotReachHere(); 1493 break; 1494 } 1495 } else { 1496 if (opr2->is_address()) { 1497 LIR_Address * addr = opr2->as_address_ptr(); 1498 BasicType type = addr->type(); 1499 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1500 else __ ld(as_Address(addr), O7); 1501 __ cmp(opr1->as_register(), O7); 1502 } else { 1503 __ cmp(opr1->as_register(), opr2->as_register()); 1504 } 1505 } 1506 } else if (opr1->is_double_cpu()) { 1507 Register xlo = opr1->as_register_lo(); 1508 Register xhi = opr1->as_register_hi(); 1509 if (opr2->is_constant() && opr2->as_jlong() == 0) { 1510 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); 1511 __ orcc(xhi, G0, G0); 1512 } else if (opr2->is_register()) { 1513 Register ylo = opr2->as_register_lo(); 1514 Register yhi = opr2->as_register_hi(); 1515 __ cmp(xlo, ylo); 1516 } else { 1517 ShouldNotReachHere(); 1518 } 1519 } else if (opr1->is_address()) { 1520 LIR_Address * addr = opr1->as_address_ptr(); 1521 BasicType type = addr->type(); 1522 assert (opr2->is_constant(), "Checking"); 1523 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1524 else __ ld(as_Address(addr), O7); 1525 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); 1526 } else { 1527 ShouldNotReachHere(); 1528 } 1529} 1530 1531 1532void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1533 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1534 bool is_unordered_less = (code == lir_ucmp_fd2i); 1535 if (left->is_single_fpu()) { 1536 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1537 } else if (left->is_double_fpu()) { 1538 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1539 } else { 1540 ShouldNotReachHere(); 1541 } 1542 } else if (code == lir_cmp_l2i) { 1543 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); 1544 } else { 1545 ShouldNotReachHere(); 1546 } 1547} 1548 1549 1550void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) { 1551 Assembler::Condition acond; 1552 switch (condition) { 1553 case lir_cond_equal: acond = Assembler::equal; break; 1554 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1555 case lir_cond_less: acond = Assembler::less; break; 1556 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1557 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 1558 case lir_cond_greater: acond = Assembler::greater; break; 1559 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 1560 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 1561 default: ShouldNotReachHere(); 1562 }; 1563 1564 if (opr1->is_constant() && opr1->type() == T_INT) { 1565 Register dest = result->as_register(); 1566 // load up first part of constant before branch 1567 // and do the rest in the delay slot. 1568 if (!Assembler::is_simm13(opr1->as_jint())) { 1569 __ sethi(opr1->as_jint(), dest); 1570 } 1571 } else if (opr1->is_constant()) { 1572 const2reg(opr1, result, lir_patch_none, NULL); 1573 } else if (opr1->is_register()) { 1574 reg2reg(opr1, result); 1575 } else if (opr1->is_stack()) { 1576 stack2reg(opr1, result, result->type()); 1577 } else { 1578 ShouldNotReachHere(); 1579 } 1580 Label skip; 1581 if (type == T_INT) { 1582 __ br(acond, false, Assembler::pt, skip); 1583 } else { 1584 __ brx(acond, false, Assembler::pt, skip); // checks icc on 32bit and xcc on 64bit 1585 } 1586 if (opr1->is_constant() && opr1->type() == T_INT) { 1587 Register dest = result->as_register(); 1588 if (Assembler::is_simm13(opr1->as_jint())) { 1589 __ delayed()->or3(G0, opr1->as_jint(), dest); 1590 } else { 1591 // the sethi has been done above, so just put in the low 10 bits 1592 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); 1593 } 1594 } else { 1595 // can't do anything useful in the delay slot 1596 __ delayed()->nop(); 1597 } 1598 if (opr2->is_constant()) { 1599 const2reg(opr2, result, lir_patch_none, NULL); 1600 } else if (opr2->is_register()) { 1601 reg2reg(opr2, result); 1602 } else if (opr2->is_stack()) { 1603 stack2reg(opr2, result, result->type()); 1604 } else { 1605 ShouldNotReachHere(); 1606 } 1607 __ bind(skip); 1608} 1609 1610 1611void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1612 assert(info == NULL, "unused on this code path"); 1613 assert(left->is_register(), "wrong items state"); 1614 assert(dest->is_register(), "wrong items state"); 1615 1616 if (right->is_register()) { 1617 if (dest->is_float_kind()) { 1618 1619 FloatRegister lreg, rreg, res; 1620 FloatRegisterImpl::Width w; 1621 if (right->is_single_fpu()) { 1622 w = FloatRegisterImpl::S; 1623 lreg = left->as_float_reg(); 1624 rreg = right->as_float_reg(); 1625 res = dest->as_float_reg(); 1626 } else { 1627 w = FloatRegisterImpl::D; 1628 lreg = left->as_double_reg(); 1629 rreg = right->as_double_reg(); 1630 res = dest->as_double_reg(); 1631 } 1632 1633 switch (code) { 1634 case lir_add: __ fadd(w, lreg, rreg, res); break; 1635 case lir_sub: __ fsub(w, lreg, rreg, res); break; 1636 case lir_mul: // fall through 1637 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; 1638 case lir_div: // fall through 1639 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; 1640 default: ShouldNotReachHere(); 1641 } 1642 1643 } else if (dest->is_double_cpu()) { 1644 Register dst_lo = dest->as_register_lo(); 1645 Register op1_lo = left->as_pointer_register(); 1646 Register op2_lo = right->as_pointer_register(); 1647 1648 switch (code) { 1649 case lir_add: 1650 __ add(op1_lo, op2_lo, dst_lo); 1651 break; 1652 1653 case lir_sub: 1654 __ sub(op1_lo, op2_lo, dst_lo); 1655 break; 1656 1657 default: ShouldNotReachHere(); 1658 } 1659 } else { 1660 assert (right->is_single_cpu(), "Just Checking"); 1661 1662 Register lreg = left->as_register(); 1663 Register res = dest->as_register(); 1664 Register rreg = right->as_register(); 1665 switch (code) { 1666 case lir_add: __ add (lreg, rreg, res); break; 1667 case lir_sub: __ sub (lreg, rreg, res); break; 1668 case lir_mul: __ mulx (lreg, rreg, res); break; 1669 default: ShouldNotReachHere(); 1670 } 1671 } 1672 } else { 1673 assert (right->is_constant(), "must be constant"); 1674 1675 if (dest->is_single_cpu()) { 1676 Register lreg = left->as_register(); 1677 Register res = dest->as_register(); 1678 int simm13 = right->as_constant_ptr()->as_jint(); 1679 1680 switch (code) { 1681 case lir_add: __ add (lreg, simm13, res); break; 1682 case lir_sub: __ sub (lreg, simm13, res); break; 1683 case lir_mul: __ mulx (lreg, simm13, res); break; 1684 default: ShouldNotReachHere(); 1685 } 1686 } else { 1687 Register lreg = left->as_pointer_register(); 1688 Register res = dest->as_register_lo(); 1689 long con = right->as_constant_ptr()->as_jlong(); 1690 assert(Assembler::is_simm13(con), "must be simm13"); 1691 1692 switch (code) { 1693 case lir_add: __ add (lreg, (int)con, res); break; 1694 case lir_sub: __ sub (lreg, (int)con, res); break; 1695 case lir_mul: __ mulx (lreg, (int)con, res); break; 1696 default: ShouldNotReachHere(); 1697 } 1698 } 1699 } 1700} 1701 1702 1703void LIR_Assembler::fpop() { 1704 // do nothing 1705} 1706 1707 1708void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1709 switch (code) { 1710 case lir_tan: { 1711 assert(thread->is_valid(), "preserve the thread object for performance reasons"); 1712 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); 1713 break; 1714 } 1715 case lir_sqrt: { 1716 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1717 FloatRegister src_reg = value->as_double_reg(); 1718 FloatRegister dst_reg = dest->as_double_reg(); 1719 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); 1720 break; 1721 } 1722 case lir_abs: { 1723 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1724 FloatRegister src_reg = value->as_double_reg(); 1725 FloatRegister dst_reg = dest->as_double_reg(); 1726 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); 1727 break; 1728 } 1729 default: { 1730 ShouldNotReachHere(); 1731 break; 1732 } 1733 } 1734} 1735 1736 1737void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1738 if (right->is_constant()) { 1739 if (dest->is_single_cpu()) { 1740 int simm13 = right->as_constant_ptr()->as_jint(); 1741 switch (code) { 1742 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; 1743 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; 1744 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; 1745 default: ShouldNotReachHere(); 1746 } 1747 } else { 1748 long c = right->as_constant_ptr()->as_jlong(); 1749 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); 1750 int simm13 = (int)c; 1751 switch (code) { 1752 case lir_logic_and: 1753 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1754 break; 1755 1756 case lir_logic_or: 1757 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1758 break; 1759 1760 case lir_logic_xor: 1761 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1762 break; 1763 1764 default: ShouldNotReachHere(); 1765 } 1766 } 1767 } else { 1768 assert(right->is_register(), "right should be in register"); 1769 1770 if (dest->is_single_cpu()) { 1771 switch (code) { 1772 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; 1773 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; 1774 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; 1775 default: ShouldNotReachHere(); 1776 } 1777 } else { 1778 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 1779 left->as_register_lo(); 1780 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 1781 right->as_register_lo(); 1782 1783 switch (code) { 1784 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; 1785 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; 1786 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; 1787 default: ShouldNotReachHere(); 1788 } 1789 } 1790 } 1791} 1792 1793 1794int LIR_Assembler::shift_amount(BasicType t) { 1795 int elem_size = type2aelembytes(t); 1796 switch (elem_size) { 1797 case 1 : return 0; 1798 case 2 : return 1; 1799 case 4 : return 2; 1800 case 8 : return 3; 1801 } 1802 ShouldNotReachHere(); 1803 return -1; 1804} 1805 1806 1807void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 1808 assert(exceptionOop->as_register() == Oexception, "should match"); 1809 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); 1810 1811 info->add_register_oop(exceptionOop); 1812 1813 // reuse the debug info from the safepoint poll for the throw op itself 1814 address pc_for_athrow = __ pc(); 1815 int pc_for_athrow_offset = __ offset(); 1816 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 1817 __ set(pc_for_athrow, Oissuing_pc, rspec); 1818 add_call_info(pc_for_athrow_offset, info); // for exception handler 1819 1820 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 1821 __ delayed()->nop(); 1822} 1823 1824 1825void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 1826 assert(exceptionOop->as_register() == Oexception, "should match"); 1827 1828 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); 1829 __ delayed()->nop(); 1830} 1831 1832void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 1833 Register src = op->src()->as_register(); 1834 Register dst = op->dst()->as_register(); 1835 Register src_pos = op->src_pos()->as_register(); 1836 Register dst_pos = op->dst_pos()->as_register(); 1837 Register length = op->length()->as_register(); 1838 Register tmp = op->tmp()->as_register(); 1839 Register tmp2 = O7; 1840 1841 int flags = op->flags(); 1842 ciArrayKlass* default_type = op->expected_type(); 1843 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 1844 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 1845 1846 // higher 32bits must be null 1847 __ sra(dst_pos, 0, dst_pos); 1848 __ sra(src_pos, 0, src_pos); 1849 __ sra(length, 0, length); 1850 1851 // set up the arraycopy stub information 1852 ArrayCopyStub* stub = op->stub(); 1853 1854 // always do stub if no type information is available. it's ok if 1855 // the known type isn't loaded since the code sanity checks 1856 // in debug mode and the type isn't required when we know the exact type 1857 // also check that the type is an array type. 1858 if (op->expected_type() == NULL) { 1859 __ mov(src, O0); 1860 __ mov(src_pos, O1); 1861 __ mov(dst, O2); 1862 __ mov(dst_pos, O3); 1863 __ mov(length, O4); 1864 address copyfunc_addr = StubRoutines::generic_arraycopy(); 1865 1866 if (copyfunc_addr == NULL) { // Use C version if stub was not generated 1867 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); 1868 } else { 1869#ifndef PRODUCT 1870 if (PrintC1Statistics) { 1871 address counter = (address)&Runtime1::_generic_arraycopystub_cnt; 1872 __ inc_counter(counter, G1, G3); 1873 } 1874#endif 1875 __ call_VM_leaf(tmp, copyfunc_addr); 1876 } 1877 1878 if (copyfunc_addr != NULL) { 1879 __ xor3(O0, -1, tmp); 1880 __ sub(length, tmp, length); 1881 __ add(src_pos, tmp, src_pos); 1882 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 1883 __ delayed()->add(dst_pos, tmp, dst_pos); 1884 } else { 1885 __ cmp_zero_and_br(Assembler::less, O0, *stub->entry()); 1886 __ delayed()->nop(); 1887 } 1888 __ bind(*stub->continuation()); 1889 return; 1890 } 1891 1892 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 1893 1894 // make sure src and dst are non-null and load array length 1895 if (flags & LIR_OpArrayCopy::src_null_check) { 1896 __ tst(src); 1897 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 1898 __ delayed()->nop(); 1899 } 1900 1901 if (flags & LIR_OpArrayCopy::dst_null_check) { 1902 __ tst(dst); 1903 __ brx(Assembler::equal, false, Assembler::pn, *stub->entry()); 1904 __ delayed()->nop(); 1905 } 1906 1907 // If the compiler was not able to prove that exact type of the source or the destination 1908 // of the arraycopy is an array type, check at runtime if the source or the destination is 1909 // an instance type. 1910 if (flags & LIR_OpArrayCopy::type_check) { 1911 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) { 1912 __ load_klass(dst, tmp); 1913 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2); 1914 __ cmp(tmp2, Klass::_lh_neutral_value); 1915 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry()); 1916 __ delayed()->nop(); 1917 } 1918 1919 if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) { 1920 __ load_klass(src, tmp); 1921 __ lduw(tmp, in_bytes(Klass::layout_helper_offset()), tmp2); 1922 __ cmp(tmp2, Klass::_lh_neutral_value); 1923 __ br(Assembler::greaterEqual, false, Assembler::pn, *stub->entry()); 1924 __ delayed()->nop(); 1925 } 1926 } 1927 1928 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 1929 // test src_pos register 1930 __ cmp_zero_and_br(Assembler::less, src_pos, *stub->entry()); 1931 __ delayed()->nop(); 1932 } 1933 1934 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 1935 // test dst_pos register 1936 __ cmp_zero_and_br(Assembler::less, dst_pos, *stub->entry()); 1937 __ delayed()->nop(); 1938 } 1939 1940 if (flags & LIR_OpArrayCopy::length_positive_check) { 1941 // make sure length isn't negative 1942 __ cmp_zero_and_br(Assembler::less, length, *stub->entry()); 1943 __ delayed()->nop(); 1944 } 1945 1946 if (flags & LIR_OpArrayCopy::src_range_check) { 1947 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); 1948 __ add(length, src_pos, tmp); 1949 __ cmp(tmp2, tmp); 1950 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 1951 __ delayed()->nop(); 1952 } 1953 1954 if (flags & LIR_OpArrayCopy::dst_range_check) { 1955 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); 1956 __ add(length, dst_pos, tmp); 1957 __ cmp(tmp2, tmp); 1958 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 1959 __ delayed()->nop(); 1960 } 1961 1962 int shift = shift_amount(basic_type); 1963 1964 if (flags & LIR_OpArrayCopy::type_check) { 1965 // We don't know the array types are compatible 1966 if (basic_type != T_OBJECT) { 1967 // Simple test for basic type arrays 1968 if (UseCompressedClassPointers) { 1969 // We don't need decode because we just need to compare 1970 __ lduw(src, oopDesc::klass_offset_in_bytes(), tmp); 1971 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 1972 __ cmp(tmp, tmp2); 1973 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 1974 } else { 1975 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); 1976 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 1977 __ cmp(tmp, tmp2); 1978 __ brx(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 1979 } 1980 __ delayed()->nop(); 1981 } else { 1982 // For object arrays, if src is a sub class of dst then we can 1983 // safely do the copy. 1984 address copyfunc_addr = StubRoutines::checkcast_arraycopy(); 1985 1986 Label cont, slow; 1987 assert_different_registers(tmp, tmp2, G3, G1); 1988 1989 __ load_klass(src, G3); 1990 __ load_klass(dst, G1); 1991 1992 __ check_klass_subtype_fast_path(G3, G1, tmp, tmp2, &cont, copyfunc_addr == NULL ? stub->entry() : &slow, NULL); 1993 1994 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 1995 __ delayed()->nop(); 1996 1997 __ cmp(G3, 0); 1998 if (copyfunc_addr != NULL) { // use stub if available 1999 // src is not a sub class of dst so we have to do a 2000 // per-element check. 2001 __ br(Assembler::notEqual, false, Assembler::pt, cont); 2002 __ delayed()->nop(); 2003 2004 __ bind(slow); 2005 2006 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray; 2007 if ((flags & mask) != mask) { 2008 // Check that at least both of them object arrays. 2009 assert(flags & mask, "one of the two should be known to be an object array"); 2010 2011 if (!(flags & LIR_OpArrayCopy::src_objarray)) { 2012 __ load_klass(src, tmp); 2013 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) { 2014 __ load_klass(dst, tmp); 2015 } 2016 int lh_offset = in_bytes(Klass::layout_helper_offset()); 2017 2018 __ lduw(tmp, lh_offset, tmp2); 2019 2020 jint objArray_lh = Klass::array_layout_helper(T_OBJECT); 2021 __ set(objArray_lh, tmp); 2022 __ cmp(tmp, tmp2); 2023 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2024 __ delayed()->nop(); 2025 } 2026 2027 Register src_ptr = O0; 2028 Register dst_ptr = O1; 2029 Register len = O2; 2030 Register chk_off = O3; 2031 Register super_k = O4; 2032 2033 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2034 if (shift == 0) { 2035 __ add(src_ptr, src_pos, src_ptr); 2036 } else { 2037 __ sll(src_pos, shift, tmp); 2038 __ add(src_ptr, tmp, src_ptr); 2039 } 2040 2041 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2042 if (shift == 0) { 2043 __ add(dst_ptr, dst_pos, dst_ptr); 2044 } else { 2045 __ sll(dst_pos, shift, tmp); 2046 __ add(dst_ptr, tmp, dst_ptr); 2047 } 2048 __ mov(length, len); 2049 __ load_klass(dst, tmp); 2050 2051 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset()); 2052 __ ld_ptr(tmp, ek_offset, super_k); 2053 2054 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 2055 __ lduw(super_k, sco_offset, chk_off); 2056 2057 __ call_VM_leaf(tmp, copyfunc_addr); 2058 2059#ifndef PRODUCT 2060 if (PrintC1Statistics) { 2061 Label failed; 2062 __ br_notnull_short(O0, Assembler::pn, failed); 2063 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_cnt, G1, G3); 2064 __ bind(failed); 2065 } 2066#endif 2067 2068 __ br_null(O0, false, Assembler::pt, *stub->continuation()); 2069 __ delayed()->xor3(O0, -1, tmp); 2070 2071#ifndef PRODUCT 2072 if (PrintC1Statistics) { 2073 __ inc_counter((address)&Runtime1::_arraycopy_checkcast_attempt_cnt, G1, G3); 2074 } 2075#endif 2076 2077 __ sub(length, tmp, length); 2078 __ add(src_pos, tmp, src_pos); 2079 __ br(Assembler::always, false, Assembler::pt, *stub->entry()); 2080 __ delayed()->add(dst_pos, tmp, dst_pos); 2081 2082 __ bind(cont); 2083 } else { 2084 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2085 __ delayed()->nop(); 2086 __ bind(cont); 2087 } 2088 } 2089 } 2090 2091#ifdef ASSERT 2092 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2093 // Sanity check the known type with the incoming class. For the 2094 // primitive case the types must match exactly with src.klass and 2095 // dst.klass each exactly matching the default type. For the 2096 // object array case, if no type check is needed then either the 2097 // dst type is exactly the expected type and the src type is a 2098 // subtype which we can't check or src is the same array as dst 2099 // but not necessarily exactly of type default_type. 2100 Label known_ok, halt; 2101 metadata2reg(op->expected_type()->constant_encoding(), tmp); 2102 if (UseCompressedClassPointers) { 2103 // tmp holds the default type. It currently comes uncompressed after the 2104 // load of a constant, so encode it. 2105 __ encode_klass_not_null(tmp); 2106 // load the raw value of the dst klass, since we will be comparing 2107 // uncompressed values directly. 2108 __ lduw(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2109 if (basic_type != T_OBJECT) { 2110 __ cmp(tmp, tmp2); 2111 __ br(Assembler::notEqual, false, Assembler::pn, halt); 2112 // load the raw value of the src klass. 2113 __ delayed()->lduw(src, oopDesc::klass_offset_in_bytes(), tmp2); 2114 __ cmp_and_br_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2115 } else { 2116 __ cmp(tmp, tmp2); 2117 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2118 __ delayed()->cmp(src, dst); 2119 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2120 __ delayed()->nop(); 2121 } 2122 } else { 2123 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2124 if (basic_type != T_OBJECT) { 2125 __ cmp(tmp, tmp2); 2126 __ brx(Assembler::notEqual, false, Assembler::pn, halt); 2127 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); 2128 __ cmp_and_brx_short(tmp, tmp2, Assembler::equal, Assembler::pn, known_ok); 2129 } else { 2130 __ cmp(tmp, tmp2); 2131 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2132 __ delayed()->cmp(src, dst); 2133 __ brx(Assembler::equal, false, Assembler::pn, known_ok); 2134 __ delayed()->nop(); 2135 } 2136 } 2137 __ bind(halt); 2138 __ stop("incorrect type information in arraycopy"); 2139 __ bind(known_ok); 2140 } 2141#endif 2142 2143#ifndef PRODUCT 2144 if (PrintC1Statistics) { 2145 address counter = Runtime1::arraycopy_count_address(basic_type); 2146 __ inc_counter(counter, G1, G3); 2147 } 2148#endif 2149 2150 Register src_ptr = O0; 2151 Register dst_ptr = O1; 2152 Register len = O2; 2153 2154 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2155 if (shift == 0) { 2156 __ add(src_ptr, src_pos, src_ptr); 2157 } else { 2158 __ sll(src_pos, shift, tmp); 2159 __ add(src_ptr, tmp, src_ptr); 2160 } 2161 2162 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2163 if (shift == 0) { 2164 __ add(dst_ptr, dst_pos, dst_ptr); 2165 } else { 2166 __ sll(dst_pos, shift, tmp); 2167 __ add(dst_ptr, tmp, dst_ptr); 2168 } 2169 2170 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0; 2171 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0; 2172 const char *name; 2173 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false); 2174 2175 // arraycopy stubs takes a length in number of elements, so don't scale it. 2176 __ mov(length, len); 2177 __ call_VM_leaf(tmp, entry); 2178 2179 __ bind(*stub->continuation()); 2180} 2181 2182 2183void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2184 if (dest->is_single_cpu()) { 2185 if (left->type() == T_OBJECT) { 2186 switch (code) { 2187 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; 2188 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; 2189 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2190 default: ShouldNotReachHere(); 2191 } 2192 } else 2193 switch (code) { 2194 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; 2195 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; 2196 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2197 default: ShouldNotReachHere(); 2198 } 2199 } else { 2200 switch (code) { 2201 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2202 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2203 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2204 default: ShouldNotReachHere(); 2205 } 2206 } 2207} 2208 2209 2210void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2211 if (left->type() == T_OBJECT) { 2212 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) 2213 Register l = left->as_register(); 2214 Register d = dest->as_register_lo(); 2215 switch (code) { 2216 case lir_shl: __ sllx (l, count, d); break; 2217 case lir_shr: __ srax (l, count, d); break; 2218 case lir_ushr: __ srlx (l, count, d); break; 2219 default: ShouldNotReachHere(); 2220 } 2221 return; 2222 } 2223 2224 if (dest->is_single_cpu()) { 2225 count = count & 0x1F; // Java spec 2226 switch (code) { 2227 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; 2228 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; 2229 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; 2230 default: ShouldNotReachHere(); 2231 } 2232 } else if (dest->is_double_cpu()) { 2233 count = count & 63; // Java spec 2234 switch (code) { 2235 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2236 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2237 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2238 default: ShouldNotReachHere(); 2239 } 2240 } else { 2241 ShouldNotReachHere(); 2242 } 2243} 2244 2245 2246void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2247 assert(op->tmp1()->as_register() == G1 && 2248 op->tmp2()->as_register() == G3 && 2249 op->tmp3()->as_register() == G4 && 2250 op->obj()->as_register() == O0 && 2251 op->klass()->as_register() == G5, "must be"); 2252 if (op->init_check()) { 2253 __ ldub(op->klass()->as_register(), 2254 in_bytes(InstanceKlass::init_state_offset()), 2255 op->tmp1()->as_register()); 2256 add_debug_info_for_null_check_here(op->stub()->info()); 2257 __ cmp(op->tmp1()->as_register(), InstanceKlass::fully_initialized); 2258 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); 2259 __ delayed()->nop(); 2260 } 2261 __ allocate_object(op->obj()->as_register(), 2262 op->tmp1()->as_register(), 2263 op->tmp2()->as_register(), 2264 op->tmp3()->as_register(), 2265 op->header_size(), 2266 op->object_size(), 2267 op->klass()->as_register(), 2268 *op->stub()->entry()); 2269 __ bind(*op->stub()->continuation()); 2270 __ verify_oop(op->obj()->as_register()); 2271} 2272 2273 2274void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2275 assert(op->tmp1()->as_register() == G1 && 2276 op->tmp2()->as_register() == G3 && 2277 op->tmp3()->as_register() == G4 && 2278 op->tmp4()->as_register() == O1 && 2279 op->klass()->as_register() == G5, "must be"); 2280 2281 __ signx(op->len()->as_register()); 2282 if (UseSlowPath || 2283 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2284 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2285 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2286 __ delayed()->nop(); 2287 } else { 2288 __ allocate_array(op->obj()->as_register(), 2289 op->len()->as_register(), 2290 op->tmp1()->as_register(), 2291 op->tmp2()->as_register(), 2292 op->tmp3()->as_register(), 2293 arrayOopDesc::header_size(op->type()), 2294 type2aelembytes(op->type()), 2295 op->klass()->as_register(), 2296 *op->stub()->entry()); 2297 } 2298 __ bind(*op->stub()->continuation()); 2299} 2300 2301 2302void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2303 ciMethodData *md, ciProfileData *data, 2304 Register recv, Register tmp1, Label* update_done) { 2305 uint i; 2306 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2307 Label next_test; 2308 // See if the receiver is receiver[n]. 2309 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2310 mdo_offset_bias); 2311 __ ld_ptr(receiver_addr, tmp1); 2312 __ verify_klass_ptr(tmp1); 2313 __ cmp_and_brx_short(recv, tmp1, Assembler::notEqual, Assembler::pt, next_test); 2314 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2315 mdo_offset_bias); 2316 __ ld_ptr(data_addr, tmp1); 2317 __ add(tmp1, DataLayout::counter_increment, tmp1); 2318 __ st_ptr(tmp1, data_addr); 2319 __ ba(*update_done); 2320 __ delayed()->nop(); 2321 __ bind(next_test); 2322 } 2323 2324 // Didn't find receiver; find next empty slot and fill it in 2325 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2326 Label next_test; 2327 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2328 mdo_offset_bias); 2329 __ ld_ptr(recv_addr, tmp1); 2330 __ br_notnull_short(tmp1, Assembler::pt, next_test); 2331 __ st_ptr(recv, recv_addr); 2332 __ set(DataLayout::counter_increment, tmp1); 2333 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2334 mdo_offset_bias); 2335 __ ba(*update_done); 2336 __ delayed()->nop(); 2337 __ bind(next_test); 2338 } 2339} 2340 2341 2342void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2343 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2344 md = method->method_data_or_null(); 2345 assert(md != NULL, "Sanity"); 2346 data = md->bci_to_data(bci); 2347 assert(data != NULL, "need data for checkcast"); 2348 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2349 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2350 // The offset is large so bias the mdo by the base of the slot so 2351 // that the ld can use simm13s to reference the slots of the data 2352 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2353 } 2354} 2355 2356void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2357 // we always need a stub for the failure case. 2358 CodeStub* stub = op->stub(); 2359 Register obj = op->object()->as_register(); 2360 Register k_RInfo = op->tmp1()->as_register(); 2361 Register klass_RInfo = op->tmp2()->as_register(); 2362 Register dst = op->result_opr()->as_register(); 2363 Register Rtmp1 = op->tmp3()->as_register(); 2364 ciKlass* k = op->klass(); 2365 2366 2367 if (obj == k_RInfo) { 2368 k_RInfo = klass_RInfo; 2369 klass_RInfo = obj; 2370 } 2371 2372 ciMethodData* md; 2373 ciProfileData* data; 2374 int mdo_offset_bias = 0; 2375 if (op->should_profile()) { 2376 ciMethod* method = op->profiled_method(); 2377 assert(method != NULL, "Should have method"); 2378 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2379 2380 Label not_null; 2381 __ br_notnull_short(obj, Assembler::pn, not_null); 2382 Register mdo = k_RInfo; 2383 Register data_val = Rtmp1; 2384 metadata2reg(md->constant_encoding(), mdo); 2385 if (mdo_offset_bias > 0) { 2386 __ set(mdo_offset_bias, data_val); 2387 __ add(mdo, data_val, mdo); 2388 } 2389 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2390 __ ldub(flags_addr, data_val); 2391 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2392 __ stb(data_val, flags_addr); 2393 __ ba(*obj_is_null); 2394 __ delayed()->nop(); 2395 __ bind(not_null); 2396 } else { 2397 __ br_null(obj, false, Assembler::pn, *obj_is_null); 2398 __ delayed()->nop(); 2399 } 2400 2401 Label profile_cast_failure, profile_cast_success; 2402 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2403 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2404 2405 // patching may screw with our temporaries on sparc, 2406 // so let's do it before loading the class 2407 if (k->is_loaded()) { 2408 metadata2reg(k->constant_encoding(), k_RInfo); 2409 } else { 2410 klass2reg_with_patching(k_RInfo, op->info_for_patch()); 2411 } 2412 assert(obj != k_RInfo, "must be different"); 2413 2414 // get object class 2415 // not a safepoint as obj null check happens earlier 2416 __ load_klass(obj, klass_RInfo); 2417 if (op->fast_check()) { 2418 assert_different_registers(klass_RInfo, k_RInfo); 2419 __ cmp(k_RInfo, klass_RInfo); 2420 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); 2421 __ delayed()->nop(); 2422 } else { 2423 bool need_slow_path = true; 2424 if (k->is_loaded()) { 2425 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) 2426 need_slow_path = false; 2427 // perform the fast part of the checking logic 2428 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, 2429 (need_slow_path ? success_target : NULL), 2430 failure_target, NULL, 2431 RegisterOrConstant(k->super_check_offset())); 2432 } else { 2433 // perform the fast part of the checking logic 2434 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, 2435 failure_target, NULL); 2436 } 2437 if (need_slow_path) { 2438 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2439 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2440 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2441 __ delayed()->nop(); 2442 __ cmp(G3, 0); 2443 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2444 __ delayed()->nop(); 2445 // Fall through to success case 2446 } 2447 } 2448 2449 if (op->should_profile()) { 2450 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2451 assert_different_registers(obj, mdo, recv, tmp1); 2452 __ bind(profile_cast_success); 2453 metadata2reg(md->constant_encoding(), mdo); 2454 if (mdo_offset_bias > 0) { 2455 __ set(mdo_offset_bias, tmp1); 2456 __ add(mdo, tmp1, mdo); 2457 } 2458 __ load_klass(obj, recv); 2459 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); 2460 // Jump over the failure case 2461 __ ba(*success); 2462 __ delayed()->nop(); 2463 // Cast failure case 2464 __ bind(profile_cast_failure); 2465 metadata2reg(md->constant_encoding(), mdo); 2466 if (mdo_offset_bias > 0) { 2467 __ set(mdo_offset_bias, tmp1); 2468 __ add(mdo, tmp1, mdo); 2469 } 2470 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2471 __ ld_ptr(data_addr, tmp1); 2472 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2473 __ st_ptr(tmp1, data_addr); 2474 __ ba(*failure); 2475 __ delayed()->nop(); 2476 } 2477 __ ba(*success); 2478 __ delayed()->nop(); 2479} 2480 2481void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2482 LIR_Code code = op->code(); 2483 if (code == lir_store_check) { 2484 Register value = op->object()->as_register(); 2485 Register array = op->array()->as_register(); 2486 Register k_RInfo = op->tmp1()->as_register(); 2487 Register klass_RInfo = op->tmp2()->as_register(); 2488 Register Rtmp1 = op->tmp3()->as_register(); 2489 2490 __ verify_oop(value); 2491 CodeStub* stub = op->stub(); 2492 // check if it needs to be profiled 2493 ciMethodData* md; 2494 ciProfileData* data; 2495 int mdo_offset_bias = 0; 2496 if (op->should_profile()) { 2497 ciMethod* method = op->profiled_method(); 2498 assert(method != NULL, "Should have method"); 2499 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2500 } 2501 Label profile_cast_success, profile_cast_failure, done; 2502 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2503 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2504 2505 if (op->should_profile()) { 2506 Label not_null; 2507 __ br_notnull_short(value, Assembler::pn, not_null); 2508 Register mdo = k_RInfo; 2509 Register data_val = Rtmp1; 2510 metadata2reg(md->constant_encoding(), mdo); 2511 if (mdo_offset_bias > 0) { 2512 __ set(mdo_offset_bias, data_val); 2513 __ add(mdo, data_val, mdo); 2514 } 2515 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2516 __ ldub(flags_addr, data_val); 2517 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2518 __ stb(data_val, flags_addr); 2519 __ ba_short(done); 2520 __ bind(not_null); 2521 } else { 2522 __ br_null_short(value, Assembler::pn, done); 2523 } 2524 add_debug_info_for_null_check_here(op->info_for_exception()); 2525 __ load_klass(array, k_RInfo); 2526 __ load_klass(value, klass_RInfo); 2527 2528 // get instance klass 2529 __ ld_ptr(Address(k_RInfo, ObjArrayKlass::element_klass_offset()), k_RInfo); 2530 // perform the fast part of the checking logic 2531 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); 2532 2533 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2534 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2535 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2536 __ delayed()->nop(); 2537 __ cmp(G3, 0); 2538 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2539 __ delayed()->nop(); 2540 // fall through to the success case 2541 2542 if (op->should_profile()) { 2543 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2544 assert_different_registers(value, mdo, recv, tmp1); 2545 __ bind(profile_cast_success); 2546 metadata2reg(md->constant_encoding(), mdo); 2547 if (mdo_offset_bias > 0) { 2548 __ set(mdo_offset_bias, tmp1); 2549 __ add(mdo, tmp1, mdo); 2550 } 2551 __ load_klass(value, recv); 2552 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2553 __ ba_short(done); 2554 // Cast failure case 2555 __ bind(profile_cast_failure); 2556 metadata2reg(md->constant_encoding(), mdo); 2557 if (mdo_offset_bias > 0) { 2558 __ set(mdo_offset_bias, tmp1); 2559 __ add(mdo, tmp1, mdo); 2560 } 2561 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2562 __ ld_ptr(data_addr, tmp1); 2563 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2564 __ st_ptr(tmp1, data_addr); 2565 __ ba(*stub->entry()); 2566 __ delayed()->nop(); 2567 } 2568 __ bind(done); 2569 } else if (code == lir_checkcast) { 2570 Register obj = op->object()->as_register(); 2571 Register dst = op->result_opr()->as_register(); 2572 Label success; 2573 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2574 __ bind(success); 2575 __ mov(obj, dst); 2576 } else if (code == lir_instanceof) { 2577 Register obj = op->object()->as_register(); 2578 Register dst = op->result_opr()->as_register(); 2579 Label success, failure, done; 2580 emit_typecheck_helper(op, &success, &failure, &failure); 2581 __ bind(failure); 2582 __ set(0, dst); 2583 __ ba_short(done); 2584 __ bind(success); 2585 __ set(1, dst); 2586 __ bind(done); 2587 } else { 2588 ShouldNotReachHere(); 2589 } 2590 2591} 2592 2593 2594void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2595 if (op->code() == lir_cas_long) { 2596 assert(VM_Version::supports_cx8(), "wrong machine"); 2597 Register addr = op->addr()->as_pointer_register(); 2598 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2599 Register cmp_value_hi = op->cmp_value()->as_register_hi(); 2600 Register new_value_lo = op->new_value()->as_register_lo(); 2601 Register new_value_hi = op->new_value()->as_register_hi(); 2602 Register t1 = op->tmp1()->as_register(); 2603 Register t2 = op->tmp2()->as_register(); 2604 __ mov(cmp_value_lo, t1); 2605 __ mov(new_value_lo, t2); 2606 // perform the compare and swap operation 2607 __ casx(addr, t1, t2); 2608 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2609 // overwritten with the original value in "addr" and will be equal to t1. 2610 __ cmp(t1, t2); 2611 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2612 Register addr = op->addr()->as_pointer_register(); 2613 Register cmp_value = op->cmp_value()->as_register(); 2614 Register new_value = op->new_value()->as_register(); 2615 Register t1 = op->tmp1()->as_register(); 2616 Register t2 = op->tmp2()->as_register(); 2617 __ mov(cmp_value, t1); 2618 __ mov(new_value, t2); 2619 if (op->code() == lir_cas_obj) { 2620 if (UseCompressedOops) { 2621 __ encode_heap_oop(t1); 2622 __ encode_heap_oop(t2); 2623 __ cas(addr, t1, t2); 2624 } else { 2625 __ cas_ptr(addr, t1, t2); 2626 } 2627 } else { 2628 __ cas(addr, t1, t2); 2629 } 2630 __ cmp(t1, t2); 2631 } else { 2632 Unimplemented(); 2633 } 2634} 2635 2636void LIR_Assembler::set_24bit_FPU() { 2637 Unimplemented(); 2638} 2639 2640 2641void LIR_Assembler::reset_FPU() { 2642 Unimplemented(); 2643} 2644 2645 2646void LIR_Assembler::breakpoint() { 2647 __ breakpoint_trap(); 2648} 2649 2650 2651void LIR_Assembler::push(LIR_Opr opr) { 2652 Unimplemented(); 2653} 2654 2655 2656void LIR_Assembler::pop(LIR_Opr opr) { 2657 Unimplemented(); 2658} 2659 2660 2661void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2662 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2663 Register dst = dst_opr->as_register(); 2664 Register reg = mon_addr.base(); 2665 int offset = mon_addr.disp(); 2666 // compute pointer to BasicLock 2667 if (mon_addr.is_simm13()) { 2668 __ add(reg, offset, dst); 2669 } else { 2670 __ set(offset, dst); 2671 __ add(dst, reg, dst); 2672 } 2673} 2674 2675void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) { 2676 assert(op->crc()->is_single_cpu(), "crc must be register"); 2677 assert(op->val()->is_single_cpu(), "byte value must be register"); 2678 assert(op->result_opr()->is_single_cpu(), "result must be register"); 2679 Register crc = op->crc()->as_register(); 2680 Register val = op->val()->as_register(); 2681 Register table = op->result_opr()->as_register(); 2682 Register res = op->result_opr()->as_register(); 2683 2684 assert_different_registers(val, crc, table); 2685 2686 __ set(ExternalAddress(StubRoutines::crc_table_addr()), table); 2687 __ not1(crc); 2688 __ clruwu(crc); 2689 __ update_byte_crc32(crc, val, table); 2690 __ not1(crc); 2691 2692 __ mov(crc, res); 2693} 2694 2695void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2696 Register obj = op->obj_opr()->as_register(); 2697 Register hdr = op->hdr_opr()->as_register(); 2698 Register lock = op->lock_opr()->as_register(); 2699 2700 // obj may not be an oop 2701 if (op->code() == lir_lock) { 2702 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2703 if (UseFastLocking) { 2704 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2705 // add debug info for NullPointerException only if one is possible 2706 if (op->info() != NULL) { 2707 add_debug_info_for_null_check_here(op->info()); 2708 } 2709 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2710 } else { 2711 // always do slow locking 2712 // note: the slow locking code could be inlined here, however if we use 2713 // slow locking, speed doesn't matter anyway and this solution is 2714 // simpler and requires less duplicated code - additionally, the 2715 // slow locking code is the same in either case which simplifies 2716 // debugging 2717 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2718 __ delayed()->nop(); 2719 } 2720 } else { 2721 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2722 if (UseFastLocking) { 2723 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2724 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2725 } else { 2726 // always do slow unlocking 2727 // note: the slow unlocking code could be inlined here, however if we use 2728 // slow unlocking, speed doesn't matter anyway and this solution is 2729 // simpler and requires less duplicated code - additionally, the 2730 // slow unlocking code is the same in either case which simplifies 2731 // debugging 2732 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2733 __ delayed()->nop(); 2734 } 2735 } 2736 __ bind(*op->stub()->continuation()); 2737} 2738 2739 2740void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2741 ciMethod* method = op->profiled_method(); 2742 int bci = op->profiled_bci(); 2743 ciMethod* callee = op->profiled_callee(); 2744 2745 // Update counter for all call types 2746 ciMethodData* md = method->method_data_or_null(); 2747 assert(md != NULL, "Sanity"); 2748 ciProfileData* data = md->bci_to_data(bci); 2749 assert(data->is_CounterData(), "need CounterData for calls"); 2750 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2751 Register mdo = op->mdo()->as_register(); 2752 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2753 Register tmp1 = op->tmp1()->as_register_lo(); 2754 metadata2reg(md->constant_encoding(), mdo); 2755 int mdo_offset_bias = 0; 2756 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2757 data->size_in_bytes())) { 2758 // The offset is large so bias the mdo by the base of the slot so 2759 // that the ld can use simm13s to reference the slots of the data 2760 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2761 __ set(mdo_offset_bias, O7); 2762 __ add(mdo, O7, mdo); 2763 } 2764 2765 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2766 Bytecodes::Code bc = method->java_code_at_bci(bci); 2767 const bool callee_is_static = callee->is_loaded() && callee->is_static(); 2768 // Perform additional virtual call profiling for invokevirtual and 2769 // invokeinterface bytecodes 2770 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 2771 !callee_is_static && // required for optimized MH invokes 2772 C1ProfileVirtualCalls) { 2773 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2774 Register recv = op->recv()->as_register(); 2775 assert_different_registers(mdo, tmp1, recv); 2776 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2777 ciKlass* known_klass = op->known_holder(); 2778 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2779 // We know the type that will be seen at this call site; we can 2780 // statically update the MethodData* rather than needing to do 2781 // dynamic tests on the receiver type 2782 2783 // NOTE: we should probably put a lock around this search to 2784 // avoid collisions by concurrent compilations 2785 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2786 uint i; 2787 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2788 ciKlass* receiver = vc_data->receiver(i); 2789 if (known_klass->equals(receiver)) { 2790 Address data_addr(mdo, md->byte_offset_of_slot(data, 2791 VirtualCallData::receiver_count_offset(i)) - 2792 mdo_offset_bias); 2793 __ ld_ptr(data_addr, tmp1); 2794 __ add(tmp1, DataLayout::counter_increment, tmp1); 2795 __ st_ptr(tmp1, data_addr); 2796 return; 2797 } 2798 } 2799 2800 // Receiver type not found in profile data; select an empty slot 2801 2802 // Note that this is less efficient than it should be because it 2803 // always does a write to the receiver part of the 2804 // VirtualCallData rather than just the first time 2805 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2806 ciKlass* receiver = vc_data->receiver(i); 2807 if (receiver == NULL) { 2808 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2809 mdo_offset_bias); 2810 metadata2reg(known_klass->constant_encoding(), tmp1); 2811 __ st_ptr(tmp1, recv_addr); 2812 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2813 mdo_offset_bias); 2814 __ ld_ptr(data_addr, tmp1); 2815 __ add(tmp1, DataLayout::counter_increment, tmp1); 2816 __ st_ptr(tmp1, data_addr); 2817 return; 2818 } 2819 } 2820 } else { 2821 __ load_klass(recv, recv); 2822 Label update_done; 2823 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2824 // Receiver did not match any saved receiver and there is no empty row for it. 2825 // Increment total counter to indicate polymorphic case. 2826 __ ld_ptr(counter_addr, tmp1); 2827 __ add(tmp1, DataLayout::counter_increment, tmp1); 2828 __ st_ptr(tmp1, counter_addr); 2829 2830 __ bind(update_done); 2831 } 2832 } else { 2833 // Static call 2834 __ ld_ptr(counter_addr, tmp1); 2835 __ add(tmp1, DataLayout::counter_increment, tmp1); 2836 __ st_ptr(tmp1, counter_addr); 2837 } 2838} 2839 2840void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) { 2841 Register obj = op->obj()->as_register(); 2842 Register tmp1 = op->tmp()->as_pointer_register(); 2843 Register tmp2 = G1; 2844 Address mdo_addr = as_Address(op->mdp()->as_address_ptr()); 2845 ciKlass* exact_klass = op->exact_klass(); 2846 intptr_t current_klass = op->current_klass(); 2847 bool not_null = op->not_null(); 2848 bool no_conflict = op->no_conflict(); 2849 2850 Label update, next, none; 2851 2852 bool do_null = !not_null; 2853 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass; 2854 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set; 2855 2856 assert(do_null || do_update, "why are we here?"); 2857 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?"); 2858 2859 __ verify_oop(obj); 2860 2861 if (tmp1 != obj) { 2862 __ mov(obj, tmp1); 2863 } 2864 if (do_null) { 2865 __ br_notnull_short(tmp1, Assembler::pt, update); 2866 if (!TypeEntries::was_null_seen(current_klass)) { 2867 __ ld_ptr(mdo_addr, tmp1); 2868 __ or3(tmp1, TypeEntries::null_seen, tmp1); 2869 __ st_ptr(tmp1, mdo_addr); 2870 } 2871 if (do_update) { 2872 __ ba(next); 2873 __ delayed()->nop(); 2874 } 2875#ifdef ASSERT 2876 } else { 2877 __ br_notnull_short(tmp1, Assembler::pt, update); 2878 __ stop("unexpect null obj"); 2879#endif 2880 } 2881 2882 __ bind(update); 2883 2884 if (do_update) { 2885#ifdef ASSERT 2886 if (exact_klass != NULL) { 2887 Label ok; 2888 __ load_klass(tmp1, tmp1); 2889 metadata2reg(exact_klass->constant_encoding(), tmp2); 2890 __ cmp_and_br_short(tmp1, tmp2, Assembler::equal, Assembler::pt, ok); 2891 __ stop("exact klass and actual klass differ"); 2892 __ bind(ok); 2893 } 2894#endif 2895 2896 Label do_update; 2897 __ ld_ptr(mdo_addr, tmp2); 2898 2899 if (!no_conflict) { 2900 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) { 2901 if (exact_klass != NULL) { 2902 metadata2reg(exact_klass->constant_encoding(), tmp1); 2903 } else { 2904 __ load_klass(tmp1, tmp1); 2905 } 2906 2907 __ xor3(tmp1, tmp2, tmp1); 2908 __ btst(TypeEntries::type_klass_mask, tmp1); 2909 // klass seen before, nothing to do. The unknown bit may have been 2910 // set already but no need to check. 2911 __ brx(Assembler::zero, false, Assembler::pt, next); 2912 __ delayed()-> 2913 2914 btst(TypeEntries::type_unknown, tmp1); 2915 // already unknown. Nothing to do anymore. 2916 __ brx(Assembler::notZero, false, Assembler::pt, next); 2917 2918 if (TypeEntries::is_type_none(current_klass)) { 2919 __ delayed()->btst(TypeEntries::type_mask, tmp2); 2920 __ brx(Assembler::zero, true, Assembler::pt, do_update); 2921 // first time here. Set profile type. 2922 __ delayed()->or3(tmp2, tmp1, tmp2); 2923 } else { 2924 __ delayed()->nop(); 2925 } 2926 } else { 2927 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2928 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only"); 2929 2930 __ btst(TypeEntries::type_unknown, tmp2); 2931 // already unknown. Nothing to do anymore. 2932 __ brx(Assembler::notZero, false, Assembler::pt, next); 2933 __ delayed()->nop(); 2934 } 2935 2936 // different than before. Cannot keep accurate profile. 2937 __ or3(tmp2, TypeEntries::type_unknown, tmp2); 2938 } else { 2939 // There's a single possible klass at this profile point 2940 assert(exact_klass != NULL, "should be"); 2941 if (TypeEntries::is_type_none(current_klass)) { 2942 metadata2reg(exact_klass->constant_encoding(), tmp1); 2943 __ xor3(tmp1, tmp2, tmp1); 2944 __ btst(TypeEntries::type_klass_mask, tmp1); 2945 __ brx(Assembler::zero, false, Assembler::pt, next); 2946#ifdef ASSERT 2947 2948 { 2949 Label ok; 2950 __ delayed()->btst(TypeEntries::type_mask, tmp2); 2951 __ brx(Assembler::zero, true, Assembler::pt, ok); 2952 __ delayed()->nop(); 2953 2954 __ stop("unexpected profiling mismatch"); 2955 __ bind(ok); 2956 } 2957 // first time here. Set profile type. 2958 __ or3(tmp2, tmp1, tmp2); 2959#else 2960 // first time here. Set profile type. 2961 __ delayed()->or3(tmp2, tmp1, tmp2); 2962#endif 2963 2964 } else { 2965 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL && 2966 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent"); 2967 2968 // already unknown. Nothing to do anymore. 2969 __ btst(TypeEntries::type_unknown, tmp2); 2970 __ brx(Assembler::notZero, false, Assembler::pt, next); 2971 __ delayed()->or3(tmp2, TypeEntries::type_unknown, tmp2); 2972 } 2973 } 2974 2975 __ bind(do_update); 2976 __ st_ptr(tmp2, mdo_addr); 2977 2978 __ bind(next); 2979 } 2980} 2981 2982void LIR_Assembler::align_backward_branch_target() { 2983 __ align(OptoLoopAlignment); 2984} 2985 2986 2987void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2988 // make sure we are expecting a delay 2989 // this has the side effect of clearing the delay state 2990 // so we can use _masm instead of _masm->delayed() to do the 2991 // code generation. 2992 __ delayed(); 2993 2994 // make sure we only emit one instruction 2995 int offset = code_offset(); 2996 op->delay_op()->emit_code(this); 2997#ifdef ASSERT 2998 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { 2999 op->delay_op()->print(); 3000 } 3001 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, 3002 "only one instruction can go in a delay slot"); 3003#endif 3004 3005 // we may also be emitting the call info for the instruction 3006 // which we are the delay slot of. 3007 CodeEmitInfo* call_info = op->call_info(); 3008 if (call_info) { 3009 add_call_info(code_offset(), call_info); 3010 } 3011 3012 if (VerifyStackAtCalls) { 3013 _masm->sub(FP, SP, O7); 3014 _masm->cmp(O7, initial_frame_size_in_bytes()); 3015 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); 3016 } 3017} 3018 3019 3020void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3021 assert(left->is_register(), "can only handle registers"); 3022 3023 if (left->is_single_cpu()) { 3024 __ neg(left->as_register(), dest->as_register()); 3025 } else if (left->is_single_fpu()) { 3026 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); 3027 } else if (left->is_double_fpu()) { 3028 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); 3029 } else { 3030 assert (left->is_double_cpu(), "Must be a long"); 3031 Register Rlow = left->as_register_lo(); 3032 Register Rhi = left->as_register_hi(); 3033 __ sub(G0, Rlow, dest->as_register_lo()); 3034 } 3035} 3036 3037 3038void LIR_Assembler::fxch(int i) { 3039 Unimplemented(); 3040} 3041 3042void LIR_Assembler::fld(int i) { 3043 Unimplemented(); 3044} 3045 3046void LIR_Assembler::ffree(int i) { 3047 Unimplemented(); 3048} 3049 3050void LIR_Assembler::rt_call(LIR_Opr result, address dest, 3051 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3052 3053 // if tmp is invalid, then the function being called doesn't destroy the thread 3054 if (tmp->is_valid()) { 3055 __ save_thread(tmp->as_pointer_register()); 3056 } 3057 __ call(dest, relocInfo::runtime_call_type); 3058 __ delayed()->nop(); 3059 if (info != NULL) { 3060 add_call_info_here(info); 3061 } 3062 if (tmp->is_valid()) { 3063 __ restore_thread(tmp->as_pointer_register()); 3064 } 3065 3066#ifdef ASSERT 3067 __ verify_thread(); 3068#endif // ASSERT 3069} 3070 3071 3072void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3073 ShouldNotReachHere(); 3074 3075 NEEDS_CLEANUP; 3076 if (type == T_LONG) { 3077 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); 3078 3079 // (extended to allow indexed as well as constant displaced for JSR-166) 3080 Register idx = noreg; // contains either constant offset or index 3081 3082 int disp = mem_addr->disp(); 3083 if (mem_addr->index() == LIR_OprFact::illegalOpr) { 3084 if (!Assembler::is_simm13(disp)) { 3085 idx = O7; 3086 __ set(disp, idx); 3087 } 3088 } else { 3089 assert(disp == 0, "not both indexed and disp"); 3090 idx = mem_addr->index()->as_register(); 3091 } 3092 3093 int null_check_offset = -1; 3094 3095 Register base = mem_addr->base()->as_register(); 3096 if (src->is_register() && dest->is_address()) { 3097 // G4 is high half, G5 is low half 3098 // clear the top bits of G5, and scale up G4 3099 __ srl (src->as_register_lo(), 0, G5); 3100 __ sllx(src->as_register_hi(), 32, G4); 3101 // combine the two halves into the 64 bits of G4 3102 __ or3(G4, G5, G4); 3103 null_check_offset = __ offset(); 3104 if (idx == noreg) { 3105 __ stx(G4, base, disp); 3106 } else { 3107 __ stx(G4, base, idx); 3108 } 3109 } else if (src->is_address() && dest->is_register()) { 3110 null_check_offset = __ offset(); 3111 if (idx == noreg) { 3112 __ ldx(base, disp, G5); 3113 } else { 3114 __ ldx(base, idx, G5); 3115 } 3116 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi 3117 __ mov (G5, dest->as_register_lo()); // copy low half into lo 3118 } else { 3119 Unimplemented(); 3120 } 3121 if (info != NULL) { 3122 add_debug_info_for_null_check(null_check_offset, info); 3123 } 3124 3125 } else { 3126 // use normal move for all other volatiles since they don't need 3127 // special handling to remain atomic. 3128 move_op(src, dest, type, lir_patch_none, info, false, false, false); 3129 } 3130} 3131 3132void LIR_Assembler::membar() { 3133 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode 3134 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3135} 3136 3137void LIR_Assembler::membar_acquire() { 3138 // no-op on TSO 3139} 3140 3141void LIR_Assembler::membar_release() { 3142 // no-op on TSO 3143} 3144 3145void LIR_Assembler::membar_loadload() { 3146 // no-op 3147 //__ membar(Assembler::Membar_mask_bits(Assembler::loadload)); 3148} 3149 3150void LIR_Assembler::membar_storestore() { 3151 // no-op 3152 //__ membar(Assembler::Membar_mask_bits(Assembler::storestore)); 3153} 3154 3155void LIR_Assembler::membar_loadstore() { 3156 // no-op 3157 //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore)); 3158} 3159 3160void LIR_Assembler::membar_storeload() { 3161 __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 3162} 3163 3164void LIR_Assembler::on_spin_wait() { 3165 Unimplemented(); 3166} 3167 3168// Pack two sequential registers containing 32 bit values 3169// into a single 64 bit register. 3170// src and src->successor() are packed into dst 3171// src and dst may be the same register. 3172// Note: src is destroyed 3173void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { 3174 Register rs = src->as_register(); 3175 Register rd = dst->as_register_lo(); 3176 __ sllx(rs, 32, rs); 3177 __ srl(rs->successor(), 0, rs->successor()); 3178 __ or3(rs, rs->successor(), rd); 3179} 3180 3181// Unpack a 64 bit value in a register into 3182// two sequential registers. 3183// src is unpacked into dst and dst->successor() 3184void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { 3185 Register rs = src->as_register_lo(); 3186 Register rd = dst->as_register_hi(); 3187 assert_different_registers(rs, rd, rd->successor()); 3188 __ srlx(rs, 32, rd); 3189 __ srl (rs, 0, rd->successor()); 3190} 3191 3192void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 3193 const LIR_Address* addr = addr_opr->as_address_ptr(); 3194 assert(addr->scale() == LIR_Address::times_1, "can't handle complex addresses yet"); 3195 const Register dest_reg = dest->as_pointer_register(); 3196 const Register base_reg = addr->base()->as_pointer_register(); 3197 3198 if (Assembler::is_simm13(addr->disp())) { 3199 if (addr->index()->is_valid()) { 3200 const Register index_reg = addr->index()->as_pointer_register(); 3201 assert(index_reg != G3_scratch, "invariant"); 3202 __ add(base_reg, addr->disp(), G3_scratch); 3203 __ add(index_reg, G3_scratch, dest_reg); 3204 } else { 3205 __ add(base_reg, addr->disp(), dest_reg); 3206 } 3207 } else { 3208 __ set(addr->disp(), G3_scratch); 3209 if (addr->index()->is_valid()) { 3210 const Register index_reg = addr->index()->as_pointer_register(); 3211 assert(index_reg != G3_scratch, "invariant"); 3212 __ add(index_reg, G3_scratch, G3_scratch); 3213 } 3214 __ add(base_reg, G3_scratch, dest_reg); 3215 } 3216} 3217 3218 3219void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3220 assert(result_reg->is_register(), "check"); 3221 __ mov(G2_thread, result_reg->as_register()); 3222} 3223 3224#ifdef ASSERT 3225// emit run-time assertion 3226void LIR_Assembler::emit_assert(LIR_OpAssert* op) { 3227 assert(op->code() == lir_assert, "must be"); 3228 3229 if (op->in_opr1()->is_valid()) { 3230 assert(op->in_opr2()->is_valid(), "both operands must be valid"); 3231 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op); 3232 } else { 3233 assert(op->in_opr2()->is_illegal(), "both operands must be illegal"); 3234 assert(op->condition() == lir_cond_always, "no other conditions allowed"); 3235 } 3236 3237 Label ok; 3238 if (op->condition() != lir_cond_always) { 3239 Assembler::Condition acond; 3240 switch (op->condition()) { 3241 case lir_cond_equal: acond = Assembler::equal; break; 3242 case lir_cond_notEqual: acond = Assembler::notEqual; break; 3243 case lir_cond_less: acond = Assembler::less; break; 3244 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 3245 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 3246 case lir_cond_greater: acond = Assembler::greater; break; 3247 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 3248 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 3249 default: ShouldNotReachHere(); 3250 }; 3251 __ br(acond, false, Assembler::pt, ok); 3252 __ delayed()->nop(); 3253 } 3254 if (op->halt()) { 3255 const char* str = __ code_string(op->msg()); 3256 __ stop(str); 3257 } else { 3258 breakpoint(); 3259 } 3260 __ bind(ok); 3261} 3262#endif 3263 3264void LIR_Assembler::peephole(LIR_List* lir) { 3265 LIR_OpList* inst = lir->instructions_list(); 3266 for (int i = 0; i < inst->length(); i++) { 3267 LIR_Op* op = inst->at(i); 3268 switch (op->code()) { 3269 case lir_cond_float_branch: 3270 case lir_branch: { 3271 LIR_OpBranch* branch = op->as_OpBranch(); 3272 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); 3273 LIR_Op* delay_op = NULL; 3274 // we'd like to be able to pull following instructions into 3275 // this slot but we don't know enough to do it safely yet so 3276 // only optimize block to block control flow. 3277 if (LIRFillDelaySlots && branch->block()) { 3278 LIR_Op* prev = inst->at(i - 1); 3279 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { 3280 // swap previous instruction into delay slot 3281 inst->at_put(i - 1, op); 3282 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3283#ifndef PRODUCT 3284 if (LIRTracePeephole) { 3285 tty->print_cr("delayed"); 3286 inst->at(i - 1)->print(); 3287 inst->at(i)->print(); 3288 tty->cr(); 3289 } 3290#endif 3291 continue; 3292 } 3293 } 3294 3295 if (!delay_op) { 3296 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); 3297 } 3298 inst->insert_before(i + 1, delay_op); 3299 break; 3300 } 3301 case lir_static_call: 3302 case lir_virtual_call: 3303 case lir_icvirtual_call: 3304 case lir_optvirtual_call: 3305 case lir_dynamic_call: { 3306 LIR_Op* prev = inst->at(i - 1); 3307 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && 3308 (op->code() != lir_virtual_call || 3309 !prev->result_opr()->is_single_cpu() || 3310 prev->result_opr()->as_register() != O0) && 3311 LIR_Assembler::is_single_instruction(prev)) { 3312 // Only moves without info can be put into the delay slot. 3313 // Also don't allow the setup of the receiver in the delay 3314 // slot for vtable calls. 3315 inst->at_put(i - 1, op); 3316 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3317#ifndef PRODUCT 3318 if (LIRTracePeephole) { 3319 tty->print_cr("delayed"); 3320 inst->at(i - 1)->print(); 3321 inst->at(i)->print(); 3322 tty->cr(); 3323 } 3324#endif 3325 } else { 3326 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); 3327 inst->insert_before(i + 1, delay_op); 3328 i++; 3329 } 3330 break; 3331 } 3332 } 3333 } 3334} 3335 3336void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) { 3337 LIR_Address* addr = src->as_address_ptr(); 3338 3339 assert(data == dest, "swap uses only 2 operands"); 3340 assert (code == lir_xchg, "no xadd on sparc"); 3341 3342 if (data->type() == T_INT) { 3343 __ swap(as_Address(addr), data->as_register()); 3344 } else if (data->is_oop()) { 3345 Register obj = data->as_register(); 3346 Register narrow = tmp->as_register(); 3347 assert(UseCompressedOops, "swap is 32bit only"); 3348 __ encode_heap_oop(obj, narrow); 3349 __ swap(as_Address(addr), narrow); 3350 __ decode_heap_oop(narrow, obj); 3351 } else { 3352 ShouldNotReachHere(); 3353 } 3354} 3355 3356#undef __ 3357