c1_LIRAssembler_sparc.cpp revision 196:d1605aabd0a1
1/* 2 * Copyright 2000-2008 Sun Microsystems, Inc. All Rights Reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 20 * CA 95054 USA or visit www.sun.com if you need additional information or 21 * have any questions. 22 * 23 */ 24 25# include "incls/_precompiled.incl" 26# include "incls/_c1_LIRAssembler_sparc.cpp.incl" 27 28#define __ _masm-> 29 30 31//------------------------------------------------------------ 32 33 34bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 35 if (opr->is_constant()) { 36 LIR_Const* constant = opr->as_constant_ptr(); 37 switch (constant->type()) { 38 case T_INT: { 39 jint value = constant->as_jint(); 40 return Assembler::is_simm13(value); 41 } 42 43 default: 44 return false; 45 } 46 } 47 return false; 48} 49 50 51bool LIR_Assembler::is_single_instruction(LIR_Op* op) { 52 switch (op->code()) { 53 case lir_null_check: 54 return true; 55 56 57 case lir_add: 58 case lir_ushr: 59 case lir_shr: 60 case lir_shl: 61 // integer shifts and adds are always one instruction 62 return op->result_opr()->is_single_cpu(); 63 64 65 case lir_move: { 66 LIR_Op1* op1 = op->as_Op1(); 67 LIR_Opr src = op1->in_opr(); 68 LIR_Opr dst = op1->result_opr(); 69 70 if (src == dst) { 71 NEEDS_CLEANUP; 72 // this works around a problem where moves with the same src and dst 73 // end up in the delay slot and then the assembler swallows the mov 74 // since it has no effect and then it complains because the delay slot 75 // is empty. returning false stops the optimizer from putting this in 76 // the delay slot 77 return false; 78 } 79 80 // don't put moves involving oops into the delay slot since the VerifyOops code 81 // will make it much larger than a single instruction. 82 if (VerifyOops) { 83 return false; 84 } 85 86 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || 87 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { 88 return false; 89 } 90 91 if (dst->is_register()) { 92 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { 93 return !PatchALot; 94 } else if (src->is_single_stack()) { 95 return true; 96 } 97 } 98 99 if (src->is_register()) { 100 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { 101 return !PatchALot; 102 } else if (dst->is_single_stack()) { 103 return true; 104 } 105 } 106 107 if (dst->is_register() && 108 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || 109 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { 110 return true; 111 } 112 113 return false; 114 } 115 116 default: 117 return false; 118 } 119 ShouldNotReachHere(); 120} 121 122 123LIR_Opr LIR_Assembler::receiverOpr() { 124 return FrameMap::O0_oop_opr; 125} 126 127 128LIR_Opr LIR_Assembler::incomingReceiverOpr() { 129 return FrameMap::I0_oop_opr; 130} 131 132 133LIR_Opr LIR_Assembler::osrBufferPointer() { 134 return FrameMap::I0_opr; 135} 136 137 138int LIR_Assembler::initial_frame_size_in_bytes() { 139 return in_bytes(frame_map()->framesize_in_bytes()); 140} 141 142 143// inline cache check: the inline cached class is in G5_inline_cache_reg(G5); 144// we fetch the class of the receiver (O0) and compare it with the cached class. 145// If they do not match we jump to slow case. 146int LIR_Assembler::check_icache() { 147 int offset = __ offset(); 148 __ inline_cache_check(O0, G5_inline_cache_reg); 149 return offset; 150} 151 152 153void LIR_Assembler::osr_entry() { 154 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 155 // 156 // 1. Create a new compiled activation. 157 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 158 // at the osr_bci; it is not initialized. 159 // 3. Jump to the continuation address in compiled code to resume execution. 160 161 // OSR entry point 162 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 163 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 164 ValueStack* entry_state = osr_entry->end()->state(); 165 int number_of_locks = entry_state->locks_size(); 166 167 // Create a frame for the compiled activation. 168 __ build_frame(initial_frame_size_in_bytes()); 169 170 // OSR buffer is 171 // 172 // locals[nlocals-1..0] 173 // monitors[number_of_locks-1..0] 174 // 175 // locals is a direct copy of the interpreter frame so in the osr buffer 176 // so first slot in the local array is the last local from the interpreter 177 // and last slot is local[0] (receiver) from the interpreter 178 // 179 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 180 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 181 // in the interpreter frame (the method lock if a sync method) 182 183 // Initialize monitors in the compiled activation. 184 // I0: pointer to osr buffer 185 // 186 // All other registers are dead at this point and the locals will be 187 // copied into place by code emitted in the IR. 188 189 Register OSR_buf = osrBufferPointer()->as_register(); 190 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 191 int monitor_offset = BytesPerWord * method()->max_locals() + 192 (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1); 193 for (int i = 0; i < number_of_locks; i++) { 194 int slot_offset = monitor_offset - ((i * BasicObjectLock::size()) * BytesPerWord); 195#ifdef ASSERT 196 // verify the interpreter's monitor has a non-null object 197 { 198 Label L; 199 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); 200 __ cmp(G0, O7); 201 __ br(Assembler::notEqual, false, Assembler::pt, L); 202 __ delayed()->nop(); 203 __ stop("locked object is NULL"); 204 __ bind(L); 205 } 206#endif // ASSERT 207 // Copy the lock field into the compiled activation. 208 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::lock_offset_in_bytes()), O7); 209 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); 210 __ ld_ptr(Address(OSR_buf, 0, slot_offset + BasicObjectLock::obj_offset_in_bytes()), O7); 211 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); 212 } 213 } 214} 215 216 217// Optimized Library calls 218// This is the fast version of java.lang.String.compare; it has not 219// OSR-entry and therefore, we generate a slow version for OSR's 220void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { 221 Register str0 = left->as_register(); 222 Register str1 = right->as_register(); 223 224 Label Ldone; 225 226 Register result = dst->as_register(); 227 { 228 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 229 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 230 // Also, get string0.count-string1.count in o7 and get the condition code set 231 // Note: some instructions have been hoisted for better instruction scheduling 232 233 Register tmp0 = L0; 234 Register tmp1 = L1; 235 Register tmp2 = L2; 236 237 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array 238 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position 239 int count_offset = java_lang_String:: count_offset_in_bytes(); 240 241 __ ld_ptr(Address(str0, 0, value_offset), tmp0); 242 __ ld(Address(str0, 0, offset_offset), tmp2); 243 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); 244 __ ld(Address(str0, 0, count_offset), str0); 245 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 246 247 // str1 may be null 248 add_debug_info_for_null_check_here(info); 249 250 __ ld_ptr(Address(str1, 0, value_offset), tmp1); 251 __ add(tmp0, tmp2, tmp0); 252 253 __ ld(Address(str1, 0, offset_offset), tmp2); 254 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); 255 __ ld(Address(str1, 0, count_offset), str1); 256 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 257 __ subcc(str0, str1, O7); 258 __ add(tmp1, tmp2, tmp1); 259 } 260 261 { 262 // Compute the minimum of the string lengths, scale it and store it in limit 263 Register count0 = I0; 264 Register count1 = I1; 265 Register limit = L3; 266 267 Label Lskip; 268 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter 269 __ br(Assembler::greater, true, Assembler::pt, Lskip); 270 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter 271 __ bind(Lskip); 272 273 // If either string is empty (or both of them) the result is the difference in lengths 274 __ cmp(limit, 0); 275 __ br(Assembler::equal, true, Assembler::pn, Ldone); 276 __ delayed()->mov(O7, result); // result is difference in lengths 277 } 278 279 { 280 // Neither string is empty 281 Label Lloop; 282 283 Register base0 = L0; 284 Register base1 = L1; 285 Register chr0 = I0; 286 Register chr1 = I1; 287 Register limit = L3; 288 289 // Shift base0 and base1 to the end of the arrays, negate limit 290 __ add(base0, limit, base0); 291 __ add(base1, limit, base1); 292 __ neg(limit); // limit = -min{string0.count, strin1.count} 293 294 __ lduh(base0, limit, chr0); 295 __ bind(Lloop); 296 __ lduh(base1, limit, chr1); 297 __ subcc(chr0, chr1, chr0); 298 __ br(Assembler::notZero, false, Assembler::pn, Ldone); 299 assert(chr0 == result, "result must be pre-placed"); 300 __ delayed()->inccc(limit, sizeof(jchar)); 301 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 302 __ delayed()->lduh(base0, limit, chr0); 303 } 304 305 // If strings are equal up to min length, return the length difference. 306 __ mov(O7, result); 307 308 // Otherwise, return the difference between the first mismatched chars. 309 __ bind(Ldone); 310} 311 312 313// -------------------------------------------------------------------------------------------- 314 315void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { 316 if (!GenerateSynchronizationCode) return; 317 318 Register obj_reg = obj_opr->as_register(); 319 Register lock_reg = lock_opr->as_register(); 320 321 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 322 Register reg = mon_addr.base(); 323 int offset = mon_addr.disp(); 324 // compute pointer to BasicLock 325 if (mon_addr.is_simm13()) { 326 __ add(reg, offset, lock_reg); 327 } 328 else { 329 __ set(offset, lock_reg); 330 __ add(reg, lock_reg, lock_reg); 331 } 332 // unlock object 333 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); 334 // _slow_case_stubs->append(slow_case); 335 // temporary fix: must be created after exceptionhandler, therefore as call stub 336 _slow_case_stubs->append(slow_case); 337 if (UseFastLocking) { 338 // try inlined fast unlocking first, revert to slow locking if it fails 339 // note: lock_reg points to the displaced header since the displaced header offset is 0! 340 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 341 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 342 } else { 343 // always do slow unlocking 344 // note: the slow unlocking code could be inlined here, however if we use 345 // slow unlocking, speed doesn't matter anyway and this solution is 346 // simpler and requires less duplicated code - additionally, the 347 // slow unlocking code is the same in either case which simplifies 348 // debugging 349 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); 350 __ delayed()->nop(); 351 } 352 // done 353 __ bind(*slow_case->continuation()); 354} 355 356 357void LIR_Assembler::emit_exception_handler() { 358 // if the last instruction is a call (typically to do a throw which 359 // is coming at the end after block reordering) the return address 360 // must still point into the code area in order to avoid assertion 361 // failures when searching for the corresponding bci => add a nop 362 // (was bug 5/14/1999 - gri) 363 __ nop(); 364 365 // generate code for exception handler 366 ciMethod* method = compilation()->method(); 367 368 address handler_base = __ start_a_stub(exception_handler_size); 369 370 if (handler_base == NULL) { 371 // not enough space left for the handler 372 bailout("exception handler overflow"); 373 return; 374 } 375#ifdef ASSERT 376 int offset = code_offset(); 377#endif // ASSERT 378 compilation()->offsets()->set_value(CodeOffsets::Exceptions, code_offset()); 379 380 381 if (compilation()->has_exception_handlers() || JvmtiExport::can_post_exceptions()) { 382 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 383 __ delayed()->nop(); 384 } 385 386 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 387 __ delayed()->nop(); 388 debug_only(__ stop("should have gone to the caller");) 389 assert(code_offset() - offset <= exception_handler_size, "overflow"); 390 391 __ end_a_stub(); 392} 393 394void LIR_Assembler::emit_deopt_handler() { 395 // if the last instruction is a call (typically to do a throw which 396 // is coming at the end after block reordering) the return address 397 // must still point into the code area in order to avoid assertion 398 // failures when searching for the corresponding bci => add a nop 399 // (was bug 5/14/1999 - gri) 400 __ nop(); 401 402 // generate code for deopt handler 403 ciMethod* method = compilation()->method(); 404 address handler_base = __ start_a_stub(deopt_handler_size); 405 if (handler_base == NULL) { 406 // not enough space left for the handler 407 bailout("deopt handler overflow"); 408 return; 409 } 410#ifdef ASSERT 411 int offset = code_offset(); 412#endif // ASSERT 413 compilation()->offsets()->set_value(CodeOffsets::Deopt, code_offset()); 414 415 Address deopt_blob(G3_scratch, SharedRuntime::deopt_blob()->unpack()); 416 417 __ JUMP(deopt_blob, 0); // sethi;jmp 418 __ delayed()->nop(); 419 420 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 421 422 debug_only(__ stop("should have gone to the caller");) 423 424 __ end_a_stub(); 425} 426 427 428void LIR_Assembler::jobject2reg(jobject o, Register reg) { 429 if (o == NULL) { 430 __ set(NULL_WORD, reg); 431 } else { 432 int oop_index = __ oop_recorder()->find_index(o); 433 RelocationHolder rspec = oop_Relocation::spec(oop_index); 434 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created 435 } 436} 437 438 439void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 440 // Allocate a new index in oop table to hold the oop once it's been patched 441 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); 442 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); 443 444 Address addr = Address(reg, address(NULL), oop_Relocation::spec(oop_index)); 445 assert(addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 446 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 447 // NULL will be dynamically patched later and the patched value may be large. We must 448 // therefore generate the sethi/add as a placeholders 449 __ sethi(addr, true); 450 __ add(addr, reg, 0); 451 452 patching_epilog(patch, lir_patch_normal, reg, info); 453} 454 455 456void LIR_Assembler::emit_op3(LIR_Op3* op) { 457 Register Rdividend = op->in_opr1()->as_register(); 458 Register Rdivisor = noreg; 459 Register Rscratch = op->in_opr3()->as_register(); 460 Register Rresult = op->result_opr()->as_register(); 461 int divisor = -1; 462 463 if (op->in_opr2()->is_register()) { 464 Rdivisor = op->in_opr2()->as_register(); 465 } else { 466 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); 467 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 468 } 469 470 assert(Rdividend != Rscratch, ""); 471 assert(Rdivisor != Rscratch, ""); 472 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); 473 474 if (Rdivisor == noreg && is_power_of_2(divisor)) { 475 // convert division by a power of two into some shifts and logical operations 476 if (op->code() == lir_idiv) { 477 if (divisor == 2) { 478 __ srl(Rdividend, 31, Rscratch); 479 } else { 480 __ sra(Rdividend, 31, Rscratch); 481 __ and3(Rscratch, divisor - 1, Rscratch); 482 } 483 __ add(Rdividend, Rscratch, Rscratch); 484 __ sra(Rscratch, log2_intptr(divisor), Rresult); 485 return; 486 } else { 487 if (divisor == 2) { 488 __ srl(Rdividend, 31, Rscratch); 489 } else { 490 __ sra(Rdividend, 31, Rscratch); 491 __ and3(Rscratch, divisor - 1,Rscratch); 492 } 493 __ add(Rdividend, Rscratch, Rscratch); 494 __ andn(Rscratch, divisor - 1,Rscratch); 495 __ sub(Rdividend, Rscratch, Rresult); 496 return; 497 } 498 } 499 500 __ sra(Rdividend, 31, Rscratch); 501 __ wry(Rscratch); 502 if (!VM_Version::v9_instructions_work()) { 503 // v9 doesn't require these nops 504 __ nop(); 505 __ nop(); 506 __ nop(); 507 __ nop(); 508 } 509 510 add_debug_info_for_div0_here(op->info()); 511 512 if (Rdivisor != noreg) { 513 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 514 } else { 515 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 516 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 517 } 518 519 Label skip; 520 __ br(Assembler::overflowSet, true, Assembler::pn, skip); 521 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); 522 __ bind(skip); 523 524 if (op->code() == lir_irem) { 525 if (Rdivisor != noreg) { 526 __ smul(Rscratch, Rdivisor, Rscratch); 527 } else { 528 __ smul(Rscratch, divisor, Rscratch); 529 } 530 __ sub(Rdividend, Rscratch, Rresult); 531 } 532} 533 534 535void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 536#ifdef ASSERT 537 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 538 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 539 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 540#endif 541 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 542 543 if (op->cond() == lir_cond_always) { 544 __ br(Assembler::always, false, Assembler::pt, *(op->label())); 545 } else if (op->code() == lir_cond_float_branch) { 546 assert(op->ublock() != NULL, "must have unordered successor"); 547 bool is_unordered = (op->ublock() == op->block()); 548 Assembler::Condition acond; 549 switch (op->cond()) { 550 case lir_cond_equal: acond = Assembler::f_equal; break; 551 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; 552 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; 553 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; 554 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; 555 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; 556 default : ShouldNotReachHere(); 557 }; 558 559 if (!VM_Version::v9_instructions_work()) { 560 __ nop(); 561 } 562 __ fb( acond, false, Assembler::pn, *(op->label())); 563 } else { 564 assert (op->code() == lir_branch, "just checking"); 565 566 Assembler::Condition acond; 567 switch (op->cond()) { 568 case lir_cond_equal: acond = Assembler::equal; break; 569 case lir_cond_notEqual: acond = Assembler::notEqual; break; 570 case lir_cond_less: acond = Assembler::less; break; 571 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 572 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 573 case lir_cond_greater: acond = Assembler::greater; break; 574 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 575 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 576 default: ShouldNotReachHere(); 577 }; 578 579 // sparc has different condition codes for testing 32-bit 580 // vs. 64-bit values. We could always test xcc is we could 581 // guarantee that 32-bit loads always sign extended but that isn't 582 // true and since sign extension isn't free, it would impose a 583 // slight cost. 584#ifdef _LP64 585 if (op->type() == T_INT) { 586 __ br(acond, false, Assembler::pn, *(op->label())); 587 } else 588#endif 589 __ brx(acond, false, Assembler::pn, *(op->label())); 590 } 591 // The peephole pass fills the delay slot 592} 593 594 595void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 596 Bytecodes::Code code = op->bytecode(); 597 LIR_Opr dst = op->result_opr(); 598 599 switch(code) { 600 case Bytecodes::_i2l: { 601 Register rlo = dst->as_register_lo(); 602 Register rhi = dst->as_register_hi(); 603 Register rval = op->in_opr()->as_register(); 604#ifdef _LP64 605 __ sra(rval, 0, rlo); 606#else 607 __ mov(rval, rlo); 608 __ sra(rval, BitsPerInt-1, rhi); 609#endif 610 break; 611 } 612 case Bytecodes::_i2d: 613 case Bytecodes::_i2f: { 614 bool is_double = (code == Bytecodes::_i2d); 615 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 616 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 617 FloatRegister rsrc = op->in_opr()->as_float_reg(); 618 if (rsrc != rdst) { 619 __ fmov(FloatRegisterImpl::S, rsrc, rdst); 620 } 621 __ fitof(w, rdst, rdst); 622 break; 623 } 624 case Bytecodes::_f2i:{ 625 FloatRegister rsrc = op->in_opr()->as_float_reg(); 626 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); 627 Label L; 628 // result must be 0 if value is NaN; test by comparing value to itself 629 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); 630 if (!VM_Version::v9_instructions_work()) { 631 __ nop(); 632 } 633 __ fb(Assembler::f_unordered, true, Assembler::pn, L); 634 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN 635 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); 636 // move integer result from float register to int register 637 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); 638 __ bind (L); 639 break; 640 } 641 case Bytecodes::_l2i: { 642 Register rlo = op->in_opr()->as_register_lo(); 643 Register rhi = op->in_opr()->as_register_hi(); 644 Register rdst = dst->as_register(); 645#ifdef _LP64 646 __ sra(rlo, 0, rdst); 647#else 648 __ mov(rlo, rdst); 649#endif 650 break; 651 } 652 case Bytecodes::_d2f: 653 case Bytecodes::_f2d: { 654 bool is_double = (code == Bytecodes::_f2d); 655 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); 656 LIR_Opr val = op->in_opr(); 657 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); 658 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 659 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; 660 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 661 __ ftof(vw, dw, rval, rdst); 662 break; 663 } 664 case Bytecodes::_i2s: 665 case Bytecodes::_i2b: { 666 Register rval = op->in_opr()->as_register(); 667 Register rdst = dst->as_register(); 668 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); 669 __ sll (rval, shift, rdst); 670 __ sra (rdst, shift, rdst); 671 break; 672 } 673 case Bytecodes::_i2c: { 674 Register rval = op->in_opr()->as_register(); 675 Register rdst = dst->as_register(); 676 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; 677 __ sll (rval, shift, rdst); 678 __ srl (rdst, shift, rdst); 679 break; 680 } 681 682 default: ShouldNotReachHere(); 683 } 684} 685 686 687void LIR_Assembler::align_call(LIR_Code) { 688 // do nothing since all instructions are word aligned on sparc 689} 690 691 692void LIR_Assembler::call(address entry, relocInfo::relocType rtype, CodeEmitInfo* info) { 693 __ call(entry, rtype); 694 // the peephole pass fills the delay slot 695} 696 697 698void LIR_Assembler::ic_call(address entry, CodeEmitInfo* info) { 699 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); 700 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); 701 __ relocate(rspec); 702 __ call(entry, relocInfo::none); 703 // the peephole pass fills the delay slot 704} 705 706 707void LIR_Assembler::vtable_call(int vtable_offset, CodeEmitInfo* info) { 708 add_debug_info_for_null_check_here(info); 709 __ ld_ptr(Address(O0, 0, oopDesc::klass_offset_in_bytes()), G3_scratch); 710 if (__ is_simm13(vtable_offset) ) { 711 __ ld_ptr(G3_scratch, vtable_offset, G5_method); 712 } else { 713 // This will generate 2 instructions 714 __ set(vtable_offset, G5_method); 715 // ld_ptr, set_hi, set 716 __ ld_ptr(G3_scratch, G5_method, G5_method); 717 } 718 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3_scratch); 719 __ callr(G3_scratch, G0); 720 // the peephole pass fills the delay slot 721} 722 723 724// load with 32-bit displacement 725int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { 726 int load_offset = code_offset(); 727 if (Assembler::is_simm13(disp)) { 728 if (info != NULL) add_debug_info_for_null_check_here(info); 729 switch(ld_type) { 730 case T_BOOLEAN: // fall through 731 case T_BYTE : __ ldsb(s, disp, d); break; 732 case T_CHAR : __ lduh(s, disp, d); break; 733 case T_SHORT : __ ldsh(s, disp, d); break; 734 case T_INT : __ ld(s, disp, d); break; 735 case T_ADDRESS:// fall through 736 case T_ARRAY : // fall through 737 case T_OBJECT: __ ld_ptr(s, disp, d); break; 738 default : ShouldNotReachHere(); 739 } 740 } else { 741 __ sethi(disp & ~0x3ff, O7, true); 742 __ add(O7, disp & 0x3ff, O7); 743 if (info != NULL) add_debug_info_for_null_check_here(info); 744 load_offset = code_offset(); 745 switch(ld_type) { 746 case T_BOOLEAN: // fall through 747 case T_BYTE : __ ldsb(s, O7, d); break; 748 case T_CHAR : __ lduh(s, O7, d); break; 749 case T_SHORT : __ ldsh(s, O7, d); break; 750 case T_INT : __ ld(s, O7, d); break; 751 case T_ADDRESS:// fall through 752 case T_ARRAY : // fall through 753 case T_OBJECT: __ ld_ptr(s, O7, d); break; 754 default : ShouldNotReachHere(); 755 } 756 } 757 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); 758 return load_offset; 759} 760 761 762// store with 32-bit displacement 763void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { 764 if (Assembler::is_simm13(offset)) { 765 if (info != NULL) add_debug_info_for_null_check_here(info); 766 switch (type) { 767 case T_BOOLEAN: // fall through 768 case T_BYTE : __ stb(value, base, offset); break; 769 case T_CHAR : __ sth(value, base, offset); break; 770 case T_SHORT : __ sth(value, base, offset); break; 771 case T_INT : __ stw(value, base, offset); break; 772 case T_ADDRESS:// fall through 773 case T_ARRAY : // fall through 774 case T_OBJECT: __ st_ptr(value, base, offset); break; 775 default : ShouldNotReachHere(); 776 } 777 } else { 778 __ sethi(offset & ~0x3ff, O7, true); 779 __ add(O7, offset & 0x3ff, O7); 780 if (info != NULL) add_debug_info_for_null_check_here(info); 781 switch (type) { 782 case T_BOOLEAN: // fall through 783 case T_BYTE : __ stb(value, base, O7); break; 784 case T_CHAR : __ sth(value, base, O7); break; 785 case T_SHORT : __ sth(value, base, O7); break; 786 case T_INT : __ stw(value, base, O7); break; 787 case T_ADDRESS:// fall through 788 case T_ARRAY : //fall through 789 case T_OBJECT: __ st_ptr(value, base, O7); break; 790 default : ShouldNotReachHere(); 791 } 792 } 793 // Note: Do the store before verification as the code might be patched! 794 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); 795} 796 797 798// load float with 32-bit displacement 799void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { 800 FloatRegisterImpl::Width w; 801 switch(ld_type) { 802 case T_FLOAT : w = FloatRegisterImpl::S; break; 803 case T_DOUBLE: w = FloatRegisterImpl::D; break; 804 default : ShouldNotReachHere(); 805 } 806 807 if (Assembler::is_simm13(disp)) { 808 if (info != NULL) add_debug_info_for_null_check_here(info); 809 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { 810 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); 811 __ ldf(FloatRegisterImpl::S, s, disp , d); 812 } else { 813 __ ldf(w, s, disp, d); 814 } 815 } else { 816 __ sethi(disp & ~0x3ff, O7, true); 817 __ add(O7, disp & 0x3ff, O7); 818 if (info != NULL) add_debug_info_for_null_check_here(info); 819 __ ldf(w, s, O7, d); 820 } 821} 822 823 824// store float with 32-bit displacement 825void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { 826 FloatRegisterImpl::Width w; 827 switch(type) { 828 case T_FLOAT : w = FloatRegisterImpl::S; break; 829 case T_DOUBLE: w = FloatRegisterImpl::D; break; 830 default : ShouldNotReachHere(); 831 } 832 833 if (Assembler::is_simm13(offset)) { 834 if (info != NULL) add_debug_info_for_null_check_here(info); 835 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { 836 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); 837 __ stf(FloatRegisterImpl::S, value , base, offset); 838 } else { 839 __ stf(w, value, base, offset); 840 } 841 } else { 842 __ sethi(offset & ~0x3ff, O7, true); 843 __ add(O7, offset & 0x3ff, O7); 844 if (info != NULL) add_debug_info_for_null_check_here(info); 845 __ stf(w, value, O7, base); 846 } 847} 848 849 850int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { 851 int store_offset; 852 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 853 assert(!unaligned, "can't handle this"); 854 // for offsets larger than a simm13 we setup the offset in O7 855 __ sethi(offset & ~0x3ff, O7, true); 856 __ add(O7, offset & 0x3ff, O7); 857 store_offset = store(from_reg, base, O7, type); 858 } else { 859 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); 860 store_offset = code_offset(); 861 switch (type) { 862 case T_BOOLEAN: // fall through 863 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; 864 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; 865 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; 866 case T_INT : __ stw(from_reg->as_register(), base, offset); break; 867 case T_LONG : 868#ifdef _LP64 869 if (unaligned || PatchALot) { 870 __ srax(from_reg->as_register_lo(), 32, O7); 871 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 872 __ stw(O7, base, offset + hi_word_offset_in_bytes); 873 } else { 874 __ stx(from_reg->as_register_lo(), base, offset); 875 } 876#else 877 assert(Assembler::is_simm13(offset + 4), "must be"); 878 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 879 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); 880#endif 881 break; 882 case T_ADDRESS:// fall through 883 case T_ARRAY : // fall through 884 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; 885 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; 886 case T_DOUBLE: 887 { 888 FloatRegister reg = from_reg->as_double_reg(); 889 // split unaligned stores 890 if (unaligned || PatchALot) { 891 assert(Assembler::is_simm13(offset + 4), "must be"); 892 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); 893 __ stf(FloatRegisterImpl::S, reg, base, offset); 894 } else { 895 __ stf(FloatRegisterImpl::D, reg, base, offset); 896 } 897 break; 898 } 899 default : ShouldNotReachHere(); 900 } 901 } 902 return store_offset; 903} 904 905 906int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { 907 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); 908 int store_offset = code_offset(); 909 switch (type) { 910 case T_BOOLEAN: // fall through 911 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; 912 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; 913 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; 914 case T_INT : __ stw(from_reg->as_register(), base, disp); break; 915 case T_LONG : 916#ifdef _LP64 917 __ stx(from_reg->as_register_lo(), base, disp); 918#else 919 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); 920 __ std(from_reg->as_register_hi(), base, disp); 921#endif 922 break; 923 case T_ADDRESS:// fall through 924 case T_ARRAY : // fall through 925 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; 926 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; 927 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; 928 default : ShouldNotReachHere(); 929 } 930 return store_offset; 931} 932 933 934int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { 935 int load_offset; 936 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 937 assert(base != O7, "destroying register"); 938 assert(!unaligned, "can't handle this"); 939 // for offsets larger than a simm13 we setup the offset in O7 940 __ sethi(offset & ~0x3ff, O7, true); 941 __ add(O7, offset & 0x3ff, O7); 942 load_offset = load(base, O7, to_reg, type); 943 } else { 944 load_offset = code_offset(); 945 switch(type) { 946 case T_BOOLEAN: // fall through 947 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; 948 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; 949 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; 950 case T_INT : __ ld(base, offset, to_reg->as_register()); break; 951 case T_LONG : 952 if (!unaligned) { 953#ifdef _LP64 954 __ ldx(base, offset, to_reg->as_register_lo()); 955#else 956 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 957 "must be sequential"); 958 __ ldd(base, offset, to_reg->as_register_hi()); 959#endif 960 } else { 961#ifdef _LP64 962 assert(base != to_reg->as_register_lo(), "can't handle this"); 963 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); 964 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); 965 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 966#else 967 if (base == to_reg->as_register_lo()) { 968 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 969 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 970 } else { 971 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 972 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 973 } 974#endif 975 } 976 break; 977 case T_ADDRESS:// fall through 978 case T_ARRAY : // fall through 979 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; 980 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; 981 case T_DOUBLE: 982 { 983 FloatRegister reg = to_reg->as_double_reg(); 984 // split unaligned loads 985 if (unaligned || PatchALot) { 986 __ ldf(FloatRegisterImpl::S, base, offset + BytesPerWord, reg->successor()); 987 __ ldf(FloatRegisterImpl::S, base, offset, reg); 988 } else { 989 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); 990 } 991 break; 992 } 993 default : ShouldNotReachHere(); 994 } 995 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); 996 } 997 return load_offset; 998} 999 1000 1001int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { 1002 int load_offset = code_offset(); 1003 switch(type) { 1004 case T_BOOLEAN: // fall through 1005 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; 1006 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; 1007 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; 1008 case T_INT : __ ld(base, disp, to_reg->as_register()); break; 1009 case T_ADDRESS:// fall through 1010 case T_ARRAY : // fall through 1011 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; 1012 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; 1013 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; 1014 case T_LONG : 1015#ifdef _LP64 1016 __ ldx(base, disp, to_reg->as_register_lo()); 1017#else 1018 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 1019 "must be sequential"); 1020 __ ldd(base, disp, to_reg->as_register_hi()); 1021#endif 1022 break; 1023 default : ShouldNotReachHere(); 1024 } 1025 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); 1026 return load_offset; 1027} 1028 1029 1030// load/store with an Address 1031void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { 1032 load(a.base(), a.disp() + offset, d, ld_type, info); 1033} 1034 1035 1036void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { 1037 store(value, dest.base(), dest.disp() + offset, type, info); 1038} 1039 1040 1041// loadf/storef with an Address 1042void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { 1043 load(a.base(), a.disp() + offset, d, ld_type, info); 1044} 1045 1046 1047void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { 1048 store(value, dest.base(), dest.disp() + offset, type, info); 1049} 1050 1051 1052// load/store with an Address 1053void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { 1054 load(as_Address(a), d, ld_type, info); 1055} 1056 1057 1058void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { 1059 store(value, as_Address(dest), type, info); 1060} 1061 1062 1063// loadf/storef with an Address 1064void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { 1065 load(as_Address(a), d, ld_type, info); 1066} 1067 1068 1069void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { 1070 store(value, as_Address(dest), type, info); 1071} 1072 1073 1074void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 1075 LIR_Const* c = src->as_constant_ptr(); 1076 switch (c->type()) { 1077 case T_INT: 1078 case T_FLOAT: { 1079 Register src_reg = O7; 1080 int value = c->as_jint_bits(); 1081 if (value == 0) { 1082 src_reg = G0; 1083 } else { 1084 __ set(value, O7); 1085 } 1086 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1087 __ stw(src_reg, addr.base(), addr.disp()); 1088 break; 1089 } 1090 case T_OBJECT: { 1091 Register src_reg = O7; 1092 jobject2reg(c->as_jobject(), src_reg); 1093 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1094 __ st_ptr(src_reg, addr.base(), addr.disp()); 1095 break; 1096 } 1097 case T_LONG: 1098 case T_DOUBLE: { 1099 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1100 1101 Register tmp = O7; 1102 int value_lo = c->as_jint_lo_bits(); 1103 if (value_lo == 0) { 1104 tmp = G0; 1105 } else { 1106 __ set(value_lo, O7); 1107 } 1108 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); 1109 int value_hi = c->as_jint_hi_bits(); 1110 if (value_hi == 0) { 1111 tmp = G0; 1112 } else { 1113 __ set(value_hi, O7); 1114 } 1115 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); 1116 break; 1117 } 1118 default: 1119 Unimplemented(); 1120 } 1121} 1122 1123 1124void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 1125 LIR_Const* c = src->as_constant_ptr(); 1126 LIR_Address* addr = dest->as_address_ptr(); 1127 Register base = addr->base()->as_pointer_register(); 1128 1129 if (info != NULL) { 1130 add_debug_info_for_null_check_here(info); 1131 } 1132 switch (c->type()) { 1133 case T_INT: 1134 case T_FLOAT: { 1135 LIR_Opr tmp = FrameMap::O7_opr; 1136 int value = c->as_jint_bits(); 1137 if (value == 0) { 1138 tmp = FrameMap::G0_opr; 1139 } else if (Assembler::is_simm13(value)) { 1140 __ set(value, O7); 1141 } 1142 if (addr->index()->is_valid()) { 1143 assert(addr->disp() == 0, "must be zero"); 1144 store(tmp, base, addr->index()->as_pointer_register(), type); 1145 } else { 1146 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1147 store(tmp, base, addr->disp(), type); 1148 } 1149 break; 1150 } 1151 case T_LONG: 1152 case T_DOUBLE: { 1153 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); 1154 assert(Assembler::is_simm13(addr->disp()) && 1155 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); 1156 1157 Register tmp = O7; 1158 int value_lo = c->as_jint_lo_bits(); 1159 if (value_lo == 0) { 1160 tmp = G0; 1161 } else { 1162 __ set(value_lo, O7); 1163 } 1164 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); 1165 int value_hi = c->as_jint_hi_bits(); 1166 if (value_hi == 0) { 1167 tmp = G0; 1168 } else { 1169 __ set(value_hi, O7); 1170 } 1171 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); 1172 break; 1173 } 1174 case T_OBJECT: { 1175 jobject obj = c->as_jobject(); 1176 LIR_Opr tmp; 1177 if (obj == NULL) { 1178 tmp = FrameMap::G0_opr; 1179 } else { 1180 tmp = FrameMap::O7_opr; 1181 jobject2reg(c->as_jobject(), O7); 1182 } 1183 // handle either reg+reg or reg+disp address 1184 if (addr->index()->is_valid()) { 1185 assert(addr->disp() == 0, "must be zero"); 1186 store(tmp, base, addr->index()->as_pointer_register(), type); 1187 } else { 1188 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1189 store(tmp, base, addr->disp(), type); 1190 } 1191 1192 break; 1193 } 1194 default: 1195 Unimplemented(); 1196 } 1197} 1198 1199 1200void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 1201 LIR_Const* c = src->as_constant_ptr(); 1202 LIR_Opr to_reg = dest; 1203 1204 switch (c->type()) { 1205 case T_INT: 1206 { 1207 jint con = c->as_jint(); 1208 if (to_reg->is_single_cpu()) { 1209 assert(patch_code == lir_patch_none, "no patching handled here"); 1210 __ set(con, to_reg->as_register()); 1211 } else { 1212 ShouldNotReachHere(); 1213 assert(to_reg->is_single_fpu(), "wrong register kind"); 1214 1215 __ set(con, O7); 1216 Address temp_slot(SP, 0, (frame::register_save_words * wordSize) + STACK_BIAS); 1217 __ st(O7, temp_slot); 1218 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); 1219 } 1220 } 1221 break; 1222 1223 case T_LONG: 1224 { 1225 jlong con = c->as_jlong(); 1226 1227 if (to_reg->is_double_cpu()) { 1228#ifdef _LP64 1229 __ set(con, to_reg->as_register_lo()); 1230#else 1231 __ set(low(con), to_reg->as_register_lo()); 1232 __ set(high(con), to_reg->as_register_hi()); 1233#endif 1234#ifdef _LP64 1235 } else if (to_reg->is_single_cpu()) { 1236 __ set(con, to_reg->as_register()); 1237#endif 1238 } else { 1239 ShouldNotReachHere(); 1240 assert(to_reg->is_double_fpu(), "wrong register kind"); 1241 Address temp_slot_lo(SP, 0, ((frame::register_save_words ) * wordSize) + STACK_BIAS); 1242 Address temp_slot_hi(SP, 0, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); 1243 __ set(low(con), O7); 1244 __ st(O7, temp_slot_lo); 1245 __ set(high(con), O7); 1246 __ st(O7, temp_slot_hi); 1247 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); 1248 } 1249 } 1250 break; 1251 1252 case T_OBJECT: 1253 { 1254 if (patch_code == lir_patch_none) { 1255 jobject2reg(c->as_jobject(), to_reg->as_register()); 1256 } else { 1257 jobject2reg_with_patching(to_reg->as_register(), info); 1258 } 1259 } 1260 break; 1261 1262 case T_FLOAT: 1263 { 1264 address const_addr = __ float_constant(c->as_jfloat()); 1265 if (const_addr == NULL) { 1266 bailout("const section overflow"); 1267 break; 1268 } 1269 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1270 if (to_reg->is_single_fpu()) { 1271 __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); 1272 __ relocate(rspec); 1273 1274 int offset = (intx)const_addr & 0x3ff; 1275 __ ldf (FloatRegisterImpl::S, O7, offset, to_reg->as_float_reg()); 1276 1277 } else { 1278 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1279 1280 __ set((intx)const_addr, O7, rspec); 1281 load(O7, 0, to_reg->as_register(), T_INT); 1282 } 1283 } 1284 break; 1285 1286 case T_DOUBLE: 1287 { 1288 address const_addr = __ double_constant(c->as_jdouble()); 1289 if (const_addr == NULL) { 1290 bailout("const section overflow"); 1291 break; 1292 } 1293 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1294 1295 if (to_reg->is_double_fpu()) { 1296 __ sethi( (intx)const_addr & ~0x3ff, O7, true, rspec); 1297 int offset = (intx)const_addr & 0x3ff; 1298 __ relocate(rspec); 1299 __ ldf (FloatRegisterImpl::D, O7, offset, to_reg->as_double_reg()); 1300 } else { 1301 assert(to_reg->is_double_cpu(), "Must be a long register."); 1302#ifdef _LP64 1303 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); 1304#else 1305 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); 1306 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); 1307#endif 1308 } 1309 1310 } 1311 break; 1312 1313 default: 1314 ShouldNotReachHere(); 1315 } 1316} 1317 1318Address LIR_Assembler::as_Address(LIR_Address* addr) { 1319 Register reg = addr->base()->as_register(); 1320 return Address(reg, 0, addr->disp()); 1321} 1322 1323 1324void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1325 switch (type) { 1326 case T_INT: 1327 case T_FLOAT: { 1328 Register tmp = O7; 1329 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1330 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1331 __ lduw(from.base(), from.disp(), tmp); 1332 __ stw(tmp, to.base(), to.disp()); 1333 break; 1334 } 1335 case T_OBJECT: { 1336 Register tmp = O7; 1337 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1338 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1339 __ ld_ptr(from.base(), from.disp(), tmp); 1340 __ st_ptr(tmp, to.base(), to.disp()); 1341 break; 1342 } 1343 case T_LONG: 1344 case T_DOUBLE: { 1345 Register tmp = O7; 1346 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1347 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1348 __ lduw(from.base(), from.disp(), tmp); 1349 __ stw(tmp, to.base(), to.disp()); 1350 __ lduw(from.base(), from.disp() + 4, tmp); 1351 __ stw(tmp, to.base(), to.disp() + 4); 1352 break; 1353 } 1354 1355 default: 1356 ShouldNotReachHere(); 1357 } 1358} 1359 1360 1361Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1362 Address base = as_Address(addr); 1363 return Address(base.base(), 0, base.disp() + hi_word_offset_in_bytes); 1364} 1365 1366 1367Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1368 Address base = as_Address(addr); 1369 return Address(base.base(), 0, base.disp() + lo_word_offset_in_bytes); 1370} 1371 1372 1373void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1374 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { 1375 1376 LIR_Address* addr = src_opr->as_address_ptr(); 1377 LIR_Opr to_reg = dest; 1378 1379 Register src = addr->base()->as_pointer_register(); 1380 Register disp_reg = noreg; 1381 int disp_value = addr->disp(); 1382 bool needs_patching = (patch_code != lir_patch_none); 1383 1384 if (addr->base()->type() == T_OBJECT) { 1385 __ verify_oop(src); 1386 } 1387 1388 PatchingStub* patch = NULL; 1389 if (needs_patching) { 1390 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1391 assert(!to_reg->is_double_cpu() || 1392 patch_code == lir_patch_none || 1393 patch_code == lir_patch_normal, "patching doesn't match register"); 1394 } 1395 1396 if (addr->index()->is_illegal()) { 1397 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1398 if (needs_patching) { 1399 __ sethi(0, O7, true); 1400 __ add(O7, 0, O7); 1401 } else { 1402 __ set(disp_value, O7); 1403 } 1404 disp_reg = O7; 1405 } 1406 } else if (unaligned || PatchALot) { 1407 __ add(src, addr->index()->as_register(), O7); 1408 src = O7; 1409 } else { 1410 disp_reg = addr->index()->as_pointer_register(); 1411 assert(disp_value == 0, "can't handle 3 operand addresses"); 1412 } 1413 1414 // remember the offset of the load. The patching_epilog must be done 1415 // before the call to add_debug_info, otherwise the PcDescs don't get 1416 // entered in increasing order. 1417 int offset = code_offset(); 1418 1419 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1420 if (disp_reg == noreg) { 1421 offset = load(src, disp_value, to_reg, type, unaligned); 1422 } else { 1423 assert(!unaligned, "can't handle this"); 1424 offset = load(src, disp_reg, to_reg, type); 1425 } 1426 1427 if (patch != NULL) { 1428 patching_epilog(patch, patch_code, src, info); 1429 } 1430 1431 if (info != NULL) add_debug_info_for_null_check(offset, info); 1432} 1433 1434 1435void LIR_Assembler::prefetchr(LIR_Opr src) { 1436 LIR_Address* addr = src->as_address_ptr(); 1437 Address from_addr = as_Address(addr); 1438 1439 if (VM_Version::has_v9()) { 1440 __ prefetch(from_addr, Assembler::severalReads); 1441 } 1442} 1443 1444 1445void LIR_Assembler::prefetchw(LIR_Opr src) { 1446 LIR_Address* addr = src->as_address_ptr(); 1447 Address from_addr = as_Address(addr); 1448 1449 if (VM_Version::has_v9()) { 1450 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); 1451 } 1452} 1453 1454 1455void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1456 Address addr; 1457 if (src->is_single_word()) { 1458 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1459 } else if (src->is_double_word()) { 1460 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1461 } 1462 1463 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1464 load(addr.base(), addr.disp(), dest, dest->type(), unaligned); 1465} 1466 1467 1468void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1469 Address addr; 1470 if (dest->is_single_word()) { 1471 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1472 } else if (dest->is_double_word()) { 1473 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1474 } 1475 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1476 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); 1477} 1478 1479 1480void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1481 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1482 if (from_reg->is_double_fpu()) { 1483 // double to double moves 1484 assert(to_reg->is_double_fpu(), "should match"); 1485 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); 1486 } else { 1487 // float to float moves 1488 assert(to_reg->is_single_fpu(), "should match"); 1489 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); 1490 } 1491 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1492 if (from_reg->is_double_cpu()) { 1493#ifdef _LP64 1494 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); 1495#else 1496 assert(to_reg->is_double_cpu() && 1497 from_reg->as_register_hi() != to_reg->as_register_lo() && 1498 from_reg->as_register_lo() != to_reg->as_register_hi(), 1499 "should both be long and not overlap"); 1500 // long to long moves 1501 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); 1502 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); 1503#endif 1504#ifdef _LP64 1505 } else if (to_reg->is_double_cpu()) { 1506 // int to int moves 1507 __ mov(from_reg->as_register(), to_reg->as_register_lo()); 1508#endif 1509 } else { 1510 // int to int moves 1511 __ mov(from_reg->as_register(), to_reg->as_register()); 1512 } 1513 } else { 1514 ShouldNotReachHere(); 1515 } 1516 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1517 __ verify_oop(to_reg->as_register()); 1518 } 1519} 1520 1521 1522void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1523 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1524 bool unaligned) { 1525 LIR_Address* addr = dest->as_address_ptr(); 1526 1527 Register src = addr->base()->as_pointer_register(); 1528 Register disp_reg = noreg; 1529 int disp_value = addr->disp(); 1530 bool needs_patching = (patch_code != lir_patch_none); 1531 1532 if (addr->base()->is_oop_register()) { 1533 __ verify_oop(src); 1534 } 1535 1536 PatchingStub* patch = NULL; 1537 if (needs_patching) { 1538 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1539 assert(!from_reg->is_double_cpu() || 1540 patch_code == lir_patch_none || 1541 patch_code == lir_patch_normal, "patching doesn't match register"); 1542 } 1543 1544 if (addr->index()->is_illegal()) { 1545 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1546 if (needs_patching) { 1547 __ sethi(0, O7, true); 1548 __ add(O7, 0, O7); 1549 } else { 1550 __ set(disp_value, O7); 1551 } 1552 disp_reg = O7; 1553 } 1554 } else if (unaligned || PatchALot) { 1555 __ add(src, addr->index()->as_register(), O7); 1556 src = O7; 1557 } else { 1558 disp_reg = addr->index()->as_pointer_register(); 1559 assert(disp_value == 0, "can't handle 3 operand addresses"); 1560 } 1561 1562 // remember the offset of the store. The patching_epilog must be done 1563 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1564 // entered in increasing order. 1565 int offset; 1566 1567 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1568 if (disp_reg == noreg) { 1569 offset = store(from_reg, src, disp_value, type, unaligned); 1570 } else { 1571 assert(!unaligned, "can't handle this"); 1572 offset = store(from_reg, src, disp_reg, type); 1573 } 1574 1575 if (patch != NULL) { 1576 patching_epilog(patch, patch_code, src, info); 1577 } 1578 1579 if (info != NULL) add_debug_info_for_null_check(offset, info); 1580} 1581 1582 1583void LIR_Assembler::return_op(LIR_Opr result) { 1584 // the poll may need a register so just pick one that isn't the return register 1585#ifdef TIERED 1586 if (result->type_field() == LIR_OprDesc::long_type) { 1587 // Must move the result to G1 1588 // Must leave proper result in O0,O1 and G1 (TIERED only) 1589 __ sllx(I0, 32, G1); // Shift bits into high G1 1590 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) 1591 __ or3 (I1, G1, G1); // OR 64 bits into G1 1592 } 1593#endif // TIERED 1594 __ set((intptr_t)os::get_polling_page(), L0); 1595 __ relocate(relocInfo::poll_return_type); 1596 __ ld_ptr(L0, 0, G0); 1597 __ ret(); 1598 __ delayed()->restore(); 1599} 1600 1601 1602int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1603 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); 1604 if (info != NULL) { 1605 add_debug_info_for_branch(info); 1606 } else { 1607 __ relocate(relocInfo::poll_type); 1608 } 1609 1610 int offset = __ offset(); 1611 __ ld_ptr(tmp->as_register(), 0, G0); 1612 1613 return offset; 1614} 1615 1616 1617void LIR_Assembler::emit_static_call_stub() { 1618 address call_pc = __ pc(); 1619 address stub = __ start_a_stub(call_stub_size); 1620 if (stub == NULL) { 1621 bailout("static call stub overflow"); 1622 return; 1623 } 1624 1625 int start = __ offset(); 1626 __ relocate(static_stub_Relocation::spec(call_pc)); 1627 1628 __ set_oop(NULL, G5); 1629 // must be set to -1 at code generation time 1630 Address a(G3, (address)-1); 1631 __ jump_to(a, 0); 1632 __ delayed()->nop(); 1633 1634 assert(__ offset() - start <= call_stub_size, "stub too big"); 1635 __ end_a_stub(); 1636} 1637 1638 1639void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1640 if (opr1->is_single_fpu()) { 1641 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1642 } else if (opr1->is_double_fpu()) { 1643 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1644 } else if (opr1->is_single_cpu()) { 1645 if (opr2->is_constant()) { 1646 switch (opr2->as_constant_ptr()->type()) { 1647 case T_INT: 1648 { jint con = opr2->as_constant_ptr()->as_jint(); 1649 if (Assembler::is_simm13(con)) { 1650 __ cmp(opr1->as_register(), con); 1651 } else { 1652 __ set(con, O7); 1653 __ cmp(opr1->as_register(), O7); 1654 } 1655 } 1656 break; 1657 1658 case T_OBJECT: 1659 // there are only equal/notequal comparisions on objects 1660 { jobject con = opr2->as_constant_ptr()->as_jobject(); 1661 if (con == NULL) { 1662 __ cmp(opr1->as_register(), 0); 1663 } else { 1664 jobject2reg(con, O7); 1665 __ cmp(opr1->as_register(), O7); 1666 } 1667 } 1668 break; 1669 1670 default: 1671 ShouldNotReachHere(); 1672 break; 1673 } 1674 } else { 1675 if (opr2->is_address()) { 1676 LIR_Address * addr = opr2->as_address_ptr(); 1677 BasicType type = addr->type(); 1678 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1679 else __ ld(as_Address(addr), O7); 1680 __ cmp(opr1->as_register(), O7); 1681 } else { 1682 __ cmp(opr1->as_register(), opr2->as_register()); 1683 } 1684 } 1685 } else if (opr1->is_double_cpu()) { 1686 Register xlo = opr1->as_register_lo(); 1687 Register xhi = opr1->as_register_hi(); 1688 if (opr2->is_constant() && opr2->as_jlong() == 0) { 1689 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); 1690#ifdef _LP64 1691 __ orcc(xhi, G0, G0); 1692#else 1693 __ orcc(xhi, xlo, G0); 1694#endif 1695 } else if (opr2->is_register()) { 1696 Register ylo = opr2->as_register_lo(); 1697 Register yhi = opr2->as_register_hi(); 1698#ifdef _LP64 1699 __ cmp(xlo, ylo); 1700#else 1701 __ subcc(xlo, ylo, xlo); 1702 __ subccc(xhi, yhi, xhi); 1703 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 1704 __ orcc(xhi, xlo, G0); 1705 } 1706#endif 1707 } else { 1708 ShouldNotReachHere(); 1709 } 1710 } else if (opr1->is_address()) { 1711 LIR_Address * addr = opr1->as_address_ptr(); 1712 BasicType type = addr->type(); 1713 assert (opr2->is_constant(), "Checking"); 1714 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1715 else __ ld(as_Address(addr), O7); 1716 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); 1717 } else { 1718 ShouldNotReachHere(); 1719 } 1720} 1721 1722 1723void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1724 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1725 bool is_unordered_less = (code == lir_ucmp_fd2i); 1726 if (left->is_single_fpu()) { 1727 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1728 } else if (left->is_double_fpu()) { 1729 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1730 } else { 1731 ShouldNotReachHere(); 1732 } 1733 } else if (code == lir_cmp_l2i) { 1734 __ lcmp(left->as_register_hi(), left->as_register_lo(), 1735 right->as_register_hi(), right->as_register_lo(), 1736 dst->as_register()); 1737 } else { 1738 ShouldNotReachHere(); 1739 } 1740} 1741 1742 1743void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1744 1745 Assembler::Condition acond; 1746 switch (condition) { 1747 case lir_cond_equal: acond = Assembler::equal; break; 1748 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1749 case lir_cond_less: acond = Assembler::less; break; 1750 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1751 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 1752 case lir_cond_greater: acond = Assembler::greater; break; 1753 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 1754 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 1755 default: ShouldNotReachHere(); 1756 }; 1757 1758 if (opr1->is_constant() && opr1->type() == T_INT) { 1759 Register dest = result->as_register(); 1760 // load up first part of constant before branch 1761 // and do the rest in the delay slot. 1762 if (!Assembler::is_simm13(opr1->as_jint())) { 1763 __ sethi(opr1->as_jint(), dest); 1764 } 1765 } else if (opr1->is_constant()) { 1766 const2reg(opr1, result, lir_patch_none, NULL); 1767 } else if (opr1->is_register()) { 1768 reg2reg(opr1, result); 1769 } else if (opr1->is_stack()) { 1770 stack2reg(opr1, result, result->type()); 1771 } else { 1772 ShouldNotReachHere(); 1773 } 1774 Label skip; 1775 __ br(acond, false, Assembler::pt, skip); 1776 if (opr1->is_constant() && opr1->type() == T_INT) { 1777 Register dest = result->as_register(); 1778 if (Assembler::is_simm13(opr1->as_jint())) { 1779 __ delayed()->or3(G0, opr1->as_jint(), dest); 1780 } else { 1781 // the sethi has been done above, so just put in the low 10 bits 1782 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); 1783 } 1784 } else { 1785 // can't do anything useful in the delay slot 1786 __ delayed()->nop(); 1787 } 1788 if (opr2->is_constant()) { 1789 const2reg(opr2, result, lir_patch_none, NULL); 1790 } else if (opr2->is_register()) { 1791 reg2reg(opr2, result); 1792 } else if (opr2->is_stack()) { 1793 stack2reg(opr2, result, result->type()); 1794 } else { 1795 ShouldNotReachHere(); 1796 } 1797 __ bind(skip); 1798} 1799 1800 1801void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1802 assert(info == NULL, "unused on this code path"); 1803 assert(left->is_register(), "wrong items state"); 1804 assert(dest->is_register(), "wrong items state"); 1805 1806 if (right->is_register()) { 1807 if (dest->is_float_kind()) { 1808 1809 FloatRegister lreg, rreg, res; 1810 FloatRegisterImpl::Width w; 1811 if (right->is_single_fpu()) { 1812 w = FloatRegisterImpl::S; 1813 lreg = left->as_float_reg(); 1814 rreg = right->as_float_reg(); 1815 res = dest->as_float_reg(); 1816 } else { 1817 w = FloatRegisterImpl::D; 1818 lreg = left->as_double_reg(); 1819 rreg = right->as_double_reg(); 1820 res = dest->as_double_reg(); 1821 } 1822 1823 switch (code) { 1824 case lir_add: __ fadd(w, lreg, rreg, res); break; 1825 case lir_sub: __ fsub(w, lreg, rreg, res); break; 1826 case lir_mul: // fall through 1827 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; 1828 case lir_div: // fall through 1829 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; 1830 default: ShouldNotReachHere(); 1831 } 1832 1833 } else if (dest->is_double_cpu()) { 1834#ifdef _LP64 1835 Register dst_lo = dest->as_register_lo(); 1836 Register op1_lo = left->as_pointer_register(); 1837 Register op2_lo = right->as_pointer_register(); 1838 1839 switch (code) { 1840 case lir_add: 1841 __ add(op1_lo, op2_lo, dst_lo); 1842 break; 1843 1844 case lir_sub: 1845 __ sub(op1_lo, op2_lo, dst_lo); 1846 break; 1847 1848 default: ShouldNotReachHere(); 1849 } 1850#else 1851 Register op1_lo = left->as_register_lo(); 1852 Register op1_hi = left->as_register_hi(); 1853 Register op2_lo = right->as_register_lo(); 1854 Register op2_hi = right->as_register_hi(); 1855 Register dst_lo = dest->as_register_lo(); 1856 Register dst_hi = dest->as_register_hi(); 1857 1858 switch (code) { 1859 case lir_add: 1860 __ addcc(op1_lo, op2_lo, dst_lo); 1861 __ addc (op1_hi, op2_hi, dst_hi); 1862 break; 1863 1864 case lir_sub: 1865 __ subcc(op1_lo, op2_lo, dst_lo); 1866 __ subc (op1_hi, op2_hi, dst_hi); 1867 break; 1868 1869 default: ShouldNotReachHere(); 1870 } 1871#endif 1872 } else { 1873 assert (right->is_single_cpu(), "Just Checking"); 1874 1875 Register lreg = left->as_register(); 1876 Register res = dest->as_register(); 1877 Register rreg = right->as_register(); 1878 switch (code) { 1879 case lir_add: __ add (lreg, rreg, res); break; 1880 case lir_sub: __ sub (lreg, rreg, res); break; 1881 case lir_mul: __ mult (lreg, rreg, res); break; 1882 default: ShouldNotReachHere(); 1883 } 1884 } 1885 } else { 1886 assert (right->is_constant(), "must be constant"); 1887 1888 if (dest->is_single_cpu()) { 1889 Register lreg = left->as_register(); 1890 Register res = dest->as_register(); 1891 int simm13 = right->as_constant_ptr()->as_jint(); 1892 1893 switch (code) { 1894 case lir_add: __ add (lreg, simm13, res); break; 1895 case lir_sub: __ sub (lreg, simm13, res); break; 1896 case lir_mul: __ mult (lreg, simm13, res); break; 1897 default: ShouldNotReachHere(); 1898 } 1899 } else { 1900 Register lreg = left->as_pointer_register(); 1901 Register res = dest->as_register_lo(); 1902 long con = right->as_constant_ptr()->as_jlong(); 1903 assert(Assembler::is_simm13(con), "must be simm13"); 1904 1905 switch (code) { 1906 case lir_add: __ add (lreg, (int)con, res); break; 1907 case lir_sub: __ sub (lreg, (int)con, res); break; 1908 case lir_mul: __ mult (lreg, (int)con, res); break; 1909 default: ShouldNotReachHere(); 1910 } 1911 } 1912 } 1913} 1914 1915 1916void LIR_Assembler::fpop() { 1917 // do nothing 1918} 1919 1920 1921void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1922 switch (code) { 1923 case lir_sin: 1924 case lir_tan: 1925 case lir_cos: { 1926 assert(thread->is_valid(), "preserve the thread object for performance reasons"); 1927 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); 1928 break; 1929 } 1930 case lir_sqrt: { 1931 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1932 FloatRegister src_reg = value->as_double_reg(); 1933 FloatRegister dst_reg = dest->as_double_reg(); 1934 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); 1935 break; 1936 } 1937 case lir_abs: { 1938 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 1939 FloatRegister src_reg = value->as_double_reg(); 1940 FloatRegister dst_reg = dest->as_double_reg(); 1941 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); 1942 break; 1943 } 1944 default: { 1945 ShouldNotReachHere(); 1946 break; 1947 } 1948 } 1949} 1950 1951 1952void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 1953 if (right->is_constant()) { 1954 if (dest->is_single_cpu()) { 1955 int simm13 = right->as_constant_ptr()->as_jint(); 1956 switch (code) { 1957 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; 1958 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; 1959 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; 1960 default: ShouldNotReachHere(); 1961 } 1962 } else { 1963 long c = right->as_constant_ptr()->as_jlong(); 1964 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); 1965 int simm13 = (int)c; 1966 switch (code) { 1967 case lir_logic_and: 1968#ifndef _LP64 1969 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); 1970#endif 1971 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1972 break; 1973 1974 case lir_logic_or: 1975#ifndef _LP64 1976 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); 1977#endif 1978 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1979 break; 1980 1981 case lir_logic_xor: 1982#ifndef _LP64 1983 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); 1984#endif 1985 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); 1986 break; 1987 1988 default: ShouldNotReachHere(); 1989 } 1990 } 1991 } else { 1992 assert(right->is_register(), "right should be in register"); 1993 1994 if (dest->is_single_cpu()) { 1995 switch (code) { 1996 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; 1997 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; 1998 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; 1999 default: ShouldNotReachHere(); 2000 } 2001 } else { 2002#ifdef _LP64 2003 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 2004 left->as_register_lo(); 2005 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 2006 right->as_register_lo(); 2007 2008 switch (code) { 2009 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; 2010 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; 2011 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; 2012 default: ShouldNotReachHere(); 2013 } 2014#else 2015 switch (code) { 2016 case lir_logic_and: 2017 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2018 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2019 break; 2020 2021 case lir_logic_or: 2022 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2023 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2024 break; 2025 2026 case lir_logic_xor: 2027 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2028 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2029 break; 2030 2031 default: ShouldNotReachHere(); 2032 } 2033#endif 2034 } 2035 } 2036} 2037 2038 2039int LIR_Assembler::shift_amount(BasicType t) { 2040 int elem_size = type2aelembytes(t); 2041 switch (elem_size) { 2042 case 1 : return 0; 2043 case 2 : return 1; 2044 case 4 : return 2; 2045 case 8 : return 3; 2046 } 2047 ShouldNotReachHere(); 2048 return -1; 2049} 2050 2051 2052void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info, bool unwind) { 2053 assert(exceptionOop->as_register() == Oexception, "should match"); 2054 assert(unwind || exceptionPC->as_register() == Oissuing_pc, "should match"); 2055 2056 info->add_register_oop(exceptionOop); 2057 2058 if (unwind) { 2059 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 2060 __ delayed()->nop(); 2061 } else { 2062 // reuse the debug info from the safepoint poll for the throw op itself 2063 address pc_for_athrow = __ pc(); 2064 int pc_for_athrow_offset = __ offset(); 2065 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 2066 __ set((intptr_t)pc_for_athrow, Oissuing_pc, rspec); 2067 add_call_info(pc_for_athrow_offset, info); // for exception handler 2068 2069 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 2070 __ delayed()->nop(); 2071 } 2072} 2073 2074 2075void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2076 Register src = op->src()->as_register(); 2077 Register dst = op->dst()->as_register(); 2078 Register src_pos = op->src_pos()->as_register(); 2079 Register dst_pos = op->dst_pos()->as_register(); 2080 Register length = op->length()->as_register(); 2081 Register tmp = op->tmp()->as_register(); 2082 Register tmp2 = O7; 2083 2084 int flags = op->flags(); 2085 ciArrayKlass* default_type = op->expected_type(); 2086 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2087 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2088 2089 // set up the arraycopy stub information 2090 ArrayCopyStub* stub = op->stub(); 2091 2092 // always do stub if no type information is available. it's ok if 2093 // the known type isn't loaded since the code sanity checks 2094 // in debug mode and the type isn't required when we know the exact type 2095 // also check that the type is an array type. 2096 if (op->expected_type() == NULL) { 2097 __ mov(src, O0); 2098 __ mov(src_pos, O1); 2099 __ mov(dst, O2); 2100 __ mov(dst_pos, O3); 2101 __ mov(length, O4); 2102 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); 2103 2104 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); 2105 __ delayed()->nop(); 2106 __ bind(*stub->continuation()); 2107 return; 2108 } 2109 2110 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 2111 2112 // make sure src and dst are non-null and load array length 2113 if (flags & LIR_OpArrayCopy::src_null_check) { 2114 __ tst(src); 2115 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2116 __ delayed()->nop(); 2117 } 2118 2119 if (flags & LIR_OpArrayCopy::dst_null_check) { 2120 __ tst(dst); 2121 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2122 __ delayed()->nop(); 2123 } 2124 2125 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2126 // test src_pos register 2127 __ tst(src_pos); 2128 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2129 __ delayed()->nop(); 2130 } 2131 2132 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2133 // test dst_pos register 2134 __ tst(dst_pos); 2135 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2136 __ delayed()->nop(); 2137 } 2138 2139 if (flags & LIR_OpArrayCopy::length_positive_check) { 2140 // make sure length isn't negative 2141 __ tst(length); 2142 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2143 __ delayed()->nop(); 2144 } 2145 2146 if (flags & LIR_OpArrayCopy::src_range_check) { 2147 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); 2148 __ add(length, src_pos, tmp); 2149 __ cmp(tmp2, tmp); 2150 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2151 __ delayed()->nop(); 2152 } 2153 2154 if (flags & LIR_OpArrayCopy::dst_range_check) { 2155 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); 2156 __ add(length, dst_pos, tmp); 2157 __ cmp(tmp2, tmp); 2158 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2159 __ delayed()->nop(); 2160 } 2161 2162 if (flags & LIR_OpArrayCopy::type_check) { 2163 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); 2164 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2165 __ cmp(tmp, tmp2); 2166 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2167 __ delayed()->nop(); 2168 } 2169 2170#ifdef ASSERT 2171 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2172 // Sanity check the known type with the incoming class. For the 2173 // primitive case the types must match exactly with src.klass and 2174 // dst.klass each exactly matching the default type. For the 2175 // object array case, if no type check is needed then either the 2176 // dst type is exactly the expected type and the src type is a 2177 // subtype which we can't check or src is the same array as dst 2178 // but not necessarily exactly of type default_type. 2179 Label known_ok, halt; 2180 jobject2reg(op->expected_type()->encoding(), tmp); 2181 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2182 if (basic_type != T_OBJECT) { 2183 __ cmp(tmp, tmp2); 2184 __ br(Assembler::notEqual, false, Assembler::pn, halt); 2185 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); 2186 __ cmp(tmp, tmp2); 2187 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2188 __ delayed()->nop(); 2189 } else { 2190 __ cmp(tmp, tmp2); 2191 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2192 __ delayed()->cmp(src, dst); 2193 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2194 __ delayed()->nop(); 2195 } 2196 __ bind(halt); 2197 __ stop("incorrect type information in arraycopy"); 2198 __ bind(known_ok); 2199 } 2200#endif 2201 2202 int shift = shift_amount(basic_type); 2203 2204 Register src_ptr = O0; 2205 Register dst_ptr = O1; 2206 Register len = O2; 2207 2208 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2209 if (shift == 0) { 2210 __ add(src_ptr, src_pos, src_ptr); 2211 } else { 2212 __ sll(src_pos, shift, tmp); 2213 __ add(src_ptr, tmp, src_ptr); 2214 } 2215 2216 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2217 if (shift == 0) { 2218 __ add(dst_ptr, dst_pos, dst_ptr); 2219 } else { 2220 __ sll(dst_pos, shift, tmp); 2221 __ add(dst_ptr, tmp, dst_ptr); 2222 } 2223 2224 if (basic_type != T_OBJECT) { 2225 if (shift == 0) { 2226 __ mov(length, len); 2227 } else { 2228 __ sll(length, shift, len); 2229 } 2230 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); 2231 } else { 2232 // oop_arraycopy takes a length in number of elements, so don't scale it. 2233 __ mov(length, len); 2234 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); 2235 } 2236 2237 __ bind(*stub->continuation()); 2238} 2239 2240 2241void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2242 if (dest->is_single_cpu()) { 2243#ifdef _LP64 2244 if (left->type() == T_OBJECT) { 2245 switch (code) { 2246 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; 2247 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; 2248 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2249 default: ShouldNotReachHere(); 2250 } 2251 } else 2252#endif 2253 switch (code) { 2254 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; 2255 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; 2256 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2257 default: ShouldNotReachHere(); 2258 } 2259 } else { 2260#ifdef _LP64 2261 switch (code) { 2262 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2263 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2264 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2265 default: ShouldNotReachHere(); 2266 } 2267#else 2268 switch (code) { 2269 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2270 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2271 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2272 default: ShouldNotReachHere(); 2273 } 2274#endif 2275 } 2276} 2277 2278 2279void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2280#ifdef _LP64 2281 if (left->type() == T_OBJECT) { 2282 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) 2283 Register l = left->as_register(); 2284 Register d = dest->as_register_lo(); 2285 switch (code) { 2286 case lir_shl: __ sllx (l, count, d); break; 2287 case lir_shr: __ srax (l, count, d); break; 2288 case lir_ushr: __ srlx (l, count, d); break; 2289 default: ShouldNotReachHere(); 2290 } 2291 return; 2292 } 2293#endif 2294 2295 if (dest->is_single_cpu()) { 2296 count = count & 0x1F; // Java spec 2297 switch (code) { 2298 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; 2299 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; 2300 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; 2301 default: ShouldNotReachHere(); 2302 } 2303 } else if (dest->is_double_cpu()) { 2304 count = count & 63; // Java spec 2305 switch (code) { 2306 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2307 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2308 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2309 default: ShouldNotReachHere(); 2310 } 2311 } else { 2312 ShouldNotReachHere(); 2313 } 2314} 2315 2316 2317void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2318 assert(op->tmp1()->as_register() == G1 && 2319 op->tmp2()->as_register() == G3 && 2320 op->tmp3()->as_register() == G4 && 2321 op->obj()->as_register() == O0 && 2322 op->klass()->as_register() == G5, "must be"); 2323 if (op->init_check()) { 2324 __ ld(op->klass()->as_register(), 2325 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), 2326 op->tmp1()->as_register()); 2327 add_debug_info_for_null_check_here(op->stub()->info()); 2328 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); 2329 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); 2330 __ delayed()->nop(); 2331 } 2332 __ allocate_object(op->obj()->as_register(), 2333 op->tmp1()->as_register(), 2334 op->tmp2()->as_register(), 2335 op->tmp3()->as_register(), 2336 op->header_size(), 2337 op->object_size(), 2338 op->klass()->as_register(), 2339 *op->stub()->entry()); 2340 __ bind(*op->stub()->continuation()); 2341 __ verify_oop(op->obj()->as_register()); 2342} 2343 2344 2345void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2346 assert(op->tmp1()->as_register() == G1 && 2347 op->tmp2()->as_register() == G3 && 2348 op->tmp3()->as_register() == G4 && 2349 op->tmp4()->as_register() == O1 && 2350 op->klass()->as_register() == G5, "must be"); 2351 if (UseSlowPath || 2352 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2353 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2354 __ br(Assembler::always, false, Assembler::pn, *op->stub()->entry()); 2355 __ delayed()->nop(); 2356 } else { 2357 __ allocate_array(op->obj()->as_register(), 2358 op->len()->as_register(), 2359 op->tmp1()->as_register(), 2360 op->tmp2()->as_register(), 2361 op->tmp3()->as_register(), 2362 arrayOopDesc::header_size(op->type()), 2363 type2aelembytes(op->type()), 2364 op->klass()->as_register(), 2365 *op->stub()->entry()); 2366 } 2367 __ bind(*op->stub()->continuation()); 2368} 2369 2370 2371void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2372 LIR_Code code = op->code(); 2373 if (code == lir_store_check) { 2374 Register value = op->object()->as_register(); 2375 Register array = op->array()->as_register(); 2376 Register k_RInfo = op->tmp1()->as_register(); 2377 Register klass_RInfo = op->tmp2()->as_register(); 2378 Register Rtmp1 = op->tmp3()->as_register(); 2379 2380 __ verify_oop(value); 2381 2382 CodeStub* stub = op->stub(); 2383 Label done; 2384 __ cmp(value, 0); 2385 __ br(Assembler::equal, false, Assembler::pn, done); 2386 __ delayed()->nop(); 2387 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); 2388 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); 2389 2390 // get instance klass 2391 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); 2392 // get super_check_offset 2393 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL); 2394 // See if we get an immediate positive hit 2395 __ ld_ptr(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr->as_register()); 2396 __ cmp(k_RInfo, O7); 2397 __ br(Assembler::equal, false, Assembler::pn, done); 2398 __ delayed()->nop(); 2399 // check for immediate negative hit 2400 __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 2401 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); 2402 __ delayed()->nop(); 2403 // check for self 2404 __ cmp(klass_RInfo, k_RInfo); 2405 __ br(Assembler::equal, false, Assembler::pn, done); 2406 __ delayed()->nop(); 2407 2408 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); 2409 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2410 __ delayed()->nop(); 2411 __ cmp(G3, 0); 2412 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2413 __ delayed()->nop(); 2414 __ bind(done); 2415 } else if (op->code() == lir_checkcast) { 2416 // we always need a stub for the failure case. 2417 CodeStub* stub = op->stub(); 2418 Register obj = op->object()->as_register(); 2419 Register k_RInfo = op->tmp1()->as_register(); 2420 Register klass_RInfo = op->tmp2()->as_register(); 2421 Register dst = op->result_opr()->as_register(); 2422 Register Rtmp1 = op->tmp3()->as_register(); 2423 ciKlass* k = op->klass(); 2424 2425 if (obj == k_RInfo) { 2426 k_RInfo = klass_RInfo; 2427 klass_RInfo = obj; 2428 } 2429 if (op->profiled_method() != NULL) { 2430 ciMethod* method = op->profiled_method(); 2431 int bci = op->profiled_bci(); 2432 2433 // We need two temporaries to perform this operation on SPARC, 2434 // so to keep things simple we perform a redundant test here 2435 Label profile_done; 2436 __ cmp(obj, 0); 2437 __ br(Assembler::notEqual, false, Assembler::pn, profile_done); 2438 __ delayed()->nop(); 2439 // Object is null; update methodDataOop 2440 ciMethodData* md = method->method_data(); 2441 if (md == NULL) { 2442 bailout("out of memory building methodDataOop"); 2443 return; 2444 } 2445 ciProfileData* data = md->bci_to_data(bci); 2446 assert(data != NULL, "need data for checkcast"); 2447 assert(data->is_BitData(), "need BitData for checkcast"); 2448 Register mdo = k_RInfo; 2449 Register data_val = Rtmp1; 2450 jobject2reg(md->encoding(), mdo); 2451 2452 int mdo_offset_bias = 0; 2453 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2454 // The offset is large so bias the mdo by the base of the slot so 2455 // that the ld can use simm13s to reference the slots of the data 2456 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2457 __ set(mdo_offset_bias, data_val); 2458 __ add(mdo, data_val, mdo); 2459 } 2460 2461 2462 Address flags_addr(mdo, 0, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2463 __ ldub(flags_addr, data_val); 2464 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2465 __ stb(data_val, flags_addr); 2466 __ bind(profile_done); 2467 } 2468 2469 Label done; 2470 // patching may screw with our temporaries on sparc, 2471 // so let's do it before loading the class 2472 if (k->is_loaded()) { 2473 jobject2reg(k->encoding(), k_RInfo); 2474 } else { 2475 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 2476 } 2477 assert(obj != k_RInfo, "must be different"); 2478 __ cmp(obj, 0); 2479 __ br(Assembler::equal, false, Assembler::pn, done); 2480 __ delayed()->nop(); 2481 2482 // get object class 2483 // not a safepoint as obj null check happens earlier 2484 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); 2485 if (op->fast_check()) { 2486 assert_different_registers(klass_RInfo, k_RInfo); 2487 __ cmp(k_RInfo, klass_RInfo); 2488 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2489 __ delayed()->nop(); 2490 __ bind(done); 2491 } else { 2492 if (k->is_loaded()) { 2493 load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL); 2494 2495 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 2496 // See if we get an immediate positive hit 2497 __ cmp(Rtmp1, k_RInfo ); 2498 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); 2499 __ delayed()->nop(); 2500 } else { 2501 // See if we get an immediate positive hit 2502 assert_different_registers(Rtmp1, k_RInfo, klass_RInfo); 2503 __ cmp(Rtmp1, k_RInfo ); 2504 __ br(Assembler::equal, false, Assembler::pn, done); 2505 // check for self 2506 __ delayed()->cmp(klass_RInfo, k_RInfo); 2507 __ br(Assembler::equal, false, Assembler::pn, done); 2508 __ delayed()->nop(); 2509 2510 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); 2511 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2512 __ delayed()->nop(); 2513 __ cmp(G3, 0); 2514 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2515 __ delayed()->nop(); 2516 } 2517 __ bind(done); 2518 } else { 2519 assert_different_registers(Rtmp1, klass_RInfo, k_RInfo); 2520 2521 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), Rtmp1, T_INT, NULL); 2522 // See if we get an immediate positive hit 2523 load(klass_RInfo, Rtmp1, FrameMap::O7_oop_opr, T_OBJECT); 2524 __ cmp(k_RInfo, O7); 2525 __ br(Assembler::equal, false, Assembler::pn, done); 2526 __ delayed()->nop(); 2527 // check for immediate negative hit 2528 __ cmp(Rtmp1, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 2529 __ br(Assembler::notEqual, false, Assembler::pn, *stub->entry()); 2530 // check for self 2531 __ delayed()->cmp(klass_RInfo, k_RInfo); 2532 __ br(Assembler::equal, false, Assembler::pn, done); 2533 __ delayed()->nop(); 2534 2535 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); 2536 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2537 __ delayed()->nop(); 2538 __ cmp(G3, 0); 2539 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2540 __ delayed()->nop(); 2541 __ bind(done); 2542 } 2543 2544 } 2545 __ mov(obj, dst); 2546 } else if (code == lir_instanceof) { 2547 Register obj = op->object()->as_register(); 2548 Register k_RInfo = op->tmp1()->as_register(); 2549 Register klass_RInfo = op->tmp2()->as_register(); 2550 Register dst = op->result_opr()->as_register(); 2551 Register Rtmp1 = op->tmp3()->as_register(); 2552 ciKlass* k = op->klass(); 2553 2554 Label done; 2555 if (obj == k_RInfo) { 2556 k_RInfo = klass_RInfo; 2557 klass_RInfo = obj; 2558 } 2559 // patching may screw with our temporaries on sparc, 2560 // so let's do it before loading the class 2561 if (k->is_loaded()) { 2562 jobject2reg(k->encoding(), k_RInfo); 2563 } else { 2564 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 2565 } 2566 assert(obj != k_RInfo, "must be different"); 2567 __ cmp(obj, 0); 2568 __ br(Assembler::equal, true, Assembler::pn, done); 2569 __ delayed()->set(0, dst); 2570 2571 // get object class 2572 // not a safepoint as obj null check happens earlier 2573 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); 2574 if (op->fast_check()) { 2575 __ cmp(k_RInfo, klass_RInfo); 2576 __ br(Assembler::equal, true, Assembler::pt, done); 2577 __ delayed()->set(1, dst); 2578 __ set(0, dst); 2579 __ bind(done); 2580 } else { 2581 if (k->is_loaded()) { 2582 assert_different_registers(Rtmp1, klass_RInfo, k_RInfo); 2583 load(klass_RInfo, k->super_check_offset(), Rtmp1, T_OBJECT, NULL); 2584 2585 if (sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes() != k->super_check_offset()) { 2586 // See if we get an immediate positive hit 2587 __ cmp(Rtmp1, k_RInfo ); 2588 __ br(Assembler::equal, true, Assembler::pt, done); 2589 __ delayed()->set(1, dst); 2590 __ set(0, dst); 2591 __ bind(done); 2592 } else { 2593 // See if we get an immediate positive hit 2594 assert_different_registers(Rtmp1, k_RInfo, klass_RInfo); 2595 __ cmp(Rtmp1, k_RInfo ); 2596 __ br(Assembler::equal, true, Assembler::pt, done); 2597 __ delayed()->set(1, dst); 2598 // check for self 2599 __ cmp(klass_RInfo, k_RInfo); 2600 __ br(Assembler::equal, true, Assembler::pt, done); 2601 __ delayed()->set(1, dst); 2602 2603 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); 2604 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2605 __ delayed()->nop(); 2606 __ mov(G3, dst); 2607 __ bind(done); 2608 } 2609 } else { 2610 assert(dst != klass_RInfo && dst != k_RInfo, "need 3 registers"); 2611 2612 load(k_RInfo, sizeof(oopDesc) + Klass::super_check_offset_offset_in_bytes(), dst, T_INT, NULL); 2613 // See if we get an immediate positive hit 2614 load(klass_RInfo, dst, FrameMap::O7_oop_opr, T_OBJECT); 2615 __ cmp(k_RInfo, O7); 2616 __ br(Assembler::equal, true, Assembler::pt, done); 2617 __ delayed()->set(1, dst); 2618 // check for immediate negative hit 2619 __ cmp(dst, sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()); 2620 __ br(Assembler::notEqual, true, Assembler::pt, done); 2621 __ delayed()->set(0, dst); 2622 // check for self 2623 __ cmp(klass_RInfo, k_RInfo); 2624 __ br(Assembler::equal, true, Assembler::pt, done); 2625 __ delayed()->set(1, dst); 2626 2627 // assert(sub.is_same(FrameMap::G3_RInfo) && super.is_same(FrameMap::G1_RInfo), "incorrect call setup"); 2628 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2629 __ delayed()->nop(); 2630 __ mov(G3, dst); 2631 __ bind(done); 2632 } 2633 } 2634 } else { 2635 ShouldNotReachHere(); 2636 } 2637 2638} 2639 2640 2641void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2642 if (op->code() == lir_cas_long) { 2643 assert(VM_Version::supports_cx8(), "wrong machine"); 2644 Register addr = op->addr()->as_pointer_register(); 2645 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2646 Register cmp_value_hi = op->cmp_value()->as_register_hi(); 2647 Register new_value_lo = op->new_value()->as_register_lo(); 2648 Register new_value_hi = op->new_value()->as_register_hi(); 2649 Register t1 = op->tmp1()->as_register(); 2650 Register t2 = op->tmp2()->as_register(); 2651#ifdef _LP64 2652 __ mov(cmp_value_lo, t1); 2653 __ mov(new_value_lo, t2); 2654#else 2655 // move high and low halves of long values into single registers 2656 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg 2657 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half 2658 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value 2659 __ sllx(new_value_hi, 32, t2); 2660 __ srl(new_value_lo, 0, new_value_lo); 2661 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap 2662#endif 2663 // perform the compare and swap operation 2664 __ casx(addr, t1, t2); 2665 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2666 // overwritten with the original value in "addr" and will be equal to t1. 2667 __ cmp(t1, t2); 2668 2669 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2670 Register addr = op->addr()->as_pointer_register(); 2671 Register cmp_value = op->cmp_value()->as_register(); 2672 Register new_value = op->new_value()->as_register(); 2673 Register t1 = op->tmp1()->as_register(); 2674 Register t2 = op->tmp2()->as_register(); 2675 __ mov(cmp_value, t1); 2676 __ mov(new_value, t2); 2677#ifdef _LP64 2678 if (op->code() == lir_cas_obj) { 2679 __ casx(addr, t1, t2); 2680 } else 2681#endif 2682 { 2683 __ cas(addr, t1, t2); 2684 } 2685 __ cmp(t1, t2); 2686 } else { 2687 Unimplemented(); 2688 } 2689} 2690 2691void LIR_Assembler::set_24bit_FPU() { 2692 Unimplemented(); 2693} 2694 2695 2696void LIR_Assembler::reset_FPU() { 2697 Unimplemented(); 2698} 2699 2700 2701void LIR_Assembler::breakpoint() { 2702 __ breakpoint_trap(); 2703} 2704 2705 2706void LIR_Assembler::push(LIR_Opr opr) { 2707 Unimplemented(); 2708} 2709 2710 2711void LIR_Assembler::pop(LIR_Opr opr) { 2712 Unimplemented(); 2713} 2714 2715 2716void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2717 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2718 Register dst = dst_opr->as_register(); 2719 Register reg = mon_addr.base(); 2720 int offset = mon_addr.disp(); 2721 // compute pointer to BasicLock 2722 if (mon_addr.is_simm13()) { 2723 __ add(reg, offset, dst); 2724 } else { 2725 __ set(offset, dst); 2726 __ add(dst, reg, dst); 2727 } 2728} 2729 2730 2731void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2732 Register obj = op->obj_opr()->as_register(); 2733 Register hdr = op->hdr_opr()->as_register(); 2734 Register lock = op->lock_opr()->as_register(); 2735 2736 // obj may not be an oop 2737 if (op->code() == lir_lock) { 2738 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2739 if (UseFastLocking) { 2740 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2741 // add debug info for NullPointerException only if one is possible 2742 if (op->info() != NULL) { 2743 add_debug_info_for_null_check_here(op->info()); 2744 } 2745 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2746 } else { 2747 // always do slow locking 2748 // note: the slow locking code could be inlined here, however if we use 2749 // slow locking, speed doesn't matter anyway and this solution is 2750 // simpler and requires less duplicated code - additionally, the 2751 // slow locking code is the same in either case which simplifies 2752 // debugging 2753 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2754 __ delayed()->nop(); 2755 } 2756 } else { 2757 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2758 if (UseFastLocking) { 2759 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2760 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2761 } else { 2762 // always do slow unlocking 2763 // note: the slow unlocking code could be inlined here, however if we use 2764 // slow unlocking, speed doesn't matter anyway and this solution is 2765 // simpler and requires less duplicated code - additionally, the 2766 // slow unlocking code is the same in either case which simplifies 2767 // debugging 2768 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2769 __ delayed()->nop(); 2770 } 2771 } 2772 __ bind(*op->stub()->continuation()); 2773} 2774 2775 2776void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2777 ciMethod* method = op->profiled_method(); 2778 int bci = op->profiled_bci(); 2779 2780 // Update counter for all call types 2781 ciMethodData* md = method->method_data(); 2782 if (md == NULL) { 2783 bailout("out of memory building methodDataOop"); 2784 return; 2785 } 2786 ciProfileData* data = md->bci_to_data(bci); 2787 assert(data->is_CounterData(), "need CounterData for calls"); 2788 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2789 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2790 Register mdo = op->mdo()->as_register(); 2791 Register tmp1 = op->tmp1()->as_register(); 2792 jobject2reg(md->encoding(), mdo); 2793 int mdo_offset_bias = 0; 2794 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2795 data->size_in_bytes())) { 2796 // The offset is large so bias the mdo by the base of the slot so 2797 // that the ld can use simm13s to reference the slots of the data 2798 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2799 __ set(mdo_offset_bias, O7); 2800 __ add(mdo, O7, mdo); 2801 } 2802 2803 Address counter_addr(mdo, 0, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2804 __ lduw(counter_addr, tmp1); 2805 __ add(tmp1, DataLayout::counter_increment, tmp1); 2806 __ stw(tmp1, counter_addr); 2807 Bytecodes::Code bc = method->java_code_at_bci(bci); 2808 // Perform additional virtual call profiling for invokevirtual and 2809 // invokeinterface bytecodes 2810 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 2811 Tier1ProfileVirtualCalls) { 2812 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2813 Register recv = op->recv()->as_register(); 2814 assert_different_registers(mdo, tmp1, recv); 2815 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2816 ciKlass* known_klass = op->known_holder(); 2817 if (Tier1OptimizeVirtualCallProfiling && known_klass != NULL) { 2818 // We know the type that will be seen at this call site; we can 2819 // statically update the methodDataOop rather than needing to do 2820 // dynamic tests on the receiver type 2821 2822 // NOTE: we should probably put a lock around this search to 2823 // avoid collisions by concurrent compilations 2824 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2825 uint i; 2826 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2827 ciKlass* receiver = vc_data->receiver(i); 2828 if (known_klass->equals(receiver)) { 2829 Address data_addr(mdo, 0, md->byte_offset_of_slot(data, 2830 VirtualCallData::receiver_count_offset(i)) - 2831 mdo_offset_bias); 2832 __ lduw(data_addr, tmp1); 2833 __ add(tmp1, DataLayout::counter_increment, tmp1); 2834 __ stw(tmp1, data_addr); 2835 return; 2836 } 2837 } 2838 2839 // Receiver type not found in profile data; select an empty slot 2840 2841 // Note that this is less efficient than it should be because it 2842 // always does a write to the receiver part of the 2843 // VirtualCallData rather than just the first time 2844 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2845 ciKlass* receiver = vc_data->receiver(i); 2846 if (receiver == NULL) { 2847 Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2848 mdo_offset_bias); 2849 jobject2reg(known_klass->encoding(), tmp1); 2850 __ st_ptr(tmp1, recv_addr); 2851 Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2852 mdo_offset_bias); 2853 __ lduw(data_addr, tmp1); 2854 __ add(tmp1, DataLayout::counter_increment, tmp1); 2855 __ stw(tmp1, data_addr); 2856 return; 2857 } 2858 } 2859 } else { 2860 load(Address(recv, 0, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); 2861 Label update_done; 2862 uint i; 2863 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2864 Label next_test; 2865 // See if the receiver is receiver[n]. 2866 Address receiver_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2867 mdo_offset_bias); 2868 __ ld_ptr(receiver_addr, tmp1); 2869 __ verify_oop(tmp1); 2870 __ cmp(recv, tmp1); 2871 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); 2872 __ delayed()->nop(); 2873 Address data_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2874 mdo_offset_bias); 2875 __ lduw(data_addr, tmp1); 2876 __ add(tmp1, DataLayout::counter_increment, tmp1); 2877 __ stw(tmp1, data_addr); 2878 __ br(Assembler::always, false, Assembler::pt, update_done); 2879 __ delayed()->nop(); 2880 __ bind(next_test); 2881 } 2882 2883 // Didn't find receiver; find next empty slot and fill it in 2884 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2885 Label next_test; 2886 Address recv_addr(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2887 mdo_offset_bias); 2888 load(recv_addr, tmp1, T_OBJECT); 2889 __ tst(tmp1); 2890 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); 2891 __ delayed()->nop(); 2892 __ st_ptr(recv, recv_addr); 2893 __ set(DataLayout::counter_increment, tmp1); 2894 __ st_ptr(tmp1, Address(mdo, 0, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2895 mdo_offset_bias)); 2896 if (i < (VirtualCallData::row_limit() - 1)) { 2897 __ br(Assembler::always, false, Assembler::pt, update_done); 2898 __ delayed()->nop(); 2899 } 2900 __ bind(next_test); 2901 } 2902 2903 __ bind(update_done); 2904 } 2905 } 2906} 2907 2908 2909void LIR_Assembler::align_backward_branch_target() { 2910 __ align(16); 2911} 2912 2913 2914void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2915 // make sure we are expecting a delay 2916 // this has the side effect of clearing the delay state 2917 // so we can use _masm instead of _masm->delayed() to do the 2918 // code generation. 2919 __ delayed(); 2920 2921 // make sure we only emit one instruction 2922 int offset = code_offset(); 2923 op->delay_op()->emit_code(this); 2924#ifdef ASSERT 2925 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { 2926 op->delay_op()->print(); 2927 } 2928 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, 2929 "only one instruction can go in a delay slot"); 2930#endif 2931 2932 // we may also be emitting the call info for the instruction 2933 // which we are the delay slot of. 2934 CodeEmitInfo * call_info = op->call_info(); 2935 if (call_info) { 2936 add_call_info(code_offset(), call_info); 2937 } 2938 2939 if (VerifyStackAtCalls) { 2940 _masm->sub(FP, SP, O7); 2941 _masm->cmp(O7, initial_frame_size_in_bytes()); 2942 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); 2943 } 2944} 2945 2946 2947void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 2948 assert(left->is_register(), "can only handle registers"); 2949 2950 if (left->is_single_cpu()) { 2951 __ neg(left->as_register(), dest->as_register()); 2952 } else if (left->is_single_fpu()) { 2953 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); 2954 } else if (left->is_double_fpu()) { 2955 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); 2956 } else { 2957 assert (left->is_double_cpu(), "Must be a long"); 2958 Register Rlow = left->as_register_lo(); 2959 Register Rhi = left->as_register_hi(); 2960#ifdef _LP64 2961 __ sub(G0, Rlow, dest->as_register_lo()); 2962#else 2963 __ subcc(G0, Rlow, dest->as_register_lo()); 2964 __ subc (G0, Rhi, dest->as_register_hi()); 2965#endif 2966 } 2967} 2968 2969 2970void LIR_Assembler::fxch(int i) { 2971 Unimplemented(); 2972} 2973 2974void LIR_Assembler::fld(int i) { 2975 Unimplemented(); 2976} 2977 2978void LIR_Assembler::ffree(int i) { 2979 Unimplemented(); 2980} 2981 2982void LIR_Assembler::rt_call(LIR_Opr result, address dest, 2983 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 2984 2985 // if tmp is invalid, then the function being called doesn't destroy the thread 2986 if (tmp->is_valid()) { 2987 __ save_thread(tmp->as_register()); 2988 } 2989 __ call(dest, relocInfo::runtime_call_type); 2990 __ delayed()->nop(); 2991 if (info != NULL) { 2992 add_call_info_here(info); 2993 } 2994 if (tmp->is_valid()) { 2995 __ restore_thread(tmp->as_register()); 2996 } 2997 2998#ifdef ASSERT 2999 __ verify_thread(); 3000#endif // ASSERT 3001} 3002 3003 3004void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3005#ifdef _LP64 3006 ShouldNotReachHere(); 3007#endif 3008 3009 NEEDS_CLEANUP; 3010 if (type == T_LONG) { 3011 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); 3012 3013 // (extended to allow indexed as well as constant displaced for JSR-166) 3014 Register idx = noreg; // contains either constant offset or index 3015 3016 int disp = mem_addr->disp(); 3017 if (mem_addr->index() == LIR_OprFact::illegalOpr) { 3018 if (!Assembler::is_simm13(disp)) { 3019 idx = O7; 3020 __ set(disp, idx); 3021 } 3022 } else { 3023 assert(disp == 0, "not both indexed and disp"); 3024 idx = mem_addr->index()->as_register(); 3025 } 3026 3027 int null_check_offset = -1; 3028 3029 Register base = mem_addr->base()->as_register(); 3030 if (src->is_register() && dest->is_address()) { 3031 // G4 is high half, G5 is low half 3032 if (VM_Version::v9_instructions_work()) { 3033 // clear the top bits of G5, and scale up G4 3034 __ srl (src->as_register_lo(), 0, G5); 3035 __ sllx(src->as_register_hi(), 32, G4); 3036 // combine the two halves into the 64 bits of G4 3037 __ or3(G4, G5, G4); 3038 null_check_offset = __ offset(); 3039 if (idx == noreg) { 3040 __ stx(G4, base, disp); 3041 } else { 3042 __ stx(G4, base, idx); 3043 } 3044 } else { 3045 __ mov (src->as_register_hi(), G4); 3046 __ mov (src->as_register_lo(), G5); 3047 null_check_offset = __ offset(); 3048 if (idx == noreg) { 3049 __ std(G4, base, disp); 3050 } else { 3051 __ std(G4, base, idx); 3052 } 3053 } 3054 } else if (src->is_address() && dest->is_register()) { 3055 null_check_offset = __ offset(); 3056 if (VM_Version::v9_instructions_work()) { 3057 if (idx == noreg) { 3058 __ ldx(base, disp, G5); 3059 } else { 3060 __ ldx(base, idx, G5); 3061 } 3062 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi 3063 __ mov (G5, dest->as_register_lo()); // copy low half into lo 3064 } else { 3065 if (idx == noreg) { 3066 __ ldd(base, disp, G4); 3067 } else { 3068 __ ldd(base, idx, G4); 3069 } 3070 // G4 is high half, G5 is low half 3071 __ mov (G4, dest->as_register_hi()); 3072 __ mov (G5, dest->as_register_lo()); 3073 } 3074 } else { 3075 Unimplemented(); 3076 } 3077 if (info != NULL) { 3078 add_debug_info_for_null_check(null_check_offset, info); 3079 } 3080 3081 } else { 3082 // use normal move for all other volatiles since they don't need 3083 // special handling to remain atomic. 3084 move_op(src, dest, type, lir_patch_none, info, false, false); 3085 } 3086} 3087 3088void LIR_Assembler::membar() { 3089 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode 3090 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3091} 3092 3093void LIR_Assembler::membar_acquire() { 3094 // no-op on TSO 3095} 3096 3097void LIR_Assembler::membar_release() { 3098 // no-op on TSO 3099} 3100 3101// Macro to Pack two sequential registers containing 32 bit values 3102// into a single 64 bit register. 3103// rs and rs->successor() are packed into rd 3104// rd and rs may be the same register. 3105// Note: rs and rs->successor() are destroyed. 3106void LIR_Assembler::pack64( Register rs, Register rd ) { 3107 __ sllx(rs, 32, rs); 3108 __ srl(rs->successor(), 0, rs->successor()); 3109 __ or3(rs, rs->successor(), rd); 3110} 3111 3112// Macro to unpack a 64 bit value in a register into 3113// two sequential registers. 3114// rd is unpacked into rd and rd->successor() 3115void LIR_Assembler::unpack64( Register rd ) { 3116 __ mov(rd, rd->successor()); 3117 __ srax(rd, 32, rd); 3118 __ sra(rd->successor(), 0, rd->successor()); 3119} 3120 3121 3122void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 3123 LIR_Address* addr = addr_opr->as_address_ptr(); 3124 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); 3125 __ add(addr->base()->as_register(), addr->disp(), dest->as_register()); 3126} 3127 3128 3129void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3130 assert(result_reg->is_register(), "check"); 3131 __ mov(G2_thread, result_reg->as_register()); 3132} 3133 3134 3135void LIR_Assembler::peephole(LIR_List* lir) { 3136 LIR_OpList* inst = lir->instructions_list(); 3137 for (int i = 0; i < inst->length(); i++) { 3138 LIR_Op* op = inst->at(i); 3139 switch (op->code()) { 3140 case lir_cond_float_branch: 3141 case lir_branch: { 3142 LIR_OpBranch* branch = op->as_OpBranch(); 3143 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); 3144 LIR_Op* delay_op = NULL; 3145 // we'd like to be able to pull following instructions into 3146 // this slot but we don't know enough to do it safely yet so 3147 // only optimize block to block control flow. 3148 if (LIRFillDelaySlots && branch->block()) { 3149 LIR_Op* prev = inst->at(i - 1); 3150 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { 3151 // swap previous instruction into delay slot 3152 inst->at_put(i - 1, op); 3153 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3154#ifndef PRODUCT 3155 if (LIRTracePeephole) { 3156 tty->print_cr("delayed"); 3157 inst->at(i - 1)->print(); 3158 inst->at(i)->print(); 3159 } 3160#endif 3161 continue; 3162 } 3163 } 3164 3165 if (!delay_op) { 3166 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); 3167 } 3168 inst->insert_before(i + 1, delay_op); 3169 break; 3170 } 3171 case lir_static_call: 3172 case lir_virtual_call: 3173 case lir_icvirtual_call: 3174 case lir_optvirtual_call: { 3175 LIR_Op* delay_op = NULL; 3176 LIR_Op* prev = inst->at(i - 1); 3177 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && 3178 (op->code() != lir_virtual_call || 3179 !prev->result_opr()->is_single_cpu() || 3180 prev->result_opr()->as_register() != O0) && 3181 LIR_Assembler::is_single_instruction(prev)) { 3182 // Only moves without info can be put into the delay slot. 3183 // Also don't allow the setup of the receiver in the delay 3184 // slot for vtable calls. 3185 inst->at_put(i - 1, op); 3186 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3187#ifndef PRODUCT 3188 if (LIRTracePeephole) { 3189 tty->print_cr("delayed"); 3190 inst->at(i - 1)->print(); 3191 inst->at(i)->print(); 3192 } 3193#endif 3194 continue; 3195 } 3196 3197 if (!delay_op) { 3198 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); 3199 inst->insert_before(i + 1, delay_op); 3200 } 3201 break; 3202 } 3203 } 3204 } 3205} 3206 3207 3208 3209 3210#undef __ 3211