1/* 2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_S390_VM_ASSEMBLER_S390_HPP 27#define CPU_S390_VM_ASSEMBLER_S390_HPP 28 29#undef LUCY_DBG 30 31// Immediate is an abstraction to represent the various immediate 32// operands which exist on z/Architecture. Neither this class nor 33// instances hereof have an own state. It consists of methods only. 34class Immediate VALUE_OBJ_CLASS_SPEC { 35 36 public: 37 static bool is_simm(int64_t x, unsigned int nbits) { 38 // nbits < 2 --> false 39 // nbits >= 64 --> true 40 assert(2 <= nbits && nbits < 64, "Don't call, use statically known result."); 41 const int64_t min = -(1L << (nbits-1)); 42 const int64_t maxplus1 = (1L << (nbits-1)); 43 return min <= x && x < maxplus1; 44 } 45 static bool is_simm32(int64_t x) { 46 return is_simm(x, 32); 47 } 48 static bool is_simm20(int64_t x) { 49 return is_simm(x, 20); 50 } 51 static bool is_simm16(int64_t x) { 52 return is_simm(x, 16); 53 } 54 static bool is_simm8(int64_t x) { 55 return is_simm(x, 8); 56 } 57 58 // Test if x is within signed immediate range for nbits. 59 static bool is_uimm(int64_t x, unsigned int nbits) { 60 // nbits == 0 --> false 61 // nbits >= 64 --> true 62 assert(1 <= nbits && nbits < 64, "don't call, use statically known result"); 63 const uint64_t xu = (unsigned long)x; 64 const uint64_t maxplus1 = 1UL << nbits; 65 return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large. 66 } 67 static bool is_uimm32(int64_t x) { 68 return is_uimm(x, 32); 69 } 70 static bool is_uimm16(int64_t x) { 71 return is_uimm(x, 16); 72 } 73 static bool is_uimm12(int64_t x) { 74 return is_uimm(x, 12); 75 } 76 static bool is_uimm8(int64_t x) { 77 return is_uimm(x, 8); 78 } 79}; 80 81// Displacement is an abstraction to represent the various 82// displacements which exist with addresses on z/ArchiTecture. 83// Neither this class nor instances hereof have an own state. It 84// consists of methods only. 85class Displacement VALUE_OBJ_CLASS_SPEC { 86 87 public: // These tests are used outside the (Macro)Assembler world, e.g. in ad-file. 88 89 static bool is_longDisp(int64_t x) { // Fits in a 20-bit displacement field. 90 return Immediate::is_simm20(x); 91 } 92 static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field. 93 return Immediate::is_uimm12(x); 94 } 95 static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints. 96 return is_longDisp(x); 97 } 98}; 99 100// RelAddr is an abstraction to represent relative addresses in the 101// form they are used on z/Architecture for instructions which access 102// their operand with pc-relative addresses. Neither this class nor 103// instances hereof have an own state. It consists of methods only. 104class RelAddr VALUE_OBJ_CLASS_SPEC { 105 106 private: // No public use at all. Solely for (Macro)Assembler. 107 108 static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) { 109 // Guard against illegal branch targets, e.g. -1. Occurrences in 110 // CompiledStaticCall and ad-file. Do not assert (it's a test 111 // function!). Just return false in case of illegal operands. 112 if ((((uint64_t)target) & 0x0001L) != 0) return false; 113 if ((((uint64_t)pc) & 0x0001L) != 0) return false; 114 115 if (shortForm) { 116 return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes. 117 } else { 118 return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes. 119 } 120 } 121 122 static bool is_in_range_of_RelAddr16(address target, address pc) { 123 return is_in_range_of_RelAddr(target, pc, true); 124 } 125 static bool is_in_range_of_RelAddr16(ptrdiff_t distance) { 126 return is_in_range_of_RelAddr((address)distance, 0, true); 127 } 128 129 static bool is_in_range_of_RelAddr32(address target, address pc) { 130 return is_in_range_of_RelAddr(target, pc, false); 131 } 132 static bool is_in_range_of_RelAddr32(ptrdiff_t distance) { 133 return is_in_range_of_RelAddr((address)distance, 0, false); 134 } 135 136 static int pcrel_off(address target, address pc, bool shortForm) { 137 assert(((uint64_t)target & 0x0001L) == 0, "target of a relative address must be aligned"); 138 assert(((uint64_t)pc & 0x0001L) == 0, "origin of a relative address must be aligned"); 139 140 if ((target == NULL) || (target == pc)) { 141 return 0; // Yet unknown branch destination. 142 } else { 143 guarantee(is_in_range_of_RelAddr(target, pc, shortForm), "target not within reach"); 144 return (int)((target - pc)>>1); 145 } 146 } 147 148 static int pcrel_off16(address target, address pc) { 149 return pcrel_off(target, pc, true); 150 } 151 static int pcrel_off16(ptrdiff_t distance) { 152 return pcrel_off((address)distance, 0, true); 153 } 154 155 static int pcrel_off32(address target, address pc) { 156 return pcrel_off(target, pc, false); 157 } 158 static int pcrel_off32(ptrdiff_t distance) { 159 return pcrel_off((address)distance, 0, false); 160 } 161 162 static ptrdiff_t inv_pcrel_off16(int offset) { 163 return ((ptrdiff_t)offset)<<1; 164 } 165 166 static ptrdiff_t inv_pcrel_off32(int offset) { 167 return ((ptrdiff_t)offset)<<1; 168 } 169 170 friend class Assembler; 171 friend class MacroAssembler; 172 friend class NativeGeneralJump; 173}; 174 175// Address is an abstraction used to represent a memory location 176// as passed to Z assembler instructions. 177// 178// Note: A register location is represented via a Register, not 179// via an address for efficiency & simplicity reasons. 180class Address VALUE_OBJ_CLASS_SPEC { 181 private: 182 Register _base; // Base register. 183 Register _index; // Index register 184 intptr_t _disp; // Constant displacement. 185 186 public: 187 Address() : 188 _base(noreg), 189 _index(noreg), 190 _disp(0) {} 191 192 Address(Register base, Register index, intptr_t disp = 0) : 193 _base(base), 194 _index(index), 195 _disp(disp) {} 196 197 Address(Register base, intptr_t disp = 0) : 198 _base(base), 199 _index(noreg), 200 _disp(disp) {} 201 202 Address(Register base, RegisterOrConstant roc, intptr_t disp = 0) : 203 _base(base), 204 _index(noreg), 205 _disp(disp) { 206 if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register(); 207 } 208 209#ifdef ASSERT 210 // ByteSize is only a class when ASSERT is defined, otherwise it's an int. 211 Address(Register base, ByteSize disp) : 212 _base(base), 213 _index(noreg), 214 _disp(in_bytes(disp)) {} 215 216 Address(Register base, Register index, ByteSize disp) : 217 _base(base), 218 _index(index), 219 _disp(in_bytes(disp)) {} 220#endif 221 222 // Aborts if disp is a register and base and index are set already. 223 Address plus_disp(RegisterOrConstant disp) const { 224 Address a = (*this); 225 a._disp += disp.constant_or_zero(); 226 if (disp.is_register()) { 227 if (a._index == noreg) { 228 a._index = disp.as_register(); 229 } else { 230 guarantee(_base == noreg, "can not encode"); a._base = disp.as_register(); 231 } 232 } 233 return a; 234 } 235 236 // A call to this is generated by adlc for replacement variable $xxx$$Address. 237 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 238 239 bool is_same_address(Address a) const { 240 return _base == a._base && _index == a._index && _disp == a._disp; 241 } 242 243 // testers 244 bool has_base() const { return _base != noreg; } 245 bool has_index() const { return _index != noreg; } 246 bool has_disp() const { return true; } // There is no "invalid" value. 247 248 bool is_disp12() const { return Immediate::is_uimm12(disp()); } 249 bool is_disp20() const { return Immediate::is_simm20(disp()); } 250 bool is_RSform() { return has_base() && !has_index() && is_disp12(); } 251 bool is_RSYform() { return has_base() && !has_index() && is_disp20(); } 252 bool is_RXform() { return has_base() && has_index() && is_disp12(); } 253 bool is_RXEform() { return has_base() && has_index() && is_disp12(); } 254 bool is_RXYform() { return has_base() && has_index() && is_disp20(); } 255 256 bool uses(Register r) { return _base == r || _index == r; }; 257 258 // accessors 259 Register base() const { return _base; } 260 Register baseOrR0() const { assert(_base != Z_R0, ""); return _base == noreg ? Z_R0 : _base; } 261 Register index() const { return _index; } 262 Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; } 263 intptr_t disp() const { return _disp; } 264 // Specific version for short displacement instructions. 265 int disp12() const { 266 assert(is_disp12(), "displacement out of range for uimm12"); 267 return _disp; 268 } 269 // Specific version for long displacement instructions. 270 int disp20() const { 271 assert(is_disp20(), "displacement out of range for simm20"); 272 return _disp; 273 } 274 intptr_t value() const { return _disp; } 275 276 friend class Assembler; 277}; 278 279class AddressLiteral VALUE_OBJ_CLASS_SPEC { 280 private: 281 address _address; 282 RelocationHolder _rspec; 283 284 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 285 switch (rtype) { 286 case relocInfo::external_word_type: 287 return external_word_Relocation::spec(addr); 288 case relocInfo::internal_word_type: 289 return internal_word_Relocation::spec(addr); 290 case relocInfo::opt_virtual_call_type: 291 return opt_virtual_call_Relocation::spec(); 292 case relocInfo::static_call_type: 293 return static_call_Relocation::spec(); 294 case relocInfo::runtime_call_w_cp_type: 295 return runtime_call_w_cp_Relocation::spec(); 296 case relocInfo::none: 297 return RelocationHolder(); 298 default: 299 ShouldNotReachHere(); 300 return RelocationHolder(); 301 } 302 } 303 304 protected: 305 // creation 306 AddressLiteral() : _address(NULL), _rspec(NULL) {} 307 308 public: 309 AddressLiteral(address addr, RelocationHolder const& rspec) 310 : _address(addr), 311 _rspec(rspec) {} 312 313 // Some constructors to avoid casting at the call site. 314 AddressLiteral(jobject obj, RelocationHolder const& rspec) 315 : _address((address) obj), 316 _rspec(rspec) {} 317 318 AddressLiteral(intptr_t value, RelocationHolder const& rspec) 319 : _address((address) value), 320 _rspec(rspec) {} 321 322 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 323 : _address((address) addr), 324 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 325 326 // Some constructors to avoid casting at the call site. 327 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none) 328 : _address((address) addr), 329 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 330 331 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none) 332 : _address((address) addr), 333 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 334 335 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none) 336 : _address((address) addr), 337 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 338 339 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none) 340 : _address((address) addr), 341 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 342 343 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none) 344 : _address((address) addr), 345 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 346 347 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none) 348 : _address((address) addr), 349 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 350 351 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none) 352 : _address((address) addr), 353 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 354 355 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none) 356 : _address((address) addr), 357 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 358 359 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 360 : _address((address) addr), 361 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 362 363 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none) 364 : _address((address) addr), 365 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 366 367 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none) 368 : _address((address) addr), 369 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 370 371 intptr_t value() const { return (intptr_t) _address; } 372 373 const relocInfo::relocType rtype() const { return _rspec.type(); } 374 const RelocationHolder& rspec() const { return _rspec; } 375 376 RelocationHolder rspec(int offset) const { 377 return offset == 0 ? _rspec : _rspec.plus(offset); 378 } 379}; 380 381// Convenience classes 382class ExternalAddress: public AddressLiteral { 383 private: 384 static relocInfo::relocType reloc_for_target(address target) { 385 // Sometimes ExternalAddress is used for values which aren't 386 // exactly addresses, like the card table base. 387 // External_word_type can't be used for values in the first page 388 // so just skip the reloc in that case. 389 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 390 } 391 392 public: 393 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {} 394 ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {} 395}; 396 397// Argument is an abstraction used to represent an outgoing actual 398// argument or an incoming formal parameter, whether it resides in 399// memory or in a register, in a manner consistent with the 400// z/Architecture Application Binary Interface, or ABI. This is often 401// referred to as the native or C calling convention. 402class Argument VALUE_OBJ_CLASS_SPEC { 403 private: 404 int _number; 405 bool _is_in; 406 407 public: 408 enum { 409 // Only 5 registers may contain integer parameters. 410 n_register_parameters = 5, 411 // Can have up to 4 floating registers. 412 n_float_register_parameters = 4 413 }; 414 415 // creation 416 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {} 417 Argument(int number) : _number(number) {} 418 419 int number() const { return _number; } 420 421 Argument successor() const { return Argument(number() + 1); } 422 423 // Locating register-based arguments: 424 bool is_register() const { return _number < n_register_parameters; } 425 426 // Locating Floating Point register-based arguments: 427 bool is_float_register() const { return _number < n_float_register_parameters; } 428 429 FloatRegister as_float_register() const { 430 assert(is_float_register(), "must be a register argument"); 431 return as_FloatRegister((number() *2) + 1); 432 } 433 434 FloatRegister as_double_register() const { 435 assert(is_float_register(), "must be a register argument"); 436 return as_FloatRegister((number() *2)); 437 } 438 439 Register as_register() const { 440 assert(is_register(), "must be a register argument"); 441 return as_Register(number() + Z_ARG1->encoding()); 442 } 443 444 // debugging 445 const char* name() const; 446 447 friend class Assembler; 448}; 449 450 451// The z/Architecture Assembler: Pure assembler doing NO optimizations 452// on the instruction level; i.e., what you write is what you get. The 453// Assembler is generating code into a CodeBuffer. 454class Assembler : public AbstractAssembler { 455 protected: 456 457 friend class AbstractAssembler; 458 friend class AddressLiteral; 459 460 // Code patchers need various routines like inv_wdisp(). 461 friend class NativeInstruction; 462#ifndef COMPILER2 463 friend class NativeGeneralJump; 464#endif 465 friend class Relocation; 466 467 public: 468 469// Addressing 470 471// address calculation 472#define LA_ZOPC (unsigned int)(0x41 << 24) 473#define LAY_ZOPC (unsigned long)(0xe3L << 40 | 0x71L) 474#define LARL_ZOPC (unsigned long)(0xc0L << 40 | 0x00L << 32) 475 476 477// Data Transfer 478 479// register to register transfer 480#define LR_ZOPC (unsigned int)(24 << 8) 481#define LBR_ZOPC (unsigned int)(0xb926 << 16) 482#define LHR_ZOPC (unsigned int)(0xb927 << 16) 483#define LGBR_ZOPC (unsigned int)(0xb906 << 16) 484#define LGHR_ZOPC (unsigned int)(0xb907 << 16) 485#define LGFR_ZOPC (unsigned int)(0xb914 << 16) 486#define LGR_ZOPC (unsigned int)(0xb904 << 16) 487 488#define LLHR_ZOPC (unsigned int)(0xb995 << 16) 489#define LLGCR_ZOPC (unsigned int)(0xb984 << 16) 490#define LLGHR_ZOPC (unsigned int)(0xb985 << 16) 491#define LLGTR_ZOPC (unsigned int)(185 << 24 | 23 << 16) 492#define LLGFR_ZOPC (unsigned int)(185 << 24 | 22 << 16) 493 494#define LTR_ZOPC (unsigned int)(18 << 8) 495#define LTGFR_ZOPC (unsigned int)(185 << 24 | 18 << 16) 496#define LTGR_ZOPC (unsigned int)(185 << 24 | 2 << 16) 497 498#define LER_ZOPC (unsigned int)(56 << 8) 499#define LEDBR_ZOPC (unsigned int)(179 << 24 | 68 << 16) 500#define LEXBR_ZOPC (unsigned int)(179 << 24 | 70 << 16) 501#define LDEBR_ZOPC (unsigned int)(179 << 24 | 4 << 16) 502#define LDR_ZOPC (unsigned int)(40 << 8) 503#define LDXBR_ZOPC (unsigned int)(179 << 24 | 69 << 16) 504#define LXEBR_ZOPC (unsigned int)(179 << 24 | 6 << 16) 505#define LXDBR_ZOPC (unsigned int)(179 << 24 | 5 << 16) 506#define LXR_ZOPC (unsigned int)(179 << 24 | 101 << 16) 507#define LTEBR_ZOPC (unsigned int)(179 << 24 | 2 << 16) 508#define LTDBR_ZOPC (unsigned int)(179 << 24 | 18 << 16) 509#define LTXBR_ZOPC (unsigned int)(179 << 24 | 66 << 16) 510 511#define LRVR_ZOPC (unsigned int)(0xb91f << 16) 512#define LRVGR_ZOPC (unsigned int)(0xb90f << 16) 513 514#define LDGR_ZOPC (unsigned int)(0xb3c1 << 16) // z10 515#define LGDR_ZOPC (unsigned int)(0xb3cd << 16) // z10 516 517#define LOCR_ZOPC (unsigned int)(0xb9f2 << 16) // z196 518#define LOCGR_ZOPC (unsigned int)(0xb9e2 << 16) // z196 519 520// immediate to register transfer 521#define IIHH_ZOPC (unsigned int)(165 << 24) 522#define IIHL_ZOPC (unsigned int)(165 << 24 | 1 << 16) 523#define IILH_ZOPC (unsigned int)(165 << 24 | 2 << 16) 524#define IILL_ZOPC (unsigned int)(165 << 24 | 3 << 16) 525#define IIHF_ZOPC (unsigned long)(0xc0L << 40 | 8L << 32) 526#define IILF_ZOPC (unsigned long)(0xc0L << 40 | 9L << 32) 527#define LLIHH_ZOPC (unsigned int)(165 << 24 | 12 << 16) 528#define LLIHL_ZOPC (unsigned int)(165 << 24 | 13 << 16) 529#define LLILH_ZOPC (unsigned int)(165 << 24 | 14 << 16) 530#define LLILL_ZOPC (unsigned int)(165 << 24 | 15 << 16) 531#define LLIHF_ZOPC (unsigned long)(0xc0L << 40 | 14L << 32) 532#define LLILF_ZOPC (unsigned long)(0xc0L << 40 | 15L << 32) 533#define LHI_ZOPC (unsigned int)(167 << 24 | 8 << 16) 534#define LGHI_ZOPC (unsigned int)(167 << 24 | 9 << 16) 535#define LGFI_ZOPC (unsigned long)(0xc0L << 40 | 1L << 32) 536 537#define LZER_ZOPC (unsigned int)(0xb374 << 16) 538#define LZDR_ZOPC (unsigned int)(0xb375 << 16) 539 540// LOAD: memory to register transfer 541#define LB_ZOPC (unsigned long)(227L << 40 | 118L) 542#define LH_ZOPC (unsigned int)(72 << 24) 543#define LHY_ZOPC (unsigned long)(227L << 40 | 120L) 544#define L_ZOPC (unsigned int)(88 << 24) 545#define LY_ZOPC (unsigned long)(227L << 40 | 88L) 546#define LT_ZOPC (unsigned long)(0xe3L << 40 | 0x12L) 547#define LGB_ZOPC (unsigned long)(227L << 40 | 119L) 548#define LGH_ZOPC (unsigned long)(227L << 40 | 21L) 549#define LGF_ZOPC (unsigned long)(227L << 40 | 20L) 550#define LG_ZOPC (unsigned long)(227L << 40 | 4L) 551#define LTG_ZOPC (unsigned long)(0xe3L << 40 | 0x02L) 552#define LTGF_ZOPC (unsigned long)(0xe3L << 40 | 0x32L) 553 554#define LLC_ZOPC (unsigned long)(0xe3L << 40 | 0x94L) 555#define LLH_ZOPC (unsigned long)(0xe3L << 40 | 0x95L) 556#define LLGT_ZOPC (unsigned long)(227L << 40 | 23L) 557#define LLGC_ZOPC (unsigned long)(227L << 40 | 144L) 558#define LLGH_ZOPC (unsigned long)(227L << 40 | 145L) 559#define LLGF_ZOPC (unsigned long)(227L << 40 | 22L) 560 561#define IC_ZOPC (unsigned int)(0x43 << 24) 562#define ICY_ZOPC (unsigned long)(0xe3L << 40 | 0x73L) 563#define ICM_ZOPC (unsigned int)(0xbf << 24) 564#define ICMY_ZOPC (unsigned long)(0xebL << 40 | 0x81L) 565#define ICMH_ZOPC (unsigned long)(0xebL << 40 | 0x80L) 566 567#define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL) 568#define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL) 569#define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL) 570 571 572// LOAD relative: memory to register transfer 573#define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10 574#define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10 575#define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10 576#define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10 577#define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10 578 579#define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10 580#define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10 581#define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10 582 583#define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196 584#define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196 585 586#define LMG_ZOPC (unsigned long)(235L << 40 | 4L) 587 588#define LE_ZOPC (unsigned int)(0x78 << 24) 589#define LEY_ZOPC (unsigned long)(237L << 40 | 100L) 590#define LDEB_ZOPC (unsigned long)(237L << 40 | 4) 591#define LD_ZOPC (unsigned int)(0x68 << 24) 592#define LDY_ZOPC (unsigned long)(237L << 40 | 101L) 593#define LXEB_ZOPC (unsigned long)(237L << 40 | 6) 594#define LXDB_ZOPC (unsigned long)(237L << 40 | 5) 595 596// STORE: register to memory transfer 597#define STC_ZOPC (unsigned int)(0x42 << 24) 598#define STCY_ZOPC (unsigned long)(227L << 40 | 114L) 599#define STH_ZOPC (unsigned int)(64 << 24) 600#define STHY_ZOPC (unsigned long)(227L << 40 | 112L) 601#define ST_ZOPC (unsigned int)(80 << 24) 602#define STY_ZOPC (unsigned long)(227L << 40 | 80L) 603#define STG_ZOPC (unsigned long)(227L << 40 | 36L) 604 605#define STCM_ZOPC (unsigned long)(0xbeL << 24) 606#define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL) 607#define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL) 608 609// STORE relative: memory to register transfer 610#define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10 611#define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10 612#define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10 613 614#define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196 615#define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196 616 617#define STMG_ZOPC (unsigned long)(235L << 40 | 36L) 618 619#define STE_ZOPC (unsigned int)(0x70 << 24) 620#define STEY_ZOPC (unsigned long)(237L << 40 | 102L) 621#define STD_ZOPC (unsigned int)(0x60 << 24) 622#define STDY_ZOPC (unsigned long)(237L << 40 | 103L) 623 624// MOVE: immediate to memory transfer 625#define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10 626#define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10 627#define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10 628 629 630// ALU operations 631 632// Load Positive 633#define LPR_ZOPC (unsigned int)(16 << 8) 634#define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16) 635#define LPGR_ZOPC (unsigned int)(185 << 24) 636#define LPEBR_ZOPC (unsigned int)(179 << 24) 637#define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16) 638#define LPXBR_ZOPC (unsigned int)(179 << 24 | 64 << 16) 639 640// Load Negative 641#define LNR_ZOPC (unsigned int)(17 << 8) 642#define LNGFR_ZOPC (unsigned int)(185 << 24 | 17 << 16) 643#define LNGR_ZOPC (unsigned int)(185 << 24 | 1 << 16) 644#define LNEBR_ZOPC (unsigned int)(179 << 24 | 1 << 16) 645#define LNDBR_ZOPC (unsigned int)(179 << 24 | 17 << 16) 646#define LNXBR_ZOPC (unsigned int)(179 << 24 | 65 << 16) 647 648// Load Complement 649#define LCR_ZOPC (unsigned int)(19 << 8) 650#define LCGFR_ZOPC (unsigned int)(185 << 24 | 19 << 16) 651#define LCGR_ZOPC (unsigned int)(185 << 24 | 3 << 16) 652#define LCEBR_ZOPC (unsigned int)(179 << 24 | 3 << 16) 653#define LCDBR_ZOPC (unsigned int)(179 << 24 | 19 << 16) 654#define LCXBR_ZOPC (unsigned int)(179 << 24 | 67 << 16) 655 656// Add 657// RR, signed 658#define AR_ZOPC (unsigned int)(26 << 8) 659#define AGFR_ZOPC (unsigned int)(0xb9 << 24 | 0x18 << 16) 660#define AGR_ZOPC (unsigned int)(0xb9 << 24 | 0x08 << 16) 661// RRF, signed 662#define ARK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f8 << 16) 663#define AGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e8 << 16) 664// RI, signed 665#define AHI_ZOPC (unsigned int)(167 << 24 | 10 << 16) 666#define AFI_ZOPC (unsigned long)(0xc2L << 40 | 9L << 32) 667#define AGHI_ZOPC (unsigned int)(167 << 24 | 11 << 16) 668#define AGFI_ZOPC (unsigned long)(0xc2L << 40 | 8L << 32) 669// RIE, signed 670#define AHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d8L) 671#define AGHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d9L) 672#define AIH_ZOPC (unsigned long)(0xccL << 40 | 0x08L << 32) 673// RM, signed 674#define AHY_ZOPC (unsigned long)(227L << 40 | 122L) 675#define A_ZOPC (unsigned int)(90 << 24) 676#define AY_ZOPC (unsigned long)(227L << 40 | 90L) 677#define AGF_ZOPC (unsigned long)(227L << 40 | 24L) 678#define AG_ZOPC (unsigned long)(227L << 40 | 8L) 679// In-memory arithmetic (add signed, add logical with signed immediate). 680// MI, signed 681#define ASI_ZOPC (unsigned long)(0xebL << 40 | 0x6aL) 682#define AGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7aL) 683 684// RR, Logical 685#define ALR_ZOPC (unsigned int)(30 << 8) 686#define ALGFR_ZOPC (unsigned int)(185 << 24 | 26 << 16) 687#define ALGR_ZOPC (unsigned int)(185 << 24 | 10 << 16) 688#define ALCGR_ZOPC (unsigned int)(185 << 24 | 136 << 16) 689// RRF, Logical 690#define ALRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fa << 16) 691#define ALGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00ea << 16) 692// RI, Logical 693#define ALFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0bL << 32) 694#define ALGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0aL << 32) 695// RIE, Logical 696#define ALHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00daL) 697#define ALGHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00dbL) 698// RM, Logical 699#define AL_ZOPC (unsigned int)(0x5e << 24) 700#define ALY_ZOPC (unsigned long)(227L << 40 | 94L) 701#define ALGF_ZOPC (unsigned long)(227L << 40 | 26L) 702#define ALG_ZOPC (unsigned long)(227L << 40 | 10L) 703// In-memory arithmetic (add signed, add logical with signed immediate). 704// MI, Logical 705#define ALSI_ZOPC (unsigned long)(0xebL << 40 | 0x6eL) 706#define ALGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7eL) 707 708// RR, BFP 709#define AEBR_ZOPC (unsigned int)(179 << 24 | 10 << 16) 710#define ADBR_ZOPC (unsigned int)(179 << 24 | 26 << 16) 711#define AXBR_ZOPC (unsigned int)(179 << 24 | 74 << 16) 712// RM, BFP 713#define AEB_ZOPC (unsigned long)(237L << 40 | 10) 714#define ADB_ZOPC (unsigned long)(237L << 40 | 26) 715 716// Subtract 717// RR, signed 718#define SR_ZOPC (unsigned int)(27 << 8) 719#define SGFR_ZOPC (unsigned int)(185 << 24 | 25 << 16) 720#define SGR_ZOPC (unsigned int)(185 << 24 | 9 << 16) 721// RRF, signed 722#define SRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f9 << 16) 723#define SGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e9 << 16) 724// RM, signed 725#define SH_ZOPC (unsigned int)(0x4b << 24) 726#define SHY_ZOPC (unsigned long)(227L << 40 | 123L) 727#define S_ZOPC (unsigned int)(0x5B << 24) 728#define SY_ZOPC (unsigned long)(227L << 40 | 91L) 729#define SGF_ZOPC (unsigned long)(227L << 40 | 25) 730#define SG_ZOPC (unsigned long)(227L << 40 | 9) 731// RR, Logical 732#define SLR_ZOPC (unsigned int)(31 << 8) 733#define SLGFR_ZOPC (unsigned int)(185 << 24 | 27 << 16) 734#define SLGR_ZOPC (unsigned int)(185 << 24 | 11 << 16) 735// RIL, Logical 736#define SLFI_ZOPC (unsigned long)(0xc2L << 40 | 0x05L << 32) 737#define SLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x04L << 32) 738// RRF, Logical 739#define SLRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fb << 16) 740#define SLGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00eb << 16) 741// RM, Logical 742#define SLY_ZOPC (unsigned long)(227L << 40 | 95L) 743#define SLGF_ZOPC (unsigned long)(227L << 40 | 27L) 744#define SLG_ZOPC (unsigned long)(227L << 40 | 11L) 745 746// RR, BFP 747#define SEBR_ZOPC (unsigned int)(179 << 24 | 11 << 16) 748#define SDBR_ZOPC (unsigned int)(179 << 24 | 27 << 16) 749#define SXBR_ZOPC (unsigned int)(179 << 24 | 75 << 16) 750// RM, BFP 751#define SEB_ZOPC (unsigned long)(237L << 40 | 11) 752#define SDB_ZOPC (unsigned long)(237L << 40 | 27) 753 754// Multiply 755// RR, signed 756#define MR_ZOPC (unsigned int)(28 << 8) 757#define MSR_ZOPC (unsigned int)(178 << 24 | 82 << 16) 758#define MSGFR_ZOPC (unsigned int)(185 << 24 | 28 << 16) 759#define MSGR_ZOPC (unsigned int)(185 << 24 | 12 << 16) 760// RI, signed 761#define MHI_ZOPC (unsigned int)(167 << 24 | 12 << 16) 762#define MGHI_ZOPC (unsigned int)(167 << 24 | 13 << 16) 763#define MSFI_ZOPC (unsigned long)(0xc2L << 40 | 0x01L << 32) // z10 764#define MSGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x00L << 32) // z10 765// RM, signed 766#define M_ZOPC (unsigned int)(92 << 24) 767#define MS_ZOPC (unsigned int)(0x71 << 24) 768#define MHY_ZOPC (unsigned long)(0xe3L<< 40 | 0x7cL) 769#define MSY_ZOPC (unsigned long)(227L << 40 | 81L) 770#define MSGF_ZOPC (unsigned long)(227L << 40 | 28L) 771#define MSG_ZOPC (unsigned long)(227L << 40 | 12L) 772// RR, unsigned 773#define MLR_ZOPC (unsigned int)(185 << 24 | 150 << 16) 774#define MLGR_ZOPC (unsigned int)(185 << 24 | 134 << 16) 775// RM, unsigned 776#define ML_ZOPC (unsigned long)(227L << 40 | 150L) 777#define MLG_ZOPC (unsigned long)(227L << 40 | 134L) 778 779// RR, BFP 780#define MEEBR_ZOPC (unsigned int)(179 << 24 | 23 << 16) 781#define MDEBR_ZOPC (unsigned int)(179 << 24 | 12 << 16) 782#define MDBR_ZOPC (unsigned int)(179 << 24 | 28 << 16) 783#define MXDBR_ZOPC (unsigned int)(179 << 24 | 7 << 16) 784#define MXBR_ZOPC (unsigned int)(179 << 24 | 76 << 16) 785// RM, BFP 786#define MEEB_ZOPC (unsigned long)(237L << 40 | 23) 787#define MDEB_ZOPC (unsigned long)(237L << 40 | 12) 788#define MDB_ZOPC (unsigned long)(237L << 40 | 28) 789#define MXDB_ZOPC (unsigned long)(237L << 40 | 7) 790 791// Multiply-Add 792#define MAEBR_ZOPC (unsigned int)(179 << 24 | 14 << 16) 793#define MADBR_ZOPC (unsigned int)(179 << 24 | 30 << 16) 794#define MSEBR_ZOPC (unsigned int)(179 << 24 | 15 << 16) 795#define MSDBR_ZOPC (unsigned int)(179 << 24 | 31 << 16) 796#define MAEB_ZOPC (unsigned long)(237L << 40 | 14) 797#define MADB_ZOPC (unsigned long)(237L << 40 | 30) 798#define MSEB_ZOPC (unsigned long)(237L << 40 | 15) 799#define MSDB_ZOPC (unsigned long)(237L << 40 | 31) 800 801// Divide 802// RR, signed 803#define DSGFR_ZOPC (unsigned int)(0xb91d << 16) 804#define DSGR_ZOPC (unsigned int)(0xb90d << 16) 805// RM, signed 806#define D_ZOPC (unsigned int)(93 << 24) 807#define DSGF_ZOPC (unsigned long)(227L << 40 | 29L) 808#define DSG_ZOPC (unsigned long)(227L << 40 | 13L) 809// RR, unsigned 810#define DLR_ZOPC (unsigned int)(185 << 24 | 151 << 16) 811#define DLGR_ZOPC (unsigned int)(185 << 24 | 135 << 16) 812// RM, unsigned 813#define DL_ZOPC (unsigned long)(227L << 40 | 151L) 814#define DLG_ZOPC (unsigned long)(227L << 40 | 135L) 815 816// RR, BFP 817#define DEBR_ZOPC (unsigned int)(179 << 24 | 13 << 16) 818#define DDBR_ZOPC (unsigned int)(179 << 24 | 29 << 16) 819#define DXBR_ZOPC (unsigned int)(179 << 24 | 77 << 16) 820// RM, BFP 821#define DEB_ZOPC (unsigned long)(237L << 40 | 13) 822#define DDB_ZOPC (unsigned long)(237L << 40 | 29) 823 824// Square Root 825// RR, BFP 826#define SQEBR_ZOPC (unsigned int)(0xb314 << 16) 827#define SQDBR_ZOPC (unsigned int)(0xb315 << 16) 828#define SQXBR_ZOPC (unsigned int)(0xb316 << 16) 829// RM, BFP 830#define SQEB_ZOPC (unsigned long)(237L << 40 | 20) 831#define SQDB_ZOPC (unsigned long)(237L << 40 | 21) 832 833// Compare and Test 834// RR, signed 835#define CR_ZOPC (unsigned int)(25 << 8) 836#define CGFR_ZOPC (unsigned int)(185 << 24 | 48 << 16) 837#define CGR_ZOPC (unsigned int)(185 << 24 | 32 << 16) 838// RI, signed 839#define CHI_ZOPC (unsigned int)(167 << 24 | 14 << 16) 840#define CFI_ZOPC (unsigned long)(0xc2L << 40 | 0xdL << 32) 841#define CGHI_ZOPC (unsigned int)(167 << 24 | 15 << 16) 842#define CGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xcL << 32) 843// RM, signed 844#define CH_ZOPC (unsigned int)(0x49 << 24) 845#define CHY_ZOPC (unsigned long)(227L << 40 | 121L) 846#define C_ZOPC (unsigned int)(0x59 << 24) 847#define CY_ZOPC (unsigned long)(227L << 40 | 89L) 848#define CGF_ZOPC (unsigned long)(227L << 40 | 48L) 849#define CG_ZOPC (unsigned long)(227L << 40 | 32L) 850// RR, unsigned 851#define CLR_ZOPC (unsigned int)(21 << 8) 852#define CLGFR_ZOPC (unsigned int)(185 << 24 | 49 << 16) 853#define CLGR_ZOPC (unsigned int)(185 << 24 | 33 << 16) 854// RIL, unsigned 855#define CLFI_ZOPC (unsigned long)(0xc2L << 40 | 0xfL << 32) 856#define CLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xeL << 32) 857// RM, unsigned 858#define CL_ZOPC (unsigned int)(0x55 << 24) 859#define CLY_ZOPC (unsigned long)(227L << 40 | 85L) 860#define CLGF_ZOPC (unsigned long)(227L << 40 | 49L) 861#define CLG_ZOPC (unsigned long)(227L << 40 | 33L) 862// RI, unsigned 863#define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16) 864#define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16) 865#define TMLH_ZOPC (unsigned int)(167 << 24) 866#define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16) 867 868// RR, BFP 869#define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16) 870#define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16) 871#define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16) 872// RM, BFP 873#define CEB_ZOPC (unsigned long)(237L << 40 | 9) 874#define CDB_ZOPC (unsigned long)(237L << 40 | 25) 875 876// Shift 877// arithmetic 878#define SLA_ZOPC (unsigned int)(139 << 24) 879#define SLAG_ZOPC (unsigned long)(235L << 40 | 11L) 880#define SRA_ZOPC (unsigned int)(138 << 24) 881#define SRAG_ZOPC (unsigned long)(235L << 40 | 10L) 882// logical 883#define SLL_ZOPC (unsigned int)(137 << 24) 884#define SLLG_ZOPC (unsigned long)(235L << 40 | 13L) 885#define SRL_ZOPC (unsigned int)(136 << 24) 886#define SRLG_ZOPC (unsigned long)(235L << 40 | 12L) 887 888// Rotate, then AND/XOR/OR/insert 889// rotate 890#define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10 891#define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10 892// rotate and {AND|XOR|OR|INS} 893#define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196 894#define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196 895#define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196 896#define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196 897 898// AND 899// RR, signed 900#define NR_ZOPC (unsigned int)(20 << 8) 901#define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16) 902// RRF, signed 903#define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16) 904#define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16) 905// RI, signed 906#define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16) 907#define NIHL_ZOPC (unsigned int)(165 << 24 | 5 << 16) 908#define NILH_ZOPC (unsigned int)(165 << 24 | 6 << 16) 909#define NILL_ZOPC (unsigned int)(165 << 24 | 7 << 16) 910#define NIHF_ZOPC (unsigned long)(0xc0L << 40 | 10L << 32) 911#define NILF_ZOPC (unsigned long)(0xc0L << 40 | 11L << 32) 912// RM, signed 913#define N_ZOPC (unsigned int)(0x54 << 24) 914#define NY_ZOPC (unsigned long)(227L << 40 | 84L) 915#define NG_ZOPC (unsigned long)(227L << 40 | 128L) 916 917// OR 918// RR, signed 919#define OR_ZOPC (unsigned int)(22 << 8) 920#define OGR_ZOPC (unsigned int)(185 << 24 | 129 << 16) 921// RRF, signed 922#define ORK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f6 << 16) 923#define OGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e6 << 16) 924// RI, signed 925#define OIHH_ZOPC (unsigned int)(165 << 24 | 8 << 16) 926#define OIHL_ZOPC (unsigned int)(165 << 24 | 9 << 16) 927#define OILH_ZOPC (unsigned int)(165 << 24 | 10 << 16) 928#define OILL_ZOPC (unsigned int)(165 << 24 | 11 << 16) 929#define OIHF_ZOPC (unsigned long)(0xc0L << 40 | 12L << 32) 930#define OILF_ZOPC (unsigned long)(0xc0L << 40 | 13L << 32) 931// RM, signed 932#define O_ZOPC (unsigned int)(0x56 << 24) 933#define OY_ZOPC (unsigned long)(227L << 40 | 86L) 934#define OG_ZOPC (unsigned long)(227L << 40 | 129L) 935 936// XOR 937// RR, signed 938#define XR_ZOPC (unsigned int)(23 << 8) 939#define XGR_ZOPC (unsigned int)(185 << 24 | 130 << 16) 940// RRF, signed 941#define XRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f7 << 16) 942#define XGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e7 << 16) 943// RI, signed 944#define XIHF_ZOPC (unsigned long)(0xc0L << 40 | 6L << 32) 945#define XILF_ZOPC (unsigned long)(0xc0L << 40 | 7L << 32) 946// RM, signed 947#define X_ZOPC (unsigned int)(0x57 << 24) 948#define XY_ZOPC (unsigned long)(227L << 40 | 87L) 949#define XG_ZOPC (unsigned long)(227L << 40 | 130L) 950 951 952// Data Conversion 953 954// INT to BFP 955#define CEFBR_ZOPC (unsigned int)(179 << 24 | 148 << 16) 956#define CDFBR_ZOPC (unsigned int)(179 << 24 | 149 << 16) 957#define CXFBR_ZOPC (unsigned int)(179 << 24 | 150 << 16) 958#define CEGBR_ZOPC (unsigned int)(179 << 24 | 164 << 16) 959#define CDGBR_ZOPC (unsigned int)(179 << 24 | 165 << 16) 960#define CXGBR_ZOPC (unsigned int)(179 << 24 | 166 << 16) 961// BFP to INT 962#define CFEBR_ZOPC (unsigned int)(179 << 24 | 152 << 16) 963#define CFDBR_ZOPC (unsigned int)(179 << 24 | 153 << 16) 964#define CFXBR_ZOPC (unsigned int)(179 << 24 | 154 << 16) 965#define CGEBR_ZOPC (unsigned int)(179 << 24 | 168 << 16) 966#define CGDBR_ZOPC (unsigned int)(179 << 24 | 169 << 16) 967#define CGXBR_ZOPC (unsigned int)(179 << 24 | 170 << 16) 968// INT to DEC 969#define CVD_ZOPC (unsigned int)(0x4e << 24) 970#define CVDY_ZOPC (unsigned long)(0xe3L << 40 | 0x26L) 971#define CVDG_ZOPC (unsigned long)(0xe3L << 40 | 0x2eL) 972 973 974// BFP Control 975 976#define SRNM_ZOPC (unsigned int)(178 << 24 | 153 << 16) 977#define EFPC_ZOPC (unsigned int)(179 << 24 | 140 << 16) 978#define SFPC_ZOPC (unsigned int)(179 << 24 | 132 << 16) 979#define STFPC_ZOPC (unsigned int)(178 << 24 | 156 << 16) 980#define LFPC_ZOPC (unsigned int)(178 << 24 | 157 << 16) 981 982 983// Branch Instructions 984 985// Register 986#define BCR_ZOPC (unsigned int)(7 << 8) 987#define BALR_ZOPC (unsigned int)(5 << 8) 988#define BASR_ZOPC (unsigned int)(13 << 8) 989#define BCTGR_ZOPC (unsigned long)(0xb946 << 16) 990// Absolute 991#define BC_ZOPC (unsigned int)(71 << 24) 992#define BAL_ZOPC (unsigned int)(69 << 24) 993#define BAS_ZOPC (unsigned int)(77 << 24) 994#define BXH_ZOPC (unsigned int)(134 << 24) 995#define BXHG_ZOPC (unsigned long)(235L << 40 | 68) 996// Relative 997#define BRC_ZOPC (unsigned int)(167 << 24 | 4 << 16) 998#define BRCL_ZOPC (unsigned long)(192L << 40 | 4L << 32) 999#define BRAS_ZOPC (unsigned int)(167 << 24 | 5 << 16) 1000#define BRASL_ZOPC (unsigned long)(192L << 40 | 5L << 32) 1001#define BRCT_ZOPC (unsigned int)(167 << 24 | 6 << 16) 1002#define BRCTG_ZOPC (unsigned int)(167 << 24 | 7 << 16) 1003#define BRXH_ZOPC (unsigned int)(132 << 24) 1004#define BRXHG_ZOPC (unsigned long)(236L << 40 | 68) 1005#define BRXLE_ZOPC (unsigned int)(133 << 24) 1006#define BRXLG_ZOPC (unsigned long)(236L << 40 | 69) 1007 1008 1009// Compare and Branch Instructions 1010 1011// signed comp reg/reg, branch Absolute 1012#define CRB_ZOPC (unsigned long)(0xecL << 40 | 0xf6L) // z10 1013#define CGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe4L) // z10 1014// signed comp reg/reg, branch Relative 1015#define CRJ_ZOPC (unsigned long)(0xecL << 40 | 0x76L) // z10 1016#define CGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x64L) // z10 1017// signed comp reg/imm, branch absolute 1018#define CIB_ZOPC (unsigned long)(0xecL << 40 | 0xfeL) // z10 1019#define CGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfcL) // z10 1020// signed comp reg/imm, branch relative 1021#define CIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7eL) // z10 1022#define CGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7cL) // z10 1023 1024// unsigned comp reg/reg, branch Absolute 1025#define CLRB_ZOPC (unsigned long)(0xecL << 40 | 0xf7L) // z10 1026#define CLGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe5L) // z10 1027// unsigned comp reg/reg, branch Relative 1028#define CLRJ_ZOPC (unsigned long)(0xecL << 40 | 0x77L) // z10 1029#define CLGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x65L) // z10 1030// unsigned comp reg/imm, branch absolute 1031#define CLIB_ZOPC (unsigned long)(0xecL << 40 | 0xffL) // z10 1032#define CLGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfdL) // z10 1033// unsigned comp reg/imm, branch relative 1034#define CLIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7fL) // z10 1035#define CLGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7dL) // z10 1036 1037// comp reg/reg, trap 1038#define CRT_ZOPC (unsigned int)(0xb972 << 16) // z10 1039#define CGRT_ZOPC (unsigned int)(0xb960 << 16) // z10 1040#define CLRT_ZOPC (unsigned int)(0xb973 << 16) // z10 1041#define CLGRT_ZOPC (unsigned int)(0xb961 << 16) // z10 1042// comp reg/imm, trap 1043#define CIT_ZOPC (unsigned long)(0xecL << 40 | 0x72L) // z10 1044#define CGIT_ZOPC (unsigned long)(0xecL << 40 | 0x70L) // z10 1045#define CLFIT_ZOPC (unsigned long)(0xecL << 40 | 0x73L) // z10 1046#define CLGIT_ZOPC (unsigned long)(0xecL << 40 | 0x71L) // z10 1047 1048 1049// Direct Memory Operations 1050 1051// Compare 1052#define CLI_ZOPC (unsigned int)(0x95 << 24) 1053#define CLIY_ZOPC (unsigned long)(0xebL << 40 | 0x55L) 1054#define CLC_ZOPC (unsigned long)(0xd5L << 40) 1055#define CLCL_ZOPC (unsigned int)(0x0f << 8) 1056#define CLCLE_ZOPC (unsigned int)(0xa9 << 24) 1057#define CLCLU_ZOPC (unsigned long)(0xebL << 40 | 0x8fL) 1058 1059// Move 1060#define MVI_ZOPC (unsigned int)(0x92 << 24) 1061#define MVIY_ZOPC (unsigned long)(0xebL << 40 | 0x52L) 1062#define MVC_ZOPC (unsigned long)(0xd2L << 40) 1063#define MVCL_ZOPC (unsigned int)(0x0e << 8) 1064#define MVCLE_ZOPC (unsigned int)(0xa8 << 24) 1065 1066// Test 1067#define TM_ZOPC (unsigned int)(0x91 << 24) 1068#define TMY_ZOPC (unsigned long)(0xebL << 40 | 0x51L) 1069 1070// AND 1071#define NI_ZOPC (unsigned int)(0x94 << 24) 1072#define NIY_ZOPC (unsigned long)(0xebL << 40 | 0x54L) 1073#define NC_ZOPC (unsigned long)(0xd4L << 40) 1074 1075// OR 1076#define OI_ZOPC (unsigned int)(0x96 << 24) 1077#define OIY_ZOPC (unsigned long)(0xebL << 40 | 0x56L) 1078#define OC_ZOPC (unsigned long)(0xd6L << 40) 1079 1080// XOR 1081#define XI_ZOPC (unsigned int)(0x97 << 24) 1082#define XIY_ZOPC (unsigned long)(0xebL << 40 | 0x57L) 1083#define XC_ZOPC (unsigned long)(0xd7L << 40) 1084 1085// Search String 1086#define SRST_ZOPC (unsigned int)(178 << 24 | 94 << 16) 1087#define SRSTU_ZOPC (unsigned int)(185 << 24 | 190 << 16) 1088 1089// Translate characters 1090#define TROO_ZOPC (unsigned int)(0xb9 << 24 | 0x93 << 16) 1091#define TROT_ZOPC (unsigned int)(0xb9 << 24 | 0x92 << 16) 1092#define TRTO_ZOPC (unsigned int)(0xb9 << 24 | 0x91 << 16) 1093#define TRTT_ZOPC (unsigned int)(0xb9 << 24 | 0x90 << 16) 1094 1095 1096// Miscellaneous Operations 1097 1098// Execute 1099#define EX_ZOPC (unsigned int)(68L << 24) 1100#define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10 1101 1102// Compare and Swap 1103#define CS_ZOPC (unsigned int)(0xba << 24) 1104#define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L) 1105#define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L) 1106 1107// Interlocked-Update 1108#define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196 1109#define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196 1110#define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196 1111#define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196 1112#define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196 1113#define LANG_ZOPC (unsigned long)(0xebL << 40 | 0xe4L) // z196 1114#define LAX_ZOPC (unsigned long)(0xebL << 40 | 0xf7L) // z196 1115#define LAXG_ZOPC (unsigned long)(0xebL << 40 | 0xe7L) // z196 1116#define LAO_ZOPC (unsigned long)(0xebL << 40 | 0xf6L) // z196 1117#define LAOG_ZOPC (unsigned long)(0xebL << 40 | 0xe6L) // z196 1118 1119// System Functions 1120#define STCK_ZOPC (unsigned int)(0xb2 << 24 | 0x05 << 16) 1121#define STCKF_ZOPC (unsigned int)(0xb2 << 24 | 0x7c << 16) 1122#define STFLE_ZOPC (unsigned int)(0xb2 << 24 | 0xb0 << 16) 1123#define ECTG_ZOPC (unsigned long)(0xc8L <<40 | 0x01L << 32) // z10 1124#define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10 1125 1126// Execution Prediction 1127#define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10 1128#define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10 1129#define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12 1130#define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12 1131 1132// Transaction Control 1133#define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12 1134#define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12 1135#define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12 1136#define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12 1137#define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12 1138#define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12 1139 1140// Crypto and Checksum 1141#define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32 1142#define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher 1143#define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher 1144#define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest) 1145#define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest) 1146#define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code 1147 1148// Various 1149#define TCEB_ZOPC (unsigned long)(237L << 40 | 16) 1150#define TCDB_ZOPC (unsigned long)(237L << 40 | 17) 1151#define TAM_ZOPC (unsigned long)(267) 1152 1153#define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16) 1154#define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16) 1155#define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16) 1156#define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16) 1157 1158 1159// OpCode field masks 1160 1161#define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1162#define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16) 1163#define RSI_MASK (unsigned int)(0xff << 24) 1164#define RIE_MASK (unsigned long)(0xffL << 40 | 0xffL) 1165#define RIL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1166 1167#define BASR_MASK (unsigned int)(0xff << 8) 1168#define BCR_MASK (unsigned int)(0xff << 8) 1169#define BRC_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1170#define LGHI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1171#define LLI_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1172#define II_MASK (unsigned int)(0xff << 24 | 0x0f << 16) 1173#define LLIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1174#define IIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1175#define BRASL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32) 1176#define TM_MASK (unsigned int)(0xff << 24) 1177#define TMY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1178#define LB_MASK (unsigned long)(0xffL << 40 | 0xffL) 1179#define LH_MASK (unsigned int)(0xff << 24) 1180#define L_MASK (unsigned int)(0xff << 24) 1181#define LY_MASK (unsigned long)(0xffL << 40 | 0xffL) 1182#define LG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1183#define LLGH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1184#define LLGF_MASK (unsigned long)(0xffL << 40 | 0xffL) 1185#define SLAG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1186#define LARL_MASK (unsigned long)(0xff0fL << 32) 1187#define LGRL_MASK (unsigned long)(0xff0fL << 32) 1188#define LE_MASK (unsigned int)(0xff << 24) 1189#define LD_MASK (unsigned int)(0xff << 24) 1190#define ST_MASK (unsigned int)(0xff << 24) 1191#define STC_MASK (unsigned int)(0xff << 24) 1192#define STG_MASK (unsigned long)(0xffL << 40 | 0xffL) 1193#define STH_MASK (unsigned int)(0xff << 24) 1194#define STE_MASK (unsigned int)(0xff << 24) 1195#define STD_MASK (unsigned int)(0xff << 24) 1196#define CMPBRANCH_MASK (unsigned long)(0xffL << 40 | 0xffL) 1197#define REL_LONG_MASK (unsigned long)(0xff0fL << 32) 1198 1199 public: 1200 // Condition code masks. Details: 1201 // - Mask bit#3 must be zero for all compare and branch/trap instructions to ensure 1202 // future compatibility. 1203 // - For all arithmetic instructions which set the condition code, mask bit#3 1204 // indicates overflow ("unordered" in float operations). 1205 // - "unordered" float comparison results have to be treated as low. 1206 // - When overflow/unordered is detected, none of the branch conditions is true, 1207 // except for bcondOverflow/bcondNotOrdered and bcondAlways. 1208 // - For INT comparisons, the inverse condition can be calculated as (14-cond). 1209 // - For FLOAT comparisons, the inverse condition can be calculated as (15-cond). 1210 enum branch_condition { 1211 bcondNever = 0, 1212 bcondAlways = 15, 1213 1214 // Specific names. Make use of lightweight sync. 1215 // Full and lightweight sync operation. 1216 bcondFullSync = 15, 1217 bcondLightSync = 14, 1218 bcondNop = 0, 1219 1220 // arithmetic compare instructions 1221 // arithmetic load and test, insert instructions 1222 // Mask bit#3 must be zero for future compatibility. 1223 bcondEqual = 8, 1224 bcondNotEqual = 6, 1225 bcondLow = 4, 1226 bcondNotLow = 10, 1227 bcondHigh = 2, 1228 bcondNotHigh = 12, 1229 // arithmetic calculation instructions 1230 // Mask bit#3 indicates overflow if detected by instr. 1231 // Mask bit#3 = 0 (overflow is not handled by compiler). 1232 bcondOverflow = 1, 1233 bcondNotOverflow = 14, 1234 bcondZero = bcondEqual, 1235 bcondNotZero = bcondNotEqual, 1236 bcondNegative = bcondLow, 1237 bcondNotNegative = bcondNotLow, 1238 bcondPositive = bcondHigh, 1239 bcondNotPositive = bcondNotHigh, 1240 bcondNotOrdered = 1, // float comparisons 1241 bcondOrdered = 14, // float comparisons 1242 bcondLowOrNotOrdered = bcondLow|bcondNotOrdered, // float comparisons 1243 bcondHighOrNotOrdered = bcondHigh|bcondNotOrdered, // float comparisons 1244 // unsigned arithmetic calculation instructions 1245 // Mask bit#0 is not used by these instructions. 1246 // There is no indication of overflow for these instr. 1247 bcondLogZero = 2, 1248 bcondLogNotZero = 5, 1249 bcondLogNotZero_Borrow = 4, 1250 bcondLogNotZero_NoBorrow = 1, 1251 // string search instructions 1252 bcondFound = 4, 1253 bcondNotFound = 2, 1254 bcondInterrupted = 1, 1255 // bit test instructions 1256 bcondAllZero = 8, 1257 bcondMixed = 6, 1258 bcondAllOne = 1, 1259 bcondNotAllZero = 7 // for tmll 1260 }; 1261 1262 enum Condition { 1263 // z/Architecture 1264 negative = 0, 1265 less = 0, 1266 positive = 1, 1267 greater = 1, 1268 zero = 2, 1269 equal = 2, 1270 summary_overflow = 3, 1271 }; 1272 1273 // Rounding mode for float-2-int conversions. 1274 enum RoundingMode { 1275 current_mode = 0, // Mode taken from FPC register. 1276 biased_to_nearest = 1, 1277 to_nearest = 4, 1278 to_zero = 5, 1279 to_plus_infinity = 6, 1280 to_minus_infinity = 7 1281 }; 1282 1283 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc. 1284 static branch_condition inverse_condition(branch_condition cc); 1285 static branch_condition inverse_float_condition(branch_condition cc); 1286 1287 1288 //----------------------------------------------- 1289 // instruction property getter methods 1290 //----------------------------------------------- 1291 1292 // Calculate length of instruction. 1293 static int instr_len(unsigned char *instr); 1294 1295 // Longest instructions are 6 bytes on z/Architecture. 1296 static int instr_maxlen() { return 6; } 1297 1298 // Average instruction is 4 bytes on z/Architecture (just a guess). 1299 static int instr_avglen() { return 4; } 1300 1301 // Shortest instructions are 2 bytes on z/Architecture. 1302 static int instr_minlen() { return 2; } 1303 1304 // Move instruction at pc right-justified into passed long int. 1305 // Return instr len in bytes as function result. 1306 static unsigned int get_instruction(unsigned char *pc, unsigned long *instr); 1307 1308 // Move instruction in passed (long int) into storage at pc. 1309 // This code is _NOT_ MT-safe!! 1310 static void set_instruction(unsigned char *pc, unsigned long instr, unsigned int len) { 1311 memcpy(pc, ((unsigned char *)&instr)+sizeof(unsigned long)-len, len); 1312 } 1313 1314 1315 //------------------------------------------ 1316 // instruction field test methods 1317 //------------------------------------------ 1318 1319 // Only used once in s390.ad to implement Matcher::is_short_branch_offset(). 1320 static bool is_within_range_of_RelAddr16(address target, address origin) { 1321 return RelAddr::is_in_range_of_RelAddr16(target, origin); 1322 } 1323 1324 1325 //---------------------------------- 1326 // some diagnostic output 1327 //---------------------------------- 1328 1329 static void print_dbg_msg(outputStream* out, unsigned long inst, const char* msg, int ilen) PRODUCT_RETURN; 1330 static void dump_code_range(outputStream* out, address pc, const unsigned int range, const char* msg = " ") PRODUCT_RETURN; 1331 1332 protected: 1333 1334 //------------------------------------------------------- 1335 // instruction field helper methods (internal) 1336 //------------------------------------------------------- 1337 1338 // Return a mask of 1s between hi_bit and lo_bit (inclusive). 1339 static long fmask(unsigned int hi_bit, unsigned int lo_bit) { 1340 assert(hi_bit >= lo_bit && hi_bit < 48, "bad bits"); 1341 return ((1L<<(hi_bit-lo_bit+1)) - 1) << lo_bit; 1342 } 1343 1344 // extract u_field 1345 // unsigned value 1346 static long inv_u_field(long x, int hi_bit, int lo_bit) { 1347 return (x & fmask(hi_bit, lo_bit)) >> lo_bit; 1348 } 1349 1350 // extract s_field 1351 // Signed value, may need sign extension. 1352 static long inv_s_field(long x, int hi_bit, int lo_bit) { 1353 x = inv_u_field(x, hi_bit, lo_bit); 1354 // Highest extracted bit set -> sign extension. 1355 return (x >= (1L<<(hi_bit-lo_bit)) ? x | ((-1L)<<(hi_bit-lo_bit)) : x); 1356 } 1357 1358 // Extract primary opcode from instruction. 1359 static int z_inv_op(int x) { return inv_u_field(x, 31, 24); } 1360 static int z_inv_op(long x) { return inv_u_field(x, 47, 40); } 1361 1362 static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); } // Regs are encoded in 4 bits. 1363 static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); } // Mask is 8 bits long. 1364 static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); } // 6-byte instructions only 1365 static int inv_simm16(long x) { return (inv_s_field(x, 15, 0)); } // 4-byte instructions only 1366 static int inv_simm20(long x) { return (inv_u_field(x, 27, 16) | // 6-byte instructions only 1367 inv_s_field(x, 15, 8)<<12); } 1368 static int inv_simm32(long x) { return (inv_s_field(x, 31, 0)); } // 6-byte instructions only 1369 static int inv_uimm12(long x) { return (inv_u_field(x, 11, 0)); } // 4-byte instructions only 1370 1371 // Encode u_field from long value. 1372 static long u_field(long x, int hi_bit, int lo_bit) { 1373 long r = x << lo_bit; 1374 assert((r & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 1375 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 1376 return r; 1377 } 1378 1379 public: 1380 1381 //-------------------------------------------------- 1382 // instruction field construction methods 1383 //-------------------------------------------------- 1384 1385 // Compute relative address (32 bit) for branch. 1386 // Only used once in nativeInst_s390.cpp. 1387 static intptr_t z_pcrel_off(address dest, address pc) { 1388 return RelAddr::pcrel_off32(dest, pc); 1389 } 1390 1391 // Extract 20-bit signed displacement. 1392 // Only used in disassembler_s390.cpp for temp enhancements. 1393 static int inv_simm20_xx(address iLoc) { 1394 unsigned long instr = 0; 1395 unsigned long iLen = get_instruction(iLoc, &instr); 1396 return inv_simm20(instr); 1397 } 1398 1399 // unsigned immediate, in low bits, nbits long 1400 static long uimm(long x, int nbits) { 1401 assert(Immediate::is_uimm(x, nbits), "unsigned constant out of range"); 1402 return x & fmask(nbits - 1, 0); 1403 } 1404 1405 // Cast '1' to long to avoid sign extension if nbits = 32. 1406 // signed immediate, in low bits, nbits long 1407 static long simm(long x, int nbits) { 1408 assert(Immediate::is_simm(x, nbits), "value out of range"); 1409 return x & fmask(nbits - 1, 0); 1410 } 1411 1412 static long imm(int64_t x, int nbits) { 1413 // Assert that x can be represented with nbits bits ignoring the sign bits, 1414 // i.e. the more higher bits should all be 0 or 1. 1415 assert((x >> nbits) == 0 || (x >> nbits) == -1, "value out of range"); 1416 return x & fmask(nbits-1, 0); 1417 } 1418 1419 // A 20-bit displacement is only in instructions of the 1420 // RSY, RXY, or SIY format. In these instructions, the D 1421 // field consists of a DL (low) field in bit positions 20-31 1422 // and of a DH (high) field in bit positions 32-39. The 1423 // value of the displacement is formed by appending the 1424 // contents of the DH field to the left of the contents of 1425 // the DL field. 1426 static long simm20(int64_t ui20) { 1427 assert(Immediate::is_simm(ui20, 20), "value out of range"); 1428 return ( ((ui20 & 0xfffL) << (48-32)) | // DL 1429 (((ui20 >> 12) & 0xffL) << (48-40))); // DH 1430 } 1431 1432 static long reg(Register r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1433 static long reg(int r, int s, int len) { return u_field(r, (len-s)-1, (len-s)-4); } 1434 static long regt(Register r, int s, int len) { return reg(r, s, len); } 1435 static long regz(Register r, int s, int len) { assert(r != Z_R0, "cannot use register R0 in memory access"); return reg(r, s, len); } 1436 1437 static long uimm4( int64_t ui4, int s, int len) { return uimm(ui4, 4) << (len-s-4); } 1438 static long uimm6( int64_t ui6, int s, int len) { return uimm(ui6, 6) << (len-s-6); } 1439 static long uimm8( int64_t ui8, int s, int len) { return uimm(ui8, 8) << (len-s-8); } 1440 static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); } 1441 static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); } 1442 static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension 1443 1444 static long simm8( int64_t si8, int s, int len) { return simm(si8, 8) << (len-s-8); } 1445 static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); } 1446 static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); } 1447 static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); } 1448 static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); } 1449 1450 static long imm8( int64_t i8, int s, int len) { return imm(i8, 8) << (len-s-8); } 1451 static long imm12(int64_t i12, int s, int len) { return imm(i12, 12) << (len-s-12); } 1452 static long imm16(int64_t i16, int s, int len) { return imm(i16, 16) << (len-s-16); } 1453 static long imm24(int64_t i24, int s, int len) { return imm(i24, 24) << (len-s-24); } 1454 static long imm32(int64_t i32, int s, int len) { return imm(i32, 32) << (len-s-32); } 1455 1456 static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); } 1457 static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); } 1458 1459 // Rounding mode for float-2-int conversions. 1460 static long rounding_mode(RoundingMode m, int s, int len) { 1461 assert(m != 2 && m != 3, "invalid mode"); 1462 return uimm(m, 4) << (len-s-4); 1463 } 1464 1465 //-------------------------------------------- 1466 // instruction field getter methods 1467 //-------------------------------------------- 1468 1469 static int get_imm32(address a, int instruction_number) { 1470 int imm; 1471 int *p =((int *)(a + 2 + 6 * instruction_number)); 1472 imm = *p; 1473 return imm; 1474 } 1475 1476 static short get_imm16(address a, int instruction_number) { 1477 short imm; 1478 short *p =((short *)a) + 2 * instruction_number + 1; 1479 imm = *p; 1480 return imm; 1481 } 1482 1483 1484 //-------------------------------------------- 1485 // instruction field setter methods 1486 //-------------------------------------------- 1487 1488 static void set_imm32(address a, int64_t s) { 1489 assert(Immediate::is_simm32(s) || Immediate::is_uimm32(s), "to big"); 1490 int* p = (int *) (a + 2); 1491 *p = s; 1492 } 1493 1494 static void set_imm16(int* instr, int64_t s) { 1495 assert(Immediate::is_simm16(s) || Immediate::is_uimm16(s), "to big"); 1496 short* p = ((short *)instr) + 1; 1497 *p = s; 1498 } 1499 1500 public: 1501 1502 static unsigned int align(unsigned int x, unsigned int a) { return ((x + (a - 1)) & ~(a - 1)); } 1503 static bool is_aligned(unsigned int x, unsigned int a) { return (0 == x % a); } 1504 1505 inline void emit_16(int x); 1506 inline void emit_32(int x); 1507 inline void emit_48(long x); 1508 1509 // Compare and control flow instructions 1510 // ===================================== 1511 1512 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1513 1514 // compare instructions 1515 // compare register 1516 inline void z_cr( Register r1, Register r2); // compare (r1, r2) ; int32 1517 inline void z_cgr( Register r1, Register r2); // compare (r1, r2) ; int64 1518 inline void z_cgfr(Register r1, Register r2); // compare (r1, r2) ; int64 <--> int32 1519 // compare immediate 1520 inline void z_chi( Register r1, int64_t i2); // compare (r1, i2_imm16) ; int32 1521 inline void z_cfi( Register r1, int64_t i2); // compare (r1, i2_imm32) ; int32 1522 inline void z_cghi(Register r1, int64_t i2); // compare (r1, i2_imm16) ; int64 1523 inline void z_cgfi(Register r1, int64_t i2); // compare (r1, i2_imm32) ; int64 1524 // compare memory 1525 inline void z_ch( Register r1, const Address &a); // compare (r1, *(a)) ; int32 <--> int16 1526 inline void z_ch( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 <--> int16 1527 inline void z_c( Register r1, const Address &a); // compare (r1, *(a)) ; int32 1528 inline void z_c( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 1529 inline void z_cy( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1530 inline void z_cy( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32 1531 inline void z_cy( Register r1, const Address& a); // compare (r1, *(a)) ; int32 1532 //inline void z_cgf(Register r1,const Address &a); // compare (r1, *(a)) ; int64 <--> int32 1533 //inline void z_cgf(Register r1,int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2)) ; int64 <--> int32 1534 inline void z_cg( Register r1, const Address &a); // compare (r1, *(a)) ; int64 1535 inline void z_cg( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm20+x2+b2)) ; int64 1536 1537 // compare logical instructions 1538 // compare register 1539 inline void z_clr( Register r1, Register r2); // compare (r1, r2) ; uint32 1540 inline void z_clgr( Register r1, Register r2); // compare (r1, r2) ; uint64 1541 // compare immediate 1542 inline void z_clfi( Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint32 1543 inline void z_clgfi(Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint64 1544 inline void z_cl( Register r1, const Address &a); // compare (r1, *(a) ; uint32 1545 inline void z_cl( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2) ; uint32 1546 inline void z_cly( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1547 inline void z_cly( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; uint32 1548 inline void z_cly( Register r1, const Address& a); // compare (r1, *(a)) ; uint32 1549 inline void z_clg( Register r1, const Address &a); // compare (r1, *(a) ; uint64 1550 inline void z_clg( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_imm20+x2+b2) ; uint64 1551 1552 // test under mask 1553 inline void z_tmll(Register r1, int64_t i2); // test under mask, see docu 1554 inline void z_tmlh(Register r1, int64_t i2); // test under mask, see docu 1555 inline void z_tmhl(Register r1, int64_t i2); // test under mask, see docu 1556 inline void z_tmhh(Register r1, int64_t i2); // test under mask, see docu 1557 1558 // branch instructions 1559 inline void z_bc( branch_condition m1, int64_t d2, Register x2, Register b2);// branch m1 ? pc = (d2_uimm12+x2+b2) 1560 inline void z_bcr( branch_condition m1, Register r2); // branch (m1 && r2!=R0) ? pc = r2 1561 inline void z_brc( branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm16 1562 inline void z_brc( branch_condition i1, address a); // branch i1 ? pc = a 1563 inline void z_brc( branch_condition i1, Label& L); // branch i1 ? pc = Label 1564 //inline void z_brcl(branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm32 1565 inline void z_brcl(branch_condition i1, address a); // branch i1 ? pc = a 1566 inline void z_brcl(branch_condition i1, Label& L); // branch i1 ? pc = Label 1567 inline void z_bctgr(Register r1, Register r2); // branch on count r1 -= 1; (r1!=0) ? pc = r2 ; r1 is int64 1568 1569 // branch unconditional / always 1570 inline void z_br(Register r2); // branch to r2, nop if r2 == Z_R0 1571 1572 1573 // See also commodity routines compare64_and_branch(), compare32_and_branch(). 1574 // signed comparison and branch 1575 inline void z_crb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int32 -- z10 1576 inline void z_cgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int64 -- z10 1577 inline void z_crj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int32 -- z10 1578 inline void z_crj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int32 -- z10 1579 inline void z_cgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int64 -- z10 1580 inline void z_cgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int64 -- z10 1581 inline void z_cib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int32 -- z10 1582 inline void z_cgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int64 -- z10 1583 inline void z_cij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int32 -- z10 1584 inline void z_cij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int32 -- z10 1585 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int64 -- z10 1586 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int64 -- z10 1587 // unsigned comparison and branch 1588 inline void z_clrb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint32 -- z10 1589 inline void z_clgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint64 -- z10 1590 inline void z_clrj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint32 -- z10 1591 inline void z_clrj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint32 -- z10 1592 inline void z_clgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint64 -- z10 1593 inline void z_clgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint64 -- z10 1594 inline void z_clib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint32 -- z10 1595 inline void z_clgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint64 -- z10 1596 inline void z_clij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint32 -- z10 1597 inline void z_clij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint32 -- z10 1598 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint64 -- z10 1599 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint64 -- z10 1600 1601 // Compare and trap instructions. 1602 // signed comparison 1603 inline void z_crt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int32 -- z10 1604 inline void z_cgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int64 -- z10 1605 inline void z_cit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int32 -- z10 1606 inline void z_cgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int64 -- z10 1607 // unsigned comparison 1608 inline void z_clrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint32 -- z10 1609 inline void z_clgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint64 -- z10 1610 inline void z_clfit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint32 -- z10 1611 inline void z_clgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint64 -- z10 1612 1613 inline void z_illtrap(); 1614 inline void z_illtrap(int id); 1615 inline void z_illtrap_eyecatcher(unsigned short xpattern, unsigned short pattern); 1616 1617 1618 // load address, add for addresses 1619 // =============================== 1620 1621 // The versions without suffix z assert that the base reg is != Z_R0. 1622 // Z_R0 is interpreted as constant '0'. The variants with Address operand 1623 // check this automatically, so no two versions are needed. 1624 inline void z_layz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1625 inline void z_lay(Register r1, const Address &a); // r1 = a 1626 inline void z_lay(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_imm20+x2+b2 1627 inline void z_laz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg. 1628 inline void z_la(Register r1, const Address &a); // r1 = a ; unsigned immediate! 1629 inline void z_la(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_uimm12+x2+b2 ; unsigned immediate! 1630 inline void z_larl(Register r1, int64_t i2); // r1 = pc + i2_imm32<<1; 1631 inline void z_larl(Register r1, address a2); // r1 = pc + i2_imm32<<1; 1632 1633 // Load instructions for integers 1634 // ============================== 1635 1636 // Address as base + index + offset 1637 inline void z_lb( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int8 1638 inline void z_lb( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int8 1639 inline void z_lh( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1640 inline void z_lh( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 <- int16 1641 inline void z_lhy(Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16 1642 inline void z_lhy(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int16 1643 inline void z_l( Register r1, const Address& a); // load r1 = *(a) ; int32 1644 inline void z_l( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 1645 inline void z_ly( Register r1, const Address& a); // load r1 = *(a) ; int32 1646 inline void z_ly( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 1647 1648 inline void z_lgb(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int8 1649 inline void z_lgb(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int8 1650 inline void z_lgh(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int16 1651 inline void z_lgh(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm12+x2+b2) ; int64 <- int16 1652 inline void z_lgf(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int32 1653 inline void z_lgf(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1654 inline void z_lg( Register r1, const Address& a); // load r1 = *(a) ; int64 <- int64 1655 inline void z_lg( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int64 1656 1657 // load and test 1658 inline void z_lt( Register r1, const Address &a); // load and test r1 = *(a) ; int32 1659 inline void z_lt( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int32 1660 inline void z_ltg( Register r1, const Address &a); // load and test r1 = *(a) ; int64 1661 inline void z_ltg( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 1662 inline void z_ltgf(Register r1, const Address &a); // load and test r1 = *(a) ; int64 <- int32 1663 inline void z_ltgf(Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 <- int32 1664 1665 // load unsigned integer - zero extended 1666 inline void z_llc( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint8 1667 inline void z_llc( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint8 1668 inline void z_llh( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint16 1669 inline void z_llh( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint16 1670 inline void z_llgc(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint8 1671 inline void z_llgc(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint8 1672 inline void z_llgc( Register r1, int64_t d2, Register b2); // load r1 = *(d2_imm20+b2) ; uint64 <- uint8 1673 inline void z_llgh(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint16 1674 inline void z_llgh(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint16 1675 inline void z_llgf(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint32 1676 inline void z_llgf(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint32 1677 1678 // pc relative addressing 1679 inline void z_lhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 <- int16 -- z10 1680 inline void z_lrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 -- z10 1681 inline void z_lghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int16 -- z10 1682 inline void z_lgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int32 -- z10 1683 inline void z_lgrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 -- z10 1684 1685 inline void z_llhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint32 <- uint16 -- z10 1686 inline void z_llghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint16 -- z10 1687 inline void z_llgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint32 -- z10 1688 1689 // Store instructions for integers 1690 // =============================== 1691 1692 // Address as base + index + offset 1693 inline void z_stc( Register r1, const Address &d); // store *(a) = r1 ; int8 1694 inline void z_stc( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int8 1695 inline void z_stcy(Register r1, const Address &d); // store *(a) = r1 ; int8 1696 inline void z_stcy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int8 1697 inline void z_sth( Register r1, const Address &d); // store *(a) = r1 ; int16 1698 inline void z_sth( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int16 1699 inline void z_sthy(Register r1, const Address &d); // store *(a) = r1 ; int16 1700 inline void z_sthy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int16 1701 inline void z_st( Register r1, const Address &d); // store *(a) = r1 ; int32 1702 inline void z_st( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int32 1703 inline void z_sty( Register r1, const Address &d); // store *(a) = r1 ; int32 1704 inline void z_sty( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int32 1705 inline void z_stg( Register r1, const Address &d); // store *(a) = r1 ; int64 1706 inline void z_stg( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int64 1707 1708 inline void z_stcm( Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1709 inline void z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1710 inline void z_stcmh(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask 1711 1712 // pc relative addressing 1713 inline void z_sthrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int16 -- z10 1714 inline void z_strl( Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int32 -- z10 1715 inline void z_stgrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int64 -- z10 1716 1717 1718 // Load and store immediates 1719 // ========================= 1720 1721 // load immediate 1722 inline void z_lhi( Register r1, int64_t i2); // r1 = i2_imm16 ; int32 <- int16 1723 inline void z_lghi(Register r1, int64_t i2); // r1 = i2_imm16 ; int64 <- int16 1724 inline void z_lgfi(Register r1, int64_t i2); // r1 = i2_imm32 ; int64 <- int32 1725 1726 inline void z_llihf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- (uint32<<32) 1727 inline void z_llilf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- uint32 1728 inline void z_llihh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<48) 1729 inline void z_llihl(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<32) 1730 inline void z_llilh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<16) 1731 inline void z_llill(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- uint16 1732 1733 // insert immediate 1734 inline void z_ic( Register r1, int64_t d2, Register x2, Register b2); // insert character 1735 inline void z_icy( Register r1, int64_t d2, Register x2, Register b2); // insert character 1736 inline void z_icm( Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1737 inline void z_icmy(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1738 inline void z_icmh(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask 1739 1740 inline void z_iihh(Register r1, int64_t i2); // insert immediate r1[ 0-15] = i2_imm16 1741 inline void z_iihl(Register r1, int64_t i2); // insert immediate r1[16-31] = i2_imm16 1742 inline void z_iilh(Register r1, int64_t i2); // insert immediate r1[32-47] = i2_imm16 1743 inline void z_iill(Register r1, int64_t i2); // insert immediate r1[48-63] = i2_imm16 1744 inline void z_iihf(Register r1, int64_t i2); // insert immediate r1[32-63] = i2_imm32 1745 inline void z_iilf(Register r1, int64_t i2); // insert immediate r1[ 0-31] = i2_imm32 1746 1747 // store immediate 1748 inline void z_mvhhi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int16 1749 inline void z_mvhhi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int16 1750 inline void z_mvhi( const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int32 1751 inline void z_mvhi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int32 1752 inline void z_mvghi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int64 1753 inline void z_mvghi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int64 1754 1755 // Move and Convert instructions 1756 // ============================= 1757 1758 // move, sign extend 1759 inline void z_lbr(Register r1, Register r2); // move r1 = r2 ; int32 <- int8 1760 inline void z_lhr( Register r1, Register r2); // move r1 = r2 ; int32 <- int16 1761 inline void z_lr(Register r1, Register r2); // move r1 = r2 ; int32, no sign extension 1762 inline void z_lgbr(Register r1, Register r2); // move r1 = r2 ; int64 <- int8 1763 inline void z_lghr(Register r1, Register r2); // move r1 = r2 ; int64 <- int16 1764 inline void z_lgfr(Register r1, Register r2); // move r1 = r2 ; int64 <- int32 1765 inline void z_lgr(Register r1, Register r2); // move r1 = r2 ; int64 1766 // move, zero extend 1767 inline void z_llhr( Register r1, Register r2); // move r1 = r2 ; uint32 <- uint16 1768 inline void z_llgcr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint8 1769 inline void z_llghr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint16 1770 inline void z_llgfr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint32 1771 1772 // move and test register 1773 inline void z_ltr(Register r1, Register r2); // load/move and test r1 = r2; int32 1774 inline void z_ltgr(Register r1, Register r2); // load/move and test r1 = r2; int64 1775 inline void z_ltgfr(Register r1, Register r2); // load/move and test r1 = r2; int64 <-- int32 1776 1777 // move and byte-reverse 1778 inline void z_lrvr( Register r1, Register r2); // move and reverse byte order r1 = r2; int32 1779 inline void z_lrvgr(Register r1, Register r2); // move and reverse byte order r1 = r2; int64 1780 1781 1782 // Arithmetic instructions (Integer only) 1783 // ====================================== 1784 // For float arithmetic instructions scroll further down 1785 // Add logical differs in the condition codes set! 1786 1787 // add registers 1788 inline void z_ar( Register r1, Register r2); // add r1 = r1 + r2 ; int32 1789 inline void z_agr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 1790 inline void z_agfr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 <- int32 1791 inline void z_ark( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int32 1792 inline void z_agrk( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int64 1793 1794 inline void z_alr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int32 1795 inline void z_algr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 1796 inline void z_algfr(Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 <- int32 1797 inline void z_alrk( Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int32 1798 inline void z_algrk(Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int64 1799 inline void z_alcgr(Register r1, Register r2); // add logical with carry r1 = r1 + r2 + c ; int64 1800 1801 // add immediate 1802 inline void z_ahi( Register r1, int64_t i2); // add r1 = r1 + i2_imm16 ; int32 1803 inline void z_afi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 1804 inline void z_alfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 1805 inline void z_aghi( Register r1, int64_t i2); // add logical r1 = r1 + i2_imm16 ; int64 1806 inline void z_agfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int64 1807 inline void z_algfi(Register r1, int64_t i2); // add logical r1 = r1 + i2_imm32 ; int64 1808 inline void z_ahik( Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int32 1809 inline void z_aghik(Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int64 1810 inline void z_aih( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 (HiWord) 1811 1812 // add memory 1813 inline void z_a( Register r1, int64_t d2, Register x2, Register b2); // add r1 = r1 + *(d2_uimm12+s2+b2) ; int32 1814 inline void z_ay( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int32 1815 inline void z_ag( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int64 1816 inline void z_agf( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 1817 inline void z_al( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_uimm12+x2+b2) ; int32 1818 inline void z_aly( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int32 1819 inline void z_alg( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 1820 inline void z_algf(Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32 1821 inline void z_a( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1822 inline void z_ay( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1823 inline void z_al( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1824 inline void z_aly( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32 1825 inline void z_ag( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 1826 inline void z_agf( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 1827 inline void z_alg( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 1828 inline void z_algf(Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32 1829 1830 1831 inline void z_alhsik( Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int32 1832 inline void z_alghsik(Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int64 1833 1834 inline void z_asi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int32 -- z10 1835 inline void z_agsi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int64 -- z10 1836 inline void z_alsi( int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint32 -- z10 1837 inline void z_algsi(int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint64 -- z10 1838 inline void z_asi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int32 -- z10 1839 inline void z_agsi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int64 -- z10 1840 inline void z_alsi( const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint32 -- z10 1841 inline void z_algsi(const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint64 -- z10 1842 1843 // negate 1844 inline void z_lcr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int32 1845 inline void z_lcgr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int64 1846 inline void z_lcgfr(Register r1, Register r2); // neg r1 = -r2 ; int64 <- int32 1847 inline void z_lnr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int32 1848 inline void z_lngr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int64 1849 inline void z_lngfr(Register r1, Register r2); // neg r1 = -|r2| ; int64 <- int32 1850 1851 // subtract intstructions 1852 // sub registers 1853 inline void z_sr( Register r1, Register r2); // sub r1 = r1 - r2 ; int32 1854 inline void z_sgr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 1855 inline void z_sgfr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 <- int32 1856 inline void z_srk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int32 1857 inline void z_sgrk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int64 1858 1859 inline void z_slr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int32 1860 inline void z_slgr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 1861 inline void z_slgfr(Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 <- int32 1862 inline void z_slrk( Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int32 1863 inline void z_slgrk(Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int64 1864 inline void z_slfi( Register r1, int64_t i2); // sub logical r1 = r1 - i2_uimm32 ; int32 1865 inline void z_slgfi(Register r1, int64_t i2); // add logical r1 = r1 - i2_uimm32 ; int64 1866 1867 // sub memory 1868 inline void z_s( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 1869 inline void z_sy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 + *(d2_imm20+s2+b2) ; int32 1870 inline void z_sg( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 1871 inline void z_sgf( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 - int32 1872 inline void z_slg( Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 1873 inline void z_slgf(Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 - uint32 1874 inline void z_s( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 1875 inline void z_sy( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32 1876 inline void z_sg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 1877 inline void z_sgf( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 - int32 1878 inline void z_slg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 1879 inline void z_slgf(Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 - uint32 1880 1881 inline void z_sh( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 1882 inline void z_shy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 1883 inline void z_sh( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16 1884 inline void z_shy( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16 1885 1886 // Multiplication instructions 1887 // mul registers 1888 inline void z_msr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 1889 inline void z_msgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 1890 inline void z_msgfr(Register r1, Register r2); // mul r1 = r1 * r2 ; int64 <- int32 1891 inline void z_mlr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 unsigned 1892 inline void z_mlgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 unsigned 1893 // mul register - memory 1894 inline void z_mhy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1895 inline void z_msy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1896 inline void z_msg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1897 inline void z_msgf(Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1898 inline void z_ml( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1899 inline void z_mlg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2) 1900 inline void z_mhy( Register r1, const Address& a); // mul r1 = r1 * *(a) 1901 inline void z_msy( Register r1, const Address& a); // mul r1 = r1 * *(a) 1902 inline void z_msg( Register r1, const Address& a); // mul r1 = r1 * *(a) 1903 inline void z_msgf(Register r1, const Address& a); // mul r1 = r1 * *(a) 1904 inline void z_ml( Register r1, const Address& a); // mul r1 = r1 * *(a) 1905 inline void z_mlg( Register r1, const Address& a); // mul r1 = r1 * *(a) 1906 1907 inline void z_msfi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int32 -- z10 1908 inline void z_msgfi(Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int64 -- z10 1909 inline void z_mhi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int32 1910 inline void z_mghi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int64 1911 1912 // Division instructions 1913 inline void z_dsgr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 1914 inline void z_dsgfr(Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair! 1915 1916 1917 // Logic instructions 1918 // =================== 1919 1920 // and 1921 inline void z_n( Register r1, int64_t d2, Register x2, Register b2); 1922 inline void z_ny( Register r1, int64_t d2, Register x2, Register b2); 1923 inline void z_ng( Register r1, int64_t d2, Register x2, Register b2); 1924 inline void z_n( Register r1, const Address& a); 1925 inline void z_ny( Register r1, const Address& a); 1926 inline void z_ng( Register r1, const Address& a); 1927 1928 inline void z_nr( Register r1, Register r2); // and r1 = r1 & r2 ; int32 1929 inline void z_ngr( Register r1, Register r2); // and r1 = r1 & r2 ; int64 1930 inline void z_nrk( Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int32 1931 inline void z_ngrk(Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int64 1932 1933 inline void z_nihh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 0-15 1934 inline void z_nihl(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 16-31 1935 inline void z_nilh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 32-47 1936 inline void z_nill(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 48-63 1937 inline void z_nihf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 0-31 1938 inline void z_nilf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 32-63 see also MacroAssembler::nilf. 1939 1940 // or 1941 inline void z_o( Register r1, int64_t d2, Register x2, Register b2); 1942 inline void z_oy( Register r1, int64_t d2, Register x2, Register b2); 1943 inline void z_og( Register r1, int64_t d2, Register x2, Register b2); 1944 inline void z_o( Register r1, const Address& a); 1945 inline void z_oy( Register r1, const Address& a); 1946 inline void z_og( Register r1, const Address& a); 1947 1948 inline void z_or( Register r1, Register r2); // or r1 = r1 | r2; int32 1949 inline void z_ogr( Register r1, Register r2); // or r1 = r1 | r2; int64 1950 inline void z_ork( Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int32 1951 inline void z_ogrk(Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int64 1952 1953 inline void z_oihh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 0-15 1954 inline void z_oihl(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 16-31 1955 inline void z_oilh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 32-47 1956 inline void z_oill(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 48-63 1957 inline void z_oihf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 0-31 1958 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63 1959 1960 // xor 1961 inline void z_x( Register r1, int64_t d2, Register x2, Register b2); 1962 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2); 1963 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2); 1964 inline void z_x( Register r1, const Address& a); 1965 inline void z_xy( Register r1, const Address& a); 1966 inline void z_xg( Register r1, const Address& a); 1967 1968 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32 1969 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64 1970 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32 1971 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64 1972 1973 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31 1974 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63 1975 1976 // shift 1977 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved! 1978 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved! 1979 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended 1980 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended 1981 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added 1982 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added 1983 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended 1984 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended 1985 1986 // rotate 1987 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10 1988 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10 1989 1990 // rotate the AND/XOR/OR/insert 1991 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196 1992 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196 1993 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196 1994 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196 1995 1996 1997 // memory-immediate instructions (8-bit immediate) 1998 // =============================================== 1999 2000 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 2001 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 2002 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 2003 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 2004 inline void z_oi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 2005 inline void z_xi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 2006 inline void z_cliy(int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8 2007 inline void z_mviy(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8 2008 inline void z_tmy( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8 2009 inline void z_niy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8 2010 inline void z_oiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8 2011 inline void z_xiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8 2012 inline void z_cli( const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2013 inline void z_mvi( const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2014 inline void z_tm( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2015 inline void z_ni( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2016 inline void z_oi( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2017 inline void z_xi( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2018 inline void z_cliy(const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8 2019 inline void z_mviy(const Address& a, int64_t imm8); // store *(a) = imm8 ; int8 2020 inline void z_tmy( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8 2021 inline void z_niy( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8 2022 inline void z_oiy( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8 2023 inline void z_xiy( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8 2024 2025 2026 //------------------------------ 2027 // Interlocked-Update 2028 //------------------------------ 2029 inline void z_laa( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, signed -- z196 2030 inline void z_laag( Register r1, Register r3, int64_t d2, Register b2); // load and add int64, signed -- z196 2031 inline void z_laal( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, unsigned -- z196 2032 inline void z_laalg(Register r1, Register r3, int64_t d2, Register b2); // load and add int64, unsigned -- z196 2033 inline void z_lan( Register r1, Register r3, int64_t d2, Register b2); // load and and int32 -- z196 2034 inline void z_lang( Register r1, Register r3, int64_t d2, Register b2); // load and and int64 -- z196 2035 inline void z_lax( Register r1, Register r3, int64_t d2, Register b2); // load and xor int32 -- z196 2036 inline void z_laxg( Register r1, Register r3, int64_t d2, Register b2); // load and xor int64 -- z196 2037 inline void z_lao( Register r1, Register r3, int64_t d2, Register b2); // load and or int32 -- z196 2038 inline void z_laog( Register r1, Register r3, int64_t d2, Register b2); // load and or int64 -- z196 2039 2040 inline void z_laa( Register r1, Register r3, const Address& a); // load and add int32, signed -- z196 2041 inline void z_laag( Register r1, Register r3, const Address& a); // load and add int64, signed -- z196 2042 inline void z_laal( Register r1, Register r3, const Address& a); // load and add int32, unsigned -- z196 2043 inline void z_laalg(Register r1, Register r3, const Address& a); // load and add int64, unsigned -- z196 2044 inline void z_lan( Register r1, Register r3, const Address& a); // load and and int32 -- z196 2045 inline void z_lang( Register r1, Register r3, const Address& a); // load and and int64 -- z196 2046 inline void z_lax( Register r1, Register r3, const Address& a); // load and xor int32 -- z196 2047 inline void z_laxg( Register r1, Register r3, const Address& a); // load and xor int64 -- z196 2048 inline void z_lao( Register r1, Register r3, const Address& a); // load and or int32 -- z196 2049 inline void z_laog( Register r1, Register r3, const Address& a); // load and or int64 -- z196 2050 2051 //-------------------------------- 2052 // Execution Prediction 2053 //-------------------------------- 2054 inline void z_pfd( int64_t m1, int64_t d2, Register x2, Register b2); // prefetch 2055 inline void z_pfd( int64_t m1, Address a); 2056 inline void z_pfdrl(int64_t m1, int64_t i2); // prefetch 2057 inline void z_bpp( int64_t m1, int64_t i2, int64_t d3, Register b3); // branch prediction -- EC12 2058 inline void z_bprp( int64_t m1, int64_t i2, int64_t i3); // branch prediction -- EC12 2059 2060 //------------------------------- 2061 // Transaction Control 2062 //------------------------------- 2063 inline void z_tbegin(int64_t d1, Register b1, int64_t i2); // begin transaction -- EC12 2064 inline void z_tbeginc(int64_t d1, Register b1, int64_t i2); // begin transaction (constrained) -- EC12 2065 inline void z_tend(); // end transaction -- EC12 2066 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12 2067 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12 2068 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12 2069 2070 //--------------------------------- 2071 // Conditional Execution 2072 //--------------------------------- 2073 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196 2074 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196 2075 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196 2076 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196 2077 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196 2078 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196 2079 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196 2080 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196 2081 2082 2083 // Complex CISC instructions 2084 // ========================== 2085 2086 inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32 2087 inline void z_km( Register r1, Register r2); // cipher message 2088 inline void z_kmc( Register r1, Register r2); // cipher message with chaining 2089 inline void z_kimd(Register r1, Register r2); // msg digest (SHA) 2090 inline void z_klmd(Register r1, Register r2); // msg digest (SHA) 2091 inline void z_kmac(Register r1, Register r2); // msg authentication code 2092 2093 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute 2094 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10 2095 inline void z_exrl(Register r1, address a2); // execute relative long -- z10 2096 2097 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time 2098 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute 2099 2100 inline void z_srst(Register r1, Register r2); // search string 2101 inline void z_srstu(Register r1, Register r2); // search string unicode 2102 2103 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes 2104 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes 2105 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory 2106 2107 inline void z_stfle(int64_t d2, Register b2); // store facility list extended 2108 2109 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes 2110 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes 2111 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes 2112 inline void z_nc(Address dst, int64_t len, Address src2); // and *dst = *dst & *src2, ands len bytes in memory 2113 inline void z_oc(Address dst, int64_t len, Address src2); // or *dst = *dst | *src2, ors len bytes in memory 2114 inline void z_xc(Address dst, int64_t len, Address src2); // xor *dst = *dst ^ *src2, xors len bytes in memory 2115 2116 // compare instructions 2117 inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes 2118 inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2); // compare logical long extended, see docu 2119 inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2); // compare logical long unicode, see docu 2120 2121 // Translate characters 2122 inline void z_troo(Register r1, Register r2, int64_t m3); 2123 inline void z_trot(Register r1, Register r2, int64_t m3); 2124 inline void z_trto(Register r1, Register r2, int64_t m3); 2125 inline void z_trtt(Register r1, Register r2, int64_t m3); 2126 2127 2128 // Floatingpoint instructions 2129 // ========================== 2130 2131 // compare instructions 2132 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float 2133 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float 2134 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float 2135 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double 2136 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double 2137 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double 2138 2139 // load instructions 2140 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float 2141 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float 2142 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double 2143 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double 2144 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2145 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float 2146 inline void z_ld( FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2147 inline void z_ldy(FloatRegister r1, const Address &a); // load r1 = *(a) ; double 2148 2149 // store instructions 2150 inline void z_ste( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; float 2151 inline void z_stey(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; float 2152 inline void z_std( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; double 2153 inline void z_stdy(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; double 2154 inline void z_ste( FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2155 inline void z_stey(FloatRegister r1, const Address &a); // store *(a) = r1 ; float 2156 inline void z_std( FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2157 inline void z_stdy(FloatRegister r1, const Address &a); // store *(a) = r1 ; double 2158 2159 // load and store immediates 2160 inline void z_lzer(FloatRegister r1); // r1 = 0 ; single 2161 inline void z_lzdr(FloatRegister r1); // r1 = 0 ; double 2162 2163 // Move and Convert instructions 2164 inline void z_ler(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; float 2165 inline void z_ldr(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; double 2166 inline void z_ledbr(FloatRegister r1, FloatRegister r2); // conv / round r1 = r2 ; float <- double 2167 inline void z_ldebr(FloatRegister r1, FloatRegister r2); // conv r1 = r2 ; double <- float 2168 2169 // move between integer and float registers 2170 inline void z_cefbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int32 2171 inline void z_cdfbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int32 2172 inline void z_cegbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int64 2173 inline void z_cdgbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int64 2174 2175 // rounding mode for float-2-int conversions 2176 inline void z_cfebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- float 2177 inline void z_cfdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- double 2178 inline void z_cgebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- float 2179 inline void z_cgdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- double 2180 2181 inline void z_ldgr(FloatRegister r1, Register r2); // fr1 = r2 ; what kind of conversion? -- z10 2182 inline void z_lgdr(Register r1, FloatRegister r2); // r1 = fr2 ; what kind of conversion? -- z10 2183 2184 2185 // ADD 2186 inline void z_aebr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; float 2187 inline void z_adbr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; double 2188 inline void z_aeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; float 2189 inline void z_adb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; double 2190 inline void z_aeb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; float 2191 inline void z_adb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; double 2192 2193 // SUB 2194 inline void z_sebr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; float 2195 inline void z_sdbr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; double 2196 inline void z_seb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; float 2197 inline void z_sdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; double 2198 inline void z_seb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; float 2199 inline void z_sdb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; double 2200 // negate 2201 inline void z_lcebr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; float 2202 inline void z_lcdbr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; double 2203 2204 // Absolute value, monadic if fr2 == noreg. 2205 inline void z_lpdbr( FloatRegister fr1, FloatRegister fr2 = fnoreg); // fr1 = |fr2| 2206 2207 2208 // MUL 2209 inline void z_meebr(FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; float 2210 inline void z_mdbr( FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; double 2211 inline void z_meeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; float 2212 inline void z_mdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; double 2213 inline void z_meeb( FloatRegister f1, const Address& a); 2214 inline void z_mdb( FloatRegister f1, const Address& a); 2215 2216 // MUL-ADD 2217 inline void z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; float 2218 inline void z_madbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; double 2219 inline void z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; float 2220 inline void z_msdbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; double 2221 inline void z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; float 2222 inline void z_madb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; double 2223 inline void z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; float 2224 inline void z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; double 2225 inline void z_maeb(FloatRegister f1, FloatRegister f3, const Address& a); 2226 inline void z_madb(FloatRegister f1, FloatRegister f3, const Address& a); 2227 inline void z_mseb(FloatRegister f1, FloatRegister f3, const Address& a); 2228 inline void z_msdb(FloatRegister f1, FloatRegister f3, const Address& a); 2229 2230 // DIV 2231 inline void z_debr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; float 2232 inline void z_ddbr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; double 2233 inline void z_deb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; float 2234 inline void z_ddb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; double 2235 inline void z_deb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; float 2236 inline void z_ddb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; double 2237 2238 // square root 2239 inline void z_sqdbr(FloatRegister fr1, FloatRegister fr2); // fr1 = sqrt(fr2) ; double 2240 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register x2, Register b2); // fr1 = srqt( *(d2+x2+b2) 2241 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register b2); // fr1 = srqt( *(d2+b2) 2242 2243 // Nop instruction 2244 // =============== 2245 2246 // branch never (nop) 2247 inline void z_nop(); 2248 2249 // =============================================================================================== 2250 2251 // Simplified emitters: 2252 // ==================== 2253 2254 2255 // Some memory instructions without index register (just convenience). 2256 inline void z_layz(Register r1, int64_t d2, Register b2 = Z_R0); 2257 inline void z_lay(Register r1, int64_t d2, Register b2); 2258 inline void z_laz(Register r1, int64_t d2, Register b2); 2259 inline void z_la(Register r1, int64_t d2, Register b2); 2260 inline void z_l(Register r1, int64_t d2, Register b2); 2261 inline void z_ly(Register r1, int64_t d2, Register b2); 2262 inline void z_lg(Register r1, int64_t d2, Register b2); 2263 inline void z_st(Register r1, int64_t d2, Register b2); 2264 inline void z_sty(Register r1, int64_t d2, Register b2); 2265 inline void z_stg(Register r1, int64_t d2, Register b2); 2266 inline void z_lgf(Register r1, int64_t d2, Register b2); 2267 inline void z_lgh(Register r1, int64_t d2, Register b2); 2268 inline void z_llgh(Register r1, int64_t d2, Register b2); 2269 inline void z_llgf(Register r1, int64_t d2, Register b2); 2270 inline void z_lgb(Register r1, int64_t d2, Register b2); 2271 inline void z_cl( Register r1, int64_t d2, Register b2); 2272 inline void z_c(Register r1, int64_t d2, Register b2); 2273 inline void z_cg(Register r1, int64_t d2, Register b2); 2274 inline void z_sh(Register r1, int64_t d2, Register b2); 2275 inline void z_shy(Register r1, int64_t d2, Register b2); 2276 inline void z_ste(FloatRegister r1, int64_t d2, Register b2); 2277 inline void z_std(FloatRegister r1, int64_t d2, Register b2); 2278 inline void z_stdy(FloatRegister r1, int64_t d2, Register b2); 2279 inline void z_stey(FloatRegister r1, int64_t d2, Register b2); 2280 inline void z_ld(FloatRegister r1, int64_t d2, Register b2); 2281 inline void z_ldy(FloatRegister r1, int64_t d2, Register b2); 2282 inline void z_le(FloatRegister r1, int64_t d2, Register b2); 2283 inline void z_ley(FloatRegister r1, int64_t d2, Register b2); 2284 2285 inline void z_agf(Register r1, int64_t d2, Register b2); 2286 2287 inline void z_exrl(Register r1, Label& L); 2288 inline void z_larl(Register r1, Label& L); 2289 inline void z_bru( Label& L); 2290 inline void z_brul(Label& L); 2291 inline void z_brul(address a); 2292 inline void z_brh( Label& L); 2293 inline void z_brl( Label& L); 2294 inline void z_bre( Label& L); 2295 inline void z_brnh(Label& L); 2296 inline void z_brnl(Label& L); 2297 inline void z_brne(Label& L); 2298 inline void z_brz( Label& L); 2299 inline void z_brnz(Label& L); 2300 inline void z_brnaz(Label& L); 2301 inline void z_braz(Label& L); 2302 inline void z_brnp(Label& L); 2303 2304 inline void z_btrue( Label& L); 2305 inline void z_bfalse(Label& L); 2306 2307 inline void z_brno( Label& L); 2308 2309 2310 inline void z_basr(Register r1, Register r2); 2311 inline void z_brasl(Register r1, address a); 2312 inline void z_brct(Register r1, address a); 2313 inline void z_brct(Register r1, Label& L); 2314 2315 inline void z_brxh(Register r1, Register r3, address a); 2316 inline void z_brxh(Register r1, Register r3, Label& L); 2317 2318 inline void z_brxle(Register r1, Register r3, address a); 2319 inline void z_brxle(Register r1, Register r3, Label& L); 2320 2321 inline void z_brxhg(Register r1, Register r3, address a); 2322 inline void z_brxhg(Register r1, Register r3, Label& L); 2323 2324 inline void z_brxlg(Register r1, Register r3, address a); 2325 inline void z_brxlg(Register r1, Register r3, Label& L); 2326 2327 // Ppopulation count intrinsics. 2328 inline void z_flogr(Register r1, Register r2); // find leftmost one 2329 inline void z_popcnt(Register r1, Register r2); // population count 2330 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high 2331 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low 2332 2333 inline void z_tam(); 2334 inline void z_stck(int64_t d2, Register b2); 2335 inline void z_stckf(int64_t d2, Register b2); 2336 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2); 2337 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2); 2338 2339 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2); 2340 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2); 2341 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2); 2342 inline void z_cs( Register r1, Register r3, const Address& a); 2343 inline void z_csy(Register r1, Register r3, const Address& a); 2344 inline void z_csg(Register r1, Register r3, const Address& a); 2345 2346 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2); 2347 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2); 2348 inline void z_cvd(Register r1, int64_t d2, Register b2); 2349 inline void z_cvdg(Register r1, int64_t d2, Register b2); 2350 2351 // Instruction queries: 2352 // instruction properties and recognize emitted instructions 2353 // =========================================================== 2354 2355 static int nop_size() { return 2; } 2356 2357 static int z_brul_size() { return 6; } 2358 2359 static bool is_z_basr(short x) { 2360 return (BASR_ZOPC == (x & BASR_MASK)); 2361 } 2362 static bool is_z_algr(long x) { 2363 return (ALGR_ZOPC == (x & RRE_MASK)); 2364 } 2365 static bool is_z_lb(long x) { 2366 return (LB_ZOPC == (x & LB_MASK)); 2367 } 2368 static bool is_z_lh(int x) { 2369 return (LH_ZOPC == (x & LH_MASK)); 2370 } 2371 static bool is_z_l(int x) { 2372 return (L_ZOPC == (x & L_MASK)); 2373 } 2374 static bool is_z_lgr(long x) { 2375 return (LGR_ZOPC == (x & RRE_MASK)); 2376 } 2377 static bool is_z_ly(long x) { 2378 return (LY_ZOPC == (x & LY_MASK)); 2379 } 2380 static bool is_z_lg(long x) { 2381 return (LG_ZOPC == (x & LG_MASK)); 2382 } 2383 static bool is_z_llgh(long x) { 2384 return (LLGH_ZOPC == (x & LLGH_MASK)); 2385 } 2386 static bool is_z_llgf(long x) { 2387 return (LLGF_ZOPC == (x & LLGF_MASK)); 2388 } 2389 static bool is_z_le(int x) { 2390 return (LE_ZOPC == (x & LE_MASK)); 2391 } 2392 static bool is_z_ld(int x) { 2393 return (LD_ZOPC == (x & LD_MASK)); 2394 } 2395 static bool is_z_st(int x) { 2396 return (ST_ZOPC == (x & ST_MASK)); 2397 } 2398 static bool is_z_stc(int x) { 2399 return (STC_ZOPC == (x & STC_MASK)); 2400 } 2401 static bool is_z_stg(long x) { 2402 return (STG_ZOPC == (x & STG_MASK)); 2403 } 2404 static bool is_z_sth(int x) { 2405 return (STH_ZOPC == (x & STH_MASK)); 2406 } 2407 static bool is_z_ste(int x) { 2408 return (STE_ZOPC == (x & STE_MASK)); 2409 } 2410 static bool is_z_std(int x) { 2411 return (STD_ZOPC == (x & STD_MASK)); 2412 } 2413 static bool is_z_slag(long x) { 2414 return (SLAG_ZOPC == (x & SLAG_MASK)); 2415 } 2416 static bool is_z_tmy(long x) { 2417 return (TMY_ZOPC == (x & TMY_MASK)); 2418 } 2419 static bool is_z_tm(long x) { 2420 return ((unsigned int)TM_ZOPC == (x & (unsigned int)TM_MASK)); 2421 } 2422 static bool is_z_bcr(long x) { 2423 return (BCR_ZOPC == (x & BCR_MASK)); 2424 } 2425 static bool is_z_nop(long x) { 2426 return is_z_bcr(x) && ((x & 0x00ff) == 0); 2427 } 2428 static bool is_z_nop(address x) { 2429 return is_z_nop(* (short *) x); 2430 } 2431 static bool is_z_br(long x) { 2432 return is_z_bcr(x) && ((x & 0x00f0) == 0x00f0); 2433 } 2434 static bool is_z_brc(long x, int cond) { 2435 return ((unsigned int)BRC_ZOPC == (x & BRC_MASK)) && ((cond<<20) == (x & 0x00f00000U)); 2436 } 2437 // Make use of lightweight sync. 2438 static bool is_z_sync_full(long x) { 2439 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondFullSync) && ((x & 0x000f)==0x0000); 2440 } 2441 static bool is_z_sync_light(long x) { 2442 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondLightSync) && ((x & 0x000f)==0x0000); 2443 } 2444 static bool is_z_sync(long x) { 2445 return is_z_sync_full(x) || is_z_sync_light(x); 2446 } 2447 2448 static bool is_z_brasl(long x) { 2449 return (BRASL_ZOPC == (x & BRASL_MASK)); 2450 } 2451 static bool is_z_brasl(address a) { 2452 long x = (*((long *)a))>>16; 2453 return is_z_brasl(x); 2454 } 2455 static bool is_z_larl(long x) { 2456 return (LARL_ZOPC == (x & LARL_MASK)); 2457 } 2458 static bool is_z_lgrl(long x) { 2459 return (LGRL_ZOPC == (x & LGRL_MASK)); 2460 } 2461 static bool is_z_lgrl(address a) { 2462 long x = (*((long *)a))>>16; 2463 return is_z_lgrl(x); 2464 } 2465 2466 static bool is_z_lghi(unsigned long x) { 2467 return (unsigned int)LGHI_ZOPC == (x & (unsigned int)LGHI_MASK); 2468 } 2469 2470 static bool is_z_llill(unsigned long x) { 2471 return (unsigned int)LLILL_ZOPC == (x & (unsigned int)LLI_MASK); 2472 } 2473 static bool is_z_llilh(unsigned long x) { 2474 return (unsigned int)LLILH_ZOPC == (x & (unsigned int)LLI_MASK); 2475 } 2476 static bool is_z_llihl(unsigned long x) { 2477 return (unsigned int)LLIHL_ZOPC == (x & (unsigned int)LLI_MASK); 2478 } 2479 static bool is_z_llihh(unsigned long x) { 2480 return (unsigned int)LLIHH_ZOPC == (x & (unsigned int)LLI_MASK); 2481 } 2482 static bool is_z_llilf(unsigned long x) { 2483 return LLILF_ZOPC == (x & LLIF_MASK); 2484 } 2485 static bool is_z_llihf(unsigned long x) { 2486 return LLIHF_ZOPC == (x & LLIF_MASK); 2487 } 2488 2489 static bool is_z_iill(unsigned long x) { 2490 return (unsigned int)IILL_ZOPC == (x & (unsigned int)II_MASK); 2491 } 2492 static bool is_z_iilh(unsigned long x) { 2493 return (unsigned int)IILH_ZOPC == (x & (unsigned int)II_MASK); 2494 } 2495 static bool is_z_iihl(unsigned long x) { 2496 return (unsigned int)IIHL_ZOPC == (x & (unsigned int)II_MASK); 2497 } 2498 static bool is_z_iihh(unsigned long x) { 2499 return (unsigned int)IIHH_ZOPC == (x & (unsigned int)II_MASK); 2500 } 2501 static bool is_z_iilf(unsigned long x) { 2502 return IILF_ZOPC == (x & IIF_MASK); 2503 } 2504 static bool is_z_iihf(unsigned long x) { 2505 return IIHF_ZOPC == (x & IIF_MASK); 2506 } 2507 2508 static inline bool is_equal(unsigned long inst, unsigned long idef); 2509 static inline bool is_equal(unsigned long inst, unsigned long idef, unsigned long imask); 2510 static inline bool is_equal(address iloc, unsigned long idef); 2511 static inline bool is_equal(address iloc, unsigned long idef, unsigned long imask); 2512 2513 static inline bool is_sigtrap_range_check(address pc); 2514 static inline bool is_sigtrap_zero_check(address pc); 2515 2516 //----------------- 2517 // memory barriers 2518 //----------------- 2519 // machine barrier instructions: 2520 // 2521 // - z_sync Two-way memory barrier, aka fence. 2522 // Only load-after-store-order is not guaranteed in the 2523 // z/Architecture memory model, i.e. only 'fence' is needed. 2524 // 2525 // semantic barrier instructions: 2526 // (as defined in orderAccess.hpp) 2527 // 2528 // - z_release orders Store|Store, empty implementation 2529 // Load|Store 2530 // - z_acquire orders Load|Store, empty implementation 2531 // Load|Load 2532 // - z_fence orders Store|Store, implemented as z_sync. 2533 // Load|Store, 2534 // Load|Load, 2535 // Store|Load 2536 // 2537 // For this implementation to be correct, we need H/W fixes on (very) old H/W: 2538 // For z990, it is Driver-55: MCL232 in the J13484 (i390/ML) Stream. 2539 // For z9, it is Driver-67: MCL065 in the G40963 (i390/ML) Stream. 2540 // These drivers are a prereq. Otherwise, memory synchronization will not work. 2541 2542 inline void z_sync(); 2543 inline void z_release(); 2544 inline void z_acquire(); 2545 inline void z_fence(); 2546 2547 // Creation 2548 Assembler(CodeBuffer* code) : AbstractAssembler(code) { } 2549 2550}; 2551 2552#endif // CPU_S390_VM_ASSEMBLER_S390_HPP 2553