1/* 2 * Copyright (c) 2002, 2015, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2015 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26#ifndef CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP 27#define CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP 28 29#include "asm/assembler.inline.hpp" 30#include "asm/macroAssembler.hpp" 31#include "asm/codeBuffer.hpp" 32#include "code/codeCache.hpp" 33 34inline bool MacroAssembler::is_ld_largeoffset(address a) { 35 const int inst1 = *(int *)a; 36 const int inst2 = *(int *)(a+4); 37 return (is_ld(inst1)) || 38 (is_addis(inst1) && is_ld(inst2) && inv_ra_field(inst2) == inv_rt_field(inst1)); 39} 40 41inline int MacroAssembler::get_ld_largeoffset_offset(address a) { 42 assert(MacroAssembler::is_ld_largeoffset(a), "must be ld with large offset"); 43 44 const int inst1 = *(int *)a; 45 if (is_ld(inst1)) { 46 return inv_d1_field(inst1); 47 } else { 48 const int inst2 = *(int *)(a+4); 49 return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2); 50 } 51} 52 53inline void MacroAssembler::round_to(Register r, int modulus) { 54 assert(is_power_of_2_long((jlong)modulus), "must be power of 2"); 55 addi(r, r, modulus-1); 56 clrrdi(r, r, log2_long((jlong)modulus)); 57} 58 59// Move register if destination register and target register are different. 60inline void MacroAssembler::mr_if_needed(Register rd, Register rs) { 61 if (rs != rd) mr(rd, rs); 62} 63inline void MacroAssembler::fmr_if_needed(FloatRegister rd, FloatRegister rs) { 64 if (rs != rd) fmr(rd, rs); 65} 66inline void MacroAssembler::endgroup_if_needed(bool needed) { 67 if (needed) { 68 endgroup(); 69 } 70} 71 72inline void MacroAssembler::membar(int bits) { 73 // Comment: Usage of elemental_membar(bits) is not recommended for Power 8. 74 // If elemental_membar(bits) is used, disable optimization of acquire-release 75 // (Matcher::post_membar_release where we use PPC64_ONLY(xop == Op_MemBarRelease ||))! 76 if (bits & StoreLoad) { sync(); } 77 else if (bits) { lwsync(); } 78} 79inline void MacroAssembler::release() { membar(LoadStore | StoreStore); } 80inline void MacroAssembler::acquire() { membar(LoadLoad | LoadStore); } 81inline void MacroAssembler::fence() { membar(LoadLoad | LoadStore | StoreLoad | StoreStore); } 82 83// Address of the global TOC. 84inline address MacroAssembler::global_toc() { 85 return CodeCache::low_bound(); 86} 87 88// Offset of given address to the global TOC. 89inline int MacroAssembler::offset_to_global_toc(const address addr) { 90 intptr_t offset = (intptr_t)addr - (intptr_t)MacroAssembler::global_toc(); 91 assert(Assembler::is_uimm((long)offset, 31), "must be in range"); 92 return (int)offset; 93} 94 95// Address of current method's TOC. 96inline address MacroAssembler::method_toc() { 97 return code()->consts()->start(); 98} 99 100// Offset of given address to current method's TOC. 101inline int MacroAssembler::offset_to_method_toc(address addr) { 102 intptr_t offset = (intptr_t)addr - (intptr_t)method_toc(); 103 assert(Assembler::is_uimm((long)offset, 31), "must be in range"); 104 return (int)offset; 105} 106 107inline bool MacroAssembler::is_calculate_address_from_global_toc_at(address a, address bound) { 108 const address inst2_addr = a; 109 const int inst2 = *(int *) a; 110 111 // The relocation points to the second instruction, the addi. 112 if (!is_addi(inst2)) return false; 113 114 // The addi reads and writes the same register dst. 115 const int dst = inv_rt_field(inst2); 116 if (inv_ra_field(inst2) != dst) return false; 117 118 // Now, find the preceding addis which writes to dst. 119 int inst1 = 0; 120 address inst1_addr = inst2_addr - BytesPerInstWord; 121 while (inst1_addr >= bound) { 122 inst1 = *(int *) inst1_addr; 123 if (is_addis(inst1) && inv_rt_field(inst1) == dst) { 124 // stop, found the addis which writes dst 125 break; 126 } 127 inst1_addr -= BytesPerInstWord; 128 } 129 130 if (!(inst1 == 0 || inv_ra_field(inst1) == 29 /* R29 */)) return false; 131 return is_addis(inst1); 132} 133 134#ifdef _LP64 135// Detect narrow oop constants. 136inline bool MacroAssembler::is_set_narrow_oop(address a, address bound) { 137 const address inst2_addr = a; 138 const int inst2 = *(int *)a; 139 // The relocation points to the second instruction, the ori. 140 if (!is_ori(inst2)) return false; 141 142 // The ori reads and writes the same register dst. 143 const int dst = inv_rta_field(inst2); 144 if (inv_rs_field(inst2) != dst) return false; 145 146 // Now, find the preceding addis which writes to dst. 147 int inst1 = 0; 148 address inst1_addr = inst2_addr - BytesPerInstWord; 149 while (inst1_addr >= bound) { 150 inst1 = *(int *) inst1_addr; 151 if (is_lis(inst1) && inv_rs_field(inst1) == dst) return true; 152 inst1_addr -= BytesPerInstWord; 153 } 154 return false; 155} 156#endif 157 158 159inline bool MacroAssembler::is_load_const_at(address a) { 160 const int* p_inst = (int *) a; 161 bool b = is_lis(*p_inst++); 162 if (is_ori(*p_inst)) { 163 p_inst++; 164 b = b && is_rldicr(*p_inst++); // TODO: could be made more precise: `sldi'! 165 b = b && is_oris(*p_inst++); 166 b = b && is_ori(*p_inst); 167 } else if (is_lis(*p_inst)) { 168 p_inst++; 169 b = b && is_ori(*p_inst++); 170 b = b && is_ori(*p_inst); 171 // TODO: could enhance reliability by adding is_insrdi 172 } else return false; 173 return b; 174} 175 176inline void MacroAssembler::set_oop_constant(jobject obj, Register d) { 177 set_oop(constant_oop_address(obj), d); 178} 179 180inline void MacroAssembler::set_oop(AddressLiteral obj_addr, Register d) { 181 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 182 load_const(d, obj_addr); 183} 184 185inline void MacroAssembler::pd_patch_instruction(address branch, address target) { 186 jint& stub_inst = *(jint*) branch; 187 stub_inst = patched_branch(target - branch, stub_inst, 0); 188} 189 190// Relocation of conditional far branches. 191inline bool MacroAssembler::is_bc_far_variant1_at(address instruction_addr) { 192 // Variant 1, the 1st instruction contains the destination address: 193 // 194 // bcxx DEST 195 // nop 196 // 197 const int instruction_1 = *(int*)(instruction_addr); 198 const int instruction_2 = *(int*)(instruction_addr + 4); 199 return is_bcxx(instruction_1) && 200 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) != (intptr_t)(instruction_addr + 2*4)) && 201 is_nop(instruction_2); 202} 203 204// Relocation of conditional far branches. 205inline bool MacroAssembler::is_bc_far_variant2_at(address instruction_addr) { 206 // Variant 2, the 2nd instruction contains the destination address: 207 // 208 // b!cxx SKIP 209 // bxx DEST 210 // SKIP: 211 // 212 const int instruction_1 = *(int*)(instruction_addr); 213 const int instruction_2 = *(int*)(instruction_addr + 4); 214 return is_bcxx(instruction_1) && 215 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) == (intptr_t)(instruction_addr + 2*4)) && 216 is_bxx(instruction_2); 217} 218 219// Relocation for conditional branches 220inline bool MacroAssembler::is_bc_far_variant3_at(address instruction_addr) { 221 // Variant 3, far cond branch to the next instruction, already patched to nops: 222 // 223 // nop 224 // endgroup 225 // SKIP/DEST: 226 // 227 const int instruction_1 = *(int*)(instruction_addr); 228 const int instruction_2 = *(int*)(instruction_addr + 4); 229 return is_nop(instruction_1) && 230 is_endgroup(instruction_2); 231} 232 233 234// Convenience bc_far versions 235inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); } 236inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); } 237inline void MacroAssembler::beq_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, equal), L, optimize); } 238inline void MacroAssembler::bso_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, summary_overflow), L, optimize); } 239inline void MacroAssembler::bge_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, less), L, optimize); } 240inline void MacroAssembler::ble_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, greater), L, optimize); } 241inline void MacroAssembler::bne_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, equal), L, optimize); } 242inline void MacroAssembler::bns_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, summary_overflow), L, optimize); } 243 244inline address MacroAssembler::call_stub(Register function_entry) { 245 mtctr(function_entry); 246 bctrl(); 247 return pc(); 248} 249 250inline void MacroAssembler::call_stub_and_return_to(Register function_entry, Register return_pc) { 251 assert_different_registers(function_entry, return_pc); 252 mtlr(return_pc); 253 mtctr(function_entry); 254 bctr(); 255} 256 257// Get the pc where the last emitted call will return to. 258inline address MacroAssembler::last_calls_return_pc() { 259 return _last_calls_return_pc; 260} 261 262// Read from the polling page, its address is already in a register. 263inline void MacroAssembler::load_from_polling_page(Register polling_page_address, int offset) { 264 ld(R0, offset, polling_page_address); 265} 266 267// Trap-instruction-based checks. 268 269inline void MacroAssembler::trap_null_check(Register a, trap_to_bits cmp) { 270 assert(TrapBasedNullChecks, "sanity"); 271 tdi(cmp, a/*reg a*/, 0); 272} 273inline void MacroAssembler::trap_zombie_not_entrant() { 274 tdi(traptoUnconditional, 0/*reg 0*/, 1); 275} 276inline void MacroAssembler::trap_should_not_reach_here() { 277 tdi_unchecked(traptoUnconditional, 0/*reg 0*/, 2); 278} 279 280inline void MacroAssembler::trap_ic_miss_check(Register a, Register b) { 281 td(traptoGreaterThanUnsigned | traptoLessThanUnsigned, a, b); 282} 283 284// Do an explicit null check if access to a+offset will not raise a SIGSEGV. 285// Either issue a trap instruction that raises SIGTRAP, or do a compare that 286// branches to exception_entry. 287// No support for compressed oops (base page of heap). Does not distinguish 288// loads and stores. 289inline void MacroAssembler::null_check_throw(Register a, int offset, Register temp_reg, 290 address exception_entry) { 291 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) { 292 if (TrapBasedNullChecks) { 293 assert(UseSIGTRAP, "sanity"); 294 trap_null_check(a); 295 } else { 296 Label ok; 297 cmpdi(CCR0, a, 0); 298 bne(CCR0, ok); 299 load_const_optimized(temp_reg, exception_entry); 300 mtctr(temp_reg); 301 bctr(); 302 bind(ok); 303 } 304 } 305} 306 307inline void MacroAssembler::null_check(Register a, int offset, Label *Lis_null) { 308 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) { 309 if (TrapBasedNullChecks) { 310 assert(UseSIGTRAP, "sanity"); 311 trap_null_check(a); 312 } else if (Lis_null){ 313 Label ok; 314 cmpdi(CCR0, a, 0); 315 beq(CCR0, *Lis_null); 316 } 317 } 318} 319 320inline void MacroAssembler::load_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1, Register tmp) { 321 if (UseCompressedOops) { 322 // In disjoint mode decoding can save a cycle if src != dst. 323 Register narrowOop = (tmp != noreg && Universe::narrow_oop_base_disjoint()) ? tmp : d; 324 lwz(narrowOop, offs, s1); 325 // Attention: no null check here! 326 Register res = decode_heap_oop_not_null(d, narrowOop); 327 assert(res == d, "caller will not consume loaded value"); 328 } else { 329 ld(d, offs, s1); 330 } 331} 332 333inline void MacroAssembler::store_heap_oop_not_null(Register d, RegisterOrConstant offs, Register s1, Register tmp) { 334 if (UseCompressedOops) { 335 Register compressedOop = encode_heap_oop_not_null((tmp != noreg) ? tmp : d, d); 336 stw(compressedOop, offs, s1); 337 } else { 338 std(d, offs, s1); 339 } 340} 341 342inline void MacroAssembler::load_heap_oop(Register d, RegisterOrConstant offs, Register s1, Label *is_null) { 343 if (UseCompressedOops) { 344 lwz(d, offs, s1); 345 if (is_null != NULL) { 346 cmpwi(CCR0, d, 0); 347 beq(CCR0, *is_null); 348 decode_heap_oop_not_null(d); 349 } else { 350 decode_heap_oop(d); 351 } 352 } else { 353 ld(d, offs, s1); 354 if (is_null != NULL) { 355 cmpdi(CCR0, d, 0); 356 beq(CCR0, *is_null); 357 } 358 } 359} 360 361inline Register MacroAssembler::encode_heap_oop_not_null(Register d, Register src) { 362 Register current = (src != noreg) ? src : d; // Oop to be compressed is in d if no src provided. 363 if (Universe::narrow_oop_base_overlaps()) { 364 sub_const_optimized(d, current, Universe::narrow_oop_base(), R0); 365 current = d; 366 } 367 if (Universe::narrow_oop_shift() != 0) { 368 rldicl(d, current, 64-Universe::narrow_oop_shift(), 32); // Clears the upper bits. 369 current = d; 370 } 371 return current; // Encoded oop is in this register. 372} 373 374inline Register MacroAssembler::encode_heap_oop(Register d, Register src) { 375 if (Universe::narrow_oop_base() != NULL) { 376 if (VM_Version::has_isel()) { 377 cmpdi(CCR0, src, 0); 378 Register co = encode_heap_oop_not_null(d, src); 379 assert(co == d, "sanity"); 380 isel_0(d, CCR0, Assembler::equal); 381 } else { 382 Label isNull; 383 or_(d, src, src); // move and compare 0 384 beq(CCR0, isNull); 385 encode_heap_oop_not_null(d, src); 386 bind(isNull); 387 } 388 return d; 389 } else { 390 return encode_heap_oop_not_null(d, src); 391 } 392} 393 394inline Register MacroAssembler::decode_heap_oop_not_null(Register d, Register src) { 395 if (Universe::narrow_oop_base_disjoint() && src != noreg && src != d && 396 Universe::narrow_oop_shift() != 0) { 397 load_const_optimized(d, Universe::narrow_oop_base(), R0); 398 rldimi(d, src, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 399 return d; 400 } 401 402 Register current = (src != noreg) ? src : d; // Compressed oop is in d if no src provided. 403 if (Universe::narrow_oop_shift() != 0) { 404 sldi(d, current, Universe::narrow_oop_shift()); 405 current = d; 406 } 407 if (Universe::narrow_oop_base() != NULL) { 408 add_const_optimized(d, current, Universe::narrow_oop_base(), R0); 409 current = d; 410 } 411 return current; // Decoded oop is in this register. 412} 413 414inline void MacroAssembler::decode_heap_oop(Register d) { 415 Label isNull; 416 bool use_isel = false; 417 if (Universe::narrow_oop_base() != NULL) { 418 cmpwi(CCR0, d, 0); 419 if (VM_Version::has_isel()) { 420 use_isel = true; 421 } else { 422 beq(CCR0, isNull); 423 } 424 } 425 decode_heap_oop_not_null(d); 426 if (use_isel) { 427 isel_0(d, CCR0, Assembler::equal); 428 } 429 bind(isNull); 430} 431 432// SIGTRAP-based range checks for arrays. 433inline void MacroAssembler::trap_range_check_l(Register a, Register b) { 434 tw (traptoLessThanUnsigned, a/*reg a*/, b/*reg b*/); 435} 436inline void MacroAssembler::trap_range_check_l(Register a, int si16) { 437 twi(traptoLessThanUnsigned, a/*reg a*/, si16); 438} 439inline void MacroAssembler::trap_range_check_le(Register a, int si16) { 440 twi(traptoEqual | traptoLessThanUnsigned, a/*reg a*/, si16); 441} 442inline void MacroAssembler::trap_range_check_g(Register a, int si16) { 443 twi(traptoGreaterThanUnsigned, a/*reg a*/, si16); 444} 445inline void MacroAssembler::trap_range_check_ge(Register a, Register b) { 446 tw (traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, b/*reg b*/); 447} 448inline void MacroAssembler::trap_range_check_ge(Register a, int si16) { 449 twi(traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, si16); 450} 451 452// unsigned integer multiplication 64*64 -> 128 bits 453inline void MacroAssembler::multiply64(Register dest_hi, Register dest_lo, 454 Register x, Register y) { 455 mulld(dest_lo, x, y); 456 mulhdu(dest_hi, x, y); 457} 458 459#if defined(ABI_ELFv2) 460inline address MacroAssembler::function_entry() { return pc(); } 461#else 462inline address MacroAssembler::function_entry() { return emit_fd(); } 463#endif 464 465#endif // CPU_PPC_VM_MACROASSEMBLER_PPC_INLINE_HPP 466