1/* $OpenBSD: zs_ioasic.c,v 1.3 2022/01/09 05:43:00 jsg Exp $ */
2/* $NetBSD: zs_ioasic.c,v 1.40 2009/05/12 13:21:22 cegger Exp $ */
3
4/*-
5 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the
10 * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * Zilog Z8530 Dual UART driver (machine-dependent part).  This driver
36 * handles Z8530 chips attached to the DECstation/Alpha IOASIC.  Modified
37 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe.  NetBSD/pmax
38 * adaption by Mattias Drochner.  Merge work by Tohru Nishimura.
39 *
40 * Runs two serial lines per chip using slave drivers.
41 * Plain tty/async lines use the zstty slave.
42 */
43
44#if 0
45#include "zskbd.h"
46#endif
47
48#include <sys/param.h>
49#include <sys/systm.h>
50#include <sys/conf.h>
51#include <sys/device.h>
52#include <sys/malloc.h>
53#include <sys/ioctl.h>
54#include <sys/kernel.h>
55#include <sys/proc.h>
56#include <sys/tty.h>
57#include <sys/time.h>
58#include <sys/syslog.h>
59
60#include <machine/autoconf.h>
61#include <machine/z8530var.h>
62
63#include <dev/cons.h>
64
65#include <dev/ic/z8530reg.h>
66
67#include <dev/tc/tcvar.h>
68#include <dev/tc/ioasicreg.h>
69#include <dev/tc/ioasicvar.h>
70
71#include <dev/tc/zs_ioasicvar.h>
72
73#if defined(__alpha__)
74#include <machine/rpb.h>
75#endif
76
77/*
78 * Helpers for console support.
79 */
80static void	zs_ioasic_cninit(tc_addr_t, tc_offset_t, int);
81static int	zs_ioasic_cngetc(dev_t);
82static void	zs_ioasic_cnputc(dev_t, int);
83static void	zs_ioasic_cnpollc(dev_t, int);
84
85#if 0
86cons_decl(zs_ioasic_);
87#endif
88struct consdev zs_ioasic_cons = {
89	NULL,
90	NULL,
91	zs_ioasic_cngetc,
92	zs_ioasic_cnputc,
93	zs_ioasic_cnpollc,
94	NULL
95};
96
97static tc_offset_t zs_ioasic_console_offset;
98static int zs_ioasic_console_channel;
99static int zs_ioasic_console;
100static struct zs_chanstate zs_ioasic_conschanstate_store;
101
102static int	zs_ioasic_isconsole(tc_offset_t, int);
103static void	zs_putc(struct zs_chanstate *, int);
104
105/*
106 * Some warts needed by z8530tty.c
107 */
108int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
109#if defined(__alpha__)
110int zs_major = 15;
111#endif
112
113/*
114 * ZS chips are fed a 7.372 MHz clock.
115 */
116#define	PCLK	(9600 * 768)	/* PCLK pin input clock rate */
117
118/* The layout of this is hardware-dependent (padding, order). */
119struct zshan {
120#if defined(__alpha__) || defined(alpha)
121	volatile u_int	zc_csr;		/* ctrl,status, and indirect access */
122	u_int		zc_pad0;
123	volatile u_int	zc_data;	/* data */
124	u_int		sc_pad1;
125#endif
126};
127
128struct zsdevice {
129	/* Yes, they are backwards. */
130	struct	zshan zs_chan_b;
131	struct	zshan zs_chan_a;
132};
133
134static const uint8_t zs_ioasic_init_reg[16] = {
135	0,				/* 0: CMD (reset, etc.) */
136	0,				/* 1: No interrupts yet. */
137	0xf0,				/* 2: IVECT */
138	ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
139	ZSWR4_CLK_X16 | ZSWR4_ONESB,
140	ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
141	0,				/* 6: TXSYNC/SYNCLO */
142	0,				/* 7: RXSYNC/SYNCHI */
143	0,				/* 8: alias for data port */
144	ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT,
145	0,				/*10: Misc. TX/RX control bits */
146	ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
147	22,				/*12: BAUDLO (default=9600) */
148	0,				/*13: BAUDHI (default=9600) */
149	ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
150	ZSWR15_BREAK_IE
151};
152
153static struct zshan *
154zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel)
155{
156	struct zsdevice *addr;
157	struct zshan *zc;
158
159#if defined(__alpha__)
160	addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr);
161#endif
162
163	if (channel == 0)
164		zc = &addr->zs_chan_a;
165	else
166		zc = &addr->zs_chan_b;
167
168	return (zc);
169}
170
171
172/****************************************************************
173 * Autoconfig
174 ****************************************************************/
175
176/* Definition of the driver for autoconfig. */
177static int	zs_ioasic_match(struct device *, void *, void *);
178static void	zs_ioasic_attach(struct device *, struct device *, void *);
179static int	zs_ioasic_print(void *, const char *name);
180static int	zs_ioasic_submatch(struct device *, void *, void *);
181
182struct cfdriver zs_cd = {
183	NULL, "zs", DV_TTY
184};
185
186const struct cfattach zs_ioasic_ca = {
187	sizeof(struct zsc_softc), zs_ioasic_match, zs_ioasic_attach
188};
189
190/* Interrupt handlers. */
191static int	zs_ioasic_hardintr(void *);
192static void	zs_ioasic_softintr(void *);
193
194/*
195 * Is the zs chip present?
196 */
197static int
198zs_ioasic_match(struct device *parent, void *vcf, void *aux)
199{
200	struct ioasicdev_attach_args *d = aux;
201	tc_addr_t zs_addr;
202
203	/*
204	 * Make sure that we're looking for the right kind of device.
205	 */
206	if (strncmp(d->iada_modname, "z8530   ", TC_ROM_LLEN) != 0 &&
207	    strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0)
208		return (0);
209
210	/*
211	 * Find out the device address, and check it for validity.
212	 */
213	zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr);
214	if (tc_badaddr(zs_addr))
215		return (0);
216
217	return (1);
218}
219
220/*
221 * Attach a found zs.
222 */
223static void
224zs_ioasic_attach(struct device *parent, struct device *self, void *aux)
225{
226	struct zsc_softc *zs = (void *)self;
227	struct zsc_attach_args zs_args;
228	struct zs_chanstate *cs;
229	struct ioasicdev_attach_args *d = aux;
230	struct zshan *zc;
231	int s, channel;
232	u_long zflg;
233
234	printf("\n");
235
236	/*
237	 * Initialize software state for each channel.
238	 */
239	for (channel = 0; channel < 2; channel++) {
240		zs_args.channel = channel;
241		zs_args.hwflags = 0;
242		zs_args.type = NULL;
243
244		if (zs_ioasic_isconsole(d->iada_offset, channel)) {
245			cs = &zs_ioasic_conschanstate_store;
246			zs_args.hwflags |= ZS_HWFLAG_CONSOLE;
247		} else {
248			cs = malloc(sizeof(struct zs_chanstate),
249			    M_DEVBUF, M_NOWAIT | M_ZERO);
250			zc = zs_ioasic_get_chan_addr(d->iada_addr, channel);
251			cs->cs_reg_csr = (volatile void *)&zc->zc_csr;
252
253			memcpy(cs->cs_creg, zs_ioasic_init_reg, 16);
254			memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);
255
256			cs->cs_defcflag = zs_def_cflag;
257			cs->cs_defspeed = 9600;		/* XXX */
258			(void)zs_set_modes(cs, cs->cs_defcflag);
259		}
260
261		zs->zsc_cs[channel] = cs;
262		zs->zsc_addroffset = d->iada_offset; /* cookie only */
263		cs->cs_channel = channel;
264		cs->cs_ops = &zsops_null;
265		cs->cs_brg_clk = PCLK / 16;
266
267		/*
268		 * DCD and CTS interrupts are only meaningful on
269		 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
270		 *
271		 * XXX This is sorta gross.
272		 */
273		if (d->iada_offset == 0x00100000 && channel == 1) {
274			cs->cs_creg[15] |= ZSWR15_DCD_IE;
275			cs->cs_preg[15] |= ZSWR15_DCD_IE;
276			zflg = ZIP_FLAGS_DCDCTS;
277		} else
278			zflg = 0;
279		if (channel == 1)
280			zflg |= ZIP_FLAGS_DTRRTS;
281		cs->cs_private = (void *)zflg;
282
283		/*
284		 * Clear the master interrupt enable.
285		 * The INTENA is common to both channels,
286		 * so just do it on the A channel.
287		 */
288		if (channel == 0) {
289			zs_write_reg(cs, 9, 0);
290		}
291
292		/*
293		 * Set up the flow/modem control channel pointer to
294		 * deal with the weird wiring on the TC Alpha and
295		 * DECstation.
296		 */
297		if (channel == 1)
298			cs->cs_ctl_chan = zs->zsc_cs[0];
299		else
300			cs->cs_ctl_chan = NULL;
301
302		if (d->iada_offset == 0x00100000) {
303			if (channel == 0)
304				zs_args.type = "vsms";
305			else
306				zs_args.type = "zstty";
307		} else {
308			if (channel == 0)
309				zs_args.type = "lkkbd";
310			else {
311#if defined(__alpha__)
312				if (cputype != ST_DEC_3000_300)
313#endif
314					zs_args.type = "zstty";
315			}
316		}
317
318		/*
319		 * Look for a child driver for this channel.
320		 * The child attach will setup the hardware.
321		 */
322		if (zs_args.type == NULL ||
323		    config_found_sm(self, (void *)&zs_args, zs_ioasic_print,
324		                    zs_ioasic_submatch) ==
325		      NULL) {
326			/* No sub-driver.  Just reset it. */
327			uint8_t reset = (channel == 0) ?
328			    ZSWR9_A_RESET : ZSWR9_B_RESET;
329			s = splhigh();
330			zs_write_reg(cs, 9, reset);
331			splx(s);
332		}
333	}
334
335	/*
336	 * Set up the ioasic interrupt handler.
337	 */
338	ioasic_intr_establish(parent, d->iada_cookie, IPL_TTY,
339	    zs_ioasic_hardintr, zs, self->dv_xname);
340	zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, zs_ioasic_softintr, zs);
341	if (zs->zsc_sih == NULL)
342		panic("%s: unable to register softintr", __func__);
343
344	/*
345	 * Set the master interrupt enable and interrupt vector.  The
346	 * Sun does this only on one channel.  The old Alpha SCC driver
347	 * did it on both.  We'll do it on both.
348	 */
349	s = splhigh();
350	/* interrupt vector */
351	zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]);
352	zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]);
353
354	/* master interrupt control (enable) */
355	zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]);
356	zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]);
357#if defined(__alpha__)
358	/* ioasic interrupt enable */
359	*(volatile u_int *)(ioasic_base + IOASIC_IMSK) |=
360	    IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0;
361	tc_mb();
362#endif
363	splx(s);
364}
365
366static int
367zs_ioasic_print(void *aux, const char *pnp)
368{
369	struct zsc_attach_args *args = aux;
370
371	if (pnp != NULL)
372		printf("%s at %s", args->type, pnp);
373
374	if (args->channel != -1)
375		printf(" channel %d", args->channel);
376
377	return (UNCONF);
378}
379
380static int
381zs_ioasic_submatch(struct device *parent, void *vcf, void *aux)
382{
383	struct cfdata *cf = (struct cfdata *)vcf;
384	struct zsc_attach_args *za = (struct zsc_attach_args *)aux;
385
386	if (strcmp(cf->cf_driver->cd_name, za->type) != 0)
387		return 0;
388
389	return (*cf->cf_attach->ca_match)(parent, cf, aux);
390}
391
392/*
393 * Hardware interrupt handler.
394 */
395static int
396zs_ioasic_hardintr(void *arg)
397{
398	struct zsc_softc *zsc = arg;
399	int rval;
400
401	/*
402	 * Call the upper-level MI hardware interrupt handler.
403	 */
404	rval = zsc_intr_hard(zsc);
405
406	/*
407	 * Check to see if we need to schedule any software-level
408	 * processing interrupts.
409	 */
410	if (rval != 0) {
411		if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq)
412			softintr_schedule(zsc->zsc_sih);
413	}
414
415	return rval;
416}
417
418/*
419 * Software-level interrupt (character processing, lower priority).
420 */
421static void
422zs_ioasic_softintr(void *arg)
423{
424	struct zsc_softc *zsc = arg;
425	int s;
426
427	s = spltty();
428	(void)zsc_intr_soft(zsc);
429	splx(s);
430}
431
432/*
433 * MD functions for setting the baud rate and control modes.
434 */
435int
436zs_set_speed(struct zs_chanstate *cs, int bps)
437{
438	int tconst, real_bps;
439
440	if (bps == 0)
441		return (0);
442
443#ifdef DIAGNOSTIC
444	if (cs->cs_brg_clk == 0)
445		panic("zs_set_speed");
446#endif
447
448	tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
449	if (tconst < 0)
450		return (EINVAL);
451
452	/* Convert back to make sure we can do it. */
453	real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
454
455#if 0
456	/* XXX - Allow some tolerance here? */
457	if (real_bps != bps)
458		return (EINVAL);
459#endif
460
461	cs->cs_preg[12] = tconst;
462	cs->cs_preg[13] = tconst >> 8;
463
464	/* Caller will stuff the pending registers. */
465	return (0);
466}
467
468int
469zs_set_modes(struct zs_chanstate *cs, int cflag)
470{
471	u_long privflags = (u_long)cs->cs_private;
472	int s;
473
474	/*
475	 * Output hardware flow control on the chip is horrendous:
476	 * if carrier detect drops, the receiver is disabled, and if
477	 * CTS drops, the transmitter is stopped MID CHARACTER!
478	 * Therefore, NEVER set the HFC bit, and instead use the
479	 * status interrupt to detect CTS changes.
480	 */
481	s = splzs();
482	cs->cs_rr0_pps = 0;
483	if ((cflag & (CLOCAL | MDMBUF)) != 0) {
484		cs->cs_rr0_dcd = 0;
485		if ((cflag & MDMBUF) == 0)
486			cs->cs_rr0_pps = ZSRR0_DCD;
487	} else
488		cs->cs_rr0_dcd = ZSRR0_DCD;
489	if ((cflag & CRTSCTS) != 0) {
490		cs->cs_wr5_dtr = ZSWR5_DTR;
491		cs->cs_wr5_rts = ZSWR5_RTS;
492		cs->cs_rr0_cts = ZSRR0_CTS;
493#if defined(CDTRCTS)
494	} else if ((cflag & CDTRCTS) != 0) {
495		cs->cs_wr5_dtr = 0;
496		cs->cs_wr5_rts = ZSWR5_DTR;
497		cs->cs_rr0_cts = ZSRR0_CTS;
498#endif
499	} else if ((cflag & MDMBUF) != 0) {
500		cs->cs_wr5_dtr = 0;
501		cs->cs_wr5_rts = ZSWR5_DTR;
502		cs->cs_rr0_cts = ZSRR0_DCD;
503	} else {
504		cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
505		cs->cs_wr5_rts = 0;
506		cs->cs_rr0_cts = 0;
507	}
508
509	if ((privflags & ZIP_FLAGS_DCDCTS) == 0) {
510		cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD);
511		cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD);
512	}
513	if ((privflags & ZIP_FLAGS_DTRRTS) == 0) {
514		cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR);
515		cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR);
516	}
517	splx(s);
518
519	/* Caller will stuff the pending registers. */
520	return (0);
521}
522
523/*
524 * Functions to read and write individual registers in a channel.
525 * The ZS chip requires a 1.6 uSec. recovery time between accesses,
526 * and the Alpha TC hardware does NOT take care of this for you.
527 * The delay is now handled inside the chip access functions.
528 * These could be inlines, but with the delay, speed is moot.
529 */
530
531uint8_t
532zs_read_reg(struct zs_chanstate *cs, uint8_t reg)
533{
534	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
535	unsigned val;
536
537	zc->zc_csr = reg << 8;
538	tc_wmb();
539	DELAY(5);
540	val = (zc->zc_csr >> 8) & 0xff;
541	/* tc_mb(); */
542	DELAY(5);
543	return (val);
544}
545
546void
547zs_write_reg(struct zs_chanstate *cs, uint8_t reg, uint8_t val)
548{
549	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
550
551	zc->zc_csr = reg << 8;
552	tc_wmb();
553	DELAY(5);
554	zc->zc_csr = val << 8;
555	tc_wmb();
556	DELAY(5);
557}
558
559uint8_t
560zs_read_csr(struct zs_chanstate *cs)
561{
562	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
563	unsigned val;
564
565	val = (zc->zc_csr >> 8) & 0xff;
566	/* tc_mb(); */
567	DELAY(5);
568	return (val);
569}
570
571void
572zs_write_csr(struct zs_chanstate *cs, uint8_t val)
573{
574	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
575
576	zc->zc_csr = val << 8;
577	tc_wmb();
578	DELAY(5);
579}
580
581uint8_t
582zs_read_data(struct zs_chanstate *cs)
583{
584	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
585	unsigned val;
586
587	val = (zc->zc_data) >> 8 & 0xff;
588	/* tc_mb(); */
589	DELAY(5);
590	return (val);
591}
592
593void
594zs_write_data(struct zs_chanstate *cs, uint8_t val)
595{
596	volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
597
598	zc->zc_data = val << 8;
599	tc_wmb();
600	DELAY(5);
601}
602
603/****************************************************************
604 * Console support functions
605 ****************************************************************/
606
607/*
608 * Handle user request to enter kernel debugger.
609 */
610void
611zs_abort(struct zs_chanstate *cs)
612{
613	u_int rr0;
614
615	/* Wait for end of break. */
616	/* XXX - Limit the wait? */
617	do {
618		rr0 = zs_read_csr(cs);
619	} while (rr0 & ZSRR0_BREAK);
620
621#if defined(DDB)
622	db_enter();
623#else
624	printf("zs_abort: ignoring break on console\n");
625#endif
626}
627
628/*
629 * Polled input char.
630 */
631int
632zs_getc(struct zs_chanstate *cs)
633{
634	int s, c;
635	u_int rr0;
636
637	s = splhigh();
638	/* Wait for a character to arrive. */
639	do {
640		rr0 = zs_read_csr(cs);
641	} while ((rr0 & ZSRR0_RX_READY) == 0);
642
643	c = zs_read_data(cs);
644	splx(s);
645
646	/*
647	 * This is used by the kd driver to read scan codes,
648	 * so don't translate '\r' ==> '\n' here...
649	 */
650	return (c);
651}
652
653/*
654 * Polled output char.
655 */
656static void
657zs_putc(struct zs_chanstate *cs, int c)
658{
659	int s;
660	u_int rr0;
661
662	s = splhigh();
663	/* Wait for transmitter to become ready. */
664	do {
665		rr0 = zs_read_csr(cs);
666	} while ((rr0 & ZSRR0_TX_READY) == 0);
667
668	zs_write_data(cs, c);
669
670	/* Wait for the character to be transmitted. */
671	do {
672		rr0 = zs_read_csr(cs);
673	} while ((rr0 & ZSRR0_TX_READY) == 0);
674	splx(s);
675}
676
677/*****************************************************************/
678
679/*
680 * zs_ioasic_cninit --
681 *	Initialize the serial channel for either a keyboard or
682 *	a serial console.
683 */
684static void
685zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel)
686{
687	struct zs_chanstate *cs;
688	tc_addr_t zs_addr;
689	struct zshan *zc;
690	u_long zflg;
691
692	/*
693	 * Initialize the console finder helpers.
694	 */
695	zs_ioasic_console_offset = zs_offset;
696	zs_ioasic_console_channel = channel;
697	zs_ioasic_console = 1;
698
699	/*
700	 * Pointer to channel state.
701	 */
702	cs = &zs_ioasic_conschanstate_store;
703
704	/*
705	 * Compute the physical address of the chip, "map" it via
706	 * K0SEG, and then get the address of the actual channel.
707	 */
708#if defined(__alpha__)
709	zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset);
710#endif
711	zc = zs_ioasic_get_chan_addr(zs_addr, channel);
712
713	/* Setup temporary chanstate. */
714	cs->cs_reg_csr = (volatile void *)&zc->zc_csr;
715
716	cs->cs_channel = channel;
717	cs->cs_ops = &zsops_null;
718	cs->cs_brg_clk = PCLK / 16;
719
720	/* Initialize the pending registers. */
721	memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);
722	/* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */
723
724	/*
725	 * DCD and CTS interrupts are only meaningful on
726	 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
727	 *
728	 * XXX This is sorta gross.
729	 */
730	if (zs_offset == 0x00100000 && channel == 1)
731		zflg = ZIP_FLAGS_DCDCTS;
732	else
733		zflg = 0;
734	if (channel == 1)
735		zflg |= ZIP_FLAGS_DTRRTS;
736	cs->cs_private = (void *)zflg;
737
738	/* Clear the master interrupt enable. */
739	zs_write_reg(cs, 9, 0);
740
741	/* Reset the whole SCC chip. */
742	zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
743
744	/* Copy "pending" to "current" and H/W. */
745	zs_loadchannelregs(cs);
746}
747
748/*
749 * zs_ioasic_cnattach --
750 *	Initialize and attach a serial console.
751 */
752void
753zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel)
754{
755	struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
756
757	zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
758	cs->cs_defspeed = 9600;
759	cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
760
761	/* Point the console at the SCC. */
762	cn_tab = &zs_ioasic_cons;
763	cn_tab->cn_pri = CN_FORCED;
764	cn_tab->cn_dev = makedev(zs_major, (zs_offset == 0x100000) ? 0 : 1);
765}
766
767#if 0
768/*
769 * zs_ioasic_lk201_cnattach --
770 *	Initialize and attach a keyboard.
771 */
772int
773zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset,
774    int channel)
775{
776#if (NZSKBD > 0)
777	struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
778
779	zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
780	cs->cs_defspeed = 4800;
781	cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
782	return (zskbd_cnattach(cs));
783#else
784	return (ENXIO);
785#endif
786}
787#endif
788
789static int
790zs_ioasic_isconsole(tc_offset_t offset, int channel)
791{
792	if (zs_ioasic_console &&
793	    offset == zs_ioasic_console_offset &&
794	    channel == zs_ioasic_console_channel)
795		return (1);
796
797	return (0);
798}
799
800/*
801 * Polled console input putchar.
802 */
803static int
804zs_ioasic_cngetc(dev_t dev)
805{
806	return (zs_getc(&zs_ioasic_conschanstate_store));
807}
808
809/*
810 * Polled console output putchar.
811 */
812static void
813zs_ioasic_cnputc(dev_t dev, int c)
814{
815	zs_putc(&zs_ioasic_conschanstate_store, c);
816}
817
818/*
819 * Set polling/no polling on console.
820 */
821static void
822zs_ioasic_cnpollc(dev_t dev, int onoff)
823{
824}
825