1/* $OpenBSD: sdhcreg.h,v 1.10 2023/10/01 08:56:24 kettenis Exp $ */ 2 3/* 4 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19#ifndef _SDHCREG_H_ 20#define _SDHCREG_H_ 21 22/* PCI base address registers */ 23#define SDHC_PCI_BAR_START PCI_MAPREG_START 24#define SDHC_PCI_BAR_END PCI_MAPREG_END 25 26/* PCI interface classes */ 27#define SDHC_PCI_INTERFACE_NO_DMA 0x00 28#define SDHC_PCI_INTERFACE_DMA 0x01 29#define SDHC_PCI_INTERFACE_VENDOR 0x02 30 31/* Host standard register set */ 32#define SDHC_DMA_ADDR 0x00 33#define SDHC_BLOCK_SIZE 0x04 34#define SDHC_BLOCK_COUNT 0x06 35#define SDHC_BLOCK_COUNT_MAX 512 36#define SDHC_ARGUMENT 0x08 37#define SDHC_TRANSFER_MODE 0x0c 38#define SDHC_MULTI_BLOCK_MODE (1<<5) 39#define SDHC_READ_MODE (1<<4) 40#define SDHC_AUTO_CMD12_ENABLE (1<<2) 41#define SDHC_BLOCK_COUNT_ENABLE (1<<1) 42#define SDHC_DMA_ENABLE (1<<0) 43#define SDHC_COMMAND 0x0e 44/* 14-15 reserved */ 45#define SDHC_COMMAND_INDEX_SHIFT 8 46#define SDHC_COMMAND_INDEX_MASK 0x3f 47#define SDHC_COMMAND_TYPE_ABORT (3<<6) 48#define SDHC_COMMAND_TYPE_RESUME (2<<6) 49#define SDHC_COMMAND_TYPE_SUSPEND (1<<6) 50#define SDHC_COMMAND_TYPE_NORMAL (0<<6) 51#define SDHC_DATA_PRESENT_SELECT (1<<5) 52#define SDHC_INDEX_CHECK_ENABLE (1<<4) 53#define SDHC_CRC_CHECK_ENABLE (1<<3) 54/* 2 reserved */ 55#define SDHC_RESP_LEN_48_CHK_BUSY (3<<0) 56#define SDHC_RESP_LEN_48 (2<<0) 57#define SDHC_RESP_LEN_136 (1<<0) 58#define SDHC_NO_RESPONSE (0<<0) 59#define SDHC_RESPONSE 0x10 /* - 0x1f */ 60#define SDHC_DATA 0x20 61#define SDHC_PRESENT_STATE 0x24 62/* 25-31 reserved */ 63#define SDHC_CMD_LINE_SIGNAL_LEVEL (1<<24) 64#define SDHC_DAT3_LINE_LEVEL (1<<23) 65#define SDHC_DAT2_LINE_LEVEL (1<<22) 66#define SDHC_DAT1_LINE_LEVEL (1<<21) 67#define SDHC_DAT0_LINE_LEVEL (1<<20) 68#define SDHC_WRITE_PROTECT_SWITCH (1<<19) 69#define SDHC_CARD_DETECT_PIN_LEVEL (1<<18) 70#define SDHC_CARD_STATE_STABLE (1<<17) 71#define SDHC_CARD_INSERTED (1<<16) 72/* 12-15 reserved */ 73#define SDHC_BUFFER_READ_ENABLE (1<<11) 74#define SDHC_BUFFER_WRITE_ENABLE (1<<10) 75#define SDHC_READ_TRANSFER_ACTIVE (1<<9) 76#define SDHC_WRITE_TRANSFER_ACTIVE (1<<8) 77/* 3-7 reserved */ 78#define SDHC_DAT_ACTIVE (1<<2) 79#define SDHC_CMD_INHIBIT_DAT (1<<1) 80#define SDHC_CMD_INHIBIT_CMD (1<<0) 81#define SDHC_CMD_INHIBIT_MASK 0x0003 82#define SDHC_HOST_CTL 0x28 83#define SDHC_8BIT_MODE (1<<5) 84#define SDHC_DMA_SELECT (3<<3) 85#define SDHC_DMA_SELECT_SDMA (0<<3) 86#define SDHC_DMA_SELECT_ADMA32 (2<<3) 87#define SDHC_DMA_SELECT_ADMA64 (3<<3) 88#define SDHC_HIGH_SPEED (1<<2) 89#define SDHC_4BIT_MODE (1<<1) 90#define SDHC_LED_ON (1<<0) 91#define SDHC_POWER_CTL 0x29 92#define SDHC_VOLTAGE_SHIFT 1 93#define SDHC_VOLTAGE_MASK 0x07 94#define SDHC_VOLTAGE_3_3V 0x07 95#define SDHC_VOLTAGE_3_0V 0x06 96#define SDHC_VOLTAGE_1_8V 0x05 97#define SDHC_BUS_POWER (1<<0) 98#define SDHC_BLOCK_GAP_CTL 0x2a 99#define SDHC_WAKEUP_CTL 0x2b 100#define SDHC_CLOCK_CTL 0x2c 101#define SDHC_SDCLK_DIV_SHIFT 8 102#define SDHC_SDCLK_DIV_MASK 0xff 103#define SDHC_SDCLK_DIV_RSHIFT_V3 2 104#define SDHC_SDCLK_DIV_MASK_V3 0x300 105#define SDHC_SDCLK_ENABLE (1<<2) 106#define SDHC_INTCLK_STABLE (1<<1) 107#define SDHC_INTCLK_ENABLE (1<<0) 108#define SDHC_TIMEOUT_CTL 0x2e 109#define SDHC_TIMEOUT_MAX 0x0e 110#define SDHC_SOFTWARE_RESET 0x2f 111#define SDHC_RESET_MASK 0x5 112#define SDHC_RESET_DAT (1<<2) 113#define SDHC_RESET_CMD (1<<1) 114#define SDHC_RESET_ALL (1<<0) 115#define SDHC_NINTR_STATUS 0x30 116#define SDHC_ERROR_INTERRUPT (1<<15) 117#define SDHC_RETUNING_EVENT (1<<12) 118#define SDHC_CARD_INTERRUPT (1<<8) 119#define SDHC_CARD_REMOVAL (1<<7) 120#define SDHC_CARD_INSERTION (1<<6) 121#define SDHC_BUFFER_READ_READY (1<<5) 122#define SDHC_BUFFER_WRITE_READY (1<<4) 123#define SDHC_DMA_INTERRUPT (1<<3) 124#define SDHC_BLOCK_GAP_EVENT (1<<2) 125#define SDHC_TRANSFER_COMPLETE (1<<1) 126#define SDHC_COMMAND_COMPLETE (1<<0) 127#define SDHC_NINTR_STATUS_MASK 0x91ff 128#define SDHC_EINTR_STATUS 0x32 129#define SDHC_ADMA_ERROR (1<<9) 130#define SDHC_AUTO_CMD12_ERROR (1<<8) 131#define SDHC_CURRENT_LIMIT_ERROR (1<<7) 132#define SDHC_DATA_END_BIT_ERROR (1<<6) 133#define SDHC_DATA_CRC_ERROR (1<<5) 134#define SDHC_DATA_TIMEOUT_ERROR (1<<4) 135#define SDHC_CMD_INDEX_ERROR (1<<3) 136#define SDHC_CMD_END_BIT_ERROR (1<<2) 137#define SDHC_CMD_CRC_ERROR (1<<1) 138#define SDHC_CMD_TIMEOUT_ERROR (1<<0) 139#define SDHC_EINTR_STATUS_MASK 0x03ff /* excluding vendor signals */ 140#define SDHC_NINTR_STATUS_EN 0x34 141#define SDHC_EINTR_STATUS_EN 0x36 142#define SDHC_NINTR_SIGNAL_EN 0x38 143#define SDHC_NINTR_SIGNAL_MASK 0x01ff 144#define SDHC_EINTR_SIGNAL_EN 0x3a 145#define SDHC_EINTR_SIGNAL_MASK 0x03ff /* excluding vendor signals */ 146#define SDHC_CMD12_ERROR_STATUS 0x3c 147#define SDHC_HOST_CTL2 0x3e 148#define SDHC_SAMPLING_CLOCK_SEL (1<<7) 149#define SDHC_EXECUTE_TUNING (1<<6) 150#define SDHC_1_8V_SIGNAL_EN (1<<3) 151#define SDHC_UHS_MODE_SELECT_SHIFT 0 152#define SDHC_UHS_MODE_SELECT_MASK 0x7 153#define SDHC_UHS_MODE_SELECT_SDR12 0 154#define SDHC_UHS_MODE_SELECT_SDR25 1 155#define SDHC_UHS_MODE_SELECT_SDR50 2 156#define SDHC_UHS_MODE_SELECT_SDR104 3 157#define SDHC_UHS_MODE_SELECT_DDR50 4 158#define SDHC_CAPABILITIES 0x40 159#define SDHC_64BIT_DMA_SUPP (1<<28) 160#define SDHC_VOLTAGE_SUPP_1_8V (1<<26) 161#define SDHC_VOLTAGE_SUPP_3_0V (1<<25) 162#define SDHC_VOLTAGE_SUPP_3_3V (1<<24) 163#define SDHC_SDMA_SUPP (1<<22) 164#define SDHC_HIGH_SPEED_SUPP (1<<21) 165#define SDHC_ADMA2_SUPP (1<<19) 166#define SDHC_8BIT_MODE_SUPP (1<<18) 167#define SDHC_MAX_BLK_LEN_512 0 168#define SDHC_MAX_BLK_LEN_1024 1 169#define SDHC_MAX_BLK_LEN_2048 2 170#define SDHC_MAX_BLK_LEN_SHIFT 16 171#define SDHC_MAX_BLK_LEN_MASK 0x3 172#define SDHC_BASE_FREQ_SHIFT 8 173#define SDHC_BASE_FREQ_MASK 0x3f 174#define SDHC_BASE_FREQ_MASK_V3 0xff 175#define SDHC_TIMEOUT_FREQ_UNIT (1<<7) /* 0=KHz, 1=MHz */ 176#define SDHC_TIMEOUT_FREQ_SHIFT 0 177#define SDHC_TIMEOUT_FREQ_MASK 0x1f 178#define SDHC_CAPABILITIES2 0x44 179#define SDHC_SDR50_SUPP (1<<0) 180#define SDHC_SDR104_SUPP (1<<1) 181#define SDHC_DDR50_SUPP (1<<2) 182#define SDHC_DRIVER_TYPE_A (1<<4) 183#define SDHC_DRIVER_TYPE_C (1<<5) 184#define SDHC_DRIVER_TYPE_D (1<<6) 185#define SDHC_TIMER_COUNT_SHIFT 8 186#define SDHC_TIMER_COUNT_MASK 0xf 187#define SDHC_TUNING_SDR50 (1<<13) 188#define SDHC_RETUNING_MODES_SHIFT 14 189#define SDHC_RETUNING_MODES_MASK 0x3 190#define SDHC_RETUNING_MODE_1 (0 << SDHC_RETUNING_MODES_SHIFT) 191#define SDHC_RETUNING_MODE_2 (1 << SDHC_RETUNING_MODES_SHIFT) 192#define SDHC_RETUNING_MODE_3 (2 << SDHC_RETUNING_MODES_SHIFT) 193#define SDHC_CLOCK_MULTIPLIER_SHIFT 16 194#define SDHC_CLOCK_MULTIPLIER_MASK 0xff 195#define SDHC_ADMA_ERROR_STATUS 0x54 196#define SDHC_ADMA_LENGTH_MISMATCH (1<<2) 197#define SDHC_ADMA_ERROR_STATE (3<<0) 198#define SDHC_ADMA_SYSTEM_ADDR 0x58 199#define SDHC_MAX_CAPABILITIES 0x48 200#define SDHC_SLOT_INTR_STATUS 0xfc 201#define SDHC_HOST_CTL_VERSION 0xfe 202#define SDHC_SPEC_VERS_SHIFT 0 203#define SDHC_SPEC_VERS_MASK 0xff 204#define SDHC_SPEC_VERS_4_10 0x04 205#define SDHC_SPEC_VERS_4_20 0x05 206#define SDHC_VENDOR_VERS_SHIFT 8 207#define SDHC_VENDOR_VERS_MASK 0xff 208#define SDHC_SPEC_V1 0 209#define SDHC_SPEC_V2 1 210#define SDHC_SPEC_V3 2 211 212/* SDHC_CLOCK_CTL encoding */ 213#define SDHC_SDCLK_DIV(div) \ 214 (((div) & SDHC_SDCLK_DIV_MASK) << SDHC_SDCLK_DIV_SHIFT) 215#define SDHC_SDCLK_DIV_V3(div) \ 216 (SDHC_SDCLK_DIV(div) | \ 217 (((div) & SDHC_SDCLK_DIV_MASK_V3) >> SDHC_SDCLK_DIV_RSHIFT_V3)) 218#define SDHC_SDCLK_DIV_MAX 256 219#define SDHC_SDCLK_DIV_MAX_V3 2046 220 221/* SDHC_CAPABILITIES decoding */ 222#define SDHC_BASE_FREQ_KHZ(cap) \ 223 ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK) * 1000) 224#define SDHC_BASE_FREQ_KHZ_V3(cap) \ 225 ((((cap) >> SDHC_BASE_FREQ_SHIFT) & SDHC_BASE_FREQ_MASK_V3) * 1000) 226#define SDHC_TIMEOUT_FREQ(cap) \ 227 (((cap) >> SDHC_TIMEOUT_FREQ_SHIFT) & SDHC_TIMEOUT_FREQ_MASK) 228#define SDHC_TIMEOUT_FREQ_KHZ(cap) \ 229 (((cap) & SDHC_TIMEOUT_FREQ_UNIT) ? \ 230 SDHC_TIMEOUT_FREQ(cap) * 1000: \ 231 SDHC_TIMEOUT_FREQ(cap)) 232 233/* SDHC_HOST_CTL_VERSION decoding */ 234#define SDHC_SPEC_VERSION(hcv) \ 235 (((hcv) >> SDHC_SPEC_VERS_SHIFT) & SDHC_SPEC_VERS_MASK) 236#define SDHC_VENDOR_VERSION(hcv) \ 237 (((hcv) >> SDHC_VENDOR_VERS_SHIFT) & SDHC_VENDOR_VERS_MASK) 238 239#define SDHC_PRESENT_STATE_BITS \ 240 "\20\31CL\30D3L\27D2L\26D1L\25D0L\24WPS\23CD\22CSS\21CI" \ 241 "\14BRE\13BWE\12RTA\11WTA\3DLA\2CID\1CIC" 242#define SDHC_NINTR_STATUS_BITS \ 243 "\20\20ERROR\11CARD\10REMOVAL\7INSERTION\6READ\5WRITE" \ 244 "\4DMA\3GAP\2XFER\1CMD" 245#define SDHC_EINTR_STATUS_BITS \ 246 "\20\11ACMD12\10CL\7DEB\6DCRC\5DT\4CI\3CEB\2CCRC\1CT" 247#define SDHC_CAPABILITIES_BITS \ 248 "\20\33Vdd1.8V\32Vdd3.0V\31Vdd3.3V\30SUSPEND\27DMA\26HIGHSPEED" 249 250#define SDHC_ADMA2_VALID (1<<0) 251#define SDHC_ADMA2_END (1<<1) 252#define SDHC_ADMA2_INT (1<<2) 253#define SDHC_ADMA2_ACT (3<<4) 254#define SDHC_ADMA2_ACT_NOP (0<<4) 255#define SDHC_ADMA2_ACT_TRANS (2<<4) 256#define SDHC_ADMA2_ACT_LINK (3<<4) 257 258struct sdhc_adma2_descriptor32 { 259 uint16_t attribute; 260 uint16_t length; 261 uint32_t address; 262} __packed; 263 264struct sdhc_adma2_descriptor64 { 265 uint16_t attribute; 266 uint16_t length; 267 uint32_t address_lo; 268 uint32_t address_hi; 269} __packed; 270 271#endif 272