siop_pci_common.c revision 1.5
1/* $OpenBSD: siop_pci_common.c,v 1.5 2001/04/15 06:01:30 krw Exp $ */ 2/* $NetBSD: siop_pci_common.c,v 1.6 2001/01/10 15:50:20 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/device.h> 38#include <sys/malloc.h> 39#include <sys/buf.h> 40#include <sys/kernel.h> 41 42#include <machine/endian.h> 43 44#include <dev/pci/pcireg.h> 45#include <dev/pci/pcivar.h> 46#include <dev/pci/pcidevs.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50 51#include <dev/ic/siopreg.h> 52#include <dev/ic/siopvar.h> 53#include <dev/pci/siop_pci_common.h> 54 55/* List (array, really :) of chips we know how to handle */ 56const struct siop_product_desc siop_products[] = { 57 { PCI_PRODUCT_SYMBIOS_810, 58 0x00, 59 SF_PCI_RL | SF_CHIP_LS, 60 4, 8, 3, SF_CLOCK_2500, 0 61 }, 62 { PCI_PRODUCT_SYMBIOS_810, 63 0x10, 64 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 65 4, 8, 3, SF_CLOCK_2500, 0 66 }, 67 { PCI_PRODUCT_SYMBIOS_815, 68 0x00, 69 SF_PCI_RL | SF_PCI_BOF, 70 4, 8, 3, SF_CLOCK_2500, 0 71 }, 72 { PCI_PRODUCT_SYMBIOS_820, 73 0x00, 74 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 75 4, 8, 3, SF_CLOCK_2500, 0 76 }, 77 { PCI_PRODUCT_SYMBIOS_825, 78 0x00, 79 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 80 4, 8, 3, SF_CLOCK_2500, 0 81 }, 82 { PCI_PRODUCT_SYMBIOS_825, 83 0x10, 84 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 85 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 86 SF_BUS_WIDE, 87 7, 8, 3, SF_CLOCK_2500, 4096 88 }, 89 { PCI_PRODUCT_SYMBIOS_860, 90 0x00, 91 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 92 SF_CHIP_PF | SF_CHIP_LS | 93 SF_BUS_ULTRA, 94 4, 8, 5, SF_CLOCK_1250, 0 95 }, 96 { PCI_PRODUCT_SYMBIOS_875, 97 0x00, 98 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 99 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 100 SF_BUS_ULTRA | SF_BUS_WIDE, 101 7, 16, 5, SF_CLOCK_1250, 4096 102 }, 103 { PCI_PRODUCT_SYMBIOS_875, 104 0x02, 105 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 106 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 107 SF_CHIP_LS | SF_CHIP_10REGS | 108 SF_BUS_ULTRA | SF_BUS_WIDE, 109 7, 16, 5, SF_CLOCK_1250, 4096 110 }, 111 { PCI_PRODUCT_SYMBIOS_875J, 112 0x00, 113 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 114 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 115 SF_CHIP_LS | SF_CHIP_10REGS | 116 SF_BUS_ULTRA | SF_BUS_WIDE, 117 7, 16, 5, SF_CLOCK_1250, 4096 118 }, 119 { PCI_PRODUCT_SYMBIOS_885, 120 0x00, 121 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 122 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 123 SF_CHIP_LS | SF_CHIP_10REGS | 124 SF_BUS_ULTRA | SF_BUS_WIDE, 125 7, 16, 5, SF_CLOCK_1250, 4096 126 }, 127 { PCI_PRODUCT_SYMBIOS_895, 128 0x00, 129 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 130 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 131 SF_CHIP_LS | SF_CHIP_10REGS | 132 SF_BUS_ULTRA2 | SF_BUS_WIDE, 133 7, 31, 7, SF_CLOCK_625, 4096 134 }, 135 { PCI_PRODUCT_SYMBIOS_895A, 136 0x00, 137 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 138 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 139 SF_CHIP_LS | SF_CHIP_10REGS | 140 SF_BUS_ULTRA2 | SF_BUS_WIDE, 141 7, 31, 7, SF_CLOCK_625, 8192 142 }, 143 { PCI_PRODUCT_SYMBIOS_896, 144 0x00, 145 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 146 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 147 SF_CHIP_LS | SF_CHIP_10REGS | 148 SF_BUS_ULTRA2 | SF_BUS_WIDE, 149 7, 31, 7, SF_CLOCK_625, 8192 150 }, 151 { PCI_PRODUCT_SYMBIOS_1010, 152 0x00, 153 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 154 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 155 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_C10 | 156 SF_BUS_ULTRA2 | SF_BUS_WIDE, 157 7, 62, 0, SF_CLOCK_625, 8192 158 }, 159 { PCI_PRODUCT_SYMBIOS_1510D, 160 0x00, 161 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 162 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 163 SF_CHIP_LS | SF_CHIP_10REGS | 164 SF_BUS_ULTRA2 | SF_BUS_WIDE, 165 7, 31, 7, SF_CLOCK_625, 4096 166 }, 167 { 0, 168 0x00, 169 0x00, 170 0, 0, 0, 0, 0 171 }, 172}; 173 174const struct siop_product_desc * 175siop_lookup_product(id, rev) 176 u_int32_t id; 177 int rev; 178{ 179 const struct siop_product_desc *pp; 180 const struct siop_product_desc *rp = NULL; 181 182 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 183 return NULL; 184 185 for (pp = siop_products; pp->product != 0; pp++) { 186 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 187 if (rp == NULL || pp->revision > rp->revision) 188 rp = pp; 189 } 190 return rp; 191} 192 193int 194siop_pci_attach_common(sc, pa) 195 struct siop_pci_softc *sc; 196 struct pci_attach_args *pa; 197{ 198 pci_chipset_tag_t pc = pa->pa_pc; 199 pcitag_t tag = pa->pa_tag; 200 const char *intrstr; 201 pci_intr_handle_t intrhandle; 202 bus_space_tag_t iot, memt; 203 bus_space_handle_t ioh, memh; 204 pcireg_t memtype; 205 int memh_valid, ioh_valid; 206 bus_addr_t ioaddr, memaddr; 207 208 sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 209 if (sc->sc_pp == NULL) { 210 printf("siop: broken match/attach!\n"); 211 return 0; 212 } 213 /* copy interesting infos about the chip */ 214 sc->siop.features = sc->sc_pp->features; 215 sc->siop.maxburst = sc->sc_pp->maxburst; 216 sc->siop.maxoff = sc->sc_pp->maxoff; 217 sc->siop.clock_div = sc->sc_pp->clock_div; 218 sc->siop.scf_index = sc->sc_pp->scf_index; 219 sc->siop.ram_size = sc->sc_pp->ram_size; 220 221 sc->siop.sc_reset = siop_pci_reset; 222 sc->sc_pc = pc; 223 sc->sc_tag = tag; 224 sc->siop.sc_dmat = pa->pa_dmat; 225 226 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 227 switch (memtype) { 228 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 229 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 230 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 231 &memt, &memh, &memaddr, NULL) == 0); 232 break; 233 default: 234 memh_valid = 0; 235 } 236 237 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 238 &iot, &ioh, &ioaddr, NULL) == 0); 239 240 if (memh_valid) { 241 sc->siop.sc_rt = memt; 242 sc->siop.sc_rh = memh; 243 sc->siop.sc_raddr = memaddr; 244 } else if (ioh_valid) { 245 sc->siop.sc_rt = iot; 246 sc->siop.sc_rh = ioh; 247 sc->siop.sc_raddr = ioaddr; 248 } else { 249 printf("\n%s: unable to map device registers\n", 250 sc->siop.sc_dev.dv_xname); 251 return 0; 252 } 253 254 if (sc->siop.features & SF_CHIP_RAM) { 255 int bar; 256 switch (memtype) { 257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 258 bar = 0x18; 259 break; 260 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 261 bar = 0x1c; 262 break; 263 } 264 if (pci_mapreg_map(pa, bar, memtype, 0, 265 &sc->siop.sc_ramt, &sc->siop.sc_ramh, 266 &sc->siop.sc_scriptaddr, NULL) != 0) 267 sc->siop.features &= ~SF_CHIP_RAM; 268 } 269 270 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 271 pa->pa_intrline, &intrhandle)) { 272 printf("\n%s: couldn't map interrupt\n", 273 sc->siop.sc_dev.dv_xname); 274 return 0; 275 } 276 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 277 sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 278 siop_intr, &sc->siop, sc->siop.sc_dev.dv_xname); 279 if (sc->sc_ih != NULL) 280 printf(": %s, ", (intrstr != NULL) ? intrstr : "irq ?"); 281 else { 282 printf("\n%s: couldn't establish interrupt", 283 sc->siop.sc_dev.dv_xname); 284 if (intrstr != NULL) 285 printf(" at %s", intrstr); 286 printf("\n"); 287 return 0; 288 } 289 290 if (sc->siop.features & SF_CHIP_RAM) 291 printf("has RAM\n"); 292 293 return 1; 294} 295 296void 297siop_pci_reset(sc) 298 struct siop_softc *sc; 299{ 300 int dmode; 301 302 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 303 if (sc->features & SF_PCI_RL) 304 dmode |= DMODE_ERL; 305 if (sc->features & SF_PCI_RM) 306 dmode |= DMODE_ERMP; 307 if (sc->features & SF_PCI_BOF) 308 dmode |= DMODE_BOF; 309 if (sc->features & SF_PCI_CLS) 310 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 311 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 312 DCNTL_CLSE); 313 if (sc->features & SF_PCI_WRI) 314 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 315 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 316 CTEST3_WRIE); 317 if (sc->maxburst) { 318 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 319 SIOP_CTEST5); 320 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 321 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 322 ~CTEST4_BDIS); 323 dmode &= ~DMODE_BL_MASK; 324 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 325 ctest5 &= ~CTEST5_BBCK; 326 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 327 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 328 } else if ((sc->features & SF_CHIP_C10) == 0) { 329 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 330 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 331 CTEST4_BDIS); 332 } 333 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 334} 335