1/* $OpenBSD: siop_pci_common.c,v 1.20 2024/05/24 06:02:58 jsg Exp $ */ 2/* $NetBSD: siop_pci_common.c,v 1.25 2005/06/28 00:28:42 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/device.h> 33 34#include <dev/pci/pcireg.h> 35#include <dev/pci/pcivar.h> 36#include <dev/pci/pcidevs.h> 37 38#include <scsi/scsi_all.h> 39#include <scsi/scsiconf.h> 40 41#include <dev/ic/siopreg.h> 42#include <dev/ic/siopvar_common.h> 43#include <dev/pci/siop_pci_common.h> 44 45/* List (array, really :) of chips we know how to handle */ 46const struct siop_product_desc siop_products[] = { 47 { PCI_PRODUCT_SYMBIOS_810, 48 0x00, 49 SF_PCI_RL | SF_CHIP_LS, 50 4, 8, 3, 250, 0 51 }, 52 { PCI_PRODUCT_SYMBIOS_810, 53 0x10, 54 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 55 4, 8, 3, 250, 0 56 }, 57 { PCI_PRODUCT_SYMBIOS_815, 58 0x00, 59 SF_PCI_RL | SF_PCI_BOF, 60 4, 8, 3, 250, 0 61 }, 62 { PCI_PRODUCT_SYMBIOS_820, 63 0x00, 64 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 65 4, 8, 3, 250, 0 66 }, 67 { PCI_PRODUCT_SYMBIOS_825, 68 0x00, 69 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 70 4, 8, 3, 250, 0 71 }, 72 { PCI_PRODUCT_SYMBIOS_825, 73 0x10, 74 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 75 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 76 SF_BUS_WIDE, 77 7, 8, 3, 250, 4096 78 }, 79 { PCI_PRODUCT_SYMBIOS_860, 80 0x00, 81 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 82 SF_CHIP_PF | SF_CHIP_LS | 83 SF_BUS_ULTRA, 84 4, 8, 5, 125, 0 85 }, 86 { PCI_PRODUCT_SYMBIOS_875, 87 0x00, 88 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 89 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 90 SF_BUS_ULTRA | SF_BUS_WIDE, 91 7, 16, 5, 125, 4096 92 }, 93 { PCI_PRODUCT_SYMBIOS_875, 94 0x02, 95 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 96 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 97 SF_CHIP_LS | SF_CHIP_10REGS | 98 SF_BUS_ULTRA | SF_BUS_WIDE, 99 7, 16, 5, 125, 4096 100 }, 101 { PCI_PRODUCT_SYMBIOS_875J, 102 0x00, 103 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 104 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 105 SF_CHIP_LS | SF_CHIP_10REGS | 106 SF_BUS_ULTRA | SF_BUS_WIDE, 107 7, 16, 5, 125, 4096 108 }, 109 { PCI_PRODUCT_SYMBIOS_885, 110 0x00, 111 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 112 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 113 SF_CHIP_LS | SF_CHIP_10REGS | 114 SF_BUS_ULTRA | SF_BUS_WIDE, 115 7, 16, 5, 125, 4096 116 }, 117 { PCI_PRODUCT_SYMBIOS_895, 118 0x00, 119 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 120 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 121 SF_CHIP_LS | SF_CHIP_10REGS | 122 SF_BUS_ULTRA2 | SF_BUS_WIDE, 123 7, 31, 7, 62, 4096 124 }, 125 { PCI_PRODUCT_SYMBIOS_896, 126 0x00, 127 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 128 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 129 SF_CHIP_LS | SF_CHIP_10REGS | 130 SF_BUS_ULTRA2 | SF_BUS_WIDE, 131 7, 31, 7, 62, 8192 132 }, 133 { PCI_PRODUCT_SYMBIOS_895A, 134 0x00, 135 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 136 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 137 SF_CHIP_LS | SF_CHIP_10REGS | 138 SF_BUS_ULTRA2 | SF_BUS_WIDE, 139 7, 31, 7, 62, 8192 140 }, 141 { PCI_PRODUCT_SYMBIOS_1010, 142 0x00, 143 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 144 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 145 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 146 SF_CHIP_GEBUG | 147 SF_BUS_ULTRA3 | SF_BUS_WIDE, 148 7, 31, 0, 62, 8192 149 }, 150 { PCI_PRODUCT_SYMBIOS_1010, 151 0x01, 152 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 153 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 154 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 155 SF_CHIP_GEBUG | 156 SF_BUS_ULTRA3 | SF_BUS_WIDE, 157 7, 62, 0, 62, 8192 158 }, 159 { PCI_PRODUCT_SYMBIOS_1010_2, 160 0x00, 161 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 162 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 163 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 164 SF_CHIP_AAIP | 165 SF_BUS_ULTRA3 | SF_BUS_WIDE, 166 7, 62, 0, 62, 8192 167 }, 168 { PCI_PRODUCT_SYMBIOS_1510D, 169 0x00, 170 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 171 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 172 SF_CHIP_LS | SF_CHIP_10REGS | 173 SF_BUS_ULTRA2 | SF_BUS_WIDE, 174 7, 31, 7, 62, 4096 175 }, 176 { 0, 177 0x00, 178 0x00, 179 0, 0, 0, 0, 0 180 }, 181}; 182 183const struct siop_product_desc * 184siop_lookup_product(u_int32_t id, int rev) 185{ 186 const struct siop_product_desc *pp; 187 const struct siop_product_desc *rp = NULL; 188 189 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 190 return NULL; 191 192 for (pp = siop_products; pp->product != 0; pp++) { 193 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 194 if (rp == NULL || pp->revision > rp->revision) 195 rp = pp; 196 } 197 return rp; 198} 199 200int 201siop_pci_attach_common(struct siop_pci_common_softc *pci_sc, 202 struct siop_common_softc *siop_sc, struct pci_attach_args *pa, 203 int (*intr)(void*)) 204{ 205 pci_chipset_tag_t pc = pa->pa_pc; 206 pcitag_t tag = pa->pa_tag; 207 const char *intrstr; 208 pci_intr_handle_t intrhandle; 209 bus_space_tag_t iot, memt; 210 bus_space_handle_t ioh, memh; 211 pcireg_t memtype; 212 int memh_valid, ioh_valid; 213 bus_addr_t ioaddr, memaddr; 214 bus_size_t iosize, memsize, ramsize; 215 216 pci_sc->sc_pp = 217 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 218 if (pci_sc->sc_pp == NULL) { 219 printf(": broken match/attach!\n"); 220 return 0; 221 } 222 /* copy interesting infos about the chip */ 223 siop_sc->features = pci_sc->sc_pp->features; 224#ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 225 siop_sc->features |= SF_CHIP_LED0; 226#endif 227 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 228 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 229 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 230 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 231 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 232 233 siop_sc->sc_reset = siop_pci_reset; 234 pci_sc->sc_pc = pc; 235 pci_sc->sc_tag = tag; 236 siop_sc->sc_dmat = pa->pa_dmat; 237 238 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 239 switch (memtype) { 240 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 241 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 242 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 243 &memt, &memh, &memaddr, &memsize, 0) == 0); 244 break; 245 default: 246 memh_valid = 0; 247 } 248 249 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 250 &iot, &ioh, &ioaddr, &iosize, 0) == 0); 251 252 if (memh_valid) { 253 siop_sc->sc_rt = memt; 254 siop_sc->sc_rh = memh; 255 siop_sc->sc_raddr = memaddr; 256 } else if (ioh_valid) { 257 siop_sc->sc_rt = iot; 258 siop_sc->sc_rh = ioh; 259 siop_sc->sc_raddr = ioaddr; 260 } else { 261 printf(": unable to map device registers\n"); 262 return 0; 263 } 264 265 if (pci_intr_map(pa, &intrhandle) != 0) { 266 printf(": couldn't map interrupt\n"); 267 goto out; 268 } 269 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 270 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 271 intr, siop_sc, siop_sc->sc_dev.dv_xname); 272 if (pci_sc->sc_ih != NULL) { 273 printf(": %s", 274 intrstr ? intrstr : "?"); 275 } else { 276 printf(": couldn't establish interrupt"); 277 if (intrstr != NULL) 278 printf(" at %s", intrstr); 279 printf("\n"); 280 goto out; 281 } 282 283 if (siop_sc->features & SF_CHIP_RAM) { 284 int bar; 285 switch (memtype) { 286 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 287 bar = 0x18; 288 break; 289 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 290 bar = 0x1c; 291 break; 292 default: 293 printf(": invalid memory type %d\n", memtype); 294 goto out; 295 } 296 if (pci_mapreg_map(pa, bar, memtype, 0, 297 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 298 &siop_sc->sc_scriptaddr, &ramsize, 0) == 0) { 299 printf(", using %luK of on-board RAM", 300 (u_long)ramsize / 1024); 301 } else { 302 printf(", can't map on-board RAM"); 303 siop_sc->features &= ~SF_CHIP_RAM; 304 } 305 } 306 307 printf("\n"); 308 309 return (1); 310 311 out: 312 if (pci_sc->sc_ih) { 313 pci_intr_disestablish(pa->pa_pc, pci_sc->sc_ih); 314 pci_sc->sc_ih = NULL; 315 } 316 if (ioh_valid) 317 bus_space_unmap(iot, ioh, iosize); 318 if (memh_valid) 319 bus_space_unmap(memt, memh, memsize); 320 return (0); 321} 322 323void 324siop_pci_reset(struct siop_common_softc *sc) 325{ 326 int dmode; 327 328 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 329 if (sc->features & SF_PCI_RL) 330 dmode |= DMODE_ERL; 331 if (sc->features & SF_PCI_RM) 332 dmode |= DMODE_ERMP; 333 if (sc->features & SF_PCI_BOF) 334 dmode |= DMODE_BOF; 335 if (sc->features & SF_PCI_CLS) 336 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 337 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 338 DCNTL_CLSE); 339 if (sc->features & SF_PCI_WRI) 340 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 341 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 342 CTEST3_WRIE); 343 if (sc->maxburst) { 344 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 345 SIOP_CTEST5); 346 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 347 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 348 ~CTEST4_BDIS); 349 dmode &= ~DMODE_BL_MASK; 350 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 351 ctest5 &= ~CTEST5_BBCK; 352 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 353 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 354 } else { 355 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 356 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 357 CTEST4_BDIS); 358 } 359 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 360} 361