siop_pci_common.c revision 1.18
141681Sdfr/* $OpenBSD: siop_pci_common.c,v 1.18 2010/07/23 07:47:13 jsg Exp $ */ 241681Sdfr/* $NetBSD: siop_pci_common.c,v 1.25 2005/06/28 00:28:42 thorpej Exp $ */ 341681Sdfr 441681Sdfr/* 541681Sdfr * Copyright (c) 2000 Manuel Bouyer. 641681Sdfr * 741681Sdfr * Redistribution and use in source and binary forms, with or without 841681Sdfr * modification, are permitted provided that the following conditions 941681Sdfr * are met: 1041681Sdfr * 1. Redistributions of source code must retain the above copyright 1141681Sdfr * notice, this list of conditions and the following disclaimer. 1241681Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1341681Sdfr * notice, this list of conditions and the following disclaimer in the 1441681Sdfr * documentation and/or other materials provided with the distribution. 1541681Sdfr * 1641681Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1741681Sdfr * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1841681Sdfr * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1941681Sdfr * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 2041681Sdfr * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2141681Sdfr * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2241681Sdfr * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2341681Sdfr * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2441681Sdfr * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2541681Sdfr * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2641681Sdfr */ 2741681Sdfr 2841681Sdfr/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 2941681Sdfr 3041681Sdfr#include <sys/param.h> 3141681Sdfr#include <sys/systm.h> 3241681Sdfr#include <sys/device.h> 3341681Sdfr#include <sys/malloc.h> 3441681Sdfr#include <sys/buf.h> 3541681Sdfr#include <sys/kernel.h> 3641681Sdfr 3741681Sdfr#include <machine/endian.h> 3841681Sdfr 3941681Sdfr#include <dev/pci/pcireg.h> 4041681Sdfr#include <dev/pci/pcivar.h> 4141681Sdfr#include <dev/pci/pcidevs.h> 4241681Sdfr 4341681Sdfr#include <scsi/scsi_all.h> 4441681Sdfr#include <scsi/scsiconf.h> 4541681Sdfr 4641681Sdfr#include <dev/ic/siopreg.h> 4741681Sdfr#include <dev/ic/siopvar_common.h> 4841681Sdfr#include <dev/pci/siop_pci_common.h> 4941681Sdfr 5041681Sdfr/* List (array, really :) of chips we know how to handle */ 5141681Sdfrconst struct siop_product_desc siop_products[] = { 5241681Sdfr { PCI_PRODUCT_SYMBIOS_810, 5341681Sdfr 0x00, 5441681Sdfr SF_PCI_RL | SF_CHIP_LS, 5541681Sdfr 4, 8, 3, 250, 0 5641681Sdfr }, 5741681Sdfr { PCI_PRODUCT_SYMBIOS_810, 5841681Sdfr 0x10, 5941681Sdfr SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 6041681Sdfr 4, 8, 3, 250, 0 6141681Sdfr }, 6241681Sdfr { PCI_PRODUCT_SYMBIOS_815, 6341681Sdfr 0x00, 6441681Sdfr SF_PCI_RL | SF_PCI_BOF, 6541681Sdfr 4, 8, 3, 250, 0 6641681Sdfr }, 6763212Sabial { PCI_PRODUCT_SYMBIOS_820, 6863212Sabial 0x00, 6941681Sdfr SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 70255362Smarkm 4, 8, 3, 250, 0 7141681Sdfr }, 7241681Sdfr { PCI_PRODUCT_SYMBIOS_825, 73 0x00, 74 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 75 4, 8, 3, 250, 0 76 }, 77 { PCI_PRODUCT_SYMBIOS_825, 78 0x10, 79 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 80 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 81 SF_BUS_WIDE, 82 7, 8, 3, 250, 4096 83 }, 84 { PCI_PRODUCT_SYMBIOS_860, 85 0x00, 86 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 87 SF_CHIP_PF | SF_CHIP_LS | 88 SF_BUS_ULTRA, 89 4, 8, 5, 125, 0 90 }, 91 { PCI_PRODUCT_SYMBIOS_875, 92 0x00, 93 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 94 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 95 SF_BUS_ULTRA | SF_BUS_WIDE, 96 7, 16, 5, 125, 4096 97 }, 98 { PCI_PRODUCT_SYMBIOS_875, 99 0x02, 100 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 101 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 102 SF_CHIP_LS | SF_CHIP_10REGS | 103 SF_BUS_ULTRA | SF_BUS_WIDE, 104 7, 16, 5, 125, 4096 105 }, 106 { PCI_PRODUCT_SYMBIOS_875J, 107 0x00, 108 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 109 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 110 SF_CHIP_LS | SF_CHIP_10REGS | 111 SF_BUS_ULTRA | SF_BUS_WIDE, 112 7, 16, 5, 125, 4096 113 }, 114 { PCI_PRODUCT_SYMBIOS_885, 115 0x00, 116 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 117 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 118 SF_CHIP_LS | SF_CHIP_10REGS | 119 SF_BUS_ULTRA | SF_BUS_WIDE, 120 7, 16, 5, 125, 4096 121 }, 122 { PCI_PRODUCT_SYMBIOS_895, 123 0x00, 124 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 125 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 126 SF_CHIP_LS | SF_CHIP_10REGS | 127 SF_BUS_ULTRA2 | SF_BUS_WIDE, 128 7, 31, 7, 62, 4096 129 }, 130 { PCI_PRODUCT_SYMBIOS_896, 131 0x00, 132 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 133 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 134 SF_CHIP_LS | SF_CHIP_10REGS | 135 SF_BUS_ULTRA2 | SF_BUS_WIDE, 136 7, 31, 7, 62, 8192 137 }, 138 { PCI_PRODUCT_SYMBIOS_895A, 139 0x00, 140 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 141 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 142 SF_CHIP_LS | SF_CHIP_10REGS | 143 SF_BUS_ULTRA2 | SF_BUS_WIDE, 144 7, 31, 7, 62, 8192 145 }, 146 { PCI_PRODUCT_SYMBIOS_1010, 147 0x00, 148 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 149 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 150 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 151 SF_CHIP_GEBUG | 152 SF_BUS_ULTRA3 | SF_BUS_WIDE, 153 7, 31, 0, 62, 8192 154 }, 155 { PCI_PRODUCT_SYMBIOS_1010, 156 0x01, 157 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 158 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 159 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 160 SF_CHIP_GEBUG | 161 SF_BUS_ULTRA3 | SF_BUS_WIDE, 162 7, 62, 0, 62, 8192 163 }, 164 { PCI_PRODUCT_SYMBIOS_1010_2, 165 0x00, 166 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 167 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 168 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 169 SF_CHIP_AAIP | 170 SF_BUS_ULTRA3 | SF_BUS_WIDE, 171 7, 62, 0, 62, 8192 172 }, 173 { PCI_PRODUCT_SYMBIOS_1510D, 174 0x00, 175 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 176 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 177 SF_CHIP_LS | SF_CHIP_10REGS | 178 SF_BUS_ULTRA2 | SF_BUS_WIDE, 179 7, 31, 7, 62, 4096 180 }, 181 { 0, 182 0x00, 183 0x00, 184 0, 0, 0, 0, 0 185 }, 186}; 187 188const struct siop_product_desc * 189siop_lookup_product(u_int32_t id, int rev) 190{ 191 const struct siop_product_desc *pp; 192 const struct siop_product_desc *rp = NULL; 193 194 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 195 return NULL; 196 197 for (pp = siop_products; pp->product != 0; pp++) { 198 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 199 if (rp == NULL || pp->revision > rp->revision) 200 rp = pp; 201 } 202 return rp; 203} 204 205int 206siop_pci_attach_common(struct siop_pci_common_softc *pci_sc, 207 struct siop_common_softc *siop_sc, struct pci_attach_args *pa, 208 int (*intr)(void*)) 209{ 210 pci_chipset_tag_t pc = pa->pa_pc; 211 pcitag_t tag = pa->pa_tag; 212 const char *intrstr; 213 pci_intr_handle_t intrhandle; 214 bus_space_tag_t iot, memt; 215 bus_space_handle_t ioh, memh; 216 pcireg_t memtype; 217 int memh_valid, ioh_valid; 218 bus_addr_t ioaddr, memaddr; 219 bus_size_t iosize, memsize, ramsize; 220 221 pci_sc->sc_pp = 222 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 223 if (pci_sc->sc_pp == NULL) { 224 printf(": broken match/attach!\n"); 225 return 0; 226 } 227 /* copy interesting infos about the chip */ 228 siop_sc->features = pci_sc->sc_pp->features; 229#ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 230 siop_sc->features |= SF_CHIP_LED0; 231#endif 232 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 233 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 234 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 235 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 236 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 237 238 siop_sc->sc_reset = siop_pci_reset; 239 pci_sc->sc_pc = pc; 240 pci_sc->sc_tag = tag; 241 siop_sc->sc_dmat = pa->pa_dmat; 242 243 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 244 switch (memtype) { 245 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 246 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 247 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 248 &memt, &memh, &memaddr, &memsize, 0) == 0); 249 break; 250 default: 251 memh_valid = 0; 252 } 253 254 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 255 &iot, &ioh, &ioaddr, &iosize, 0) == 0); 256 257 if (memh_valid) { 258 siop_sc->sc_rt = memt; 259 siop_sc->sc_rh = memh; 260 siop_sc->sc_raddr = memaddr; 261 } else if (ioh_valid) { 262 siop_sc->sc_rt = iot; 263 siop_sc->sc_rh = ioh; 264 siop_sc->sc_raddr = ioaddr; 265 } else { 266 printf(": unable to map device registers\n"); 267 return 0; 268 } 269 270 if (pci_intr_map(pa, &intrhandle) != 0) { 271 printf(": couldn't map interrupt\n"); 272 goto out; 273 } 274 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 275 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 276 intr, siop_sc, siop_sc->sc_dev.dv_xname); 277 if (pci_sc->sc_ih != NULL) { 278 printf(": %s", 279 intrstr ? intrstr : "?"); 280 } else { 281 printf(": couldn't establish interrupt"); 282 if (intrstr != NULL) 283 printf(" at %s", intrstr); 284 printf("\n"); 285 goto out; 286 } 287 288 if (siop_sc->features & SF_CHIP_RAM) { 289 int bar; 290 switch (memtype) { 291 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 292 bar = 0x18; 293 break; 294 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 295 bar = 0x1c; 296 break; 297 default: 298 printf(": invalid memory type %d\n", memtype); 299 goto out; 300 } 301 if (pci_mapreg_map(pa, bar, memtype, 0, 302 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 303 &siop_sc->sc_scriptaddr, &ramsize, 0) == 0) { 304 printf(", using %luK of on-board RAM", 305 (u_long)ramsize / 1024); 306 } else { 307 printf(", can't map on-board RAM"); 308 siop_sc->features &= ~SF_CHIP_RAM; 309 } 310 } 311 312 printf("\n"); 313 314 return (1); 315 316 out: 317 if (pci_sc->sc_ih) { 318 pci_intr_disestablish(pa->pa_pc, pci_sc->sc_ih); 319 pci_sc->sc_ih = NULL; 320 } 321 if (ioh_valid) 322 bus_space_unmap(iot, ioh, iosize); 323 if (memh_valid) 324 bus_space_unmap(memt, memh, memsize); 325 return (0); 326} 327 328void 329siop_pci_reset(struct siop_common_softc *sc) 330{ 331 int dmode; 332 333 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 334 if (sc->features & SF_PCI_RL) 335 dmode |= DMODE_ERL; 336 if (sc->features & SF_PCI_RM) 337 dmode |= DMODE_ERMP; 338 if (sc->features & SF_PCI_BOF) 339 dmode |= DMODE_BOF; 340 if (sc->features & SF_PCI_CLS) 341 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 342 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 343 DCNTL_CLSE); 344 if (sc->features & SF_PCI_WRI) 345 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 346 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 347 CTEST3_WRIE); 348 if (sc->maxburst) { 349 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 350 SIOP_CTEST5); 351 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 352 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 353 ~CTEST4_BDIS); 354 dmode &= ~DMODE_BL_MASK; 355 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 356 ctest5 &= ~CTEST5_BBCK; 357 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 358 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 359 } else { 360 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 361 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 362 CTEST4_BDIS); 363 } 364 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 365} 366