siop_pci_common.c revision 1.1
1/* $OpenBSD: siop_pci_common.c,v 1.1 2001/02/15 04:07:58 krw Exp $ */ 2/* $NetBSD: siop_pci_common.c,v 1.6 2001/01/10 15:50:20 thorpej Exp $ */ 3 4/* 5 * Copyright (c) 2000 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/device.h> 38#include <sys/malloc.h> 39#include <sys/buf.h> 40#include <sys/kernel.h> 41 42#include <machine/endian.h> 43 44#include <dev/pci/pcireg.h> 45#include <dev/pci/pcivar.h> 46#include <dev/pci/pcidevs.h> 47 48#include <scsi/scsi_all.h> 49#include <scsi/scsiconf.h> 50 51#include <dev/ic/siopreg.h> 52#include <dev/ic/siopvar.h> 53#include <dev/pci/siop_pci_common.h> 54 55/* List (array, really :) of chips we know how to handle */ 56const struct siop_product_desc siop_products[] = { 57 { PCI_PRODUCT_SYMBIOS_810, 58 0x00, 59 "Symbios Logic 53c810 (fast scsi)", 60 SF_PCI_RL | SF_CHIP_LS, 61 4, 8, 3, 250, 0 62 }, 63 { PCI_PRODUCT_SYMBIOS_810, 64 0x10, 65 "Symbios Logic 53c810a (fast scsi)", 66 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 67 4, 8, 3, 250, 0 68 }, 69 { PCI_PRODUCT_SYMBIOS_815, 70 0x00, 71 "Symbios Logic 53c815 (fast scsi)", 72 SF_PCI_RL | SF_PCI_BOF, 73 4, 8, 3, 250, 0 74 }, 75 { PCI_PRODUCT_SYMBIOS_820, 76 0x00, 77 "Symbios Logic 53c820 (fast wide scsi)", 78 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 79 4, 8, 3, 250, 0 80 }, 81 { PCI_PRODUCT_SYMBIOS_825, 82 0x00, 83 "Symbios Logic 53c825 (fast wide scsi)", 84 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 85 4, 8, 3, 250, 0 86 }, 87 { PCI_PRODUCT_SYMBIOS_825, 88 0x10, 89 "Symbios Logic 53c825a (fast wide scsi)", 90 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 91 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 92 SF_BUS_WIDE, 93 7, 8, 3, 250, 4096 94 }, 95 { PCI_PRODUCT_SYMBIOS_860, 96 0x00, 97 "Symbios Logic 53c860 (ultra scsi)", 98 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 99 SF_CHIP_PF | SF_CHIP_LS | 100 SF_BUS_ULTRA, 101 4, 8, 5, 125, 0 102 }, 103 { PCI_PRODUCT_SYMBIOS_875, 104 0x00, 105 "Symbios Logic 53c875 (ultra-wide scsi)", 106 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 107 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 108 SF_BUS_ULTRA | SF_BUS_WIDE, 109 7, 16, 5, 125, 4096 110 }, 111 { PCI_PRODUCT_SYMBIOS_875, 112 0x02, 113 "Symbios Logic 53c875 (ultra-wide scsi)", 114 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 115 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 116 SF_CHIP_LS | SF_CHIP_10REGS | 117 SF_BUS_ULTRA | SF_BUS_WIDE, 118 7, 16, 5, 125, 4096 119 }, 120 { PCI_PRODUCT_SYMBIOS_875J, 121 0x00, 122 "Symbios Logic 53c875j (ultra-wide scsi)", 123 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 124 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 125 SF_CHIP_LS | SF_CHIP_10REGS | 126 SF_BUS_ULTRA | SF_BUS_WIDE, 127 7, 16, 5, 125, 4096 128 }, 129 { PCI_PRODUCT_SYMBIOS_885, 130 0x00, 131 "Symbios Logic 53c885 (ultra-wide scsi)", 132 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 133 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 134 SF_CHIP_LS | SF_CHIP_10REGS | 135 SF_BUS_ULTRA | SF_BUS_WIDE, 136 7, 16, 5, 125, 4096 137 }, 138 { PCI_PRODUCT_SYMBIOS_895, 139 0x00, 140 "Symbios Logic 53c895 (ultra2-wide scsi)", 141 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 142 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 143 SF_CHIP_LS | SF_CHIP_10REGS | 144 SF_BUS_ULTRA2 | SF_BUS_WIDE, 145 7, 31, 7, 62, 4096 146 }, 147 { PCI_PRODUCT_SYMBIOS_896, 148 0x00, 149 "Symbios Logic 53c896 (ultra2-wide scsi)", 150 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 151 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 152 SF_CHIP_LS | SF_CHIP_10REGS | 153 SF_BUS_ULTRA2 | SF_BUS_WIDE, 154 7, 31, 7, 62, 8192 155 }, 156 { PCI_PRODUCT_SYMBIOS_895A, 157 0x00, 158 "Symbios Logic 53c895a (ultra2-wide scsi)", 159 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 160 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 161 SF_CHIP_LS | SF_CHIP_10REGS | 162 SF_BUS_ULTRA2 | SF_BUS_WIDE, 163 7, 31, 7, 62, 8192 164 }, 165 { PCI_PRODUCT_SYMBIOS_1510D, 166 0x00, 167 "Symbios Logic 53c1510d (ultra2-wide scsi)", 168 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 169 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 170 SF_CHIP_LS | SF_CHIP_10REGS | 171 SF_BUS_ULTRA2 | SF_BUS_WIDE, 172 7, 31, 7, 62, 4096 173 }, 174 { 0, 175 0x00, 176 NULL, 177 0x00, 178 0, 0, 0, 0, 0 179 }, 180}; 181 182const struct siop_product_desc * 183siop_lookup_product(id, rev) 184 u_int32_t id; 185 int rev; 186{ 187 const struct siop_product_desc *pp; 188 const struct siop_product_desc *rp = NULL; 189 190 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 191 return NULL; 192 193 for (pp = siop_products; pp->name != NULL; pp++) { 194 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 195 if (rp == NULL || pp->revision > rp->revision) 196 rp = pp; 197 } 198 return rp; 199} 200 201int 202siop_pci_attach_common(sc, pa) 203 struct siop_pci_softc *sc; 204 struct pci_attach_args *pa; 205{ 206 pci_chipset_tag_t pc = pa->pa_pc; 207 pcitag_t tag = pa->pa_tag; 208 const char *intrstr; 209 pci_intr_handle_t intrhandle; 210 bus_space_tag_t iot, memt; 211 bus_space_handle_t ioh, memh; 212 pcireg_t memtype; 213 int memh_valid, ioh_valid; 214 bus_addr_t ioaddr, memaddr; 215 216 sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 217 if (sc->sc_pp == NULL) { 218 printf("sym: broken match/attach!!\n"); 219 return 0; 220 } 221 /* copy interesting infos about the chip */ 222 sc->siop.features = sc->sc_pp->features; 223 sc->siop.maxburst = sc->sc_pp->maxburst; 224 sc->siop.maxoff = sc->sc_pp->maxoff; 225 sc->siop.clock_div = sc->sc_pp->clock_div; 226 sc->siop.clock_period = sc->sc_pp->clock_period; 227 sc->siop.ram_size = sc->sc_pp->ram_size; 228 229 sc->siop.sc_reset = siop_pci_reset; 230 printf(": %s\n", sc->sc_pp->name); 231 sc->sc_pc = pc; 232 sc->sc_tag = tag; 233 sc->siop.sc_dmat = pa->pa_dmat; 234 235 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 236 switch (memtype) { 237 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 238 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 239 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 240 &memt, &memh, &memaddr, NULL) == 0); 241 break; 242 default: 243 memh_valid = 0; 244 } 245 246 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 247 &iot, &ioh, &ioaddr, NULL) == 0); 248 249 if (memh_valid) { 250 sc->siop.sc_rt = memt; 251 sc->siop.sc_rh = memh; 252 sc->siop.sc_raddr = memaddr; 253 } else if (ioh_valid) { 254 sc->siop.sc_rt = iot; 255 sc->siop.sc_rh = ioh; 256 sc->siop.sc_raddr = ioaddr; 257 } else { 258 printf("%s: unable to map device registers\n", 259 sc->siop.sc_dev.dv_xname); 260 return 0; 261 } 262 263 if (sc->siop.features & SF_CHIP_RAM) { 264 int bar; 265 switch (memtype) { 266 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 267 bar = 0x18; 268 break; 269 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 270 bar = 0x1c; 271 break; 272 } 273 if (pci_mapreg_map(pa, bar, memtype, 0, 274 &sc->siop.sc_ramt, &sc->siop.sc_ramh, 275 &sc->siop.sc_scriptaddr, NULL) == 0) { 276 printf("%s: using on-board RAM\n", 277 sc->siop.sc_dev.dv_xname); 278 } else { 279 printf("%s: can't map on-board RAM\n", 280 sc->siop.sc_dev.dv_xname); 281 sc->siop.features &= ~SF_CHIP_RAM; 282 } 283 } 284 285 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 286 pa->pa_intrline, &intrhandle)) { 287 printf("%s: couldn't map interrupt\n", 288 sc->siop.sc_dev.dv_xname); 289 return 0; 290 } 291 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 292 sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 293 siop_intr, &sc->siop, sc->siop.sc_dev.dv_xname); 294 if (sc->sc_ih != NULL) { 295 printf("%s: interrupting at %s\n", 296 sc->siop.sc_dev.dv_xname, 297 intrstr ? intrstr : "unknown interrupt"); 298 } else { 299 printf("%s: couldn't establish interrupt", 300 sc->siop.sc_dev.dv_xname); 301 if (intrstr != NULL) 302 printf(" at %s", intrstr); 303 printf("\n"); 304 return 0; 305 } 306 return 1; 307} 308 309void 310siop_pci_reset(sc) 311 struct siop_softc *sc; 312{ 313 int dmode; 314 315 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 316 if (sc->features & SF_PCI_RL) 317 dmode |= DMODE_ERL; 318 if (sc->features & SF_PCI_RM) 319 dmode |= DMODE_ERMP; 320 if (sc->features & SF_PCI_BOF) 321 dmode |= DMODE_BOF; 322 if (sc->features & SF_PCI_CLS) 323 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 324 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 325 DCNTL_CLSE); 326 if (sc->features & SF_PCI_WRI) 327 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 328 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 329 CTEST3_WRIE); 330 if (sc->maxburst) { 331 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 332 SIOP_CTEST5); 333 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 334 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 335 ~CTEST4_BDIS); 336 dmode &= ~DMODE_BL_MASK; 337 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 338 ctest5 &= ~CTEST5_BBCK; 339 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 340 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 341 } else { 342 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 343 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 344 CTEST4_BDIS); 345 } 346 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 347} 348