1/* $OpenBSD: piixreg.h,v 1.6 2020/01/21 06:37:24 claudio Exp $ */ 2 3/* 4 * Copyright (c) 2005 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19#ifndef _DEV_PCI_PIIXREG_H_ 20#define _DEV_PCI_PIIXREG_H_ 21 22/* 23 * Intel PCI-to-ISA / IDE Xcelerator (PIIX) register definitions. 24 */ 25 26/* 27 * Power management registers. 28 */ 29 30/* PCI configuration registers */ 31#define PIIX_SMB_BASE 0x90 /* SMBus base address */ 32#define PIIX_SMB_BASE_MASK 0xfffe 33#define PIIX_SMB_HOSTC 0xd0 /* SMBus host configuration */ 34#define PIIX_SMB_HOSTC_HSTEN (1 << 16) /* enable host controller */ 35#define PIIX_SMB_HOSTC_SMI (0 << 17) /* SMI */ 36#define PIIX_SMB_HOSTC_IRQ (4 << 17) /* IRQ */ 37#define PIIX_SMB_HOSTC_INTMASK (7 << 17) 38 39/* SMBus I/O registers */ 40#define PIIX_SMB_HS 0x00 /* host status */ 41#define PIIX_SMB_HS_BUSY (1 << 0) /* running a command */ 42#define PIIX_SMB_HS_INTR (1 << 1) /* command completed */ 43#define PIIX_SMB_HS_DEVERR (1 << 2) /* command error */ 44#define PIIX_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 45#define PIIX_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 46#define PIIX_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED" 47#define PIIX_SMB_HC 0x02 /* host control */ 48#define PIIX_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 49#define PIIX_SMB_HC_KILL (1 << 1) /* kill current transaction */ 50#define PIIX_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 51#define PIIX_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 52#define PIIX_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 53#define PIIX_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 54#define PIIX_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 55#define PIIX_SMB_HC_START (1 << 6) /* start transaction */ 56#define PIIX_SMB_HCMD 0x03 /* host command */ 57#define PIIX_SMB_TXSLVA 0x04 /* transmit slave address */ 58#define PIIX_SMB_TXSLVA_READ (1 << 0) /* read direction */ 59#define PIIX_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 60#define PIIX_SMB_HD0 0x05 /* host data 0 */ 61#define PIIX_SMB_HD1 0x06 /* host data 1 */ 62#define PIIX_SMB_HBDB 0x07 /* host block data byte */ 63#define PIIX_SMB_SC 0x08 /* slave control */ 64#define PIIX_SMB_SC_ALERTEN (1 << 3) /* enable SMBALERT# */ 65 66#define PIIX_SMB_SIZE 0x10 /* SMBus I/O space size */ 67 68/* AMD SB800 configuration registers */ 69#define SB800_PMREG_BASE 0xcd6 70#define SB800_PMREG_SIZE 2 /* index/data pair */ 71#define SB800_PMREG_SMB0EN 0x2c /* 16-bit register */ 72#define SB800_PMREG_SMB0SEL 0x2e /* bus selection */ 73#define SB800_PMREG_SMB0SELEN 0x2f /* bus selection enable */ 74#define SB800_SMB0EN_EN 0x0001 75#define SB800_SMB0EN_BASE_MASK 0xffe0 76#define SB800_SMB0SELEN_EN 0x01 77 78#define SB800_SMB_HOSTC 0x10 /* I2C bus configuration */ 79#define SB800_SMB_HOSTC_INTMASK 0x1 /* 0: SMI 1: IRQ */ 80 81#define SB800_SMB_SIZE 0x14 /* SMBus I/O space size */ 82 83/* 84 * Newer FCH registers in the PMIO space. 85 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 86 */ 87#define AMDFCH41_PM_DECODE_EN 0x00 /* 16-bit register */ 88#define AMDFCH41_PM_PORT_INDEX 0x02 89#define AMDFCH41_SMBUS_EN 0x10 90 91#endif /* !_DEV_PCI_PIIXREG_H_ */ 92