1/* $OpenBSD: pciide_apollo_reg.h,v 1.10 2010/07/23 07:47:13 jsg Exp $ */ 2/* $NetBSD: pciide_apollo_reg.h,v 1.8 2001/01/05 18:04:43 bouyer Exp $ */ 3 4/* 5 * Copyright (c) 1998 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29#ifndef _DEV_PCI_PCIIDE_APOLLO_REG_H_ 30#define _DEV_PCI_PCIIDE_APOLLO_REG_H_ 31 32/* 33 * Registers definitions for VIA technologies's Apollo controllers (VT82V580VO, 34 * VT82C586A and VT82C586B). 35 * 36 * UDMA1/2/3/4 capable 37 * http://www.via.com.tw/pdf/productinfo/686a.pdf 38 * http://www.via.com.tw/pdf/productinfo/596b.pdf 39 * 40 * UDMA1/2 capable 41 * http://www.via.com.tw/pdf/productinfo/586b.pdf 42 * http://www.via.com.tw/pdf/productinfo/586a.pdf 43 */ 44 45/* misc. configuration registers */ 46#define APO_IDECONF 0x40 47#define APO_IDECONF_EN(channel) (0x00000001 << (1 - (channel))) 48#define APO_IDECONF_SERR_EN 0x00000100 /* 580 only */ 49#define APO_IDECONF_DS_SOURCE 0x00000200 /* 580 only */ 50#define APO_IDECONF_ALT_INTR_EN 0x00000400 /* 580 only */ 51#define APO_IDECONF_PERR_EN 0x00000800 /* 580 only */ 52#define APO_IDECONF_WR_BUFF_EN(channel) (0x00001000 << ((1 - (channel)) << 1)) 53#define APO_IDECONF_RD_PREF_EN(channel) (0x00002000 << ((1 - (channel)) << 1)) 54#define APO_IDECONF_DEVSEL_TME 0x00010000 /* 580 only */ 55#define APO_IDECONF_MAS_CMD_MON 0x00020000 /* 580 only */ 56#define APO_IDECONF_IO_NAT(channel) \ 57 (0x00400000 << (1 - (channel))) /* 580 only */ 58#define APO_IDECONF_FIFO_TRSH(channel, x) \ 59 ((x) & 0x3) << ((1 - (channel)) << 1 + 24) 60#define APO_IDECONF_FIFO_CONF_MASK 0x60000000 61 62/* Misc. controls register */ 63#define APO_CTLMISC 0x44 64#define APO_CTLMISC_BM_STS_RTY 0x00000008 65#define APO_CTLMISC_FIFO_HWS 0x00000010 66#define APO_CTLMISC_WR_IRDY_WS 0x00000020 67#define APO_CTLMISC_RD_IRDY_WS 0x00000040 68#define APO_CTLMISC_INTR_SWP 0x00004000 69#define APO_CTLMISC_DRDY_TIME_MASK 0x00030000 70#define APO_CTLMISC_FIFO_FLSH_RD(channel) (0x00100000 << (1 - (channel))) 71#define APO_CTLMISC_FIFO_FLSH_DMA(channel) (0x00400000 << (1 - (channel))) 72 73/* data port timings controls */ 74#define APO_DATATIM 0x48 75#define APO_DATATIM_MASK(channel) (0xffff << ((1 - (channel)) << 4)) 76#define APO_DATATIM_RECOV(channel, drive, x) (((x) & 0xf) << \ 77 (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) 78#define APO_DATATIM_PULSE(channel, drive, x) (((x) & 0xf) << \ 79 (((1 - (channel)) << 4) + ((1 - (drive)) << 3) + 4)) 80 81/* misc timings control */ 82#define APO_MISCTIM 0x4c 83 84/* UltraDMA control (586A/B and higher only) */ 85#define APO_UDMA 0x50 86#define APO_UDMA_MASK(channel) (0xffff << ((1 - (channel)) << 4)) 87#define APO_UDMA_TIME(channel, drive, x) (((x) & 0xf) << \ 88 (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) 89#define APO_UDMA_PIO_MODE(channel, drive) (0x20 << \ 90 (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) 91#define APO_UDMA_EN(channel, drive) (0x40 << \ 92 (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) 93#define APO_UDMA_EN_MTH(channel, drive) (0x80 << \ 94 (((1 - (channel)) << 4) + ((1 - (drive)) << 3))) 95#define APO_UDMA_CLK66(channel) (0x08 << ((1 - (channel)) << 4)) 96 97static int8_t apollo_udma133_tim[] = {0x07, 0x07, 0x06, 0x04, 0x02, 0x01, 0x00}; 98static int8_t apollo_udma100_tim[] = {0x07, 0x07, 0x04, 0x02, 0x01, 0x00}; 99static int8_t apollo_udma66_tim[] = {0x03, 0x03, 0x02, 0x01, 0x00}; 100static int8_t apollo_udma33_tim[] = {0x03, 0x02, 0x00}; 101static int8_t apollo_pio_set[] = {0x0a, 0x0a, 0x0a, 0x02, 0x02}; 102static int8_t apollo_pio_rec[] = {0x08, 0x08, 0x08, 0x02, 0x00}; 103 104#endif /* !_DEV_PCI_PCIIDE_APOLLO_REG_H_ */ 105