1/* $OpenBSD: ixgbe_82599.c,v 1.19 2020/03/02 01:59:01 jmatthew Exp $ */ 2 3/****************************************************************************** 4 SPDX-License-Identifier: BSD-3-Clause 5 6 Copyright (c) 2001-2017, Intel Corporation 7 All rights reserved. 8 9 Redistribution and use in source and binary forms, with or without 10 modification, are permitted provided that the following conditions are met: 11 12 1. Redistributions of source code must retain the above copyright notice, 13 this list of conditions and the following disclaimer. 14 15 2. Redistributions in binary form must reproduce the above copyright 16 notice, this list of conditions and the following disclaimer in the 17 documentation and/or other materials provided with the distribution. 18 19 3. Neither the name of the Intel Corporation nor the names of its 20 contributors may be used to endorse or promote products derived from 21 this software without specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 27 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 POSSIBILITY OF SUCH DAMAGE. 34 35******************************************************************************/ 36/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_82599.c 326022 2017-11-20 19:36:21Z pfg $*/ 37 38 39#include <dev/pci/ixgbe.h> 40#include <dev/pci/ixgbe_type.h> 41 42#define IXGBE_82599_MAX_TX_QUEUES 128 43#define IXGBE_82599_MAX_RX_QUEUES 128 44#define IXGBE_82599_RAR_ENTRIES 128 45#define IXGBE_82599_MC_TBL_SIZE 128 46#define IXGBE_82599_VFT_TBL_SIZE 128 47#define IXGBE_82599_RX_PB_SIZE 512 48 49int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 50 ixgbe_link_speed *speed, 51 bool *autoneg); 52enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw); 53void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 54void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 55void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw); 56void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 57 ixgbe_link_speed speed); 58int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 59 ixgbe_link_speed speed, 60 bool autoneg_wait_to_complete); 61int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 62 bool autoneg_wait_to_complete); 63int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 64 ixgbe_link_speed speed, 65 bool autoneg_wait_to_complete); 66int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw); 67void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw); 68int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw); 69int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 70 uint8_t *val); 71int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 72 uint8_t val); 73int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw); 74int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw); 75int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw); 76uint64_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw); 77int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval); 78int32_t prot_autoc_read_82599(struct ixgbe_hw *, bool *locked, uint32_t *reg_val); 79int32_t prot_autoc_write_82599(struct ixgbe_hw *, uint32_t reg_val, bool locked); 80 81void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw); 82 83int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 84 ixgbe_link_speed speed, 85 bool autoneg_wait_to_complete); 86 87int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw); 88bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw); 89int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw); 90int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 91 uint16_t offset, uint16_t *data); 92int32_t ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset, 93 uint8_t dev_addr, uint8_t *data); 94int32_t ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset, 95 uint8_t dev_addr, uint8_t data); 96 97void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw) 98{ 99 struct ixgbe_mac_info *mac = &hw->mac; 100 101 DEBUGFUNC("ixgbe_init_mac_link_ops_82599"); 102 103 /* 104 * enable the laser control functions for SFP+ fiber 105 * and MNG not enabled 106 */ 107 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && 108 !ixgbe_mng_enabled(hw)) { 109 mac->ops.disable_tx_laser = 110 ixgbe_disable_tx_laser_multispeed_fiber; 111 mac->ops.enable_tx_laser = 112 ixgbe_enable_tx_laser_multispeed_fiber; 113 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; 114 115 } else { 116 mac->ops.disable_tx_laser = NULL; 117 mac->ops.enable_tx_laser = NULL; 118 mac->ops.flap_tx_laser = NULL; 119 } 120 121 if (hw->phy.multispeed_fiber) { 122 /* Set up dual speed SFP+ support */ 123 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 124 mac->ops.setup_mac_link = ixgbe_setup_mac_link_82599; 125 mac->ops.set_rate_select_speed = 126 ixgbe_set_hard_rate_select_speed; 127 if (ixgbe_get_media_type(hw) == ixgbe_media_type_fiber_fixed) 128 mac->ops.set_rate_select_speed = 129 ixgbe_set_soft_rate_select_speed; 130 } else { 131 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) && 132 (hw->phy.smart_speed == ixgbe_smart_speed_auto || 133 hw->phy.smart_speed == ixgbe_smart_speed_on) && 134 !ixgbe_verify_lesm_fw_enabled_82599(hw)) { 135 mac->ops.setup_link = ixgbe_setup_mac_link_smartspeed; 136 } else { 137 mac->ops.setup_link = ixgbe_setup_mac_link_82599; 138 } 139 } 140} 141 142/** 143 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init 144 * @hw: pointer to hardware structure 145 * 146 * Initialize any function pointers that were not able to be 147 * set during init_shared_code because the PHY/SFP type was 148 * not known. Perform the SFP init if necessary. 149 * 150 **/ 151int32_t ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw) 152{ 153 struct ixgbe_mac_info *mac = &hw->mac; 154 struct ixgbe_phy_info *phy = &hw->phy; 155 int32_t ret_val = IXGBE_SUCCESS; 156 uint32_t esdp; 157 158 DEBUGFUNC("ixgbe_init_phy_ops_82599"); 159 160 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) { 161 /* Store flag indicating I2C bus access control unit. */ 162 hw->phy.qsfp_shared_i2c_bus = TRUE; 163 164 /* Initialize access to QSFP+ I2C bus */ 165 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 166 esdp |= IXGBE_ESDP_SDP0_DIR; 167 esdp &= ~IXGBE_ESDP_SDP1_DIR; 168 esdp &= ~IXGBE_ESDP_SDP0; 169 esdp &= ~IXGBE_ESDP_SDP0_NATIVE; 170 esdp &= ~IXGBE_ESDP_SDP1_NATIVE; 171 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 172 IXGBE_WRITE_FLUSH(hw); 173 174 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_82599; 175 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_82599; 176 } 177 /* Identify the PHY or SFP module */ 178 ret_val = phy->ops.identify(hw); 179 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 180 goto init_phy_ops_out; 181 182 /* Setup function pointers based on detected SFP module and speeds */ 183 ixgbe_init_mac_link_ops_82599(hw); 184 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) 185 hw->phy.ops.reset = NULL; 186 187 /* If copper media, overwrite with copper function pointers */ 188 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) { 189 mac->ops.setup_link = ixgbe_setup_copper_link_82599; 190 mac->ops.get_link_capabilities = 191 ixgbe_get_copper_link_capabilities_generic; 192 } 193 194 /* Set necessary function pointers based on PHY type */ 195 switch (hw->phy.type) { 196 case ixgbe_phy_tn: 197 phy->ops.setup_link = ixgbe_setup_phy_link_tnx; 198 phy->ops.check_link = ixgbe_check_phy_link_tnx; 199 phy->ops.get_firmware_version = 200 ixgbe_get_phy_firmware_version_tnx; 201 break; 202 default: 203 break; 204 } 205init_phy_ops_out: 206 return ret_val; 207} 208 209int32_t ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw) 210{ 211 int32_t ret_val = IXGBE_SUCCESS; 212 uint16_t list_offset, data_offset, data_value; 213 214 DEBUGFUNC("ixgbe_setup_sfp_modules_82599"); 215 216 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) { 217 ixgbe_init_mac_link_ops_82599(hw); 218 219 hw->phy.ops.reset = NULL; 220 221 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 222 &data_offset); 223 if (ret_val != IXGBE_SUCCESS) 224 goto setup_sfp_out; 225 226 /* PHY config will finish before releasing the semaphore */ 227 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 228 IXGBE_GSSR_MAC_CSR_SM); 229 if (ret_val != IXGBE_SUCCESS) { 230 ret_val = IXGBE_ERR_SWFW_SYNC; 231 goto setup_sfp_out; 232 } 233 234 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 235 goto setup_sfp_err; 236 while (data_value != 0xffff) { 237 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value); 238 IXGBE_WRITE_FLUSH(hw); 239 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value)) 240 goto setup_sfp_err; 241 } 242 243 /* Release the semaphore */ 244 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 245 /* Delay obtaining semaphore again to allow FW access 246 * prot_autoc_write uses the semaphore too. 247 */ 248 msec_delay(hw->eeprom.semaphore_delay); 249 250 /* Restart DSP and set SFI mode */ 251 ret_val = hw->mac.ops.prot_autoc_write(hw, 252 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL, 253 FALSE); 254 255 if (ret_val) { 256 DEBUGOUT("sfp module setup not complete\n"); 257 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE; 258 goto setup_sfp_out; 259 } 260 261 } 262 263setup_sfp_out: 264 return ret_val; 265 266setup_sfp_err: 267 /* Release the semaphore */ 268 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 269 /* Delay obtaining semaphore again to allow FW access */ 270 msec_delay(hw->eeprom.semaphore_delay); 271 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 272 "eeprom read at offset %d failed", data_offset); 273 return IXGBE_ERR_PHY; 274} 275 276/** 277 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read 278 * @hw: pointer to hardware structure 279 * @locked: Return the if we locked for this read. 280 * @reg_val: Value we read from AUTOC 281 * 282 * For this part (82599) we need to wrap read-modify-writes with a possible 283 * FW/SW lock. It is assumed this lock will be freed with the next 284 * prot_autoc_write_82599(). 285 */ 286int32_t prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, 287 uint32_t *reg_val) 288{ 289 int32_t ret_val; 290 291 *locked = FALSE; 292 /* If LESM is on then we need to hold the SW/FW semaphore. */ 293 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 294 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 295 IXGBE_GSSR_MAC_CSR_SM); 296 if (ret_val != IXGBE_SUCCESS) 297 return IXGBE_ERR_SWFW_SYNC; 298 299 *locked = TRUE; 300 } 301 302 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC); 303 return IXGBE_SUCCESS; 304} 305 306/** 307 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write 308 * @hw: pointer to hardware structure 309 * @autoc: value to write to AUTOC 310 * @locked: bool to indicate whether the SW/FW lock was already taken by 311 * previous proc_autoc_read_82599. 312 * 313 * This part (82599) may need to hold the SW/FW lock around all writes to 314 * AUTOC. Likewise after a write we need to do a pipeline reset. 315 */ 316int32_t prot_autoc_write_82599(struct ixgbe_hw *hw, uint32_t autoc, bool locked) 317{ 318 int32_t ret_val = IXGBE_SUCCESS; 319 320 /* Blocked by MNG FW so bail */ 321 if (ixgbe_check_reset_blocked(hw)) 322 goto out; 323 324 /* We only need to get the lock if: 325 * - We didn't do it already (in the read part of a read-modify-write) 326 * - LESM is enabled. 327 */ 328 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) { 329 ret_val = hw->mac.ops.acquire_swfw_sync(hw, 330 IXGBE_GSSR_MAC_CSR_SM); 331 if (ret_val != IXGBE_SUCCESS) 332 return IXGBE_ERR_SWFW_SYNC; 333 334 locked = TRUE; 335 } 336 337 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc); 338 ret_val = ixgbe_reset_pipeline_82599(hw); 339 340out: 341 /* Free the SW/FW semaphore as we either grabbed it here or 342 * already had it when this function was called. 343 */ 344 if (locked) 345 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 346 347 return ret_val; 348} 349 350/** 351 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type 352 * @hw: pointer to hardware structure 353 * 354 * Initialize the function pointers and assign the MAC type for 82599. 355 * Does not touch the hardware. 356 **/ 357 358int32_t ixgbe_init_ops_82599(struct ixgbe_hw *hw) 359{ 360 struct ixgbe_mac_info *mac = &hw->mac; 361 struct ixgbe_phy_info *phy = &hw->phy; 362 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 363 int32_t ret_val; 364 365 DEBUGFUNC("ixgbe_init_ops_82599"); 366 367 ixgbe_init_phy_ops_generic(hw); 368 ret_val = ixgbe_init_ops_generic(hw); 369 370 /* PHY */ 371 phy->ops.identify = ixgbe_identify_phy_82599; 372 phy->ops.init = ixgbe_init_phy_ops_82599; 373 374 /* MAC */ 375 mac->ops.reset_hw = ixgbe_reset_hw_82599; 376 mac->ops.get_media_type = ixgbe_get_media_type_82599; 377 mac->ops.get_supported_physical_layer = 378 ixgbe_get_supported_physical_layer_82599; 379 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 380 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 381 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_82599; 382 mac->ops.read_analog_reg8 = ixgbe_read_analog_reg8_82599; 383 mac->ops.write_analog_reg8 = ixgbe_write_analog_reg8_82599; 384 mac->ops.start_hw = ixgbe_start_hw_82599; 385 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 386 mac->ops.prot_autoc_read = prot_autoc_read_82599; 387 mac->ops.prot_autoc_write = prot_autoc_write_82599; 388 389 /* RAR, Multicast, VLAN */ 390 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 391 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 392 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 393 mac->rar_highwater = 1; 394 mac->ops.set_vfta = ixgbe_set_vfta_generic; 395 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 396 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 397 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 398 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_82599; 399 400 /* Link */ 401 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_82599; 402 mac->ops.check_link = ixgbe_check_mac_link_generic; 403 mac->ops.stop_mac_link_on_d3 = ixgbe_stop_mac_link_on_d3_82599; 404 ixgbe_init_mac_link_ops_82599(hw); 405 406 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE; 407 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE; 408 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES; 409 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE; 410 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES; 411 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES; 412 mac->max_msix_vectors = 0 /*ixgbe_get_pcie_msix_count_generic(hw)*/; 413 414 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 415 & IXGBE_FWSM_MODE_MASK); 416 417 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 418 419 /* EEPROM */ 420 eeprom->ops.read = ixgbe_read_eeprom_82599; 421 422 return ret_val; 423} 424 425/** 426 * ixgbe_get_link_capabilities_82599 - Determines link capabilities 427 * @hw: pointer to hardware structure 428 * @speed: pointer to link speed 429 * @autoneg: TRUE when autoneg or autotry is enabled 430 * 431 * Determines the link capabilities by reading the AUTOC register. 432 **/ 433int32_t ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw, 434 ixgbe_link_speed *speed, 435 bool *autoneg) 436{ 437 int32_t status = IXGBE_SUCCESS; 438 uint32_t autoc = 0; 439 440 DEBUGFUNC("ixgbe_get_link_capabilities_82599"); 441 442 /* Check if 1G SFP module. */ 443 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 444 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 445 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 446 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 447 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 448 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) { 449 *speed = IXGBE_LINK_SPEED_1GB_FULL; 450 *autoneg = TRUE; 451 goto out; 452 } 453 454 /* 455 * Determine link capabilities based on the stored value of AUTOC, 456 * which represents EEPROM defaults. If AUTOC value has not 457 * been stored, use the current register values. 458 */ 459 if (hw->mac.orig_link_settings_stored) 460 autoc = hw->mac.orig_autoc; 461 else 462 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 463 464 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 465 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 466 *speed = IXGBE_LINK_SPEED_1GB_FULL; 467 *autoneg = FALSE; 468 break; 469 470 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 471 *speed = IXGBE_LINK_SPEED_10GB_FULL; 472 *autoneg = FALSE; 473 break; 474 475 case IXGBE_AUTOC_LMS_1G_AN: 476 *speed = IXGBE_LINK_SPEED_1GB_FULL; 477 *autoneg = TRUE; 478 break; 479 480 case IXGBE_AUTOC_LMS_10G_SERIAL: 481 *speed = IXGBE_LINK_SPEED_10GB_FULL; 482 *autoneg = FALSE; 483 break; 484 485 case IXGBE_AUTOC_LMS_KX4_KX_KR: 486 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 487 *speed = IXGBE_LINK_SPEED_UNKNOWN; 488 if (autoc & IXGBE_AUTOC_KR_SUPP) 489 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 490 if (autoc & IXGBE_AUTOC_KX4_SUPP) 491 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 492 if (autoc & IXGBE_AUTOC_KX_SUPP) 493 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 494 *autoneg = TRUE; 495 break; 496 497 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII: 498 *speed = IXGBE_LINK_SPEED_100_FULL; 499 if (autoc & IXGBE_AUTOC_KR_SUPP) 500 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 501 if (autoc & IXGBE_AUTOC_KX4_SUPP) 502 *speed |= IXGBE_LINK_SPEED_10GB_FULL; 503 if (autoc & IXGBE_AUTOC_KX_SUPP) 504 *speed |= IXGBE_LINK_SPEED_1GB_FULL; 505 *autoneg = TRUE; 506 break; 507 508 case IXGBE_AUTOC_LMS_SGMII_1G_100M: 509 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL; 510 *autoneg = FALSE; 511 break; 512 513 default: 514 status = IXGBE_ERR_LINK_SETUP; 515 goto out; 516 break; 517 } 518 519 if (hw->phy.multispeed_fiber) { 520 *speed |= IXGBE_LINK_SPEED_10GB_FULL | 521 IXGBE_LINK_SPEED_1GB_FULL; 522 523 /* QSFP must not enable full auto-negotiation 524 * Limited autoneg is enabled at 1G 525 */ 526 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp) 527 *autoneg = FALSE; 528 else 529 *autoneg = TRUE; 530 } 531 532out: 533 return status; 534} 535 536/** 537 * ixgbe_get_media_type_82599 - Get media type 538 * @hw: pointer to hardware structure 539 * 540 * Returns the media type (fiber, copper, backplane) 541 **/ 542enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw) 543{ 544 enum ixgbe_media_type media_type; 545 546 DEBUGFUNC("ixgbe_get_media_type_82599"); 547 548 /* Detect if there is a copper PHY attached. */ 549 switch (hw->phy.type) { 550 case ixgbe_phy_cu_unknown: 551 case ixgbe_phy_tn: 552 media_type = ixgbe_media_type_copper; 553 goto out; 554 default: 555 break; 556 } 557 558 switch (hw->device_id) { 559 case IXGBE_DEV_ID_82599_KX4: 560 case IXGBE_DEV_ID_82599_KX4_MEZZ: 561 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 562 case IXGBE_DEV_ID_82599_KR: 563 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 564 case IXGBE_DEV_ID_82599_XAUI_LOM: 565 /* Default device ID is mezzanine card KX/KX4 */ 566 media_type = ixgbe_media_type_backplane; 567 break; 568 case IXGBE_DEV_ID_82599_SFP: 569 case IXGBE_DEV_ID_82599_SFP_FCOE: 570 case IXGBE_DEV_ID_82599_SFP_EM: 571 case IXGBE_DEV_ID_82599_SFP_SF2: 572 case IXGBE_DEV_ID_82599_SFP_SF_QP: 573 case IXGBE_DEV_ID_82599EN_SFP: 574 media_type = ixgbe_media_type_fiber; 575 break; 576 case IXGBE_DEV_ID_82599_CX4: 577 media_type = ixgbe_media_type_cx4; 578 break; 579 case IXGBE_DEV_ID_82599_T3_LOM: 580 media_type = ixgbe_media_type_copper; 581 break; 582 case IXGBE_DEV_ID_82599_QSFP_SF_QP: 583 media_type = ixgbe_media_type_fiber_qsfp; 584 break; 585 case IXGBE_DEV_ID_82599_BYPASS: 586 media_type = ixgbe_media_type_fiber_fixed; 587 hw->phy.multispeed_fiber = TRUE; 588 break; 589 default: 590 media_type = ixgbe_media_type_unknown; 591 break; 592 } 593out: 594 return media_type; 595} 596 597/** 598 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3 599 * @hw: pointer to hardware structure 600 * 601 * Disables link during D3 power down sequence. 602 * 603 **/ 604void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw) 605{ 606 uint32_t autoc2_reg; 607 uint16_t ee_ctrl_2 = 0; 608 609 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599"); 610 if (hw->eeprom.ops.read) 611 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2); 612 613 if (!ixgbe_mng_present(hw) && !hw->wol_enabled && 614 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) { 615 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 616 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK; 617 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 618 } 619} 620 621/** 622 * ixgbe_start_mac_link_82599 - Setup MAC link settings 623 * @hw: pointer to hardware structure 624 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 625 * 626 * Configures link settings based on values in the ixgbe_hw struct. 627 * Restarts the link. Performs autonegotiation if needed. 628 **/ 629int32_t ixgbe_start_mac_link_82599(struct ixgbe_hw *hw, 630 bool autoneg_wait_to_complete) 631{ 632 uint32_t autoc_reg; 633 uint32_t links_reg; 634 uint32_t i; 635 int32_t status = IXGBE_SUCCESS; 636 bool got_lock = FALSE; 637 638 DEBUGFUNC("ixgbe_start_mac_link_82599"); 639 640 641 /* reset_pipeline requires us to hold this lock as it writes to 642 * AUTOC. 643 */ 644 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) { 645 status = hw->mac.ops.acquire_swfw_sync(hw, 646 IXGBE_GSSR_MAC_CSR_SM); 647 if (status != IXGBE_SUCCESS) 648 goto out; 649 650 got_lock = TRUE; 651 } 652 653 /* Restart link */ 654 ixgbe_reset_pipeline_82599(hw); 655 656 if (got_lock) 657 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 658 659 /* Only poll for autoneg to complete if specified to do so */ 660 if (autoneg_wait_to_complete) { 661 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 662 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) == 663 IXGBE_AUTOC_LMS_KX4_KX_KR || 664 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 665 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 666 (autoc_reg & IXGBE_AUTOC_LMS_MASK) == 667 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 668 links_reg = 0; /* Just in case Autoneg time = 0 */ 669 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 670 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 671 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 672 break; 673 msec_delay(100); 674 } 675 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 676 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE; 677 DEBUGOUT("Autoneg did not complete.\n"); 678 } 679 } 680 } 681 682 /* Add delay to filter out noises during initial link setup */ 683 msec_delay(50); 684 685out: 686 return status; 687} 688 689/** 690 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser 691 * @hw: pointer to hardware structure 692 * 693 * The base drivers may require better control over SFP+ module 694 * PHY states. This includes selectively shutting down the Tx 695 * laser on the PHY, effectively halting physical link. 696 **/ 697void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 698{ 699 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 700 701 /* Blocked by MNG FW so bail */ 702 if (ixgbe_check_reset_blocked(hw)) 703 return; 704 705 /* Disable Tx laser; allow 100us to go dark per spec */ 706 esdp_reg |= IXGBE_ESDP_SDP3; 707 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 708 IXGBE_WRITE_FLUSH(hw); 709 usec_delay(100); 710} 711 712/** 713 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser 714 * @hw: pointer to hardware structure 715 * 716 * The base drivers may require better control over SFP+ module 717 * PHY states. This includes selectively turning on the Tx 718 * laser on the PHY, effectively starting physical link. 719 **/ 720void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 721{ 722 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 723 724 /* Enable Tx laser; allow 100ms to light up */ 725 esdp_reg &= ~IXGBE_ESDP_SDP3; 726 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 727 IXGBE_WRITE_FLUSH(hw); 728 msec_delay(100); 729} 730 731/** 732 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser 733 * @hw: pointer to hardware structure 734 * 735 * When the driver changes the link speeds that it can support, 736 * it sets autotry_restart to TRUE to indicate that we need to 737 * initiate a new autotry session with the link partner. To do 738 * so, we set the speed then disable and re-enable the Tx laser, to 739 * alert the link partner that it also needs to restart autotry on its 740 * end. This is consistent with TRUE clause 37 autoneg, which also 741 * involves a loss of signal. 742 **/ 743void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw) 744{ 745 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber"); 746 747 /* Blocked by MNG FW so bail */ 748 if (ixgbe_check_reset_blocked(hw)) 749 return; 750 751 if (hw->mac.autotry_restart) { 752 ixgbe_disable_tx_laser_multispeed_fiber(hw); 753 ixgbe_enable_tx_laser_multispeed_fiber(hw); 754 hw->mac.autotry_restart = FALSE; 755 } 756} 757 758/** 759 * ixgbe_set_hard_rate_select_speed - Set module link speed 760 * @hw: pointer to hardware structure 761 * @speed: link speed to set 762 * 763 * Set module link speed via RS0/RS1 rate select pins. 764 */ 765void ixgbe_set_hard_rate_select_speed(struct ixgbe_hw *hw, 766 ixgbe_link_speed speed) 767{ 768 uint32_t esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP); 769 770 switch (speed) { 771 case IXGBE_LINK_SPEED_10GB_FULL: 772 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5); 773 break; 774 case IXGBE_LINK_SPEED_1GB_FULL: 775 esdp_reg &= ~IXGBE_ESDP_SDP5; 776 esdp_reg |= IXGBE_ESDP_SDP5_DIR; 777 break; 778 default: 779 DEBUGOUT("Invalid fixed module speed\n"); 780 return; 781 } 782 783 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg); 784 IXGBE_WRITE_FLUSH(hw); 785} 786 787/** 788 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed 789 * @hw: pointer to hardware structure 790 * @speed: new link speed 791 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 792 * 793 * Implements the Intel SmartSpeed algorithm. 794 **/ 795int32_t ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw, 796 ixgbe_link_speed speed, 797 bool autoneg_wait_to_complete) 798{ 799 int32_t status = IXGBE_SUCCESS; 800 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN; 801 int32_t i, j; 802 bool link_up = FALSE; 803 uint32_t autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 804 805 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed"); 806 807 /* Set autoneg_advertised value based on input link speed */ 808 hw->phy.autoneg_advertised = 0; 809 810 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 811 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 812 813 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 814 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 815 816 if (speed & IXGBE_LINK_SPEED_100_FULL) 817 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 818 819 /* 820 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the 821 * autoneg advertisement if link is unable to be established at the 822 * highest negotiated rate. This can sometimes happen due to integrity 823 * issues with the physical media connection. 824 */ 825 826 /* First, try to get link with full advertisement */ 827 hw->phy.smart_speed_active = FALSE; 828 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) { 829 status = ixgbe_setup_mac_link_82599(hw, speed, 830 autoneg_wait_to_complete); 831 if (status != IXGBE_SUCCESS) 832 goto out; 833 834 /* 835 * Wait for the controller to acquire link. Per IEEE 802.3ap, 836 * Section 73.10.2, we may have to wait up to 500ms if KR is 837 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per 838 * Table 9 in the AN MAS. 839 */ 840 for (i = 0; i < 5; i++) { 841 msec_delay(100); 842 843 /* If we have link, just jump out */ 844 status = ixgbe_check_link(hw, &link_speed, &link_up, 845 FALSE); 846 if (status != IXGBE_SUCCESS) 847 goto out; 848 849 if (link_up) 850 goto out; 851 } 852 } 853 854 /* 855 * We didn't get link. If we advertised KR plus one of KX4/KX 856 * (or BX4/BX), then disable KR and try again. 857 */ 858 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) || 859 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0)) 860 goto out; 861 862 /* Turn SmartSpeed on to disable KR support */ 863 hw->phy.smart_speed_active = TRUE; 864 status = ixgbe_setup_mac_link_82599(hw, speed, 865 autoneg_wait_to_complete); 866 if (status != IXGBE_SUCCESS) 867 goto out; 868 869 /* 870 * Wait for the controller to acquire link. 600ms will allow for 871 * the AN link_fail_inhibit_timer as well for multiple cycles of 872 * parallel detect, both 10g and 1g. This allows for the maximum 873 * connect attempts as defined in the AN MAS table 73-7. 874 */ 875 for (i = 0; i < 6; i++) { 876 msec_delay(100); 877 878 /* If we have link, just jump out */ 879 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE); 880 if (status != IXGBE_SUCCESS) 881 goto out; 882 883 if (link_up) 884 goto out; 885 } 886 887 /* We didn't get link. Turn SmartSpeed back off. */ 888 hw->phy.smart_speed_active = FALSE; 889 status = ixgbe_setup_mac_link_82599(hw, speed, 890 autoneg_wait_to_complete); 891 892out: 893 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL)) 894 DEBUGOUT("Smartspeed has downgraded the link speed " 895 "from the maximum advertised\n"); 896 return status; 897} 898 899/** 900 * ixgbe_setup_mac_link_82599 - Set MAC link speed 901 * @hw: pointer to hardware structure 902 * @speed: new link speed 903 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 904 * 905 * Set the link speed in the AUTOC register and restarts link. 906 **/ 907int32_t ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw, 908 ixgbe_link_speed speed, 909 bool autoneg_wait_to_complete) 910{ 911 bool autoneg = FALSE; 912 int32_t status = IXGBE_SUCCESS; 913 uint32_t pma_pmd_1g, link_mode; 914 /* holds the value of AUTOC register at this current point in time */ 915 uint32_t current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 916 /* holds the cached value of AUTOC register */ 917 uint32_t orig_autoc = 0; 918 /* Temporary variable used for comparison purposes */ 919 uint32_t autoc = current_autoc; 920 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 921 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 922 uint32_t links_reg; 923 uint32_t i; 924 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN; 925 926 DEBUGFUNC("ixgbe_setup_mac_link_82599"); 927 928 /* Check to see if speed passed in is supported. */ 929 status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities, 930 &autoneg); 931 if (status) 932 goto out; 933 934 speed &= link_capabilities; 935 936 if (speed == IXGBE_LINK_SPEED_UNKNOWN) { 937 status = IXGBE_ERR_LINK_SETUP; 938 goto out; 939 } 940 941 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/ 942 if (hw->mac.orig_link_settings_stored) 943 orig_autoc = hw->mac.orig_autoc; 944 else 945 orig_autoc = autoc; 946 947 link_mode = autoc & IXGBE_AUTOC_LMS_MASK; 948 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 949 950 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 951 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 952 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 953 /* Set KX4/KX/KR support according to speed requested */ 954 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP); 955 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 956 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP) 957 autoc |= IXGBE_AUTOC_KX4_SUPP; 958 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) && 959 (hw->phy.smart_speed_active == FALSE)) 960 autoc |= IXGBE_AUTOC_KR_SUPP; 961 } 962 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 963 autoc |= IXGBE_AUTOC_KX_SUPP; 964 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) && 965 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN || 966 link_mode == IXGBE_AUTOC_LMS_1G_AN)) { 967 /* Switch from 1G SFI to 10G SFI if requested */ 968 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) && 969 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) { 970 autoc &= ~IXGBE_AUTOC_LMS_MASK; 971 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL; 972 } 973 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) && 974 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) { 975 /* Switch from 10G SFI to 1G SFI if requested */ 976 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 977 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) { 978 autoc &= ~IXGBE_AUTOC_LMS_MASK; 979 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel) 980 autoc |= IXGBE_AUTOC_LMS_1G_AN; 981 else 982 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN; 983 } 984 } 985 986 if (autoc != current_autoc) { 987 /* Restart link */ 988 status = hw->mac.ops.prot_autoc_write(hw, autoc, FALSE); 989 if (status != IXGBE_SUCCESS) 990 goto out; 991 992 /* Only poll for autoneg to complete if specified to do so */ 993 if (autoneg_wait_to_complete) { 994 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR || 995 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN || 996 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) { 997 links_reg = 0; /*Just in case Autoneg time=0*/ 998 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) { 999 links_reg = 1000 IXGBE_READ_REG(hw, IXGBE_LINKS); 1001 if (links_reg & IXGBE_LINKS_KX_AN_COMP) 1002 break; 1003 msec_delay(100); 1004 } 1005 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) { 1006 status = 1007 IXGBE_ERR_AUTONEG_NOT_COMPLETE; 1008 DEBUGOUT("Autoneg did not complete.\n"); 1009 } 1010 } 1011 } 1012 1013 /* Add delay to filter out noises during initial link setup */ 1014 msec_delay(50); 1015 } 1016 1017out: 1018 return status; 1019} 1020 1021/** 1022 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field 1023 * @hw: pointer to hardware structure 1024 * @speed: new link speed 1025 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete 1026 * 1027 * Restarts link on PHY and MAC based on settings passed in. 1028 **/ 1029int32_t ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw, 1030 ixgbe_link_speed speed, 1031 bool autoneg_wait_to_complete) 1032{ 1033 int32_t status; 1034 1035 DEBUGFUNC("ixgbe_setup_copper_link_82599"); 1036 1037 /* Setup the PHY according to input speed */ 1038 status = hw->phy.ops.setup_link_speed(hw, speed, 1039 autoneg_wait_to_complete); 1040 /* Set up MAC */ 1041 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete); 1042 1043 return status; 1044} 1045 1046/** 1047 * ixgbe_reset_hw_82599 - Perform hardware reset 1048 * @hw: pointer to hardware structure 1049 * 1050 * Resets the hardware by resetting the transmit and receive units, masks 1051 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1052 * reset. 1053 **/ 1054int32_t ixgbe_reset_hw_82599(struct ixgbe_hw *hw) 1055{ 1056 ixgbe_link_speed link_speed; 1057 int32_t status; 1058 uint32_t ctrl = 0; 1059 uint32_t i, autoc, autoc2; 1060 uint32_t curr_lms; 1061 bool link_up = FALSE; 1062 1063 DEBUGFUNC("ixgbe_reset_hw_82599"); 1064 1065 /* Call adapter stop to disable tx/rx and clear interrupts */ 1066 status = hw->mac.ops.stop_adapter(hw); 1067 if (status != IXGBE_SUCCESS) 1068 goto reset_hw_out; 1069 1070 /* flush pending Tx transactions */ 1071 ixgbe_clear_tx_pending(hw); 1072 1073 /* PHY ops must be identified and initialized prior to reset */ 1074 1075 /* Identify PHY and related function pointers */ 1076 status = hw->phy.ops.init(hw); 1077 1078 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1079 goto reset_hw_out; 1080 1081 /* Setup SFP module if there is one present. */ 1082 if (hw->phy.sfp_setup_needed) { 1083 status = hw->mac.ops.setup_sfp(hw); 1084 hw->phy.sfp_setup_needed = FALSE; 1085 } 1086 1087 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1088 goto reset_hw_out; 1089 1090 /* Reset PHY */ 1091 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL) 1092 hw->phy.ops.reset(hw); 1093 1094 /* remember AUTOC from before we reset */ 1095 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK; 1096 1097mac_reset_top: 1098 /* 1099 * Issue global reset to the MAC. Needs to be SW reset if link is up. 1100 * If link reset is used when link is up, it might reset the PHY when 1101 * mng is using it. If link is down or the flag to force full link 1102 * reset is set, then perform link reset. 1103 */ 1104 ctrl = IXGBE_CTRL_LNK_RST; 1105 if (!hw->force_full_reset) { 1106 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1107 if (link_up) 1108 ctrl = IXGBE_CTRL_RST; 1109 } 1110 1111 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1112 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1113 IXGBE_WRITE_FLUSH(hw); 1114 1115 /* Poll for reset bit to self-clear meaning reset is complete */ 1116 for (i = 0; i < 10; i++) { 1117 usec_delay(1); 1118 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1119 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1120 break; 1121 } 1122 1123 if (ctrl & IXGBE_CTRL_RST_MASK) { 1124 status = IXGBE_ERR_RESET_FAILED; 1125 DEBUGOUT("Reset polling failed to complete.\n"); 1126 } 1127 1128 msec_delay(50); 1129 1130 /* 1131 * Double resets are required for recovery from certain error 1132 * conditions. Between resets, it is necessary to stall to 1133 * allow time for any pending HW events to complete. 1134 */ 1135 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1136 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1137 goto mac_reset_top; 1138 } 1139 1140 /* 1141 * Store the original AUTOC/AUTOC2 values if they have not been 1142 * stored off yet. Otherwise restore the stored original 1143 * values since the reset operation sets back to defaults. 1144 */ 1145 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1146 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1147 1148 /* Enable link if disabled in NVM */ 1149 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1150 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1151 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1152 IXGBE_WRITE_FLUSH(hw); 1153 } 1154 1155 if (hw->mac.orig_link_settings_stored == FALSE) { 1156 hw->mac.orig_autoc = autoc; 1157 hw->mac.orig_autoc2 = autoc2; 1158 hw->mac.orig_link_settings_stored = TRUE; 1159 } else { 1160 1161 /* If MNG FW is running on a multi-speed device that 1162 * doesn't autoneg with out driver support we need to 1163 * leave LMS in the state it was before we MAC reset. 1164 * Likewise if we support WoL we don't want change the 1165 * LMS state. 1166 */ 1167 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) || 1168 hw->wol_enabled) 1169 hw->mac.orig_autoc = 1170 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) | 1171 curr_lms; 1172 1173 if (autoc != hw->mac.orig_autoc) { 1174 status = hw->mac.ops.prot_autoc_write(hw, 1175 hw->mac.orig_autoc, 1176 FALSE); 1177 if (status != IXGBE_SUCCESS) 1178 goto reset_hw_out; 1179 } 1180 1181 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) != 1182 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) { 1183 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK; 1184 autoc2 |= (hw->mac.orig_autoc2 & 1185 IXGBE_AUTOC2_UPPER_MASK); 1186 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2); 1187 } 1188 } 1189 1190 /* Store the permanent mac address */ 1191 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1192 1193 /* 1194 * Store MAC address from RAR0, clear receive address registers, and 1195 * clear the multicast table. Also reset num_rar_entries to 128, 1196 * since we modify this value when programming the SAN MAC address. 1197 */ 1198 hw->mac.num_rar_entries = 128; 1199 hw->mac.ops.init_rx_addrs(hw); 1200 1201reset_hw_out: 1202 return status; 1203} 1204 1205/** 1206 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register 1207 * @hw: pointer to hardware structure 1208 * @reg: analog register to read 1209 * @val: read value 1210 * 1211 * Performs read operation to Omer analog register specified. 1212 **/ 1213int32_t ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1214 uint8_t *val) 1215{ 1216 uint32_t core_ctl; 1217 1218 DEBUGFUNC("ixgbe_read_analog_reg8_82599"); 1219 1220 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD | 1221 (reg << 8)); 1222 IXGBE_WRITE_FLUSH(hw); 1223 usec_delay(10); 1224 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL); 1225 *val = (uint8_t)core_ctl; 1226 1227 return IXGBE_SUCCESS; 1228} 1229 1230/** 1231 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register 1232 * @hw: pointer to hardware structure 1233 * @reg: atlas register to write 1234 * @val: value to write 1235 * 1236 * Performs write operation to Omer analog register specified. 1237 **/ 1238int32_t ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, uint32_t reg, 1239 uint8_t val) 1240{ 1241 uint32_t core_ctl; 1242 1243 DEBUGFUNC("ixgbe_write_analog_reg8_82599"); 1244 1245 core_ctl = (reg << 8) | val; 1246 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl); 1247 IXGBE_WRITE_FLUSH(hw); 1248 usec_delay(10); 1249 1250 return IXGBE_SUCCESS; 1251} 1252 1253/** 1254 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx 1255 * @hw: pointer to hardware structure 1256 * 1257 * Starts the hardware using the generic start_hw function 1258 * and the generation start_hw function. 1259 * Then performs revision-specific operations, if any. 1260 **/ 1261int32_t ixgbe_start_hw_82599(struct ixgbe_hw *hw) 1262{ 1263 int32_t ret_val = IXGBE_SUCCESS; 1264 1265 DEBUGFUNC("ixgbe_start_hw_82599"); 1266 1267 ret_val = ixgbe_start_hw_generic(hw); 1268 if (ret_val != IXGBE_SUCCESS) 1269 goto out; 1270 1271 ret_val = ixgbe_start_hw_gen2(hw); 1272 if (ret_val != IXGBE_SUCCESS) 1273 goto out; 1274 1275 /* We need to run link autotry after the driver loads */ 1276 hw->mac.autotry_restart = TRUE; 1277 1278 if (ret_val == IXGBE_SUCCESS) 1279 ret_val = ixgbe_verify_fw_version_82599(hw); 1280out: 1281 return ret_val; 1282} 1283 1284/** 1285 * ixgbe_identify_phy_82599 - Get physical layer module 1286 * @hw: pointer to hardware structure 1287 * 1288 * Determines the physical layer module found on the current adapter. 1289 * If PHY already detected, maintains current PHY type in hw struct, 1290 * otherwise executes the PHY detection routine. 1291 **/ 1292int32_t ixgbe_identify_phy_82599(struct ixgbe_hw *hw) 1293{ 1294 int32_t status; 1295 1296 DEBUGFUNC("ixgbe_identify_phy_82599"); 1297 1298 /* Detect PHY if not unknown - returns success if already detected. */ 1299 status = ixgbe_identify_phy_generic(hw); 1300 if (status != IXGBE_SUCCESS) { 1301 /* 82599 10GBASE-T requires an external PHY */ 1302 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper) 1303 return status; 1304 else 1305 status = ixgbe_identify_module_generic(hw); 1306 } 1307 1308 /* Set PHY type none if no PHY detected */ 1309 if (hw->phy.type == ixgbe_phy_unknown) { 1310 hw->phy.type = ixgbe_phy_none; 1311 return IXGBE_SUCCESS; 1312 } 1313 1314 /* Return error if SFP module has been detected but is not supported */ 1315 if (hw->phy.type == ixgbe_phy_sfp_unsupported) 1316 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1317 1318 return status; 1319} 1320 1321/** 1322 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type 1323 * @hw: pointer to hardware structure 1324 * 1325 * Determines physical layer capabilities of the current configuration. 1326 **/ 1327uint64_t ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw) 1328{ 1329 uint64_t physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1330 uint32_t autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1331 uint32_t autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1332 uint32_t pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK; 1333 uint32_t pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK; 1334 uint32_t pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK; 1335 uint16_t ext_ability = 0; 1336 1337 DEBUGFUNC("ixgbe_get_support_physical_layer_82599"); 1338 1339 hw->phy.ops.identify(hw); 1340 1341 switch (hw->phy.type) { 1342 case ixgbe_phy_tn: 1343 case ixgbe_phy_cu_unknown: 1344 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 1345 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 1346 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 1347 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 1348 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 1349 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 1350 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 1351 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 1352 goto out; 1353 default: 1354 break; 1355 } 1356 1357 switch (autoc & IXGBE_AUTOC_LMS_MASK) { 1358 case IXGBE_AUTOC_LMS_1G_AN: 1359 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN: 1360 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) { 1361 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX | 1362 IXGBE_PHYSICAL_LAYER_1000BASE_BX; 1363 goto out; 1364 } else 1365 /* SFI mode so read SFP module */ 1366 goto sfp_check; 1367 break; 1368 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN: 1369 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4) 1370 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4; 1371 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4) 1372 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1373 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI) 1374 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI; 1375 goto out; 1376 break; 1377 case IXGBE_AUTOC_LMS_10G_SERIAL: 1378 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) { 1379 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1380 goto out; 1381 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) 1382 goto sfp_check; 1383 break; 1384 case IXGBE_AUTOC_LMS_KX4_KX_KR: 1385 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN: 1386 if (autoc & IXGBE_AUTOC_KX_SUPP) 1387 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX; 1388 if (autoc & IXGBE_AUTOC_KX4_SUPP) 1389 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4; 1390 if (autoc & IXGBE_AUTOC_KR_SUPP) 1391 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR; 1392 goto out; 1393 break; 1394 default: 1395 goto out; 1396 break; 1397 } 1398 1399sfp_check: 1400 /* SFP check must be done last since DA modules are sometimes used to 1401 * test KR mode - we need to id KR mode correctly before SFP module. 1402 * Call identify_sfp because the pluggable module may have changed */ 1403 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 1404out: 1405 return physical_layer; 1406} 1407 1408/** 1409 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599 1410 * @hw: pointer to hardware structure 1411 * @regval: register value to write to RXCTRL 1412 * 1413 * Enables the Rx DMA unit for 82599 1414 **/ 1415int32_t ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, uint32_t regval) 1416{ 1417 1418 DEBUGFUNC("ixgbe_enable_rx_dma_82599"); 1419 1420 /* 1421 * Workaround for 82599 silicon errata when enabling the Rx datapath. 1422 * If traffic is incoming before we enable the Rx unit, it could hang 1423 * the Rx DMA unit. Therefore, make sure the security engine is 1424 * completely disabled prior to enabling the Rx unit. 1425 */ 1426 1427 hw->mac.ops.disable_sec_rx_path(hw); 1428 1429 if (regval & IXGBE_RXCTRL_RXEN) 1430 ixgbe_enable_rx(hw); 1431 else 1432 ixgbe_disable_rx(hw); 1433 1434 hw->mac.ops.enable_sec_rx_path(hw); 1435 1436 return IXGBE_SUCCESS; 1437} 1438 1439/** 1440 * ixgbe_verify_fw_version_82599 - verify FW version for 82599 1441 * @hw: pointer to hardware structure 1442 * 1443 * Verifies that installed the firmware version is 0.6 or higher 1444 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher. 1445 * 1446 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or 1447 * if the FW version is not supported. 1448 **/ 1449int32_t ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw) 1450{ 1451 int32_t status = IXGBE_ERR_EEPROM_VERSION; 1452 uint16_t fw_offset, fw_ptp_cfg_offset; 1453 uint16_t fw_version; 1454 1455 DEBUGFUNC("ixgbe_verify_fw_version_82599"); 1456 1457 /* firmware check is only necessary for SFI devices */ 1458 if (hw->phy.media_type != ixgbe_media_type_fiber) { 1459 status = IXGBE_SUCCESS; 1460 goto fw_version_out; 1461 } 1462 1463 /* get the offset to the Firmware Module block */ 1464 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) { 1465 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1466 "eeprom read at offset %d failed", IXGBE_FW_PTR); 1467 return IXGBE_ERR_EEPROM_VERSION; 1468 } 1469 1470 if ((fw_offset == 0) || (fw_offset == 0xFFFF)) 1471 goto fw_version_out; 1472 1473 /* get the offset to the Pass Through Patch Configuration block */ 1474 if (hw->eeprom.ops.read(hw, (fw_offset + 1475 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR), 1476 &fw_ptp_cfg_offset)) { 1477 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1478 "eeprom read at offset %d failed", 1479 fw_offset + 1480 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR); 1481 return IXGBE_ERR_EEPROM_VERSION; 1482 } 1483 1484 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF)) 1485 goto fw_version_out; 1486 1487 /* get the firmware version */ 1488 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset + 1489 IXGBE_FW_PATCH_VERSION_4), &fw_version)) { 1490 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1491 "eeprom read at offset %d failed", 1492 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4); 1493 return IXGBE_ERR_EEPROM_VERSION; 1494 } 1495 1496 if (fw_version > 0x5) 1497 status = IXGBE_SUCCESS; 1498 1499fw_version_out: 1500 return status; 1501} 1502 1503/** 1504 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state. 1505 * @hw: pointer to hardware structure 1506 * 1507 * Returns TRUE if the LESM FW module is present and enabled. Otherwise 1508 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled. 1509 **/ 1510bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw) 1511{ 1512 bool lesm_enabled = FALSE; 1513 uint16_t fw_offset, fw_lesm_param_offset, fw_lesm_state; 1514 int32_t status; 1515 1516 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599"); 1517 1518 /* get the offset to the Firmware Module block */ 1519 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset); 1520 1521 if ((status != IXGBE_SUCCESS) || 1522 (fw_offset == 0) || (fw_offset == 0xFFFF)) 1523 goto out; 1524 1525 /* get the offset to the LESM Parameters block */ 1526 status = hw->eeprom.ops.read(hw, (fw_offset + 1527 IXGBE_FW_LESM_PARAMETERS_PTR), 1528 &fw_lesm_param_offset); 1529 1530 if ((status != IXGBE_SUCCESS) || 1531 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF)) 1532 goto out; 1533 1534 /* get the LESM state word */ 1535 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset + 1536 IXGBE_FW_LESM_STATE_1), 1537 &fw_lesm_state); 1538 1539 if ((status == IXGBE_SUCCESS) && 1540 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED)) 1541 lesm_enabled = TRUE; 1542 1543out: 1544 return lesm_enabled; 1545} 1546 1547/** 1548 * ixgbe_read_eeprom_82599 - Read EEPROM word using 1549 * fastest available method 1550 * 1551 * @hw: pointer to hardware structure 1552 * @offset: offset of word in the EEPROM to read 1553 * @data: word read from the EEPROM 1554 * 1555 * Reads a 16 bit word from the EEPROM 1556 **/ 1557int32_t ixgbe_read_eeprom_82599(struct ixgbe_hw *hw, 1558 uint16_t offset, uint16_t *data) 1559{ 1560 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1561 int32_t ret_val = IXGBE_ERR_CONFIG; 1562 1563 DEBUGFUNC("ixgbe_read_eeprom_82599"); 1564 1565 /* 1566 * If EEPROM is detected and can be addressed using 14 bits, 1567 * use EERD otherwise use bit bang 1568 */ 1569 if ((eeprom->type == ixgbe_eeprom_spi) && 1570 (offset <= IXGBE_EERD_MAX_ADDR)) 1571 ret_val = ixgbe_read_eerd_generic(hw, offset, data); 1572 else 1573 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data); 1574 1575 return ret_val; 1576} 1577 1578/** 1579 * ixgbe_reset_pipeline_82599 - perform pipeline reset 1580 * 1581 * @hw: pointer to hardware structure 1582 * 1583 * Reset pipeline by asserting Restart_AN together with LMS change to ensure 1584 * full pipeline reset. This function assumes the SW/FW lock is held. 1585 **/ 1586int32_t ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw) 1587{ 1588 int32_t ret_val; 1589 uint32_t anlp1_reg = 0; 1590 uint32_t i, autoc_reg, autoc2_reg; 1591 1592 /* Enable link if disabled in NVM */ 1593 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2); 1594 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) { 1595 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK; 1596 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg); 1597 IXGBE_WRITE_FLUSH(hw); 1598 } 1599 1600 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1601 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 1602 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */ 1603 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, 1604 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT)); 1605 /* Wait for AN to leave state 0 */ 1606 for (i = 0; i < 10; i++) { 1607 msec_delay(4); 1608 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1609 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK) 1610 break; 1611 } 1612 1613 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) { 1614 DEBUGOUT("auto negotiation not completed\n"); 1615 ret_val = IXGBE_ERR_RESET_FAILED; 1616 goto reset_pipeline_out; 1617 } 1618 1619 ret_val = IXGBE_SUCCESS; 1620 1621reset_pipeline_out: 1622 /* Write AUTOC register with original LMS field and Restart_AN */ 1623 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 1624 IXGBE_WRITE_FLUSH(hw); 1625 1626 return ret_val; 1627} 1628 1629/** 1630 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C 1631 * @hw: pointer to hardware structure 1632 * @byte_offset: byte offset to read 1633 * @dev_addr: address to read from 1634 * @data: value read 1635 * 1636 * Performs byte read operation to SFP module's EEPROM over I2C interface at 1637 * a specified device address. 1638 **/ 1639int32_t ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset, 1640 uint8_t dev_addr, uint8_t *data) 1641{ 1642 uint32_t esdp; 1643 int32_t status; 1644 int32_t timeout = 200; 1645 1646 DEBUGFUNC("ixgbe_read_i2c_byte_82599"); 1647 1648 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 1649 /* Acquire I2C bus ownership. */ 1650 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1651 esdp |= IXGBE_ESDP_SDP0; 1652 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 1653 IXGBE_WRITE_FLUSH(hw); 1654 1655 while (timeout) { 1656 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1657 if (esdp & IXGBE_ESDP_SDP1) 1658 break; 1659 1660 msec_delay(5); 1661 timeout--; 1662 } 1663 1664 if (!timeout) { 1665 DEBUGOUT("Driver can't access resource," 1666 " acquiring I2C bus timeout.\n"); 1667 status = IXGBE_ERR_I2C; 1668 goto release_i2c_access; 1669 } 1670 } 1671 1672 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data); 1673 1674release_i2c_access: 1675 1676 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 1677 /* Release I2C bus ownership. */ 1678 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1679 esdp &= ~IXGBE_ESDP_SDP0; 1680 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 1681 IXGBE_WRITE_FLUSH(hw); 1682 } 1683 1684 return status; 1685} 1686 1687/** 1688 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C 1689 * @hw: pointer to hardware structure 1690 * @byte_offset: byte offset to write 1691 * @dev_addr: address to read from 1692 * @data: value to write 1693 * 1694 * Performs byte write operation to SFP module's EEPROM over I2C interface at 1695 * a specified device address. 1696 **/ 1697int32_t ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, uint8_t byte_offset, 1698 uint8_t dev_addr, uint8_t data) 1699{ 1700 uint32_t esdp; 1701 int32_t status; 1702 int32_t timeout = 200; 1703 1704 DEBUGFUNC("ixgbe_write_i2c_byte_82599"); 1705 1706 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 1707 /* Acquire I2C bus ownership. */ 1708 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1709 esdp |= IXGBE_ESDP_SDP0; 1710 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 1711 IXGBE_WRITE_FLUSH(hw); 1712 1713 while (timeout) { 1714 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1715 if (esdp & IXGBE_ESDP_SDP1) 1716 break; 1717 1718 msec_delay(5); 1719 timeout--; 1720 } 1721 1722 if (!timeout) { 1723 DEBUGOUT("Driver can't access resource," 1724 " acquiring I2C bus timeout.\n"); 1725 status = IXGBE_ERR_I2C; 1726 goto release_i2c_access; 1727 } 1728 } 1729 1730 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data); 1731 1732release_i2c_access: 1733 1734 if (hw->phy.qsfp_shared_i2c_bus == TRUE) { 1735 /* Release I2C bus ownership. */ 1736 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 1737 esdp &= ~IXGBE_ESDP_SDP0; 1738 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 1739 IXGBE_WRITE_FLUSH(hw); 1740 } 1741 1742 return status; 1743} 1744