if_vge.c revision 1.7
1/* $OpenBSD: if_vge.c,v 1.7 2005/03/15 17:06:10 pvalchev Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#ifdef INET 102#include <netinet/in.h> 103#include <netinet/in_systm.h> 104#include <netinet/in_var.h> 105#include <netinet/ip.h> 106#include <netinet/if_ether.h> 107#endif 108 109#if NVLAN > 0 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112#endif 113 114#if NBPFILTER > 0 115#include <net/bpf.h> 116#endif 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123#include <dev/pci/pcidevs.h> 124 125#include <dev/pci/if_vgereg.h> 126#include <dev/pci/if_vgevar.h> 127 128int vge_probe (struct device *, void *, void *); 129void vge_attach (struct device *, struct device *, void *); 130 131int vge_encap (struct vge_softc *, struct mbuf *, int); 132 133int vge_allocmem (struct vge_softc *); 134int vge_newbuf (struct vge_softc *, int, struct mbuf *); 135int vge_rx_list_init (struct vge_softc *); 136int vge_tx_list_init (struct vge_softc *); 137void vge_rxeof (struct vge_softc *); 138void vge_txeof (struct vge_softc *); 139int vge_intr (void *); 140void vge_tick (void *); 141void vge_start (struct ifnet *); 142int vge_ioctl (struct ifnet *, u_long, caddr_t); 143int vge_init (struct ifnet *); 144void vge_stop (struct vge_softc *); 145void vge_watchdog (struct ifnet *); 146int vge_ifmedia_upd (struct ifnet *); 147void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 149void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 150void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 151 152void vge_miipoll_start (struct vge_softc *); 153void vge_miipoll_stop (struct vge_softc *); 154int vge_miibus_readreg (struct device *, int, int); 155void vge_miibus_writereg (struct device *, int, int, int); 156void vge_miibus_statchg (struct device *); 157 158void vge_cam_clear (struct vge_softc *); 159int vge_cam_set (struct vge_softc *, uint8_t *); 160void vge_setmulti (struct vge_softc *); 161void vge_reset (struct vge_softc *); 162 163struct cfattach vge_ca = { 164 sizeof(struct vge_softc), vge_probe, vge_attach 165}; 166 167struct cfdriver vge_cd = { 168 0, "vge", DV_IFNET 169}; 170 171#define VGE_PCI_LOIO 0x10 172#define VGE_PCI_LOMEM 0x14 173 174int vge_debug = 0; 175#define DPRINTF(x) if (vge_debug) printf x 176#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 177 178const struct pci_matchid vge_devices[] = { 179 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 180}; 181 182/* 183 * Read a word of data stored in the EEPROM at address 'addr.' 184 */ 185void 186vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 187{ 188 register int i; 189 u_int16_t word = 0; 190 191 /* 192 * Enter EEPROM embedded programming mode. In order to 193 * access the EEPROM at all, we first have to set the 194 * EELOAD bit in the CHIPCFG2 register. 195 */ 196 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 197 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 198 199 /* Select the address of the word we want to read */ 200 CSR_WRITE_1(sc, VGE_EEADDR, addr); 201 202 /* Issue read command */ 203 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 204 205 /* Wait for the done bit to be set. */ 206 for (i = 0; i < VGE_TIMEOUT; i++) { 207 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 208 break; 209 } 210 211 if (i == VGE_TIMEOUT) { 212 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 213 *dest = 0; 214 return; 215 } 216 217 /* Read the result */ 218 word = CSR_READ_2(sc, VGE_EERDDAT); 219 220 /* Turn off EEPROM access mode. */ 221 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 222 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 223 224 *dest = word; 225} 226 227/* 228 * Read a sequence of words from the EEPROM. 229 */ 230void 231vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 232 int swap) 233{ 234 int i; 235 u_int16_t word = 0, *ptr; 236 237 for (i = 0; i < cnt; i++) { 238 vge_eeprom_getword(sc, off + i, &word); 239 ptr = (u_int16_t *)(dest + (i * 2)); 240 if (swap) 241 *ptr = ntohs(word); 242 else 243 *ptr = word; 244 } 245} 246 247void 248vge_miipoll_stop(struct vge_softc *sc) 249{ 250 int i; 251 252 CSR_WRITE_1(sc, VGE_MIICMD, 0); 253 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 DELAY(1); 256 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) 261 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 262} 263 264void 265vge_miipoll_start(struct vge_softc *sc) 266{ 267 int i; 268 269 /* First, make sure we're idle. */ 270 271 CSR_WRITE_1(sc, VGE_MIICMD, 0); 272 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 273 274 for (i = 0; i < VGE_TIMEOUT; i++) { 275 DELAY(1); 276 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 277 break; 278 } 279 280 if (i == VGE_TIMEOUT) { 281 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 282 return; 283 } 284 285 /* Now enable auto poll mode. */ 286 287 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 288 289 /* And make sure it started. */ 290 291 for (i = 0; i < VGE_TIMEOUT; i++) { 292 DELAY(1); 293 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 294 break; 295 } 296 297 if (i == VGE_TIMEOUT) 298 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 299} 300 301int 302vge_miibus_readreg(struct device *dev, int phy, int reg) 303{ 304 struct vge_softc *sc = (struct vge_softc *)dev; 305 int i, s; 306 u_int16_t rval = 0; 307 308 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 309 return(0); 310 311 s = splimp(); 312 313 vge_miipoll_stop(sc); 314 315 /* Specify the register we want to read. */ 316 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 317 318 /* Issue read command. */ 319 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 320 321 /* Wait for the read command bit to self-clear. */ 322 for (i = 0; i < VGE_TIMEOUT; i++) { 323 DELAY(1); 324 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 325 break; 326 } 327 328 if (i == VGE_TIMEOUT) 329 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 330 else 331 rval = CSR_READ_2(sc, VGE_MIIDATA); 332 333 vge_miipoll_start(sc); 334 splx(s); 335 336 return (rval); 337} 338 339void 340vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 341{ 342 struct vge_softc *sc = (struct vge_softc *)dev; 343 int i, s; 344 345 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 346 return; 347 348 s = splimp(); 349 vge_miipoll_stop(sc); 350 351 /* Specify the register we want to write. */ 352 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 353 354 /* Specify the data we want to write. */ 355 CSR_WRITE_2(sc, VGE_MIIDATA, data); 356 357 /* Issue write command. */ 358 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 359 360 /* Wait for the write command bit to self-clear. */ 361 for (i = 0; i < VGE_TIMEOUT; i++) { 362 DELAY(1); 363 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 364 break; 365 } 366 367 if (i == VGE_TIMEOUT) { 368 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 369 } 370 371 vge_miipoll_start(sc); 372 splx(s); 373} 374 375void 376vge_cam_clear(struct vge_softc *sc) 377{ 378 int i; 379 380 /* 381 * Turn off all the mask bits. This tells the chip 382 * that none of the entries in the CAM filter are valid. 383 * desired entries will be enabled as we fill the filter in. 384 */ 385 386 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 387 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 388 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 389 for (i = 0; i < 8; i++) 390 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 391 392 /* Clear the VLAN filter too. */ 393 394 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 395 for (i = 0; i < 8; i++) 396 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 397 398 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 399 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 400 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 401 402 sc->vge_camidx = 0; 403} 404 405int 406vge_cam_set(struct vge_softc *sc, uint8_t *addr) 407{ 408 int i, error = 0; 409 410 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 411 return(ENOSPC); 412 413 /* Select the CAM data page. */ 414 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 415 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 416 417 /* Set the filter entry we want to update and enable writing. */ 418 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 419 420 /* Write the address to the CAM registers */ 421 for (i = 0; i < ETHER_ADDR_LEN; i++) 422 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 423 424 /* Issue a write command. */ 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 426 427 /* Wake for it to clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 436 error = EIO; 437 goto fail; 438 } 439 440 /* Select the CAM mask page. */ 441 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 442 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 443 444 /* Set the mask bit that enables this filter. */ 445 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 446 1<<(sc->vge_camidx & 7)); 447 448 sc->vge_camidx++; 449 450fail: 451 /* Turn off access to CAM. */ 452 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 455 456 return (error); 457} 458 459/* 460 * Program the multicast filter. We use the 64-entry CAM filter 461 * for perfect filtering. If there's more than 64 multicast addresses, 462 * we use the hash filter instead. 463 */ 464void 465vge_setmulti(struct vge_softc *sc) 466{ 467 struct arpcom *ac = &sc->arpcom; 468 struct ifnet *ifp = &ac->ac_if; 469 struct ether_multi *enm; 470 struct ether_multistep step; 471 u_int32_t h = 0, hashes[2] = { 0, 0 }; 472 473 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 474 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 475 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 476 return; 477 } 478 /* reset existing hash bits */ 479 CSR_WRITE_4(sc, VGE_MAR0, 0); 480 CSR_WRITE_4(sc, VGE_MAR1, 0); 481 482 /* program new ones */ 483 ETHER_FIRST_MULTI(step, ac, enm); 484 while (enm != NULL) { 485 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 486 ifp->if_flags |= IFF_ALLMULTI; 487 h = (ether_crc32_be(enm->enm_addrlo, 488 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 489 if (h < 32) 490 hashes[0] |= (1 << h); 491 else 492 hashes[1] |= (1 << (h - 32)); 493 ETHER_NEXT_MULTI(step, enm); 494 } 495 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 496 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 497 498#ifdef CAM_FILTERING 499 struct ifnet *ifp; 500 u_int32_t h, hashes[2] = { 0, 0 }; 501 int mcnt = 0; 502 struct arpcom *ac = &sc->arpcom; 503 struct ether_multi *enm; 504 struct ether_multistep step; 505 506 ifp = &sc->arpcom.ac_if; 507 508 /* First, zot all the multicast entries. */ 509 vge_cam_clear(sc); 510 CSR_WRITE_4(sc, VGE_MAR0, 0); 511 CSR_WRITE_4(sc, VGE_MAR1, 0); 512 513 /* 514 * If the user wants allmulti or promisc mode, enable reception 515 * of all multicast frames. 516 */ 517 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 518 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 519 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 520 return; 521 } 522 523 ETHER_FIRST_MULTI(step, ac, enm); 524 while (enm != NULL) { 525 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 526 ifp->if_flags |= IFF_ALLMULTI; 527 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 528 } 529 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 530 break; 531 532 h = (ether_crc32_be(enm->enm_addrlo, 533 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 534 if (h < 32) 535 hashes[0] |= (1 << h); 536 else 537 hashes[1] |= (1 << (h - 32)); 538 mcnt++; 539 ETHER_NEXT_MULTI(step, enm); 540 } 541 542 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 543 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 544#endif 545} 546 547void 548vge_reset(struct vge_softc *sc) 549{ 550 register int i; 551 552 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 553 554 for (i = 0; i < VGE_TIMEOUT; i++) { 555 DELAY(5); 556 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 557 break; 558 } 559 560 if (i == VGE_TIMEOUT) { 561 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 562 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 563 DELAY(2000); 564 } 565 566 DELAY(5000); 567 568 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 569 570 for (i = 0; i < VGE_TIMEOUT; i++) { 571 DELAY(5); 572 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 573 break; 574 } 575 576 if (i == VGE_TIMEOUT) { 577 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 578 return; 579 } 580 581 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 582} 583 584/* 585 * Probe for a VIA gigabit chip. Check the PCI vendor and device 586 * IDs against our list and return a device name if we find a match. 587 */ 588int 589vge_probe(struct device *dev, void *match, void *aux) 590{ 591 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 592 sizeof(vge_devices)/sizeof(vge_devices[0]))); 593} 594 595/* 596 * Allocate memory for RX/TX rings 597 */ 598int 599vge_allocmem(struct vge_softc *sc) 600{ 601 int nseg, rseg; 602 int i, error; 603 604 nseg = 32; 605 606 /* Allocate DMA'able memory for the TX ring */ 607 608 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 609 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 610 &sc->vge_ldata.vge_tx_list_map); 611 if (error) 612 return (ENOMEM); 613 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 614 ETHER_ALIGN, 0, 615 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 616 if (error) { 617 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 618 return (ENOMEM); 619 } 620 621 /* Load the map for the TX ring. */ 622 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 623 1, VGE_TX_LIST_SZ, 624 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 625 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 626 if (error) { 627 printf("%s: can't map TX dma buffers\n", 628 sc->vge_dev.dv_xname); 629 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 630 return (ENOMEM); 631 } 632 633 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 634 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 635 if (error) { 636 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 637 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 638 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 639 VGE_TX_LIST_SZ); 640 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 641 return (ENOMEM); 642 } 643 644 /* Create DMA maps for TX buffers */ 645 646 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 647 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 648 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 649 &sc->vge_ldata.vge_tx_dmamap[i]); 650 if (error) { 651 printf("%s: can't create DMA map for TX\n", 652 sc->vge_dev.dv_xname); 653 return (ENOMEM); 654 } 655 } 656 657 /* Allocate DMA'able memory for the RX ring */ 658 659 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 660 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 661 &sc->vge_ldata.vge_rx_list_map); 662 if (error) 663 return (ENOMEM); 664 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 665 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 666 if (error) { 667 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 668 return (ENOMEM); 669 } 670 671 /* Load the map for the RX ring. */ 672 673 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 674 1, VGE_RX_LIST_SZ, 675 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 676 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 677 if (error) { 678 printf("%s: can't map RX dma buffers\n", 679 sc->vge_dev.dv_xname); 680 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 681 return (ENOMEM); 682 } 683 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 684 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 685 if (error) { 686 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 687 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 688 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 689 VGE_RX_LIST_SZ); 690 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 691 return (ENOMEM); 692 } 693 694 /* Create DMA maps for RX buffers */ 695 696 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 697 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 698 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 699 &sc->vge_ldata.vge_rx_dmamap[i]); 700 if (error) { 701 printf("%s: can't create DMA map for RX\n", 702 sc->vge_dev.dv_xname); 703 return (ENOMEM); 704 } 705 } 706 707 return (0); 708} 709 710/* 711 * Attach the interface. Allocate softc structures, do ifmedia 712 * setup and ethernet/BPF attach. 713 */ 714void 715vge_attach(struct device *parent, struct device *self, void *aux) 716{ 717 u_char eaddr[ETHER_ADDR_LEN]; 718 u_int16_t as[3]; 719 struct vge_softc *sc = (struct vge_softc *)self; 720 struct pci_attach_args *pa = aux; 721 pci_chipset_tag_t pc = pa->pa_pc; 722 pci_intr_handle_t ih; 723 const char *intrstr = NULL; 724 struct ifnet *ifp; 725 int error = 0, i; 726 bus_size_t iosize; 727 pcireg_t command; 728 729 /* 730 * Map control/status registers. 731 */ 732 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 733 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 734 PCI_COMMAND_MASTER_ENABLE; 735 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 736 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 737 738 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) == 0) { 739 printf(": neither i/o nor mem enabled\n"); 740 return; 741 } 742 743 if (command & PCI_COMMAND_MEM_ENABLE) { 744 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 745 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 746 printf(": can't map mem space\n"); 747 return; 748 } 749 } else { 750 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 751 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 752 printf(": can't map i/o space\n"); 753 return; 754 } 755 } 756 757 /* Allocate interrupt */ 758 if (pci_intr_map(pa, &ih)) { 759 printf(": couldn't map interrupt\n"); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 764 sc->vge_dev.dv_xname); 765 if (sc->vge_intrhand == NULL) { 766 printf(": couldn't establish interrupt"); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 return; 770 } 771 printf(": %s", intrstr); 772 773 sc->sc_dmat = pa->pa_dmat; 774 775 /* Reset the adapter. */ 776 vge_reset(sc); 777 778 /* 779 * Get station address from the EEPROM. 780 */ 781 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 782 for (i = 0; i < 3; i++) { 783 eaddr[(i * 2) + 0] = as[i] & 0xff; 784 eaddr[(i * 2) + 1] = as[i] >> 8; 785 } 786 787 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 788 789 printf(", address %s\n", 790 ether_sprintf(sc->arpcom.ac_enaddr)); 791 792 error = vge_allocmem(sc); 793 794 if (error) 795 return; 796 797 ifp = &sc->arpcom.ac_if; 798 ifp->if_softc = sc; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = vge_ioctl; 801 ifp->if_start = vge_start; 802#ifdef VGE_CSUM_OFFLOAD 803 ifp->if_capabilities = IFCAP_VLAN_MTU; 804 ifp->if_hwassist = VGE_CSUM_FEATURES; 805 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 806#endif 807 ifp->if_watchdog = vge_watchdog; 808 ifp->if_init = vge_init; 809 ifp->if_baudrate = 1000000000; 810 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 811 IFQ_SET_READY(&ifp->if_snd); 812 813 /* Set interface name */ 814 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 815 816 /* Do MII setup */ 817 sc->sc_mii.mii_ifp = ifp; 818 sc->sc_mii.mii_readreg = vge_miibus_readreg; 819 sc->sc_mii.mii_writereg = vge_miibus_writereg; 820 sc->sc_mii.mii_statchg = vge_miibus_statchg; 821 ifmedia_init(&sc->sc_mii.mii_media, 0, 822 vge_ifmedia_upd, vge_ifmedia_sts); 823 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 824 MII_OFFSET_ANY, 0); 825 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 826 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 827 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 828 0, NULL); 829 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 830 } else 831 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 832 833 timeout_set(&sc->timer_handle, vge_tick, sc); 834 835 /* 836 * Call MI attach routine. 837 */ 838 if_attach(ifp); 839 ether_ifattach(ifp); 840} 841 842int 843vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 844{ 845 struct mbuf *m_new = NULL; 846 struct vge_rx_desc *r; 847 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 848 int i; 849 850 if (m == NULL) { 851 /* Allocate a new mbuf */ 852 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 853 if (m_new == NULL) 854 return (ENOBUFS); 855 856 /* Allocate a cluster */ 857 MCLGET(m_new, M_DONTWAIT); 858 if (!(m_new->m_flags & M_EXT)) { 859 m_freem(m_new); 860 return (ENOBUFS); 861 } 862 } else 863 m_new->m_data = m_new->m_ext.ext_buf; 864 865 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 866 /* Fix-up alignment so payload is doubleword-aligned */ 867 /* XXX m_adj(m_new, ETHER_ALIGN); */ 868 869 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT)) 870 return (ENOBUFS); 871 872 if (rxmap->dm_nsegs > 1) 873 goto out; 874 875 /* Map the segments into RX descriptors */ 876 r = &sc->vge_ldata.vge_rx_list[idx]; 877 878 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 879 printf("%s: tried to map a busy RX descriptor\n", 880 sc->vge_dev.dv_xname); 881 goto out; 882 } 883 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 884 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 885 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 886 r->vge_sts = htole32(0); 887 r->vge_ctl = htole32(0); 888 889 /* 890 * Note: the manual fails to document the fact that for 891 * proper operation, the driver needs to replenish the RX 892 * DMA ring 4 descriptors at a time (rather than one at a 893 * time, like most chips). We can allocate the new buffers 894 * but we should not set the OWN bits until we're ready 895 * to hand back 4 of them in one shot. 896 */ 897#define VGE_RXCHUNK 4 898 sc->vge_rx_consumed++; 899 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 900 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 901 sc->vge_ldata.vge_rx_list[i].vge_sts |= 902 htole32(VGE_RDSTS_OWN); 903 sc->vge_rx_consumed = 0; 904 } 905 906 sc->vge_ldata.vge_rx_mbuf[idx] = m_new; 907 908 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 909 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 910 911 return (0); 912out: 913 DPRINTF(("vge_newbuf: out of memory\n")); 914 if (m_new != NULL) 915 m_freem(m_new); 916 return (ENOMEM); 917} 918 919int 920vge_tx_list_init(struct vge_softc *sc) 921{ 922 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 923 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 924 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 925 926 bus_dmamap_sync(sc->sc_dmat, 927 sc->vge_ldata.vge_tx_list_map, 0, 928 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 929 BUS_DMASYNC_PREWRITE); 930 sc->vge_ldata.vge_tx_prodidx = 0; 931 sc->vge_ldata.vge_tx_considx = 0; 932 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 933 934 return (0); 935} 936 937/* Init RX descriptors and allocate mbufs with vge_newbuf() 938 * A ring is used, and last descriptor points to first. */ 939int 940vge_rx_list_init(struct vge_softc *sc) 941{ 942 int i; 943 944 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 945 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 946 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 947 948 sc->vge_rx_consumed = 0; 949 950 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 951 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 952 return (ENOBUFS); 953 } 954 955 /* Flush the RX descriptors */ 956 957 bus_dmamap_sync(sc->sc_dmat, 958 sc->vge_ldata.vge_rx_list_map, 959 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 960 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 961 962 sc->vge_ldata.vge_rx_prodidx = 0; 963 sc->vge_rx_consumed = 0; 964 sc->vge_head = sc->vge_tail = NULL; 965 966 return (0); 967} 968 969/* 970 * RX handler. We support the reception of jumbo frames that have 971 * been fragmented across multiple 2K mbuf cluster buffers. 972 */ 973void 974vge_rxeof(struct vge_softc *sc) 975{ 976 struct mbuf *m; 977 struct ifnet *ifp; 978 int i, total_len; 979 int lim = 0; 980 struct vge_rx_desc *cur_rx; 981 u_int32_t rxstat, rxctl; 982 983 ifp = &sc->arpcom.ac_if; 984 i = sc->vge_ldata.vge_rx_prodidx; 985 986 /* Invalidate the descriptor memory */ 987 988 bus_dmamap_sync(sc->sc_dmat, 989 sc->vge_ldata.vge_rx_list_map, 990 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 991 BUS_DMASYNC_POSTREAD); 992 993 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 994 struct mbuf *m0 = NULL; 995 996 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 997 m = sc->vge_ldata.vge_rx_mbuf[i]; 998 total_len = VGE_RXBYTES(cur_rx); 999 rxstat = letoh32(cur_rx->vge_sts); 1000 rxctl = letoh32(cur_rx->vge_ctl); 1001 1002 /* Invalidate the RX mbuf and unload its map */ 1003 1004 bus_dmamap_sync(sc->sc_dmat, 1005 sc->vge_ldata.vge_rx_dmamap[i], 1006 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1007 BUS_DMASYNC_POSTWRITE); 1008 bus_dmamap_unload(sc->sc_dmat, 1009 sc->vge_ldata.vge_rx_dmamap[i]); 1010 1011 /* 1012 * If the 'start of frame' bit is set, this indicates 1013 * either the first fragment in a multi-fragment receive, 1014 * or an intermediate fragment. Either way, we want to 1015 * accumulate the buffers. 1016 */ 1017 if (rxstat & VGE_RXPKT_SOF) { 1018 DPRINTF(("vge_rxeof: SOF\n")); 1019 m->m_len = MCLBYTES; 1020 if (sc->vge_head == NULL) 1021 sc->vge_head = sc->vge_tail = m; 1022 else { 1023 m->m_flags &= ~M_PKTHDR; 1024 sc->vge_tail->m_next = m; 1025 sc->vge_tail = m; 1026 } 1027 vge_newbuf(sc, i, NULL); 1028 VGE_RX_DESC_INC(i); 1029 continue; 1030 } 1031 1032 /* 1033 * Bad/error frames will have the RXOK bit cleared. 1034 * However, there's one error case we want to allow: 1035 * if a VLAN tagged frame arrives and the chip can't 1036 * match it against the CAM filter, it considers this 1037 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1038 * We don't want to drop the frame though: our VLAN 1039 * filtering is done in software. 1040 */ 1041 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1042 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1043 ifp->if_ierrors++; 1044 /* 1045 * If this is part of a multi-fragment packet, 1046 * discard all the pieces. 1047 */ 1048 if (sc->vge_head != NULL) { 1049 m_freem(sc->vge_head); 1050 sc->vge_head = sc->vge_tail = NULL; 1051 } 1052 vge_newbuf(sc, i, m); 1053 VGE_RX_DESC_INC(i); 1054 continue; 1055 } 1056 1057 /* 1058 * If allocating a replacement mbuf fails, 1059 * reload the current one. 1060 */ 1061 1062 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1063 if (sc->vge_head != NULL) { 1064 m_freem(sc->vge_head); 1065 sc->vge_head = sc->vge_tail = NULL; 1066 } 1067 1068 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1069 total_len - ETHER_CRC_LEN + ETHER_ALIGN, 1070 0, ifp, NULL); 1071 vge_newbuf(sc, i, m); 1072 if (m0 == NULL) { 1073 ifp->if_ierrors++; 1074 continue; 1075 } 1076 m_adj(m0, ETHER_ALIGN); 1077 m = m0; 1078 1079 VGE_RX_DESC_INC(i); 1080 continue; 1081 } 1082 1083 VGE_RX_DESC_INC(i); 1084 1085 if (sc->vge_head != NULL) { 1086 m->m_len = total_len % MCLBYTES; 1087 /* 1088 * Special case: if there's 4 bytes or less 1089 * in this buffer, the mbuf can be discarded: 1090 * the last 4 bytes is the CRC, which we don't 1091 * care about anyway. 1092 */ 1093 if (m->m_len <= ETHER_CRC_LEN) { 1094 sc->vge_tail->m_len -= 1095 (ETHER_CRC_LEN - m->m_len); 1096 m_freem(m); 1097 } else { 1098 m->m_len -= ETHER_CRC_LEN; 1099 m->m_flags &= ~M_PKTHDR; 1100 sc->vge_tail->m_next = m; 1101 } 1102 m = sc->vge_head; 1103 sc->vge_head = sc->vge_tail = NULL; 1104 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1105 } else 1106 m->m_pkthdr.len = m->m_len = 1107 (total_len - ETHER_CRC_LEN); 1108 1109#ifdef __STRICT_ALIGNMENT 1110 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1111 total_len); 1112 m->m_data += ETHER_ALIGN; 1113#endif 1114 ifp->if_ipackets++; 1115 m->m_pkthdr.rcvif = ifp; 1116 1117 /* Do RX checksumming if enabled */ 1118#ifdef VGE_CSUM_OFFLOAD 1119 if (ifp->if_capenable & IFCAP_RXCSUM) { 1120 1121 /* Check IP header checksum */ 1122 if (rxctl & VGE_RDCTL_IPPKT) 1123 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1124 if (rxctl & VGE_RDCTL_IPCSUMOK) 1125 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1126 1127 /* Check TCP/UDP checksum */ 1128 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1129 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1130 m->m_pkthdr.csum_flags |= 1131 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1132 m->m_pkthdr.csum_data = 0xffff; 1133 } 1134 } 1135 1136 if (rxstat & VGE_RDSTS_VTAG) 1137 VLAN_INPUT_TAG(ifp, m, 1138 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1139#endif 1140 1141#if NBPFILTER > 0 1142 if (ifp->if_bpf) 1143 bpf_mtap(ifp->if_bpf, m); 1144#endif 1145 ether_input_mbuf(ifp, m); 1146 1147 lim++; 1148 if (lim == VGE_RX_DESC_CNT) 1149 break; 1150 } 1151 1152 /* Flush the RX DMA ring */ 1153 bus_dmamap_sync(sc->sc_dmat, 1154 sc->vge_ldata.vge_rx_list_map, 1155 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1156 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1157 1158 sc->vge_ldata.vge_rx_prodidx = i; 1159 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1160} 1161 1162void 1163vge_txeof(struct vge_softc *sc) 1164{ 1165 struct ifnet *ifp; 1166 u_int32_t txstat; 1167 int idx; 1168 1169 ifp = &sc->arpcom.ac_if; 1170 idx = sc->vge_ldata.vge_tx_considx; 1171 1172 /* Invalidate the TX descriptor list */ 1173 1174 bus_dmamap_sync(sc->sc_dmat, 1175 sc->vge_ldata.vge_tx_list_map, 1176 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1177 BUS_DMASYNC_POSTREAD); 1178 1179 /* Transmitted frames can be now free'd from the TX list */ 1180 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1181 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1182 if (txstat & VGE_TDSTS_OWN) 1183 break; 1184 1185 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1186 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1187 bus_dmamap_unload(sc->sc_dmat, 1188 sc->vge_ldata.vge_tx_dmamap[idx]); 1189 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1190 ifp->if_collisions++; 1191 if (txstat & VGE_TDSTS_TXERR) 1192 ifp->if_oerrors++; 1193 else 1194 ifp->if_opackets++; 1195 1196 sc->vge_ldata.vge_tx_free++; 1197 VGE_TX_DESC_INC(idx); 1198 } 1199 1200 /* No changes made to the TX ring, so no flush needed */ 1201 1202 if (idx != sc->vge_ldata.vge_tx_considx) { 1203 sc->vge_ldata.vge_tx_considx = idx; 1204 ifp->if_flags &= ~IFF_OACTIVE; 1205 ifp->if_timer = 0; 1206 } 1207 1208 /* 1209 * If not all descriptors have been released reaped yet, 1210 * reload the timer so that we will eventually get another 1211 * interrupt that will cause us to re-enter this routine. 1212 * This is done in case the transmitter has gone idle. 1213 */ 1214 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1215 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1216} 1217 1218void 1219vge_tick(void *xsc) 1220{ 1221 struct vge_softc *sc = xsc; 1222 struct ifnet *ifp = &sc->arpcom.ac_if; 1223 struct mii_data *mii = &sc->sc_mii; 1224 int s; 1225 1226 s = splimp(); 1227 1228 mii_tick(mii); 1229 1230 if (sc->vge_link) { 1231 if (!(mii->mii_media_status & IFM_ACTIVE)) 1232 sc->vge_link = 0; 1233 } else { 1234 if (mii->mii_media_status & IFM_ACTIVE && 1235 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1236 sc->vge_link = 1; 1237 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1238 vge_start(ifp); 1239 } 1240 } 1241 timeout_add(&sc->timer_handle, hz); 1242 splx(s); 1243} 1244 1245int 1246vge_intr(void *arg) 1247{ 1248 struct vge_softc *sc = arg; 1249 struct ifnet *ifp; 1250 u_int32_t status; 1251 int claimed = 0; 1252 1253 ifp = &sc->arpcom.ac_if; 1254 1255 if (!(ifp->if_flags & IFF_UP)) 1256 return 0; 1257 1258 /* Disable interrupts */ 1259 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1260 1261 for (;;) { 1262 status = CSR_READ_4(sc, VGE_ISR); 1263 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1264 1265 /* If the card has gone away the read returns 0xffffffff. */ 1266 if (status == 0xFFFFFFFF) 1267 break; 1268 1269 if (status) { 1270 CSR_WRITE_4(sc, VGE_ISR, status); 1271 } 1272 1273 if ((status & VGE_INTRS) == 0) 1274 break; 1275 1276 claimed = 1; 1277 1278 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1279 vge_rxeof(sc); 1280 1281 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1282 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1283 vge_rxeof(sc); 1284 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1285 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1286 } 1287 1288 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1289 vge_txeof(sc); 1290 1291 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1292 DPRINTFN(2, ("DMA_STALL\n")); 1293 vge_init(ifp); 1294 } 1295 1296 if (status & VGE_ISR_LINKSTS) { 1297 timeout_del(&sc->timer_handle); 1298 vge_tick(sc); 1299 } 1300 } 1301 1302 /* Re-enable interrupts */ 1303 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1304 1305 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1306 vge_start(ifp); 1307 1308 return (claimed); 1309} 1310 1311/* 1312 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1313 * the descriptors. 1314 */ 1315int 1316vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1317{ 1318 bus_dmamap_t txmap; 1319 struct vge_tx_desc *d = NULL; 1320 struct vge_tx_frag *f; 1321 int error, frag; 1322 1323 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1324repack: 1325 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1326 m_head, BUS_DMA_NOWAIT); 1327 if (error) { 1328 printf("%s: can't map mbuf (error %d)\n", 1329 sc->vge_dev.dv_xname, error); 1330 return (ENOBUFS); 1331 } 1332 1333 d = &sc->vge_ldata.vge_tx_list[idx]; 1334 /* If owned by chip, fail */ 1335 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1336 return (ENOBUFS); 1337 1338 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1339 /* Check if we have used all 7 fragments. */ 1340 if (frag == VGE_TX_FRAGS) 1341 break; 1342 f = &d->vge_frag[frag]; 1343 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1344 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1345 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1346 } 1347 1348 /* 1349 * We used up all 7 fragments! Now what we have to do is 1350 * copy the data into a mbuf cluster and map that. 1351 */ 1352 if (frag == VGE_TX_FRAGS) { 1353 struct mbuf *m = NULL; 1354 1355 MGETHDR(m, M_DONTWAIT, MT_DATA); 1356 if (m == NULL) { 1357 m_freem(m_head); 1358 return (ENOBUFS); 1359 } 1360 if (m_head->m_pkthdr.len > MHLEN) { 1361 MCLGET(m, M_DONTWAIT); 1362 if (!(m->m_flags & M_EXT)) { 1363 m_freem(m); 1364 m_freem(m_head); 1365 return (ENOBUFS); 1366 } 1367 } 1368 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1369 mtod(m, caddr_t)); 1370 m->m_pkthdr.len = m->m_len = m_head->m_pkthdr.len; 1371 m_freem(m_head); 1372 m_head = m; 1373 goto repack; 1374 } 1375 1376 /* This chip does not do auto-padding */ 1377 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1378 f = &d->vge_frag[frag]; 1379 1380 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1381 m_head->m_pkthdr.len)); 1382 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1383 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1384 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1385 frag++; 1386 } 1387 /* For some reason, we need to tell the card fragment + 1 */ 1388 frag++; 1389 1390 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1391 BUS_DMASYNC_PREWRITE); 1392 1393 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1394 d->vge_ctl = htole32((frag << 28) | VGE_TD_LS_NORM); 1395 1396 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1397 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1398 1399 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1400 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1401 sc->vge_ldata.vge_tx_free--; 1402 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1403 1404 /* 1405 * Set up hardware VLAN tagging. 1406 */ 1407#ifdef VGE_VLAN 1408 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1409 if (mtag != NULL) 1410 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1411 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1412#endif 1413 1414 idx++; 1415 1416 return (0); 1417} 1418 1419/* 1420 * Main transmit routine. 1421 */ 1422void 1423vge_start(struct ifnet *ifp) 1424{ 1425 struct vge_softc *sc; 1426 struct mbuf *m_head = NULL; 1427 int idx, pidx = 0; 1428 1429 sc = ifp->if_softc; 1430 1431 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1432 return; 1433 1434 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1435 return; 1436 1437 idx = sc->vge_ldata.vge_tx_prodidx; 1438 1439 pidx = idx - 1; 1440 if (pidx < 0) 1441 pidx = VGE_TX_DESC_CNT - 1; 1442 1443 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1444 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1445 if (m_head == NULL) 1446 break; 1447 1448 /* 1449 * If there's a BPF listener, bounce a copy of this frame 1450 * to him. 1451 */ 1452#if NBPFILTER > 0 1453 if (ifp->if_bpf) 1454 bpf_mtap(ifp->if_bpf, m_head); 1455#endif 1456 1457 if (vge_encap(sc, m_head, idx)) { 1458 IF_PREPEND(&ifp->if_snd, m_head); 1459 ifp->if_flags |= IFF_OACTIVE; 1460 break; 1461 } 1462 1463 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1464 htole16(VGE_TXDESC_Q); 1465 1466 pidx = idx; 1467 VGE_TX_DESC_INC(idx); 1468 } 1469 1470 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1471 return; 1472 } 1473 1474 /* Flush the TX descriptors */ 1475 1476 bus_dmamap_sync(sc->sc_dmat, 1477 sc->vge_ldata.vge_tx_list_map, 1478 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1479 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1480 1481 /* Issue a transmit command. */ 1482 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1483 1484 sc->vge_ldata.vge_tx_prodidx = idx; 1485 1486 /* 1487 * Use the countdown timer for interrupt moderation. 1488 * 'TX done' interrupts are disabled. Instead, we reset the 1489 * countdown timer, which will begin counting until it hits 1490 * the value in the SSTIMER register, and then trigger an 1491 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1492 * the timer count is reloaded. Only when the transmitter 1493 * is idle will the timer hit 0 and an interrupt fire. 1494 */ 1495 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1496 1497 /* 1498 * Set a timeout in case the chip goes out to lunch. 1499 */ 1500 ifp->if_timer = 5; 1501} 1502 1503int 1504vge_init(struct ifnet *ifp) 1505{ 1506 struct vge_softc *sc = ifp->if_softc; 1507 int i; 1508 1509 /* 1510 * Cancel pending I/O and free all RX/TX buffers. 1511 */ 1512 vge_stop(sc); 1513 vge_reset(sc); 1514 1515 /* Initialize RX descriptors list */ 1516 if (vge_rx_list_init(sc) == ENOBUFS) { 1517 printf("%s: init failed: no memory for RX buffers\n", 1518 sc->vge_dev.dv_xname); 1519 vge_stop(sc); 1520 return (ENOBUFS); 1521 } 1522 /* Initialize TX descriptors */ 1523 if (vge_tx_list_init(sc) == ENOBUFS) { 1524 printf("%s: init failed: no memory for TX buffers\n", 1525 sc->vge_dev.dv_xname); 1526 vge_stop(sc); 1527 return (ENOBUFS); 1528 } 1529 1530 /* Set our station address */ 1531 for (i = 0; i < ETHER_ADDR_LEN; i++) 1532 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1533 1534 /* 1535 * Set receive FIFO threshold. Also allow transmission and 1536 * reception of VLAN tagged frames. 1537 */ 1538 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1539 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1540 1541 /* Set DMA burst length */ 1542 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1543 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1544 1545 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1546 1547 /* Set collision backoff algorithm */ 1548 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1549 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1550 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1551 1552 /* Disable LPSEL field in priority resolution */ 1553 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1554 1555 /* 1556 * Load the addresses of the DMA queues into the chip. 1557 * Note that we only use one transmit queue. 1558 */ 1559 1560 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1561 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1562 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1563 1564 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1565 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1566 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1567 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1568 1569 /* Enable and wake up the RX descriptor queue */ 1570 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1571 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1572 1573 /* Enable the TX descriptor queue */ 1574 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1575 1576 /* Set up the receive filter -- allow large frames for VLANs. */ 1577 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1578 1579 /* If we want promiscuous mode, set the allframes bit. */ 1580 if (ifp->if_flags & IFF_PROMISC) { 1581 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1582 } 1583 1584 /* Set capture broadcast bit to capture broadcast frames. */ 1585 if (ifp->if_flags & IFF_BROADCAST) { 1586 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1587 } 1588 1589 /* Set multicast bit to capture multicast frames. */ 1590 if (ifp->if_flags & IFF_MULTICAST) { 1591 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1592 } 1593 1594 /* Init the cam filter. */ 1595#ifdef CAM_FILTERING 1596 vge_cam_clear(sc); 1597#endif 1598 1599 /* Init the multicast filter. */ 1600 vge_setmulti(sc); 1601 1602 /* Enable flow control */ 1603 1604 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1605 1606 /* Enable jumbo frame reception (if desired) */ 1607 1608 /* Start the MAC. */ 1609 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1610 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1611 CSR_WRITE_1(sc, VGE_CRS0, 1612 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1613 1614 /* 1615 * Configure one-shot timer for microsecond 1616 * resulution and load it for 500 usecs. 1617 */ 1618 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1619 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1620 1621 /* 1622 * Configure interrupt moderation for receive. Enable 1623 * the holdoff counter and load it, and set the RX 1624 * suppression count to the number of descriptors we 1625 * want to allow before triggering an interrupt. 1626 * The holdoff timer is in units of 20 usecs. 1627 */ 1628 1629#ifdef notyet 1630 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1631 /* Select the interrupt holdoff timer page. */ 1632 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1633 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1634 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1635 1636 /* Enable use of the holdoff timer. */ 1637 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1638 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1639 1640 /* Select the RX suppression threshold page. */ 1641 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1642 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1643 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1644 1645 /* Restore the page select bits. */ 1646 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1647 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1648#endif 1649 1650 /* 1651 * Enable interrupts. 1652 */ 1653 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1654 CSR_WRITE_4(sc, VGE_ISR, 0); 1655 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1656 1657 /* Restore BMCR state */ 1658 mii_mediachg(&sc->sc_mii); 1659 1660 ifp->if_flags |= IFF_RUNNING; 1661 ifp->if_flags &= ~IFF_OACTIVE; 1662 1663 sc->vge_if_flags = 0; 1664 sc->vge_link = 0; 1665 1666 if (!timeout_pending(&sc->timer_handle)) 1667 timeout_add(&sc->timer_handle, hz); 1668 1669 return (0); 1670} 1671 1672/* 1673 * Set media options. 1674 */ 1675int 1676vge_ifmedia_upd(struct ifnet *ifp) 1677{ 1678 struct vge_softc *sc = ifp->if_softc; 1679 1680 return (mii_mediachg(&sc->sc_mii)); 1681} 1682 1683/* 1684 * Report current media status. 1685 */ 1686void 1687vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1688{ 1689 struct vge_softc *sc = ifp->if_softc; 1690 1691 mii_pollstat(&sc->sc_mii); 1692 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1693 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1694} 1695 1696void 1697vge_miibus_statchg(struct device *dev) 1698{ 1699 struct vge_softc *sc = (struct vge_softc *)dev; 1700 struct mii_data *mii; 1701 struct ifmedia_entry *ife; 1702 1703 mii = &sc->sc_mii; 1704 ife = mii->mii_media.ifm_cur; 1705 1706 /* 1707 * If the user manually selects a media mode, we need to turn 1708 * on the forced MAC mode bit in the DIAGCTL register. If the 1709 * user happens to choose a full duplex mode, we also need to 1710 * set the 'force full duplex' bit. This applies only to 1711 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1712 * mode is disabled, and in 1000baseT mode, full duplex is 1713 * always implied, so we turn on the forced mode bit but leave 1714 * the FDX bit cleared. 1715 */ 1716 1717 switch (IFM_SUBTYPE(ife->ifm_media)) { 1718 case IFM_AUTO: 1719 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1720 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1721 break; 1722 case IFM_1000_T: 1723 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1724 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1725 break; 1726 case IFM_100_TX: 1727 case IFM_10_T: 1728 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1729 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1730 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1731 } else { 1732 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1733 } 1734 break; 1735 default: 1736 printf("%s: unknown media type: %x\n", 1737 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1738 break; 1739 } 1740} 1741 1742int 1743vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1744{ 1745 struct vge_softc *sc = ifp->if_softc; 1746 struct ifreq *ifr = (struct ifreq *) data; 1747 struct ifaddr *ifa = (struct ifaddr *) data; 1748 int s, error = 0; 1749 1750 s = splimp(); 1751 1752 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1753 splx(s); 1754 return (error); 1755 } 1756 1757 switch (command) { 1758 case SIOCSIFADDR: 1759 ifp->if_flags |= IFF_UP; 1760 switch (ifa->ifa_addr->sa_family) { 1761#ifdef INET 1762 case AF_INET: 1763 vge_init(ifp); 1764 arp_ifinit(&sc->arpcom, ifa); 1765 break; 1766#endif 1767 default: 1768 vge_init(ifp); 1769 break; 1770 } 1771#if 0 /* XXX mtu gets reset to 0 at ifconfig up for some reason with this */ 1772 case SIOCSIFMTU: 1773 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 1774 error = EINVAL; 1775 else 1776 ifp->if_mtu = ifr->ifr_mtu; 1777 break; 1778#endif 1779 case SIOCSIFFLAGS: 1780 if (ifp->if_flags & IFF_UP) { 1781 if (ifp->if_flags & IFF_RUNNING && 1782 ifp->if_flags & IFF_PROMISC && 1783 !(sc->vge_if_flags & IFF_PROMISC)) { 1784 CSR_SETBIT_1(sc, VGE_RXCTL, 1785 VGE_RXCTL_RX_PROMISC); 1786 vge_setmulti(sc); 1787 } else if (ifp->if_flags & IFF_RUNNING && 1788 !(ifp->if_flags & IFF_PROMISC) && 1789 sc->vge_if_flags & IFF_PROMISC) { 1790 CSR_CLRBIT_1(sc, VGE_RXCTL, 1791 VGE_RXCTL_RX_PROMISC); 1792 vge_setmulti(sc); 1793 } else 1794 vge_init(ifp); 1795 } else { 1796 if (ifp->if_flags & IFF_RUNNING) 1797 vge_stop(sc); 1798 } 1799 sc->vge_if_flags = ifp->if_flags; 1800 break; 1801 case SIOCADDMULTI: 1802 case SIOCDELMULTI: 1803 error = (command == SIOCADDMULTI) ? 1804 ether_addmulti(ifr, &sc->arpcom) : 1805 ether_delmulti(ifr, &sc->arpcom); 1806 1807 if (error == ENETRESET) { 1808 if (ifp->if_flags & IFF_RUNNING) 1809 vge_setmulti(sc); 1810 error = 0; 1811 } 1812 break; 1813 case SIOCGIFMEDIA: 1814 case SIOCSIFMEDIA: 1815 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1816 break; 1817 default: 1818 error = EINVAL; 1819 break; 1820 } 1821 1822 splx(s); 1823 return (error); 1824} 1825 1826void 1827vge_watchdog(struct ifnet *ifp) 1828{ 1829 struct vge_softc *sc = ifp->if_softc; 1830 int s; 1831 1832 s = splnet(); 1833 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1834 ifp->if_oerrors++; 1835 1836 vge_txeof(sc); 1837 vge_rxeof(sc); 1838 1839 vge_init(ifp); 1840 1841 splx(s); 1842} 1843 1844/* 1845 * Stop the adapter and free any mbufs allocated to the 1846 * RX and TX lists. 1847 */ 1848void 1849vge_stop(struct vge_softc *sc) 1850{ 1851 register int i; 1852 struct ifnet *ifp; 1853 1854 ifp = &sc->arpcom.ac_if; 1855 ifp->if_timer = 0; 1856 if (timeout_pending(&sc->timer_handle)) 1857 timeout_del(&sc->timer_handle); 1858 1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1860 1861 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1862 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1863 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1864 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1865 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1866 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1867 1868 if (sc->vge_head != NULL) { 1869 m_freem(sc->vge_head); 1870 sc->vge_head = sc->vge_tail = NULL; 1871 } 1872 1873 /* Free the TX list buffers. */ 1874 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1875 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1876 bus_dmamap_unload(sc->sc_dmat, 1877 sc->vge_ldata.vge_tx_dmamap[i]); 1878 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1879 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1880 } 1881 } 1882 1883 /* Free the RX list buffers. */ 1884 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1885 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1886 bus_dmamap_unload(sc->sc_dmat, 1887 sc->vge_ldata.vge_rx_dmamap[i]); 1888 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1889 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1890 } 1891 } 1892} 1893