if_vge.c revision 1.68
1/* $OpenBSD: if_vge.c,v 1.68 2015/11/24 17:11:39 mpi Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/timeout.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_media.h> 100 101#include <netinet/in.h> 102#include <netinet/if_ether.h> 103 104#if NBPFILTER > 0 105#include <net/bpf.h> 106#endif 107 108#include <dev/mii/miivar.h> 109 110#include <dev/pci/pcireg.h> 111#include <dev/pci/pcivar.h> 112#include <dev/pci/pcidevs.h> 113 114#include <dev/pci/if_vgereg.h> 115#include <dev/pci/if_vgevar.h> 116 117int vge_probe (struct device *, void *, void *); 118void vge_attach (struct device *, struct device *, void *); 119int vge_detach (struct device *, int); 120 121int vge_encap (struct vge_softc *, struct mbuf *, int); 122 123int vge_allocmem (struct vge_softc *); 124void vge_freemem (struct vge_softc *); 125int vge_newbuf (struct vge_softc *, int, struct mbuf *); 126int vge_rx_list_init (struct vge_softc *); 127int vge_tx_list_init (struct vge_softc *); 128void vge_rxeof (struct vge_softc *); 129void vge_txeof (struct vge_softc *); 130int vge_intr (void *); 131void vge_tick (void *); 132void vge_start (struct ifnet *); 133int vge_ioctl (struct ifnet *, u_long, caddr_t); 134int vge_init (struct ifnet *); 135void vge_stop (struct vge_softc *); 136void vge_watchdog (struct ifnet *); 137int vge_ifmedia_upd (struct ifnet *); 138void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 139 140#ifdef VGE_EEPROM 141void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 142#endif 143void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 144 145void vge_miipoll_start (struct vge_softc *); 146void vge_miipoll_stop (struct vge_softc *); 147int vge_miibus_readreg (struct device *, int, int); 148void vge_miibus_writereg (struct device *, int, int, int); 149void vge_miibus_statchg (struct device *); 150 151void vge_cam_clear (struct vge_softc *); 152int vge_cam_set (struct vge_softc *, uint8_t *); 153void vge_iff (struct vge_softc *); 154void vge_reset (struct vge_softc *); 155 156struct cfattach vge_ca = { 157 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach 158}; 159 160struct cfdriver vge_cd = { 161 NULL, "vge", DV_IFNET 162}; 163 164#define VGE_PCI_LOIO 0x10 165#define VGE_PCI_LOMEM 0x14 166 167int vge_debug = 0; 168#define DPRINTF(x) if (vge_debug) printf x 169#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 170 171const struct pci_matchid vge_devices[] = { 172 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 173}; 174 175#ifdef VGE_EEPROM 176/* 177 * Read a word of data stored in the EEPROM at address 'addr.' 178 */ 179void 180vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 181{ 182 int i; 183 u_int16_t word = 0; 184 185 /* 186 * Enter EEPROM embedded programming mode. In order to 187 * access the EEPROM at all, we first have to set the 188 * EELOAD bit in the CHIPCFG2 register. 189 */ 190 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 191 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 192 193 /* Select the address of the word we want to read */ 194 CSR_WRITE_1(sc, VGE_EEADDR, addr); 195 196 /* Issue read command */ 197 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 198 199 /* Wait for the done bit to be set. */ 200 for (i = 0; i < VGE_TIMEOUT; i++) { 201 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 202 break; 203 } 204 205 if (i == VGE_TIMEOUT) { 206 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 207 *dest = 0; 208 return; 209 } 210 211 /* Read the result */ 212 word = CSR_READ_2(sc, VGE_EERDDAT); 213 214 /* Turn off EEPROM access mode. */ 215 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 216 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 217 218 *dest = word; 219} 220#endif 221 222/* 223 * Read a sequence of words from the EEPROM. 224 */ 225void 226vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 227 int swap) 228{ 229 int i; 230#ifdef VGE_EEPROM 231 u_int16_t word = 0, *ptr; 232 233 for (i = 0; i < cnt; i++) { 234 vge_eeprom_getword(sc, off + i, &word); 235 ptr = (u_int16_t *)(dest + (i * 2)); 236 if (swap) 237 *ptr = ntohs(word); 238 else 239 *ptr = word; 240 } 241#else 242 for (i = 0; i < ETHER_ADDR_LEN; i++) 243 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 244#endif 245} 246 247void 248vge_miipoll_stop(struct vge_softc *sc) 249{ 250 int i; 251 252 CSR_WRITE_1(sc, VGE_MIICMD, 0); 253 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 DELAY(1); 256 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) 261 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 262} 263 264void 265vge_miipoll_start(struct vge_softc *sc) 266{ 267 int i; 268 269 /* First, make sure we're idle. */ 270 271 CSR_WRITE_1(sc, VGE_MIICMD, 0); 272 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 273 274 for (i = 0; i < VGE_TIMEOUT; i++) { 275 DELAY(1); 276 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 277 break; 278 } 279 280 if (i == VGE_TIMEOUT) { 281 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 282 return; 283 } 284 285 /* Now enable auto poll mode. */ 286 287 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 288 289 /* And make sure it started. */ 290 291 for (i = 0; i < VGE_TIMEOUT; i++) { 292 DELAY(1); 293 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 294 break; 295 } 296 297 if (i == VGE_TIMEOUT) 298 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 299} 300 301int 302vge_miibus_readreg(struct device *dev, int phy, int reg) 303{ 304 struct vge_softc *sc = (struct vge_softc *)dev; 305 int i, s; 306 u_int16_t rval = 0; 307 308 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 309 return(0); 310 311 s = splnet(); 312 313 vge_miipoll_stop(sc); 314 315 /* Specify the register we want to read. */ 316 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 317 318 /* Issue read command. */ 319 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 320 321 /* Wait for the read command bit to self-clear. */ 322 for (i = 0; i < VGE_TIMEOUT; i++) { 323 DELAY(1); 324 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 325 break; 326 } 327 328 if (i == VGE_TIMEOUT) 329 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 330 else 331 rval = CSR_READ_2(sc, VGE_MIIDATA); 332 333 vge_miipoll_start(sc); 334 splx(s); 335 336 return (rval); 337} 338 339void 340vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 341{ 342 struct vge_softc *sc = (struct vge_softc *)dev; 343 int i, s; 344 345 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 346 return; 347 348 s = splnet(); 349 vge_miipoll_stop(sc); 350 351 /* Specify the register we want to write. */ 352 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 353 354 /* Specify the data we want to write. */ 355 CSR_WRITE_2(sc, VGE_MIIDATA, data); 356 357 /* Issue write command. */ 358 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 359 360 /* Wait for the write command bit to self-clear. */ 361 for (i = 0; i < VGE_TIMEOUT; i++) { 362 DELAY(1); 363 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 364 break; 365 } 366 367 if (i == VGE_TIMEOUT) { 368 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 369 } 370 371 vge_miipoll_start(sc); 372 splx(s); 373} 374 375void 376vge_cam_clear(struct vge_softc *sc) 377{ 378 int i; 379 380 /* 381 * Turn off all the mask bits. This tells the chip 382 * that none of the entries in the CAM filter are valid. 383 * desired entries will be enabled as we fill the filter in. 384 */ 385 386 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 387 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 388 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 389 for (i = 0; i < 8; i++) 390 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 391 392 /* Clear the VLAN filter too. */ 393 394 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 395 for (i = 0; i < 8; i++) 396 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 397 398 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 399 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 400 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 401 402 sc->vge_camidx = 0; 403} 404 405int 406vge_cam_set(struct vge_softc *sc, uint8_t *addr) 407{ 408 int i, error = 0; 409 410 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 411 return(ENOSPC); 412 413 /* Select the CAM data page. */ 414 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 415 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 416 417 /* Set the filter entry we want to update and enable writing. */ 418 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 419 420 /* Write the address to the CAM registers */ 421 for (i = 0; i < ETHER_ADDR_LEN; i++) 422 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 423 424 /* Issue a write command. */ 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 426 427 /* Wake for it to clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 436 error = EIO; 437 goto fail; 438 } 439 440 /* Select the CAM mask page. */ 441 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 442 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 443 444 /* Set the mask bit that enables this filter. */ 445 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 446 1<<(sc->vge_camidx & 7)); 447 448 sc->vge_camidx++; 449 450fail: 451 /* Turn off access to CAM. */ 452 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 455 456 return (error); 457} 458 459/* 460 * We use the 64-entry CAM filter for perfect filtering. 461 * If there's more than 64 multicast addresses, we use the 462 * hash filter instead. 463 */ 464void 465vge_iff(struct vge_softc *sc) 466{ 467 struct arpcom *ac = &sc->arpcom; 468 struct ifnet *ifp = &ac->ac_if; 469 struct ether_multi *enm; 470 struct ether_multistep step; 471 u_int32_t h = 0, hashes[2]; 472 u_int8_t rxctl; 473 int error; 474 475 vge_cam_clear(sc); 476 rxctl = CSR_READ_1(sc, VGE_RXCTL); 477 rxctl &= ~(VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_MCAST | 478 VGE_RXCTL_RX_PROMISC | VGE_RXCTL_RX_UCAST); 479 bzero(hashes, sizeof(hashes)); 480 ifp->if_flags &= ~IFF_ALLMULTI; 481 482 /* 483 * Always accept broadcast frames. 484 * Always accept frames destined to our station address. 485 */ 486 rxctl |= VGE_RXCTL_RX_BCAST | VGE_RXCTL_RX_UCAST; 487 488 if ((ifp->if_flags & IFF_PROMISC) == 0) 489 rxctl |= VGE_RXCTL_RX_MCAST; 490 491 if (ifp->if_flags & IFF_PROMISC || ac->ac_multirangecnt > 0) { 492 ifp->if_flags |= IFF_ALLMULTI; 493 if (ifp->if_flags & IFF_PROMISC) 494 rxctl |= VGE_RXCTL_RX_PROMISC; 495 hashes[0] = hashes[1] = 0xFFFFFFFF; 496 } else if (ac->ac_multicnt > VGE_CAM_MAXADDRS) { 497 ETHER_FIRST_MULTI(step, ac, enm); 498 while (enm != NULL) { 499 h = ether_crc32_be(enm->enm_addrlo, 500 ETHER_ADDR_LEN) >> 26; 501 502 hashes[h >> 5] |= 1 << (h & 0x1f); 503 504 ETHER_NEXT_MULTI(step, enm); 505 } 506 } else { 507 ETHER_FIRST_MULTI(step, ac, enm); 508 while (enm != NULL) { 509 error = vge_cam_set(sc, enm->enm_addrlo); 510 if (error) 511 break; 512 513 ETHER_NEXT_MULTI(step, enm); 514 } 515 } 516 517 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 518 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 519 CSR_WRITE_1(sc, VGE_RXCTL, rxctl); 520} 521 522void 523vge_reset(struct vge_softc *sc) 524{ 525 int i; 526 527 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 528 529 for (i = 0; i < VGE_TIMEOUT; i++) { 530 DELAY(5); 531 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 532 break; 533 } 534 535 if (i == VGE_TIMEOUT) { 536 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 537 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 538 DELAY(2000); 539 } 540 541 DELAY(5000); 542 543 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 544 545 for (i = 0; i < VGE_TIMEOUT; i++) { 546 DELAY(5); 547 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 548 break; 549 } 550 551 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 552} 553 554/* 555 * Probe for a VIA gigabit chip. Check the PCI vendor and device 556 * IDs against our list and return a device name if we find a match. 557 */ 558int 559vge_probe(struct device *dev, void *match, void *aux) 560{ 561 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 562 nitems(vge_devices))); 563} 564 565/* 566 * Allocate memory for RX/TX rings 567 */ 568int 569vge_allocmem(struct vge_softc *sc) 570{ 571 int nseg, rseg; 572 int i, error; 573 574 nseg = 32; 575 576 /* Allocate DMA'able memory for the TX ring */ 577 578 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 579 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 580 &sc->vge_ldata.vge_tx_list_map); 581 if (error) 582 return (ENOMEM); 583 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 584 ETHER_ALIGN, 0, 585 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 586 if (error) { 587 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 588 return (ENOMEM); 589 } 590 591 /* Load the map for the TX ring. */ 592 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 593 1, VGE_TX_LIST_SZ, 594 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 595 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 596 if (error) { 597 printf("%s: can't map TX dma buffers\n", 598 sc->vge_dev.dv_xname); 599 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 600 return (ENOMEM); 601 } 602 603 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 604 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 605 if (error) { 606 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 607 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 608 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 609 VGE_TX_LIST_SZ); 610 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 611 return (ENOMEM); 612 } 613 614 /* Create DMA maps for TX buffers */ 615 616 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 617 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, 618 VGE_TX_FRAGS, MCLBYTES, 0, BUS_DMA_ALLOCNOW, 619 &sc->vge_ldata.vge_tx_dmamap[i]); 620 if (error) { 621 printf("%s: can't create DMA map for TX\n", 622 sc->vge_dev.dv_xname); 623 return (ENOMEM); 624 } 625 } 626 627 /* Allocate DMA'able memory for the RX ring */ 628 629 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 630 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 631 &sc->vge_ldata.vge_rx_list_map); 632 if (error) 633 return (ENOMEM); 634 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 635 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 636 if (error) { 637 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 638 return (ENOMEM); 639 } 640 641 /* Load the map for the RX ring. */ 642 643 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 644 1, VGE_RX_LIST_SZ, 645 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 646 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 647 if (error) { 648 printf("%s: can't map RX dma buffers\n", 649 sc->vge_dev.dv_xname); 650 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 651 return (ENOMEM); 652 } 653 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 654 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 655 if (error) { 656 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 657 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 658 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 659 VGE_RX_LIST_SZ); 660 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 661 return (ENOMEM); 662 } 663 664 /* Create DMA maps for RX buffers */ 665 666 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 667 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 668 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 669 &sc->vge_ldata.vge_rx_dmamap[i]); 670 if (error) { 671 printf("%s: can't create DMA map for RX\n", 672 sc->vge_dev.dv_xname); 673 return (ENOMEM); 674 } 675 } 676 677 return (0); 678} 679 680void 681vge_freemem(struct vge_softc *sc) 682{ 683 int i; 684 685 for (i = 0; i < VGE_RX_DESC_CNT; i++) 686 bus_dmamap_destroy(sc->sc_dmat, 687 sc->vge_ldata.vge_rx_dmamap[i]); 688 689 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 690 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 691 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 692 VGE_RX_LIST_SZ); 693 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1); 694 695 for (i = 0; i < VGE_TX_DESC_CNT; i++) 696 bus_dmamap_destroy(sc->sc_dmat, 697 sc->vge_ldata.vge_tx_dmamap[i]); 698 699 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 700 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 701 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 702 VGE_TX_LIST_SZ); 703 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1); 704} 705 706/* 707 * Attach the interface. Allocate softc structures, do ifmedia 708 * setup and ethernet/BPF attach. 709 */ 710void 711vge_attach(struct device *parent, struct device *self, void *aux) 712{ 713 u_char eaddr[ETHER_ADDR_LEN]; 714 struct vge_softc *sc = (struct vge_softc *)self; 715 struct pci_attach_args *pa = aux; 716 pci_chipset_tag_t pc = pa->pa_pc; 717 pci_intr_handle_t ih; 718 const char *intrstr = NULL; 719 struct ifnet *ifp; 720 int error = 0; 721 722 /* 723 * Map control/status registers. 724 */ 725 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 726 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 727 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 728 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 729 printf(": can't map mem or i/o space\n"); 730 return; 731 } 732 } 733 734 /* Allocate interrupt */ 735 if (pci_intr_map(pa, &ih)) { 736 printf(": couldn't map interrupt\n"); 737 return; 738 } 739 intrstr = pci_intr_string(pc, ih); 740 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 741 sc->vge_dev.dv_xname); 742 if (sc->vge_intrhand == NULL) { 743 printf(": couldn't establish interrupt"); 744 if (intrstr != NULL) 745 printf(" at %s", intrstr); 746 return; 747 } 748 printf(": %s", intrstr); 749 750 sc->sc_dmat = pa->pa_dmat; 751 sc->sc_pc = pa->pa_pc; 752 753 /* Reset the adapter. */ 754 vge_reset(sc); 755 756 /* 757 * Get station address from the EEPROM. 758 */ 759 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1); 760 761 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 762 763 printf(", address %s\n", 764 ether_sprintf(sc->arpcom.ac_enaddr)); 765 766 error = vge_allocmem(sc); 767 768 if (error) 769 return; 770 771 ifp = &sc->arpcom.ac_if; 772 ifp->if_softc = sc; 773 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 774 ifp->if_ioctl = vge_ioctl; 775 ifp->if_start = vge_start; 776 ifp->if_watchdog = vge_watchdog; 777#ifdef VGE_JUMBO 778 ifp->if_hardmtu = VGE_JUMBO_MTU; 779#endif 780 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 781 IFQ_SET_READY(&ifp->if_snd); 782 783 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 784 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 785 786#if NVLAN > 0 787 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 788#endif 789 790 /* Set interface name */ 791 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 792 793 /* Do MII setup */ 794 sc->sc_mii.mii_ifp = ifp; 795 sc->sc_mii.mii_readreg = vge_miibus_readreg; 796 sc->sc_mii.mii_writereg = vge_miibus_writereg; 797 sc->sc_mii.mii_statchg = vge_miibus_statchg; 798 ifmedia_init(&sc->sc_mii.mii_media, 0, 799 vge_ifmedia_upd, vge_ifmedia_sts); 800 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 801 MII_OFFSET_ANY, MIIF_DOPAUSE); 802 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 803 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 804 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 805 0, NULL); 806 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 807 } else 808 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 809 810 timeout_set(&sc->timer_handle, vge_tick, sc); 811 812 /* 813 * Call MI attach routine. 814 */ 815 if_attach(ifp); 816 ether_ifattach(ifp); 817} 818 819int 820vge_detach(struct device *self, int flags) 821{ 822 struct vge_softc *sc = (void *)self; 823 struct ifnet *ifp = &sc->arpcom.ac_if; 824 825 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand); 826 827 vge_stop(sc); 828 829 /* Detach all PHYs */ 830 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 831 832 /* Delete any remaining media. */ 833 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 834 835 ether_ifdetach(ifp); 836 if_detach(ifp); 837 838 vge_freemem(sc); 839 840 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize); 841 return (0); 842} 843 844int 845vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 846{ 847 struct mbuf *m_new = NULL; 848 struct vge_rx_desc *r; 849 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 850 int i; 851 852 if (m == NULL) { 853 /* Allocate a new mbuf */ 854 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 855 if (m_new == NULL) 856 return (ENOBUFS); 857 858 /* Allocate a cluster */ 859 MCLGET(m_new, M_DONTWAIT); 860 if (!(m_new->m_flags & M_EXT)) { 861 m_freem(m_new); 862 return (ENOBUFS); 863 } 864 865 m = m_new; 866 } else 867 m->m_data = m->m_ext.ext_buf; 868 869 m->m_len = m->m_pkthdr.len = MCLBYTES; 870 /* Fix-up alignment so payload is doubleword-aligned */ 871 /* XXX m_adj(m, ETHER_ALIGN); */ 872 873 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 874 return (ENOBUFS); 875 876 if (rxmap->dm_nsegs > 1) 877 goto out; 878 879 /* Map the segments into RX descriptors */ 880 r = &sc->vge_ldata.vge_rx_list[idx]; 881 882 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 883 printf("%s: tried to map a busy RX descriptor\n", 884 sc->vge_dev.dv_xname); 885 goto out; 886 } 887 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 888 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 889 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 890 r->vge_sts = htole32(0); 891 r->vge_ctl = htole32(0); 892 893 /* 894 * Note: the manual fails to document the fact that for 895 * proper operation, the driver needs to replenish the RX 896 * DMA ring 4 descriptors at a time (rather than one at a 897 * time, like most chips). We can allocate the new buffers 898 * but we should not set the OWN bits until we're ready 899 * to hand back 4 of them in one shot. 900 */ 901#define VGE_RXCHUNK 4 902 sc->vge_rx_consumed++; 903 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 904 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 905 sc->vge_ldata.vge_rx_list[i].vge_sts |= 906 htole32(VGE_RDSTS_OWN); 907 sc->vge_rx_consumed = 0; 908 } 909 910 sc->vge_ldata.vge_rx_mbuf[idx] = m; 911 912 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 913 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 914 915 return (0); 916out: 917 DPRINTF(("vge_newbuf: out of memory\n")); 918 if (m_new != NULL) 919 m_freem(m_new); 920 return (ENOMEM); 921} 922 923int 924vge_tx_list_init(struct vge_softc *sc) 925{ 926 bzero(sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 927 bzero(&sc->vge_ldata.vge_tx_mbuf, 928 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 929 930 bus_dmamap_sync(sc->sc_dmat, 931 sc->vge_ldata.vge_tx_list_map, 0, 932 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 933 BUS_DMASYNC_PREWRITE); 934 sc->vge_ldata.vge_tx_prodidx = 0; 935 sc->vge_ldata.vge_tx_considx = 0; 936 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 937 938 return (0); 939} 940 941/* Init RX descriptors and allocate mbufs with vge_newbuf() 942 * A ring is used, and last descriptor points to first. */ 943int 944vge_rx_list_init(struct vge_softc *sc) 945{ 946 int i; 947 948 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 949 bzero(&sc->vge_ldata.vge_rx_mbuf, 950 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 951 952 sc->vge_rx_consumed = 0; 953 954 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 955 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 956 return (ENOBUFS); 957 } 958 959 /* Flush the RX descriptors */ 960 961 bus_dmamap_sync(sc->sc_dmat, 962 sc->vge_ldata.vge_rx_list_map, 963 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 964 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 965 966 sc->vge_ldata.vge_rx_prodidx = 0; 967 sc->vge_rx_consumed = 0; 968 sc->vge_head = sc->vge_tail = NULL; 969 970 return (0); 971} 972 973/* 974 * RX handler. We support the reception of jumbo frames that have 975 * been fragmented across multiple 2K mbuf cluster buffers. 976 */ 977void 978vge_rxeof(struct vge_softc *sc) 979{ 980 struct mbuf_list ml = MBUF_LIST_INITIALIZER(); 981 struct mbuf *m; 982 struct ifnet *ifp; 983 int i, total_len; 984 int lim = 0; 985 struct vge_rx_desc *cur_rx; 986 u_int32_t rxstat, rxctl; 987 988 ifp = &sc->arpcom.ac_if; 989 i = sc->vge_ldata.vge_rx_prodidx; 990 991 /* Invalidate the descriptor memory */ 992 993 bus_dmamap_sync(sc->sc_dmat, 994 sc->vge_ldata.vge_rx_list_map, 995 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 996 BUS_DMASYNC_POSTREAD); 997 998 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 999 struct mbuf *m0 = NULL; 1000 1001 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1002 m = sc->vge_ldata.vge_rx_mbuf[i]; 1003 total_len = VGE_RXBYTES(cur_rx); 1004 rxstat = letoh32(cur_rx->vge_sts); 1005 rxctl = letoh32(cur_rx->vge_ctl); 1006 1007 /* Invalidate the RX mbuf and unload its map */ 1008 1009 bus_dmamap_sync(sc->sc_dmat, 1010 sc->vge_ldata.vge_rx_dmamap[i], 1011 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1012 BUS_DMASYNC_POSTWRITE); 1013 bus_dmamap_unload(sc->sc_dmat, 1014 sc->vge_ldata.vge_rx_dmamap[i]); 1015 1016 /* 1017 * If the 'start of frame' bit is set, this indicates 1018 * either the first fragment in a multi-fragment receive, 1019 * or an intermediate fragment. Either way, we want to 1020 * accumulate the buffers. 1021 */ 1022 if (rxstat & VGE_RXPKT_SOF) { 1023 DPRINTF(("vge_rxeof: SOF\n")); 1024 m->m_len = MCLBYTES; 1025 if (sc->vge_head == NULL) 1026 sc->vge_head = sc->vge_tail = m; 1027 else { 1028 m->m_flags &= ~M_PKTHDR; 1029 sc->vge_tail->m_next = m; 1030 sc->vge_tail = m; 1031 } 1032 vge_newbuf(sc, i, NULL); 1033 VGE_RX_DESC_INC(i); 1034 continue; 1035 } 1036 1037 /* 1038 * Bad/error frames will have the RXOK bit cleared. 1039 * However, there's one error case we want to allow: 1040 * if a VLAN tagged frame arrives and the chip can't 1041 * match it against the CAM filter, it considers this 1042 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1043 * We don't want to drop the frame though: our VLAN 1044 * filtering is done in software. 1045 */ 1046 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1047 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1048 ifp->if_ierrors++; 1049 /* 1050 * If this is part of a multi-fragment packet, 1051 * discard all the pieces. 1052 */ 1053 if (sc->vge_head != NULL) { 1054 m_freem(sc->vge_head); 1055 sc->vge_head = sc->vge_tail = NULL; 1056 } 1057 vge_newbuf(sc, i, m); 1058 VGE_RX_DESC_INC(i); 1059 continue; 1060 } 1061 1062 /* 1063 * If allocating a replacement mbuf fails, 1064 * reload the current one. 1065 */ 1066 1067 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1068 if (sc->vge_head != NULL) { 1069 m_freem(sc->vge_head); 1070 sc->vge_head = sc->vge_tail = NULL; 1071 } 1072 1073 m0 = m_devget(mtod(m, char *), 1074 total_len - ETHER_CRC_LEN, ETHER_ALIGN); 1075 vge_newbuf(sc, i, m); 1076 if (m0 == NULL) { 1077 ifp->if_ierrors++; 1078 continue; 1079 } 1080 m = m0; 1081 1082 VGE_RX_DESC_INC(i); 1083 continue; 1084 } 1085 1086 VGE_RX_DESC_INC(i); 1087 1088 if (sc->vge_head != NULL) { 1089 m->m_len = total_len % MCLBYTES; 1090 /* 1091 * Special case: if there's 4 bytes or less 1092 * in this buffer, the mbuf can be discarded: 1093 * the last 4 bytes is the CRC, which we don't 1094 * care about anyway. 1095 */ 1096 if (m->m_len <= ETHER_CRC_LEN) { 1097 sc->vge_tail->m_len -= 1098 (ETHER_CRC_LEN - m->m_len); 1099 m_freem(m); 1100 } else { 1101 m->m_len -= ETHER_CRC_LEN; 1102 m->m_flags &= ~M_PKTHDR; 1103 sc->vge_tail->m_next = m; 1104 } 1105 m = sc->vge_head; 1106 sc->vge_head = sc->vge_tail = NULL; 1107 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1108 } else 1109 m->m_pkthdr.len = m->m_len = 1110 (total_len - ETHER_CRC_LEN); 1111 1112#ifdef __STRICT_ALIGNMENT 1113 bcopy(m->m_data, m->m_data + ETHER_ALIGN, total_len); 1114 m->m_data += ETHER_ALIGN; 1115#endif 1116 /* Do RX checksumming */ 1117 1118 /* Check IP header checksum */ 1119 if ((rxctl & VGE_RDCTL_IPPKT) && 1120 (rxctl & VGE_RDCTL_IPCSUMOK)) 1121 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1122 1123 /* Check TCP/UDP checksum */ 1124 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1125 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1126 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1127 1128#if NVLAN > 0 1129 if (rxstat & VGE_RDSTS_VTAG) { 1130 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1131 m->m_flags |= M_VLANTAG; 1132 } 1133#endif 1134 1135 ml_enqueue(&ml, m); 1136 1137 lim++; 1138 if (lim == VGE_RX_DESC_CNT) 1139 break; 1140 } 1141 1142 if_input(ifp, &ml); 1143 1144 /* Flush the RX DMA ring */ 1145 bus_dmamap_sync(sc->sc_dmat, 1146 sc->vge_ldata.vge_rx_list_map, 1147 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1148 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1149 1150 sc->vge_ldata.vge_rx_prodidx = i; 1151 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1152} 1153 1154void 1155vge_txeof(struct vge_softc *sc) 1156{ 1157 struct ifnet *ifp; 1158 u_int32_t txstat; 1159 int idx; 1160 1161 ifp = &sc->arpcom.ac_if; 1162 idx = sc->vge_ldata.vge_tx_considx; 1163 1164 /* Invalidate the TX descriptor list */ 1165 1166 bus_dmamap_sync(sc->sc_dmat, 1167 sc->vge_ldata.vge_tx_list_map, 1168 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1169 BUS_DMASYNC_POSTREAD); 1170 1171 /* Transmitted frames can be now free'd from the TX list */ 1172 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1173 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1174 if (txstat & VGE_TDSTS_OWN) 1175 break; 1176 1177 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1178 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1179 bus_dmamap_unload(sc->sc_dmat, 1180 sc->vge_ldata.vge_tx_dmamap[idx]); 1181 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1182 ifp->if_collisions++; 1183 if (txstat & VGE_TDSTS_TXERR) 1184 ifp->if_oerrors++; 1185 else 1186 ifp->if_opackets++; 1187 1188 sc->vge_ldata.vge_tx_free++; 1189 VGE_TX_DESC_INC(idx); 1190 } 1191 1192 /* No changes made to the TX ring, so no flush needed */ 1193 1194 if (idx != sc->vge_ldata.vge_tx_considx) { 1195 sc->vge_ldata.vge_tx_considx = idx; 1196 ifp->if_flags &= ~IFF_OACTIVE; 1197 ifp->if_timer = 0; 1198 } 1199 1200 /* 1201 * If not all descriptors have been released reaped yet, 1202 * reload the timer so that we will eventually get another 1203 * interrupt that will cause us to re-enter this routine. 1204 * This is done in case the transmitter has gone idle. 1205 */ 1206 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1207 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1208} 1209 1210void 1211vge_tick(void *xsc) 1212{ 1213 struct vge_softc *sc = xsc; 1214 struct ifnet *ifp = &sc->arpcom.ac_if; 1215 struct mii_data *mii = &sc->sc_mii; 1216 int s; 1217 1218 s = splnet(); 1219 1220 mii_tick(mii); 1221 1222 if (sc->vge_link) { 1223 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1224 sc->vge_link = 0; 1225 ifp->if_link_state = LINK_STATE_DOWN; 1226 if_link_state_change(ifp); 1227 } 1228 } else { 1229 if (mii->mii_media_status & IFM_ACTIVE && 1230 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1231 sc->vge_link = 1; 1232 if (mii->mii_media_status & IFM_FDX) 1233 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1234 else 1235 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1236 if_link_state_change(ifp); 1237 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1238 vge_start(ifp); 1239 } 1240 } 1241 timeout_add_sec(&sc->timer_handle, 1); 1242 splx(s); 1243} 1244 1245int 1246vge_intr(void *arg) 1247{ 1248 struct vge_softc *sc = arg; 1249 struct ifnet *ifp; 1250 u_int32_t status; 1251 int claimed = 0; 1252 1253 ifp = &sc->arpcom.ac_if; 1254 1255 if (!(ifp->if_flags & IFF_UP)) 1256 return 0; 1257 1258 /* Disable interrupts */ 1259 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1260 1261 for (;;) { 1262 status = CSR_READ_4(sc, VGE_ISR); 1263 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1264 1265 /* If the card has gone away the read returns 0xffffffff. */ 1266 if (status == 0xFFFFFFFF) 1267 break; 1268 1269 if (status) { 1270 CSR_WRITE_4(sc, VGE_ISR, status); 1271 } 1272 1273 if ((status & VGE_INTRS) == 0) 1274 break; 1275 1276 claimed = 1; 1277 1278 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1279 vge_rxeof(sc); 1280 1281 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1282 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1283 vge_rxeof(sc); 1284 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1285 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1286 } 1287 1288 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1289 vge_txeof(sc); 1290 1291 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1292 DPRINTFN(2, ("DMA_STALL\n")); 1293 vge_init(ifp); 1294 } 1295 1296 if (status & VGE_ISR_LINKSTS) { 1297 timeout_del(&sc->timer_handle); 1298 vge_tick(sc); 1299 } 1300 } 1301 1302 /* Re-enable interrupts */ 1303 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1304 1305 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1306 vge_start(ifp); 1307 1308 return (claimed); 1309} 1310 1311/* 1312 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1313 * the descriptors. 1314 */ 1315int 1316vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1317{ 1318 bus_dmamap_t txmap; 1319 struct vge_tx_desc *d = NULL; 1320 struct vge_tx_frag *f; 1321 int error, frag; 1322 u_int32_t vge_flags; 1323 unsigned int len; 1324 1325 vge_flags = 0; 1326 1327 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1328 vge_flags |= VGE_TDCTL_IPCSUM; 1329 if (m_head->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1330 vge_flags |= VGE_TDCTL_TCPCSUM; 1331 if (m_head->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1332 vge_flags |= VGE_TDCTL_UDPCSUM; 1333 1334 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1335 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1336 m_head, BUS_DMA_NOWAIT); 1337 switch (error) { 1338 case 0: 1339 break; 1340 case EFBIG: /* mbuf chain is too fragmented */ 1341 if ((error = m_defrag(m_head, M_DONTWAIT)) == 0 && 1342 (error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, m_head, 1343 BUS_DMA_NOWAIT)) == 0) 1344 break; 1345 default: 1346 return (error); 1347 } 1348 1349 d = &sc->vge_ldata.vge_tx_list[idx]; 1350 /* If owned by chip, fail */ 1351 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1352 return (ENOBUFS); 1353 1354 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1355 f = &d->vge_frag[frag]; 1356 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1357 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1358 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1359 } 1360 1361 /* This chip does not do auto-padding */ 1362 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1363 f = &d->vge_frag[frag]; 1364 1365 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1366 m_head->m_pkthdr.len)); 1367 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1368 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1369 len = VGE_MIN_FRAMELEN; 1370 frag++; 1371 } else 1372 len = m_head->m_pkthdr.len; 1373 1374 /* For some reason, we need to tell the card fragment + 1 */ 1375 frag++; 1376 1377 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1378 BUS_DMASYNC_PREWRITE); 1379 1380 d->vge_sts = htole32(len << 16); 1381 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1382 1383 if (len > ETHERMTU + ETHER_HDR_LEN) 1384 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1385 1386#if NVLAN > 0 1387 /* Set up hardware VLAN tagging. */ 1388 if (m_head->m_flags & M_VLANTAG) { 1389 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1390 VGE_TDCTL_VTAG); 1391 } 1392#endif 1393 1394 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1395 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1396 sc->vge_ldata.vge_tx_free--; 1397 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1398 1399 idx++; 1400 return (0); 1401} 1402 1403/* 1404 * Main transmit routine. 1405 */ 1406void 1407vge_start(struct ifnet *ifp) 1408{ 1409 struct vge_softc *sc; 1410 struct mbuf *m_head = NULL; 1411 int idx, pidx = 0; 1412 1413 sc = ifp->if_softc; 1414 1415 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1416 return; 1417 1418 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1419 return; 1420 1421 idx = sc->vge_ldata.vge_tx_prodidx; 1422 1423 pidx = idx - 1; 1424 if (pidx < 0) 1425 pidx = VGE_TX_DESC_CNT - 1; 1426 1427 for (;;) { 1428 if (sc->vge_ldata.vge_tx_mbuf[idx] != NULL) { 1429 ifp->if_flags |= IFF_OACTIVE; 1430 break; 1431 } 1432 1433 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1434 if (m_head == NULL) 1435 break; 1436 1437 if (vge_encap(sc, m_head, idx)) { 1438 m_freem(m_head); 1439 ifp->if_oerrors++; 1440 continue; 1441 } 1442 1443 /* 1444 * If there's a BPF listener, bounce a copy of this frame 1445 * to him. 1446 */ 1447#if NBPFILTER > 0 1448 if (ifp->if_bpf) 1449 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1450#endif 1451 1452 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1453 htole16(VGE_TXDESC_Q); 1454 1455 pidx = idx; 1456 VGE_TX_DESC_INC(idx); 1457 } 1458 1459 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1460 return; 1461 } 1462 1463 /* Flush the TX descriptors */ 1464 1465 bus_dmamap_sync(sc->sc_dmat, 1466 sc->vge_ldata.vge_tx_list_map, 1467 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1468 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1469 1470 /* Issue a transmit command. */ 1471 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1472 1473 sc->vge_ldata.vge_tx_prodidx = idx; 1474 1475 /* 1476 * Use the countdown timer for interrupt moderation. 1477 * 'TX done' interrupts are disabled. Instead, we reset the 1478 * countdown timer, which will begin counting until it hits 1479 * the value in the SSTIMER register, and then trigger an 1480 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1481 * the timer count is reloaded. Only when the transmitter 1482 * is idle will the timer hit 0 and an interrupt fire. 1483 */ 1484 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1485 1486 /* 1487 * Set a timeout in case the chip goes out to lunch. 1488 */ 1489 ifp->if_timer = 5; 1490} 1491 1492int 1493vge_init(struct ifnet *ifp) 1494{ 1495 struct vge_softc *sc = ifp->if_softc; 1496 int i; 1497 1498 /* 1499 * Cancel pending I/O and free all RX/TX buffers. 1500 */ 1501 vge_stop(sc); 1502 vge_reset(sc); 1503 1504 /* Initialize RX descriptors list */ 1505 if (vge_rx_list_init(sc) == ENOBUFS) { 1506 printf("%s: init failed: no memory for RX buffers\n", 1507 sc->vge_dev.dv_xname); 1508 vge_stop(sc); 1509 return (ENOBUFS); 1510 } 1511 /* Initialize TX descriptors */ 1512 if (vge_tx_list_init(sc) == ENOBUFS) { 1513 printf("%s: init failed: no memory for TX buffers\n", 1514 sc->vge_dev.dv_xname); 1515 vge_stop(sc); 1516 return (ENOBUFS); 1517 } 1518 1519 /* Set our station address */ 1520 for (i = 0; i < ETHER_ADDR_LEN; i++) 1521 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1522 1523 /* Set receive FIFO threshold */ 1524 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1525 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1526 1527 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1528 /* 1529 * Allow transmission and reception of VLAN tagged 1530 * frames. 1531 */ 1532 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1533 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1534 } 1535 1536 /* Set DMA burst length */ 1537 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1538 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1539 1540 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1541 1542 /* Set collision backoff algorithm */ 1543 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1544 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1545 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1546 1547 /* Disable LPSEL field in priority resolution */ 1548 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1549 1550 /* 1551 * Load the addresses of the DMA queues into the chip. 1552 * Note that we only use one transmit queue. 1553 */ 1554 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1555 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1556 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1557 1558 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1559 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1560 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1561 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1562 1563 /* Enable and wake up the RX descriptor queue */ 1564 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1565 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1566 1567 /* Enable the TX descriptor queue */ 1568 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1569 1570 /* Set up the receive filter -- allow large frames for VLANs. */ 1571 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_GIANT); 1572 1573 /* Program promiscuous mode and multicast filters. */ 1574 vge_iff(sc); 1575 1576 /* Initialize pause timer. */ 1577 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); 1578 /* 1579 * Initialize flow control parameters. 1580 * TX XON high threshold : 48 1581 * TX pause low threshold : 24 1582 * Disable half-duplex flow control 1583 */ 1584 CSR_WRITE_1(sc, VGE_CRC2, 0xFF); 1585 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_XON_ENABLE | 0x0B); 1586 1587 /* Enable jumbo frame reception (if desired) */ 1588 1589 /* Start the MAC. */ 1590 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1591 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1592 CSR_WRITE_1(sc, VGE_CRS0, 1593 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1594 1595 /* 1596 * Configure one-shot timer for microsecond 1597 * resulution and load it for 500 usecs. 1598 */ 1599 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1600 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1601 1602 /* 1603 * Configure interrupt moderation for receive. Enable 1604 * the holdoff counter and load it, and set the RX 1605 * suppression count to the number of descriptors we 1606 * want to allow before triggering an interrupt. 1607 * The holdoff timer is in units of 20 usecs. 1608 */ 1609 1610#ifdef notyet 1611 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1612 /* Select the interrupt holdoff timer page. */ 1613 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1614 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1615 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1616 1617 /* Enable use of the holdoff timer. */ 1618 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1619 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1620 1621 /* Select the RX suppression threshold page. */ 1622 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1623 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1624 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1625 1626 /* Restore the page select bits. */ 1627 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1628 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1629#endif 1630 1631 /* 1632 * Enable interrupts. 1633 */ 1634 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1635 CSR_WRITE_4(sc, VGE_ISR, 0); 1636 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1637 1638 /* Restore BMCR state */ 1639 mii_mediachg(&sc->sc_mii); 1640 1641 ifp->if_flags |= IFF_RUNNING; 1642 ifp->if_flags &= ~IFF_OACTIVE; 1643 1644 sc->vge_link = 0; 1645 1646 if (!timeout_pending(&sc->timer_handle)) 1647 timeout_add_sec(&sc->timer_handle, 1); 1648 1649 return (0); 1650} 1651 1652/* 1653 * Set media options. 1654 */ 1655int 1656vge_ifmedia_upd(struct ifnet *ifp) 1657{ 1658 struct vge_softc *sc = ifp->if_softc; 1659 1660 return (mii_mediachg(&sc->sc_mii)); 1661} 1662 1663/* 1664 * Report current media status. 1665 */ 1666void 1667vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1668{ 1669 struct vge_softc *sc = ifp->if_softc; 1670 1671 mii_pollstat(&sc->sc_mii); 1672 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1673 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1674} 1675 1676void 1677vge_miibus_statchg(struct device *dev) 1678{ 1679 struct vge_softc *sc = (struct vge_softc *)dev; 1680 struct mii_data *mii; 1681 struct ifmedia_entry *ife; 1682 1683 mii = &sc->sc_mii; 1684 ife = mii->mii_media.ifm_cur; 1685 1686 /* 1687 * If the user manually selects a media mode, we need to turn 1688 * on the forced MAC mode bit in the DIAGCTL register. If the 1689 * user happens to choose a full duplex mode, we also need to 1690 * set the 'force full duplex' bit. This applies only to 1691 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1692 * mode is disabled, and in 1000baseT mode, full duplex is 1693 * always implied, so we turn on the forced mode bit but leave 1694 * the FDX bit cleared. 1695 */ 1696 1697 switch (IFM_SUBTYPE(ife->ifm_media)) { 1698 case IFM_AUTO: 1699 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1700 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1701 break; 1702 case IFM_1000_T: 1703 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1704 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1705 break; 1706 case IFM_100_TX: 1707 case IFM_10_T: 1708 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1709 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1710 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1711 } else { 1712 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1713 } 1714 break; 1715 default: 1716 printf("%s: unknown media type: %llx\n", 1717 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1718 break; 1719 } 1720 1721 /* 1722 * 802.3x flow control 1723 */ 1724 CSR_WRITE_1(sc, VGE_CRC2, VGE_CR2_FDX_TXFLOWCTL_ENABLE | 1725 VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1726 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1727 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_TXFLOWCTL_ENABLE); 1728 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1729 CSR_WRITE_1(sc, VGE_CRS2, VGE_CR2_FDX_RXFLOWCTL_ENABLE); 1730} 1731 1732int 1733vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1734{ 1735 struct vge_softc *sc = ifp->if_softc; 1736 struct ifreq *ifr = (struct ifreq *) data; 1737 int s, error = 0; 1738 1739 s = splnet(); 1740 1741 switch (command) { 1742 case SIOCSIFADDR: 1743 ifp->if_flags |= IFF_UP; 1744 if (!(ifp->if_flags & IFF_RUNNING)) 1745 vge_init(ifp); 1746 break; 1747 1748 case SIOCSIFFLAGS: 1749 if (ifp->if_flags & IFF_UP) { 1750 if (ifp->if_flags & IFF_RUNNING) 1751 error = ENETRESET; 1752 else 1753 vge_init(ifp); 1754 } else { 1755 if (ifp->if_flags & IFF_RUNNING) 1756 vge_stop(sc); 1757 } 1758 break; 1759 1760 case SIOCGIFMEDIA: 1761 case SIOCSIFMEDIA: 1762 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1763 break; 1764 1765 default: 1766 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1767 } 1768 1769 if (error == ENETRESET) { 1770 if (ifp->if_flags & IFF_RUNNING) 1771 vge_iff(sc); 1772 error = 0; 1773 } 1774 1775 splx(s); 1776 return (error); 1777} 1778 1779void 1780vge_watchdog(struct ifnet *ifp) 1781{ 1782 struct vge_softc *sc = ifp->if_softc; 1783 int s; 1784 1785 s = splnet(); 1786 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1787 ifp->if_oerrors++; 1788 1789 vge_txeof(sc); 1790 vge_rxeof(sc); 1791 1792 vge_init(ifp); 1793 1794 splx(s); 1795} 1796 1797/* 1798 * Stop the adapter and free any mbufs allocated to the 1799 * RX and TX lists. 1800 */ 1801void 1802vge_stop(struct vge_softc *sc) 1803{ 1804 int i; 1805 struct ifnet *ifp; 1806 1807 ifp = &sc->arpcom.ac_if; 1808 ifp->if_timer = 0; 1809 1810 timeout_del(&sc->timer_handle); 1811 1812 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1813 1814 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1815 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1816 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1817 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1818 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1819 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1820 1821 if (sc->vge_head != NULL) { 1822 m_freem(sc->vge_head); 1823 sc->vge_head = sc->vge_tail = NULL; 1824 } 1825 1826 /* Free the TX list buffers. */ 1827 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1828 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1829 bus_dmamap_unload(sc->sc_dmat, 1830 sc->vge_ldata.vge_tx_dmamap[i]); 1831 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1832 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1833 } 1834 } 1835 1836 /* Free the RX list buffers. */ 1837 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1838 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1839 bus_dmamap_unload(sc->sc_dmat, 1840 sc->vge_ldata.vge_rx_dmamap[i]); 1841 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1842 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1843 } 1844 } 1845} 1846