if_vge.c revision 1.53
1/* $OpenBSD: if_vge.c,v 1.53 2012/11/29 21:10:32 brad Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/timeout.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#ifdef INET 103#include <netinet/in.h> 104#include <netinet/in_systm.h> 105#include <netinet/in_var.h> 106#include <netinet/ip.h> 107#include <netinet/if_ether.h> 108#endif 109 110#if NVLAN > 0 111#include <net/if_types.h> 112#include <net/if_vlan_var.h> 113#endif 114 115#if NBPFILTER > 0 116#include <net/bpf.h> 117#endif 118 119#include <dev/mii/mii.h> 120#include <dev/mii/miivar.h> 121 122#include <dev/pci/pcireg.h> 123#include <dev/pci/pcivar.h> 124#include <dev/pci/pcidevs.h> 125 126#include <dev/pci/if_vgereg.h> 127#include <dev/pci/if_vgevar.h> 128 129int vge_probe (struct device *, void *, void *); 130void vge_attach (struct device *, struct device *, void *); 131int vge_detach (struct device *, int); 132 133int vge_encap (struct vge_softc *, struct mbuf *, int); 134 135int vge_allocmem (struct vge_softc *); 136void vge_freemem (struct vge_softc *); 137int vge_newbuf (struct vge_softc *, int, struct mbuf *); 138int vge_rx_list_init (struct vge_softc *); 139int vge_tx_list_init (struct vge_softc *); 140void vge_rxeof (struct vge_softc *); 141void vge_txeof (struct vge_softc *); 142int vge_intr (void *); 143void vge_tick (void *); 144void vge_start (struct ifnet *); 145int vge_ioctl (struct ifnet *, u_long, caddr_t); 146int vge_init (struct ifnet *); 147void vge_stop (struct vge_softc *); 148void vge_watchdog (struct ifnet *); 149int vge_ifmedia_upd (struct ifnet *); 150void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152#ifdef VGE_EEPROM 153void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 154#endif 155void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 156 157void vge_miipoll_start (struct vge_softc *); 158void vge_miipoll_stop (struct vge_softc *); 159int vge_miibus_readreg (struct device *, int, int); 160void vge_miibus_writereg (struct device *, int, int, int); 161void vge_miibus_statchg (struct device *); 162 163void vge_cam_clear (struct vge_softc *); 164int vge_cam_set (struct vge_softc *, uint8_t *); 165void vge_setmulti (struct vge_softc *); 166void vge_reset (struct vge_softc *); 167 168struct cfattach vge_ca = { 169 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach 170}; 171 172struct cfdriver vge_cd = { 173 NULL, "vge", DV_IFNET 174}; 175 176#define VGE_PCI_LOIO 0x10 177#define VGE_PCI_LOMEM 0x14 178 179int vge_debug = 0; 180#define DPRINTF(x) if (vge_debug) printf x 181#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 182 183const struct pci_matchid vge_devices[] = { 184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 185}; 186 187#ifdef VGE_EEPROM 188/* 189 * Read a word of data stored in the EEPROM at address 'addr.' 190 */ 191void 192vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 193{ 194 int i; 195 u_int16_t word = 0; 196 197 /* 198 * Enter EEPROM embedded programming mode. In order to 199 * access the EEPROM at all, we first have to set the 200 * EELOAD bit in the CHIPCFG2 register. 201 */ 202 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 203 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 204 205 /* Select the address of the word we want to read */ 206 CSR_WRITE_1(sc, VGE_EEADDR, addr); 207 208 /* Issue read command */ 209 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 210 211 /* Wait for the done bit to be set. */ 212 for (i = 0; i < VGE_TIMEOUT; i++) { 213 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 214 break; 215 } 216 217 if (i == VGE_TIMEOUT) { 218 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 219 *dest = 0; 220 return; 221 } 222 223 /* Read the result */ 224 word = CSR_READ_2(sc, VGE_EERDDAT); 225 226 /* Turn off EEPROM access mode. */ 227 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 228 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 229 230 *dest = word; 231} 232#endif 233 234/* 235 * Read a sequence of words from the EEPROM. 236 */ 237void 238vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 239 int swap) 240{ 241 int i; 242#ifdef VGE_EEPROM 243 u_int16_t word = 0, *ptr; 244 245 for (i = 0; i < cnt; i++) { 246 vge_eeprom_getword(sc, off + i, &word); 247 ptr = (u_int16_t *)(dest + (i * 2)); 248 if (swap) 249 *ptr = ntohs(word); 250 else 251 *ptr = word; 252 } 253#else 254 for (i = 0; i < ETHER_ADDR_LEN; i++) 255 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 256#endif 257} 258 259void 260vge_miipoll_stop(struct vge_softc *sc) 261{ 262 int i; 263 264 CSR_WRITE_1(sc, VGE_MIICMD, 0); 265 266 for (i = 0; i < VGE_TIMEOUT; i++) { 267 DELAY(1); 268 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 269 break; 270 } 271 272 if (i == VGE_TIMEOUT) 273 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 274} 275 276void 277vge_miipoll_start(struct vge_softc *sc) 278{ 279 int i; 280 281 /* First, make sure we're idle. */ 282 283 CSR_WRITE_1(sc, VGE_MIICMD, 0); 284 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 285 286 for (i = 0; i < VGE_TIMEOUT; i++) { 287 DELAY(1); 288 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 289 break; 290 } 291 292 if (i == VGE_TIMEOUT) { 293 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 294 return; 295 } 296 297 /* Now enable auto poll mode. */ 298 299 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 300 301 /* And make sure it started. */ 302 303 for (i = 0; i < VGE_TIMEOUT; i++) { 304 DELAY(1); 305 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 306 break; 307 } 308 309 if (i == VGE_TIMEOUT) 310 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 311} 312 313int 314vge_miibus_readreg(struct device *dev, int phy, int reg) 315{ 316 struct vge_softc *sc = (struct vge_softc *)dev; 317 int i, s; 318 u_int16_t rval = 0; 319 320 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 321 return(0); 322 323 s = splnet(); 324 325 vge_miipoll_stop(sc); 326 327 /* Specify the register we want to read. */ 328 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 329 330 /* Issue read command. */ 331 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 332 333 /* Wait for the read command bit to self-clear. */ 334 for (i = 0; i < VGE_TIMEOUT; i++) { 335 DELAY(1); 336 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 337 break; 338 } 339 340 if (i == VGE_TIMEOUT) 341 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 342 else 343 rval = CSR_READ_2(sc, VGE_MIIDATA); 344 345 vge_miipoll_start(sc); 346 splx(s); 347 348 return (rval); 349} 350 351void 352vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 353{ 354 struct vge_softc *sc = (struct vge_softc *)dev; 355 int i, s; 356 357 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 358 return; 359 360 s = splnet(); 361 vge_miipoll_stop(sc); 362 363 /* Specify the register we want to write. */ 364 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 365 366 /* Specify the data we want to write. */ 367 CSR_WRITE_2(sc, VGE_MIIDATA, data); 368 369 /* Issue write command. */ 370 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 371 372 /* Wait for the write command bit to self-clear. */ 373 for (i = 0; i < VGE_TIMEOUT; i++) { 374 DELAY(1); 375 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 376 break; 377 } 378 379 if (i == VGE_TIMEOUT) { 380 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 381 } 382 383 vge_miipoll_start(sc); 384 splx(s); 385} 386 387void 388vge_cam_clear(struct vge_softc *sc) 389{ 390 int i; 391 392 /* 393 * Turn off all the mask bits. This tells the chip 394 * that none of the entries in the CAM filter are valid. 395 * desired entries will be enabled as we fill the filter in. 396 */ 397 398 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 399 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 400 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 401 for (i = 0; i < 8; i++) 402 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 403 404 /* Clear the VLAN filter too. */ 405 406 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 407 for (i = 0; i < 8; i++) 408 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 409 410 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 411 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 412 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 413 414 sc->vge_camidx = 0; 415} 416 417int 418vge_cam_set(struct vge_softc *sc, uint8_t *addr) 419{ 420 int i, error = 0; 421 422 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 423 return(ENOSPC); 424 425 /* Select the CAM data page. */ 426 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 427 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 428 429 /* Set the filter entry we want to update and enable writing. */ 430 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 431 432 /* Write the address to the CAM registers */ 433 for (i = 0; i < ETHER_ADDR_LEN; i++) 434 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 435 436 /* Issue a write command. */ 437 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 438 439 /* Wake for it to clear. */ 440 for (i = 0; i < VGE_TIMEOUT; i++) { 441 DELAY(1); 442 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 443 break; 444 } 445 446 if (i == VGE_TIMEOUT) { 447 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 448 error = EIO; 449 goto fail; 450 } 451 452 /* Select the CAM mask page. */ 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 455 456 /* Set the mask bit that enables this filter. */ 457 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 458 1<<(sc->vge_camidx & 7)); 459 460 sc->vge_camidx++; 461 462fail: 463 /* Turn off access to CAM. */ 464 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 465 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 466 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 467 468 return (error); 469} 470 471/* 472 * Program the multicast filter. We use the 64-entry CAM filter 473 * for perfect filtering. If there's more than 64 multicast addresses, 474 * we use the hash filter instead. 475 */ 476void 477vge_setmulti(struct vge_softc *sc) 478{ 479 struct arpcom *ac = &sc->arpcom; 480 struct ifnet *ifp = &ac->ac_if; 481 struct ether_multi *enm; 482 struct ether_multistep step; 483 int error; 484 u_int32_t h = 0, hashes[2] = { 0, 0 }; 485 486 /* First, zot all the multicast entries. */ 487 vge_cam_clear(sc); 488 CSR_WRITE_4(sc, VGE_MAR0, 0); 489 CSR_WRITE_4(sc, VGE_MAR1, 0); 490 ifp->if_flags &= ~IFF_ALLMULTI; 491 492 /* 493 * If the user wants allmulti or promisc mode, enable reception 494 * of all multicast frames. 495 */ 496 if (ifp->if_flags & IFF_PROMISC) { 497allmulti: 498 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 499 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 500 ifp->if_flags |= IFF_ALLMULTI; 501 return; 502 } 503 504 /* Now program new ones */ 505 ETHER_FIRST_MULTI(step, ac, enm); 506 while (enm != NULL) { 507 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 508 goto allmulti; 509 510 error = vge_cam_set(sc, enm->enm_addrlo); 511 if (error) 512 break; 513 514 ETHER_NEXT_MULTI(step, enm); 515 } 516 517 /* If there were too many addresses, use the hash filter. */ 518 if (error) { 519 vge_cam_clear(sc); 520 521 ETHER_FIRST_MULTI(step, ac, enm); 522 while (enm != NULL) { 523 h = ether_crc32_be(enm->enm_addrlo, 524 ETHER_ADDR_LEN) >> 26; 525 hashes[h >> 5] |= 1 << (h & 0x1f); 526 527 ETHER_NEXT_MULTI(step, enm); 528 } 529 530 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 531 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 532 } 533} 534 535void 536vge_reset(struct vge_softc *sc) 537{ 538 int i; 539 540 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 541 542 for (i = 0; i < VGE_TIMEOUT; i++) { 543 DELAY(5); 544 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 545 break; 546 } 547 548 if (i == VGE_TIMEOUT) { 549 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 550 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 551 DELAY(2000); 552 } 553 554 DELAY(5000); 555 556 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 557 558 for (i = 0; i < VGE_TIMEOUT; i++) { 559 DELAY(5); 560 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 561 break; 562 } 563 564 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 565} 566 567/* 568 * Probe for a VIA gigabit chip. Check the PCI vendor and device 569 * IDs against our list and return a device name if we find a match. 570 */ 571int 572vge_probe(struct device *dev, void *match, void *aux) 573{ 574 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 575 nitems(vge_devices))); 576} 577 578/* 579 * Allocate memory for RX/TX rings 580 */ 581int 582vge_allocmem(struct vge_softc *sc) 583{ 584 int nseg, rseg; 585 int i, error; 586 587 nseg = 32; 588 589 /* Allocate DMA'able memory for the TX ring */ 590 591 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 592 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 593 &sc->vge_ldata.vge_tx_list_map); 594 if (error) 595 return (ENOMEM); 596 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 597 ETHER_ALIGN, 0, 598 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 599 if (error) { 600 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 601 return (ENOMEM); 602 } 603 604 /* Load the map for the TX ring. */ 605 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 606 1, VGE_TX_LIST_SZ, 607 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 608 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 609 if (error) { 610 printf("%s: can't map TX dma buffers\n", 611 sc->vge_dev.dv_xname); 612 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 613 return (ENOMEM); 614 } 615 616 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 617 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 620 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 621 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 622 VGE_TX_LIST_SZ); 623 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 624 return (ENOMEM); 625 } 626 627 /* Create DMA maps for TX buffers */ 628 629 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 630 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 631 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 632 &sc->vge_ldata.vge_tx_dmamap[i]); 633 if (error) { 634 printf("%s: can't create DMA map for TX\n", 635 sc->vge_dev.dv_xname); 636 return (ENOMEM); 637 } 638 } 639 640 /* Allocate DMA'able memory for the RX ring */ 641 642 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 643 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 644 &sc->vge_ldata.vge_rx_list_map); 645 if (error) 646 return (ENOMEM); 647 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 648 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 649 if (error) { 650 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 651 return (ENOMEM); 652 } 653 654 /* Load the map for the RX ring. */ 655 656 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 657 1, VGE_RX_LIST_SZ, 658 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 659 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 660 if (error) { 661 printf("%s: can't map RX dma buffers\n", 662 sc->vge_dev.dv_xname); 663 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 664 return (ENOMEM); 665 } 666 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 667 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 668 if (error) { 669 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 670 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 671 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 672 VGE_RX_LIST_SZ); 673 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 674 return (ENOMEM); 675 } 676 677 /* Create DMA maps for RX buffers */ 678 679 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 681 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 682 &sc->vge_ldata.vge_rx_dmamap[i]); 683 if (error) { 684 printf("%s: can't create DMA map for RX\n", 685 sc->vge_dev.dv_xname); 686 return (ENOMEM); 687 } 688 } 689 690 return (0); 691} 692 693void 694vge_freemem(struct vge_softc *sc) 695{ 696 int i; 697 698 for (i = 0; i < VGE_RX_DESC_CNT; i++) 699 bus_dmamap_destroy(sc->sc_dmat, 700 sc->vge_ldata.vge_rx_dmamap[i]); 701 702 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 703 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 704 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 705 VGE_RX_LIST_SZ); 706 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1); 707 708 for (i = 0; i < VGE_TX_DESC_CNT; i++) 709 bus_dmamap_destroy(sc->sc_dmat, 710 sc->vge_ldata.vge_tx_dmamap[i]); 711 712 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 713 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 714 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 715 VGE_TX_LIST_SZ); 716 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1); 717} 718 719/* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723void 724vge_attach(struct device *parent, struct device *self, void *aux) 725{ 726 u_char eaddr[ETHER_ADDR_LEN]; 727 struct vge_softc *sc = (struct vge_softc *)self; 728 struct pci_attach_args *pa = aux; 729 pci_chipset_tag_t pc = pa->pa_pc; 730 pci_intr_handle_t ih; 731 const char *intrstr = NULL; 732 struct ifnet *ifp; 733 int error = 0; 734 735 /* 736 * Map control/status registers. 737 */ 738 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 739 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 740 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 741 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 742 printf(": can't map mem or i/o space\n"); 743 return; 744 } 745 } 746 747 /* Allocate interrupt */ 748 if (pci_intr_map(pa, &ih)) { 749 printf(": couldn't map interrupt\n"); 750 return; 751 } 752 intrstr = pci_intr_string(pc, ih); 753 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 754 sc->vge_dev.dv_xname); 755 if (sc->vge_intrhand == NULL) { 756 printf(": couldn't establish interrupt"); 757 if (intrstr != NULL) 758 printf(" at %s", intrstr); 759 return; 760 } 761 printf(": %s", intrstr); 762 763 sc->sc_dmat = pa->pa_dmat; 764 sc->sc_pc = pa->pa_pc; 765 766 /* Reset the adapter. */ 767 vge_reset(sc); 768 769 /* 770 * Get station address from the EEPROM. 771 */ 772 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1); 773 774 bcopy(eaddr, &sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 775 776 printf(", address %s\n", 777 ether_sprintf(sc->arpcom.ac_enaddr)); 778 779 error = vge_allocmem(sc); 780 781 if (error) 782 return; 783 784 ifp = &sc->arpcom.ac_if; 785 ifp->if_softc = sc; 786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 787 ifp->if_ioctl = vge_ioctl; 788 ifp->if_start = vge_start; 789 ifp->if_watchdog = vge_watchdog; 790#ifdef VGE_JUMBO 791 ifp->if_hardmtu = VGE_JUMBO_MTU; 792#endif 793 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 794 IFQ_SET_READY(&ifp->if_snd); 795 796 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 797 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 798 799#if NVLAN > 0 800 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 801#endif 802 803 /* Set interface name */ 804 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 805 806 /* Do MII setup */ 807 sc->sc_mii.mii_ifp = ifp; 808 sc->sc_mii.mii_readreg = vge_miibus_readreg; 809 sc->sc_mii.mii_writereg = vge_miibus_writereg; 810 sc->sc_mii.mii_statchg = vge_miibus_statchg; 811 ifmedia_init(&sc->sc_mii.mii_media, 0, 812 vge_ifmedia_upd, vge_ifmedia_sts); 813 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 814 MII_OFFSET_ANY, 0); 815 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 816 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 817 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 818 0, NULL); 819 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 820 } else 821 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 822 823 timeout_set(&sc->timer_handle, vge_tick, sc); 824 825 /* 826 * Call MI attach routine. 827 */ 828 if_attach(ifp); 829 ether_ifattach(ifp); 830} 831 832int 833vge_detach(struct device *self, int flags) 834{ 835 struct vge_softc *sc = (void *)self; 836 struct ifnet *ifp = &sc->arpcom.ac_if; 837 838 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand); 839 840 vge_stop(sc); 841 842 /* Detach all PHYs */ 843 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 844 845 /* Delete any remaining media. */ 846 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 847 848 ether_ifdetach(ifp); 849 if_detach(ifp); 850 851 vge_freemem(sc); 852 853 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize); 854 return (0); 855} 856 857int 858vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 859{ 860 struct mbuf *m_new = NULL; 861 struct vge_rx_desc *r; 862 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 863 int i; 864 865 if (m == NULL) { 866 /* Allocate a new mbuf */ 867 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 868 if (m_new == NULL) 869 return (ENOBUFS); 870 871 /* Allocate a cluster */ 872 MCLGET(m_new, M_DONTWAIT); 873 if (!(m_new->m_flags & M_EXT)) { 874 m_freem(m_new); 875 return (ENOBUFS); 876 } 877 878 m = m_new; 879 } else 880 m->m_data = m->m_ext.ext_buf; 881 882 m->m_len = m->m_pkthdr.len = MCLBYTES; 883 /* Fix-up alignment so payload is doubleword-aligned */ 884 /* XXX m_adj(m, ETHER_ALIGN); */ 885 886 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 887 return (ENOBUFS); 888 889 if (rxmap->dm_nsegs > 1) 890 goto out; 891 892 /* Map the segments into RX descriptors */ 893 r = &sc->vge_ldata.vge_rx_list[idx]; 894 895 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 896 printf("%s: tried to map a busy RX descriptor\n", 897 sc->vge_dev.dv_xname); 898 goto out; 899 } 900 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 901 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 902 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 903 r->vge_sts = htole32(0); 904 r->vge_ctl = htole32(0); 905 906 /* 907 * Note: the manual fails to document the fact that for 908 * proper operation, the driver needs to replenish the RX 909 * DMA ring 4 descriptors at a time (rather than one at a 910 * time, like most chips). We can allocate the new buffers 911 * but we should not set the OWN bits until we're ready 912 * to hand back 4 of them in one shot. 913 */ 914#define VGE_RXCHUNK 4 915 sc->vge_rx_consumed++; 916 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 917 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 918 sc->vge_ldata.vge_rx_list[i].vge_sts |= 919 htole32(VGE_RDSTS_OWN); 920 sc->vge_rx_consumed = 0; 921 } 922 923 sc->vge_ldata.vge_rx_mbuf[idx] = m; 924 925 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 926 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 927 928 return (0); 929out: 930 DPRINTF(("vge_newbuf: out of memory\n")); 931 if (m_new != NULL) 932 m_freem(m_new); 933 return (ENOMEM); 934} 935 936int 937vge_tx_list_init(struct vge_softc *sc) 938{ 939 bzero(sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 940 bzero(&sc->vge_ldata.vge_tx_mbuf, 941 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 942 943 bus_dmamap_sync(sc->sc_dmat, 944 sc->vge_ldata.vge_tx_list_map, 0, 945 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 946 BUS_DMASYNC_PREWRITE); 947 sc->vge_ldata.vge_tx_prodidx = 0; 948 sc->vge_ldata.vge_tx_considx = 0; 949 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 950 951 return (0); 952} 953 954/* Init RX descriptors and allocate mbufs with vge_newbuf() 955 * A ring is used, and last descriptor points to first. */ 956int 957vge_rx_list_init(struct vge_softc *sc) 958{ 959 int i; 960 961 bzero(sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 962 bzero(&sc->vge_ldata.vge_rx_mbuf, 963 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 964 965 sc->vge_rx_consumed = 0; 966 967 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 968 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 969 return (ENOBUFS); 970 } 971 972 /* Flush the RX descriptors */ 973 974 bus_dmamap_sync(sc->sc_dmat, 975 sc->vge_ldata.vge_rx_list_map, 976 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 977 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 978 979 sc->vge_ldata.vge_rx_prodidx = 0; 980 sc->vge_rx_consumed = 0; 981 sc->vge_head = sc->vge_tail = NULL; 982 983 return (0); 984} 985 986/* 987 * RX handler. We support the reception of jumbo frames that have 988 * been fragmented across multiple 2K mbuf cluster buffers. 989 */ 990void 991vge_rxeof(struct vge_softc *sc) 992{ 993 struct mbuf *m; 994 struct ifnet *ifp; 995 int i, total_len; 996 int lim = 0; 997 struct vge_rx_desc *cur_rx; 998 u_int32_t rxstat, rxctl; 999 1000 ifp = &sc->arpcom.ac_if; 1001 i = sc->vge_ldata.vge_rx_prodidx; 1002 1003 /* Invalidate the descriptor memory */ 1004 1005 bus_dmamap_sync(sc->sc_dmat, 1006 sc->vge_ldata.vge_rx_list_map, 1007 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1008 BUS_DMASYNC_POSTREAD); 1009 1010 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1011 struct mbuf *m0 = NULL; 1012 1013 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1014 m = sc->vge_ldata.vge_rx_mbuf[i]; 1015 total_len = VGE_RXBYTES(cur_rx); 1016 rxstat = letoh32(cur_rx->vge_sts); 1017 rxctl = letoh32(cur_rx->vge_ctl); 1018 1019 /* Invalidate the RX mbuf and unload its map */ 1020 1021 bus_dmamap_sync(sc->sc_dmat, 1022 sc->vge_ldata.vge_rx_dmamap[i], 1023 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1024 BUS_DMASYNC_POSTWRITE); 1025 bus_dmamap_unload(sc->sc_dmat, 1026 sc->vge_ldata.vge_rx_dmamap[i]); 1027 1028 /* 1029 * If the 'start of frame' bit is set, this indicates 1030 * either the first fragment in a multi-fragment receive, 1031 * or an intermediate fragment. Either way, we want to 1032 * accumulate the buffers. 1033 */ 1034 if (rxstat & VGE_RXPKT_SOF) { 1035 DPRINTF(("vge_rxeof: SOF\n")); 1036 m->m_len = MCLBYTES; 1037 if (sc->vge_head == NULL) 1038 sc->vge_head = sc->vge_tail = m; 1039 else { 1040 m->m_flags &= ~M_PKTHDR; 1041 sc->vge_tail->m_next = m; 1042 sc->vge_tail = m; 1043 } 1044 vge_newbuf(sc, i, NULL); 1045 VGE_RX_DESC_INC(i); 1046 continue; 1047 } 1048 1049 /* 1050 * Bad/error frames will have the RXOK bit cleared. 1051 * However, there's one error case we want to allow: 1052 * if a VLAN tagged frame arrives and the chip can't 1053 * match it against the CAM filter, it considers this 1054 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1055 * We don't want to drop the frame though: our VLAN 1056 * filtering is done in software. 1057 */ 1058 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1059 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1060 ifp->if_ierrors++; 1061 /* 1062 * If this is part of a multi-fragment packet, 1063 * discard all the pieces. 1064 */ 1065 if (sc->vge_head != NULL) { 1066 m_freem(sc->vge_head); 1067 sc->vge_head = sc->vge_tail = NULL; 1068 } 1069 vge_newbuf(sc, i, m); 1070 VGE_RX_DESC_INC(i); 1071 continue; 1072 } 1073 1074 /* 1075 * If allocating a replacement mbuf fails, 1076 * reload the current one. 1077 */ 1078 1079 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1080 if (sc->vge_head != NULL) { 1081 m_freem(sc->vge_head); 1082 sc->vge_head = sc->vge_tail = NULL; 1083 } 1084 1085 m0 = m_devget(mtod(m, char *), 1086 total_len - ETHER_CRC_LEN, ETHER_ALIGN, ifp, NULL); 1087 vge_newbuf(sc, i, m); 1088 if (m0 == NULL) { 1089 ifp->if_ierrors++; 1090 continue; 1091 } 1092 m = m0; 1093 1094 VGE_RX_DESC_INC(i); 1095 continue; 1096 } 1097 1098 VGE_RX_DESC_INC(i); 1099 1100 if (sc->vge_head != NULL) { 1101 m->m_len = total_len % MCLBYTES; 1102 /* 1103 * Special case: if there's 4 bytes or less 1104 * in this buffer, the mbuf can be discarded: 1105 * the last 4 bytes is the CRC, which we don't 1106 * care about anyway. 1107 */ 1108 if (m->m_len <= ETHER_CRC_LEN) { 1109 sc->vge_tail->m_len -= 1110 (ETHER_CRC_LEN - m->m_len); 1111 m_freem(m); 1112 } else { 1113 m->m_len -= ETHER_CRC_LEN; 1114 m->m_flags &= ~M_PKTHDR; 1115 sc->vge_tail->m_next = m; 1116 } 1117 m = sc->vge_head; 1118 sc->vge_head = sc->vge_tail = NULL; 1119 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1120 } else 1121 m->m_pkthdr.len = m->m_len = 1122 (total_len - ETHER_CRC_LEN); 1123 1124#ifdef __STRICT_ALIGNMENT 1125 bcopy(m->m_data, m->m_data + ETHER_ALIGN, total_len); 1126 m->m_data += ETHER_ALIGN; 1127#endif 1128 ifp->if_ipackets++; 1129 m->m_pkthdr.rcvif = ifp; 1130 1131 /* Do RX checksumming */ 1132 1133 /* Check IP header checksum */ 1134 if ((rxctl & VGE_RDCTL_IPPKT) && 1135 (rxctl & VGE_RDCTL_IPCSUMOK)) 1136 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1137 1138 /* Check TCP/UDP checksum */ 1139 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1140 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1141 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1142 1143#if NVLAN > 0 1144 if (rxstat & VGE_RDSTS_VTAG) { 1145 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1146 m->m_flags |= M_VLANTAG; 1147 } 1148#endif 1149 1150#if NBPFILTER > 0 1151 if (ifp->if_bpf) 1152 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1153#endif 1154 ether_input_mbuf(ifp, m); 1155 1156 lim++; 1157 if (lim == VGE_RX_DESC_CNT) 1158 break; 1159 } 1160 1161 /* Flush the RX DMA ring */ 1162 bus_dmamap_sync(sc->sc_dmat, 1163 sc->vge_ldata.vge_rx_list_map, 1164 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1165 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1166 1167 sc->vge_ldata.vge_rx_prodidx = i; 1168 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1169} 1170 1171void 1172vge_txeof(struct vge_softc *sc) 1173{ 1174 struct ifnet *ifp; 1175 u_int32_t txstat; 1176 int idx; 1177 1178 ifp = &sc->arpcom.ac_if; 1179 idx = sc->vge_ldata.vge_tx_considx; 1180 1181 /* Invalidate the TX descriptor list */ 1182 1183 bus_dmamap_sync(sc->sc_dmat, 1184 sc->vge_ldata.vge_tx_list_map, 1185 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1186 BUS_DMASYNC_POSTREAD); 1187 1188 /* Transmitted frames can be now free'd from the TX list */ 1189 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1190 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1191 if (txstat & VGE_TDSTS_OWN) 1192 break; 1193 1194 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1195 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1196 bus_dmamap_unload(sc->sc_dmat, 1197 sc->vge_ldata.vge_tx_dmamap[idx]); 1198 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1199 ifp->if_collisions++; 1200 if (txstat & VGE_TDSTS_TXERR) 1201 ifp->if_oerrors++; 1202 else 1203 ifp->if_opackets++; 1204 1205 sc->vge_ldata.vge_tx_free++; 1206 VGE_TX_DESC_INC(idx); 1207 } 1208 1209 /* No changes made to the TX ring, so no flush needed */ 1210 1211 if (idx != sc->vge_ldata.vge_tx_considx) { 1212 sc->vge_ldata.vge_tx_considx = idx; 1213 ifp->if_flags &= ~IFF_OACTIVE; 1214 ifp->if_timer = 0; 1215 } 1216 1217 /* 1218 * If not all descriptors have been released reaped yet, 1219 * reload the timer so that we will eventually get another 1220 * interrupt that will cause us to re-enter this routine. 1221 * This is done in case the transmitter has gone idle. 1222 */ 1223 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1224 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1225} 1226 1227void 1228vge_tick(void *xsc) 1229{ 1230 struct vge_softc *sc = xsc; 1231 struct ifnet *ifp = &sc->arpcom.ac_if; 1232 struct mii_data *mii = &sc->sc_mii; 1233 int s; 1234 1235 s = splnet(); 1236 1237 mii_tick(mii); 1238 1239 if (sc->vge_link) { 1240 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1241 sc->vge_link = 0; 1242 ifp->if_link_state = LINK_STATE_DOWN; 1243 if_link_state_change(ifp); 1244 } 1245 } else { 1246 if (mii->mii_media_status & IFM_ACTIVE && 1247 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1248 sc->vge_link = 1; 1249 if (mii->mii_media_status & IFM_FDX) 1250 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1251 else 1252 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1253 if_link_state_change(ifp); 1254 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1255 vge_start(ifp); 1256 } 1257 } 1258 timeout_add_sec(&sc->timer_handle, 1); 1259 splx(s); 1260} 1261 1262int 1263vge_intr(void *arg) 1264{ 1265 struct vge_softc *sc = arg; 1266 struct ifnet *ifp; 1267 u_int32_t status; 1268 int claimed = 0; 1269 1270 ifp = &sc->arpcom.ac_if; 1271 1272 if (!(ifp->if_flags & IFF_UP)) 1273 return 0; 1274 1275 /* Disable interrupts */ 1276 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1277 1278 for (;;) { 1279 status = CSR_READ_4(sc, VGE_ISR); 1280 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1281 1282 /* If the card has gone away the read returns 0xffffffff. */ 1283 if (status == 0xFFFFFFFF) 1284 break; 1285 1286 if (status) { 1287 CSR_WRITE_4(sc, VGE_ISR, status); 1288 } 1289 1290 if ((status & VGE_INTRS) == 0) 1291 break; 1292 1293 claimed = 1; 1294 1295 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1296 vge_rxeof(sc); 1297 1298 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1299 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1300 vge_rxeof(sc); 1301 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1302 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1303 } 1304 1305 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1306 vge_txeof(sc); 1307 1308 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1309 DPRINTFN(2, ("DMA_STALL\n")); 1310 vge_init(ifp); 1311 } 1312 1313 if (status & VGE_ISR_LINKSTS) { 1314 timeout_del(&sc->timer_handle); 1315 vge_tick(sc); 1316 } 1317 } 1318 1319 /* Re-enable interrupts */ 1320 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1321 1322 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1323 vge_start(ifp); 1324 1325 return (claimed); 1326} 1327 1328/* 1329 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1330 * the descriptors. 1331 */ 1332int 1333vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1334{ 1335 struct ifnet *ifp = &sc->arpcom.ac_if; 1336 bus_dmamap_t txmap; 1337 struct vge_tx_desc *d = NULL; 1338 struct vge_tx_frag *f; 1339 struct mbuf *mnew = NULL; 1340 int error, frag; 1341 u_int32_t vge_flags; 1342 1343 vge_flags = 0; 1344 1345 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1346 vge_flags |= VGE_TDCTL_IPCSUM; 1347 if (m_head->m_pkthdr.csum_flags & M_TCP_CSUM_OUT) 1348 vge_flags |= VGE_TDCTL_TCPCSUM; 1349 if (m_head->m_pkthdr.csum_flags & M_UDP_CSUM_OUT) 1350 vge_flags |= VGE_TDCTL_UDPCSUM; 1351 1352 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1353repack: 1354 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1355 m_head, BUS_DMA_NOWAIT); 1356 if (error) { 1357 printf("%s: can't map mbuf (error %d)\n", 1358 sc->vge_dev.dv_xname, error); 1359 return (ENOBUFS); 1360 } 1361 1362 d = &sc->vge_ldata.vge_tx_list[idx]; 1363 /* If owned by chip, fail */ 1364 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1365 return (ENOBUFS); 1366 1367 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1368 /* Check if we have used all 7 fragments. */ 1369 if (frag == VGE_TX_FRAGS) 1370 break; 1371 f = &d->vge_frag[frag]; 1372 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1373 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1374 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1375 } 1376 1377 /* 1378 * We used up all 7 fragments! Now what we have to do is 1379 * copy the data into a mbuf cluster and map that. 1380 */ 1381 if (frag == VGE_TX_FRAGS) { 1382 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1383 if (mnew == NULL) 1384 return (ENOBUFS); 1385 1386 if (m_head->m_pkthdr.len > MHLEN) { 1387 MCLGET(mnew, M_DONTWAIT); 1388 if (!(mnew->m_flags & M_EXT)) { 1389 m_freem(mnew); 1390 return (ENOBUFS); 1391 } 1392 } 1393 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1394 mtod(mnew, caddr_t)); 1395 mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len; 1396 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1397 m_freem(m_head); 1398 m_head = mnew; 1399 goto repack; 1400 } 1401 1402 /* This chip does not do auto-padding */ 1403 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1404 f = &d->vge_frag[frag]; 1405 1406 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1407 m_head->m_pkthdr.len)); 1408 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1409 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1410 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1411 frag++; 1412 } 1413 /* For some reason, we need to tell the card fragment + 1 */ 1414 frag++; 1415 1416 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1417 BUS_DMASYNC_PREWRITE); 1418 1419 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1420 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1421 1422 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1423 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1424 1425#if NVLAN > 0 1426 /* Set up hardware VLAN tagging. */ 1427 if (m_head->m_flags & M_VLANTAG) { 1428 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1429 VGE_TDCTL_VTAG); 1430 } 1431#endif 1432 1433 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1434 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1435 sc->vge_ldata.vge_tx_free--; 1436 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1437 1438 idx++; 1439 if (mnew == NULL) { 1440 /* if mbuf is coalesced, it is already dequeued */ 1441 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1442 } 1443 return (0); 1444} 1445 1446/* 1447 * Main transmit routine. 1448 */ 1449void 1450vge_start(struct ifnet *ifp) 1451{ 1452 struct vge_softc *sc; 1453 struct mbuf *m_head = NULL; 1454 int idx, pidx = 0; 1455 1456 sc = ifp->if_softc; 1457 1458 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1459 return; 1460 1461 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1462 return; 1463 1464 idx = sc->vge_ldata.vge_tx_prodidx; 1465 1466 pidx = idx - 1; 1467 if (pidx < 0) 1468 pidx = VGE_TX_DESC_CNT - 1; 1469 1470 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1471 IFQ_POLL(&ifp->if_snd, m_head); 1472 if (m_head == NULL) 1473 break; 1474 1475 /* 1476 * If there's a BPF listener, bounce a copy of this frame 1477 * to him. 1478 */ 1479#if NBPFILTER > 0 1480 if (ifp->if_bpf) 1481 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1482#endif 1483 1484 if (vge_encap(sc, m_head, idx)) { 1485 ifp->if_flags |= IFF_OACTIVE; 1486 break; 1487 } 1488 1489 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1490 htole16(VGE_TXDESC_Q); 1491 1492 pidx = idx; 1493 VGE_TX_DESC_INC(idx); 1494 } 1495 1496 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1497 return; 1498 } 1499 1500 /* Flush the TX descriptors */ 1501 1502 bus_dmamap_sync(sc->sc_dmat, 1503 sc->vge_ldata.vge_tx_list_map, 1504 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1505 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1506 1507 /* Issue a transmit command. */ 1508 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1509 1510 sc->vge_ldata.vge_tx_prodidx = idx; 1511 1512 /* 1513 * Use the countdown timer for interrupt moderation. 1514 * 'TX done' interrupts are disabled. Instead, we reset the 1515 * countdown timer, which will begin counting until it hits 1516 * the value in the SSTIMER register, and then trigger an 1517 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1518 * the timer count is reloaded. Only when the transmitter 1519 * is idle will the timer hit 0 and an interrupt fire. 1520 */ 1521 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1522 1523 /* 1524 * Set a timeout in case the chip goes out to lunch. 1525 */ 1526 ifp->if_timer = 5; 1527} 1528 1529int 1530vge_init(struct ifnet *ifp) 1531{ 1532 struct vge_softc *sc = ifp->if_softc; 1533 int i; 1534 1535 /* 1536 * Cancel pending I/O and free all RX/TX buffers. 1537 */ 1538 vge_stop(sc); 1539 vge_reset(sc); 1540 1541 /* Initialize RX descriptors list */ 1542 if (vge_rx_list_init(sc) == ENOBUFS) { 1543 printf("%s: init failed: no memory for RX buffers\n", 1544 sc->vge_dev.dv_xname); 1545 vge_stop(sc); 1546 return (ENOBUFS); 1547 } 1548 /* Initialize TX descriptors */ 1549 if (vge_tx_list_init(sc) == ENOBUFS) { 1550 printf("%s: init failed: no memory for TX buffers\n", 1551 sc->vge_dev.dv_xname); 1552 vge_stop(sc); 1553 return (ENOBUFS); 1554 } 1555 1556 /* Set our station address */ 1557 for (i = 0; i < ETHER_ADDR_LEN; i++) 1558 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1559 1560 /* Set receive FIFO threshold */ 1561 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1562 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1563 1564 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1565 /* 1566 * Allow transmission and reception of VLAN tagged 1567 * frames. 1568 */ 1569 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1570 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1571 } 1572 1573 /* Set DMA burst length */ 1574 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1575 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1576 1577 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1578 1579 /* Set collision backoff algorithm */ 1580 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1581 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1582 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1583 1584 /* Disable LPSEL field in priority resolution */ 1585 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1586 1587 /* 1588 * Load the addresses of the DMA queues into the chip. 1589 * Note that we only use one transmit queue. 1590 */ 1591 1592 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1593 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1594 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1595 1596 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1597 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1598 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1599 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1600 1601 /* Enable and wake up the RX descriptor queue */ 1602 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1603 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1604 1605 /* Enable the TX descriptor queue */ 1606 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1607 1608 /* Set up the receive filter -- allow large frames for VLANs. */ 1609 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1610 1611 /* If we want promiscuous mode, set the allframes bit. */ 1612 if (ifp->if_flags & IFF_PROMISC) { 1613 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1614 } 1615 1616 /* Set capture broadcast bit to capture broadcast frames. */ 1617 if (ifp->if_flags & IFF_BROADCAST) { 1618 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1619 } 1620 1621 /* Set multicast bit to capture multicast frames. */ 1622 if (ifp->if_flags & IFF_MULTICAST) { 1623 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1624 } 1625 1626 /* Init the cam filter. */ 1627 vge_cam_clear(sc); 1628 1629 /* Init the multicast filter. */ 1630 vge_setmulti(sc); 1631 1632 /* Enable flow control */ 1633 1634 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1635 1636 /* Enable jumbo frame reception (if desired) */ 1637 1638 /* Start the MAC. */ 1639 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1640 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1641 CSR_WRITE_1(sc, VGE_CRS0, 1642 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1643 1644 /* 1645 * Configure one-shot timer for microsecond 1646 * resulution and load it for 500 usecs. 1647 */ 1648 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1649 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1650 1651 /* 1652 * Configure interrupt moderation for receive. Enable 1653 * the holdoff counter and load it, and set the RX 1654 * suppression count to the number of descriptors we 1655 * want to allow before triggering an interrupt. 1656 * The holdoff timer is in units of 20 usecs. 1657 */ 1658 1659#ifdef notyet 1660 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1661 /* Select the interrupt holdoff timer page. */ 1662 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1663 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1664 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1665 1666 /* Enable use of the holdoff timer. */ 1667 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1668 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1669 1670 /* Select the RX suppression threshold page. */ 1671 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1672 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1673 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1674 1675 /* Restore the page select bits. */ 1676 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1677 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1678#endif 1679 1680 /* 1681 * Enable interrupts. 1682 */ 1683 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1684 CSR_WRITE_4(sc, VGE_ISR, 0); 1685 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1686 1687 /* Restore BMCR state */ 1688 mii_mediachg(&sc->sc_mii); 1689 1690 ifp->if_flags |= IFF_RUNNING; 1691 ifp->if_flags &= ~IFF_OACTIVE; 1692 1693 sc->vge_if_flags = 0; 1694 sc->vge_link = 0; 1695 1696 if (!timeout_pending(&sc->timer_handle)) 1697 timeout_add_sec(&sc->timer_handle, 1); 1698 1699 return (0); 1700} 1701 1702/* 1703 * Set media options. 1704 */ 1705int 1706vge_ifmedia_upd(struct ifnet *ifp) 1707{ 1708 struct vge_softc *sc = ifp->if_softc; 1709 1710 return (mii_mediachg(&sc->sc_mii)); 1711} 1712 1713/* 1714 * Report current media status. 1715 */ 1716void 1717vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1718{ 1719 struct vge_softc *sc = ifp->if_softc; 1720 1721 mii_pollstat(&sc->sc_mii); 1722 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1723 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1724} 1725 1726void 1727vge_miibus_statchg(struct device *dev) 1728{ 1729 struct vge_softc *sc = (struct vge_softc *)dev; 1730 struct mii_data *mii; 1731 struct ifmedia_entry *ife; 1732 1733 mii = &sc->sc_mii; 1734 ife = mii->mii_media.ifm_cur; 1735 1736 /* 1737 * If the user manually selects a media mode, we need to turn 1738 * on the forced MAC mode bit in the DIAGCTL register. If the 1739 * user happens to choose a full duplex mode, we also need to 1740 * set the 'force full duplex' bit. This applies only to 1741 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1742 * mode is disabled, and in 1000baseT mode, full duplex is 1743 * always implied, so we turn on the forced mode bit but leave 1744 * the FDX bit cleared. 1745 */ 1746 1747 switch (IFM_SUBTYPE(ife->ifm_media)) { 1748 case IFM_AUTO: 1749 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1750 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1751 break; 1752 case IFM_1000_T: 1753 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1754 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1755 break; 1756 case IFM_100_TX: 1757 case IFM_10_T: 1758 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1759 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1760 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1761 } else { 1762 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1763 } 1764 break; 1765 default: 1766 printf("%s: unknown media type: %x\n", 1767 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1768 break; 1769 } 1770} 1771 1772int 1773vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1774{ 1775 struct vge_softc *sc = ifp->if_softc; 1776 struct ifaddr *ifa = (struct ifaddr *) data; 1777 struct ifreq *ifr = (struct ifreq *) data; 1778 int s, error = 0; 1779 1780 s = splnet(); 1781 1782 switch (command) { 1783 case SIOCSIFADDR: 1784 ifp->if_flags |= IFF_UP; 1785 switch (ifa->ifa_addr->sa_family) { 1786#ifdef INET 1787 case AF_INET: 1788 vge_init(ifp); 1789 arp_ifinit(&sc->arpcom, ifa); 1790 break; 1791#endif 1792 default: 1793 vge_init(ifp); 1794 break; 1795 } 1796 break; 1797 1798 case SIOCSIFFLAGS: 1799 if (ifp->if_flags & IFF_UP) { 1800 if (ifp->if_flags & IFF_RUNNING && 1801 ifp->if_flags & IFF_PROMISC && 1802 !(sc->vge_if_flags & IFF_PROMISC)) { 1803 CSR_SETBIT_1(sc, VGE_RXCTL, 1804 VGE_RXCTL_RX_PROMISC); 1805 vge_setmulti(sc); 1806 } else if (ifp->if_flags & IFF_RUNNING && 1807 !(ifp->if_flags & IFF_PROMISC) && 1808 sc->vge_if_flags & IFF_PROMISC) { 1809 CSR_CLRBIT_1(sc, VGE_RXCTL, 1810 VGE_RXCTL_RX_PROMISC); 1811 vge_setmulti(sc); 1812 } else 1813 vge_init(ifp); 1814 } else { 1815 if (ifp->if_flags & IFF_RUNNING) 1816 vge_stop(sc); 1817 } 1818 sc->vge_if_flags = ifp->if_flags; 1819 break; 1820 1821 case SIOCGIFMEDIA: 1822 case SIOCSIFMEDIA: 1823 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1824 break; 1825 1826 default: 1827 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1828 } 1829 1830 if (error == ENETRESET) { 1831 if (ifp->if_flags & IFF_RUNNING) 1832 vge_setmulti(sc); 1833 error = 0; 1834 } 1835 1836 splx(s); 1837 return (error); 1838} 1839 1840void 1841vge_watchdog(struct ifnet *ifp) 1842{ 1843 struct vge_softc *sc = ifp->if_softc; 1844 int s; 1845 1846 s = splnet(); 1847 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1848 ifp->if_oerrors++; 1849 1850 vge_txeof(sc); 1851 vge_rxeof(sc); 1852 1853 vge_init(ifp); 1854 1855 splx(s); 1856} 1857 1858/* 1859 * Stop the adapter and free any mbufs allocated to the 1860 * RX and TX lists. 1861 */ 1862void 1863vge_stop(struct vge_softc *sc) 1864{ 1865 int i; 1866 struct ifnet *ifp; 1867 1868 ifp = &sc->arpcom.ac_if; 1869 ifp->if_timer = 0; 1870 1871 timeout_del(&sc->timer_handle); 1872 1873 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1874 1875 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1876 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1877 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1878 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1879 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1880 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1881 1882 if (sc->vge_head != NULL) { 1883 m_freem(sc->vge_head); 1884 sc->vge_head = sc->vge_tail = NULL; 1885 } 1886 1887 /* Free the TX list buffers. */ 1888 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1889 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1890 bus_dmamap_unload(sc->sc_dmat, 1891 sc->vge_ldata.vge_tx_dmamap[i]); 1892 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1893 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1894 } 1895 } 1896 1897 /* Free the RX list buffers. */ 1898 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1899 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1900 bus_dmamap_unload(sc->sc_dmat, 1901 sc->vge_ldata.vge_rx_dmamap[i]); 1902 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1903 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1904 } 1905 } 1906} 1907