if_vge.c revision 1.47
1/* $OpenBSD: if_vge.c,v 1.47 2010/02/24 21:44:12 kettenis Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66MHz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/timeout.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#ifdef INET 103#include <netinet/in.h> 104#include <netinet/in_systm.h> 105#include <netinet/in_var.h> 106#include <netinet/ip.h> 107#include <netinet/if_ether.h> 108#endif 109 110#if NVLAN > 0 111#include <net/if_types.h> 112#include <net/if_vlan_var.h> 113#endif 114 115#if NBPFILTER > 0 116#include <net/bpf.h> 117#endif 118 119#include <dev/mii/mii.h> 120#include <dev/mii/miivar.h> 121 122#include <dev/pci/pcireg.h> 123#include <dev/pci/pcivar.h> 124#include <dev/pci/pcidevs.h> 125 126#include <dev/pci/if_vgereg.h> 127#include <dev/pci/if_vgevar.h> 128 129int vge_probe (struct device *, void *, void *); 130void vge_attach (struct device *, struct device *, void *); 131int vge_detach (struct device *, int); 132 133int vge_encap (struct vge_softc *, struct mbuf *, int); 134 135int vge_allocmem (struct vge_softc *); 136void vge_freemem (struct vge_softc *); 137int vge_newbuf (struct vge_softc *, int, struct mbuf *); 138int vge_rx_list_init (struct vge_softc *); 139int vge_tx_list_init (struct vge_softc *); 140void vge_rxeof (struct vge_softc *); 141void vge_txeof (struct vge_softc *); 142int vge_intr (void *); 143void vge_tick (void *); 144void vge_start (struct ifnet *); 145int vge_ioctl (struct ifnet *, u_long, caddr_t); 146int vge_init (struct ifnet *); 147void vge_stop (struct vge_softc *); 148void vge_watchdog (struct ifnet *); 149int vge_ifmedia_upd (struct ifnet *); 150void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 151 152#ifdef VGE_EEPROM 153void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 154#endif 155void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 156 157void vge_miipoll_start (struct vge_softc *); 158void vge_miipoll_stop (struct vge_softc *); 159int vge_miibus_readreg (struct device *, int, int); 160void vge_miibus_writereg (struct device *, int, int, int); 161void vge_miibus_statchg (struct device *); 162 163void vge_cam_clear (struct vge_softc *); 164int vge_cam_set (struct vge_softc *, uint8_t *); 165void vge_setmulti (struct vge_softc *); 166void vge_reset (struct vge_softc *); 167 168struct cfattach vge_ca = { 169 sizeof(struct vge_softc), vge_probe, vge_attach, vge_detach 170}; 171 172struct cfdriver vge_cd = { 173 NULL, "vge", DV_IFNET 174}; 175 176#define VGE_PCI_LOIO 0x10 177#define VGE_PCI_LOMEM 0x14 178 179int vge_debug = 0; 180#define DPRINTF(x) if (vge_debug) printf x 181#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 182 183const struct pci_matchid vge_devices[] = { 184 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 185}; 186 187#ifdef VGE_EEPROM 188/* 189 * Read a word of data stored in the EEPROM at address 'addr.' 190 */ 191void 192vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 193{ 194 int i; 195 u_int16_t word = 0; 196 197 /* 198 * Enter EEPROM embedded programming mode. In order to 199 * access the EEPROM at all, we first have to set the 200 * EELOAD bit in the CHIPCFG2 register. 201 */ 202 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 203 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 204 205 /* Select the address of the word we want to read */ 206 CSR_WRITE_1(sc, VGE_EEADDR, addr); 207 208 /* Issue read command */ 209 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 210 211 /* Wait for the done bit to be set. */ 212 for (i = 0; i < VGE_TIMEOUT; i++) { 213 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 214 break; 215 } 216 217 if (i == VGE_TIMEOUT) { 218 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 219 *dest = 0; 220 return; 221 } 222 223 /* Read the result */ 224 word = CSR_READ_2(sc, VGE_EERDDAT); 225 226 /* Turn off EEPROM access mode. */ 227 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 228 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 229 230 *dest = word; 231} 232#endif 233 234/* 235 * Read a sequence of words from the EEPROM. 236 */ 237void 238vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 239 int swap) 240{ 241 int i; 242#ifdef VGE_EEPROM 243 u_int16_t word = 0, *ptr; 244 245 for (i = 0; i < cnt; i++) { 246 vge_eeprom_getword(sc, off + i, &word); 247 ptr = (u_int16_t *)(dest + (i * 2)); 248 if (swap) 249 *ptr = ntohs(word); 250 else 251 *ptr = word; 252 } 253#else 254 for (i = 0; i < ETHER_ADDR_LEN; i++) 255 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 256#endif 257} 258 259void 260vge_miipoll_stop(struct vge_softc *sc) 261{ 262 int i; 263 264 CSR_WRITE_1(sc, VGE_MIICMD, 0); 265 266 for (i = 0; i < VGE_TIMEOUT; i++) { 267 DELAY(1); 268 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 269 break; 270 } 271 272 if (i == VGE_TIMEOUT) 273 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 274} 275 276void 277vge_miipoll_start(struct vge_softc *sc) 278{ 279 int i; 280 281 /* First, make sure we're idle. */ 282 283 CSR_WRITE_1(sc, VGE_MIICMD, 0); 284 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 285 286 for (i = 0; i < VGE_TIMEOUT; i++) { 287 DELAY(1); 288 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 289 break; 290 } 291 292 if (i == VGE_TIMEOUT) { 293 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 294 return; 295 } 296 297 /* Now enable auto poll mode. */ 298 299 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 300 301 /* And make sure it started. */ 302 303 for (i = 0; i < VGE_TIMEOUT; i++) { 304 DELAY(1); 305 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 306 break; 307 } 308 309 if (i == VGE_TIMEOUT) 310 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 311} 312 313int 314vge_miibus_readreg(struct device *dev, int phy, int reg) 315{ 316 struct vge_softc *sc = (struct vge_softc *)dev; 317 int i, s; 318 u_int16_t rval = 0; 319 320 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 321 return(0); 322 323 s = splnet(); 324 325 vge_miipoll_stop(sc); 326 327 /* Specify the register we want to read. */ 328 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 329 330 /* Issue read command. */ 331 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 332 333 /* Wait for the read command bit to self-clear. */ 334 for (i = 0; i < VGE_TIMEOUT; i++) { 335 DELAY(1); 336 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 337 break; 338 } 339 340 if (i == VGE_TIMEOUT) 341 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 342 else 343 rval = CSR_READ_2(sc, VGE_MIIDATA); 344 345 vge_miipoll_start(sc); 346 splx(s); 347 348 return (rval); 349} 350 351void 352vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 353{ 354 struct vge_softc *sc = (struct vge_softc *)dev; 355 int i, s; 356 357 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 358 return; 359 360 s = splnet(); 361 vge_miipoll_stop(sc); 362 363 /* Specify the register we want to write. */ 364 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 365 366 /* Specify the data we want to write. */ 367 CSR_WRITE_2(sc, VGE_MIIDATA, data); 368 369 /* Issue write command. */ 370 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 371 372 /* Wait for the write command bit to self-clear. */ 373 for (i = 0; i < VGE_TIMEOUT; i++) { 374 DELAY(1); 375 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 376 break; 377 } 378 379 if (i == VGE_TIMEOUT) { 380 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 381 } 382 383 vge_miipoll_start(sc); 384 splx(s); 385} 386 387void 388vge_cam_clear(struct vge_softc *sc) 389{ 390 int i; 391 392 /* 393 * Turn off all the mask bits. This tells the chip 394 * that none of the entries in the CAM filter are valid. 395 * desired entries will be enabled as we fill the filter in. 396 */ 397 398 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 399 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 400 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 401 for (i = 0; i < 8; i++) 402 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 403 404 /* Clear the VLAN filter too. */ 405 406 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 407 for (i = 0; i < 8; i++) 408 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 409 410 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 411 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 412 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 413 414 sc->vge_camidx = 0; 415} 416 417int 418vge_cam_set(struct vge_softc *sc, uint8_t *addr) 419{ 420 int i, error = 0; 421 422 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 423 return(ENOSPC); 424 425 /* Select the CAM data page. */ 426 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 427 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 428 429 /* Set the filter entry we want to update and enable writing. */ 430 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 431 432 /* Write the address to the CAM registers */ 433 for (i = 0; i < ETHER_ADDR_LEN; i++) 434 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 435 436 /* Issue a write command. */ 437 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 438 439 /* Wake for it to clear. */ 440 for (i = 0; i < VGE_TIMEOUT; i++) { 441 DELAY(1); 442 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 443 break; 444 } 445 446 if (i == VGE_TIMEOUT) { 447 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 448 error = EIO; 449 goto fail; 450 } 451 452 /* Select the CAM mask page. */ 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 455 456 /* Set the mask bit that enables this filter. */ 457 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 458 1<<(sc->vge_camidx & 7)); 459 460 sc->vge_camidx++; 461 462fail: 463 /* Turn off access to CAM. */ 464 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 465 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 466 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 467 468 return (error); 469} 470 471/* 472 * Program the multicast filter. We use the 64-entry CAM filter 473 * for perfect filtering. If there's more than 64 multicast addresses, 474 * we use the hash filter instead. 475 */ 476void 477vge_setmulti(struct vge_softc *sc) 478{ 479 struct arpcom *ac = &sc->arpcom; 480 struct ifnet *ifp = &ac->ac_if; 481 struct ether_multi *enm; 482 struct ether_multistep step; 483 int error; 484 u_int32_t h = 0, hashes[2] = { 0, 0 }; 485 486 /* First, zot all the multicast entries. */ 487 vge_cam_clear(sc); 488 CSR_WRITE_4(sc, VGE_MAR0, 0); 489 CSR_WRITE_4(sc, VGE_MAR1, 0); 490 ifp->if_flags &= ~IFF_ALLMULTI; 491 492 /* 493 * If the user wants allmulti or promisc mode, enable reception 494 * of all multicast frames. 495 */ 496 if (ifp->if_flags & IFF_PROMISC) { 497allmulti: 498 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 499 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 500 ifp->if_flags |= IFF_ALLMULTI; 501 return; 502 } 503 504 /* Now program new ones */ 505 ETHER_FIRST_MULTI(step, ac, enm); 506 while (enm != NULL) { 507 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 508 goto allmulti; 509 510 error = vge_cam_set(sc, enm->enm_addrlo); 511 if (error) 512 break; 513 514 ETHER_NEXT_MULTI(step, enm); 515 } 516 517 /* If there were too many addresses, use the hash filter. */ 518 if (error) { 519 vge_cam_clear(sc); 520 521 ETHER_FIRST_MULTI(step, ac, enm); 522 while (enm != NULL) { 523 h = ether_crc32_be(enm->enm_addrlo, 524 ETHER_ADDR_LEN) >> 26; 525 hashes[h >> 5] |= 1 << (h & 0x1f); 526 527 ETHER_NEXT_MULTI(step, enm); 528 } 529 530 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 531 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 532 } 533} 534 535void 536vge_reset(struct vge_softc *sc) 537{ 538 int i; 539 540 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 541 542 for (i = 0; i < VGE_TIMEOUT; i++) { 543 DELAY(5); 544 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 545 break; 546 } 547 548 if (i == VGE_TIMEOUT) { 549 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 550 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 551 DELAY(2000); 552 } 553 554 DELAY(5000); 555 556 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 557 558 for (i = 0; i < VGE_TIMEOUT; i++) { 559 DELAY(5); 560 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 561 break; 562 } 563 564 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 565} 566 567/* 568 * Probe for a VIA gigabit chip. Check the PCI vendor and device 569 * IDs against our list and return a device name if we find a match. 570 */ 571int 572vge_probe(struct device *dev, void *match, void *aux) 573{ 574 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 575 sizeof(vge_devices)/sizeof(vge_devices[0]))); 576} 577 578/* 579 * Allocate memory for RX/TX rings 580 */ 581int 582vge_allocmem(struct vge_softc *sc) 583{ 584 int nseg, rseg; 585 int i, error; 586 587 nseg = 32; 588 589 /* Allocate DMA'able memory for the TX ring */ 590 591 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 592 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 593 &sc->vge_ldata.vge_tx_list_map); 594 if (error) 595 return (ENOMEM); 596 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 597 ETHER_ALIGN, 0, 598 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 599 if (error) { 600 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 601 return (ENOMEM); 602 } 603 604 /* Load the map for the TX ring. */ 605 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 606 1, VGE_TX_LIST_SZ, 607 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 608 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 609 if (error) { 610 printf("%s: can't map TX dma buffers\n", 611 sc->vge_dev.dv_xname); 612 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 613 return (ENOMEM); 614 } 615 616 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 617 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 618 if (error) { 619 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 620 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 621 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 622 VGE_TX_LIST_SZ); 623 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 624 return (ENOMEM); 625 } 626 627 /* Create DMA maps for TX buffers */ 628 629 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 630 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 631 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 632 &sc->vge_ldata.vge_tx_dmamap[i]); 633 if (error) { 634 printf("%s: can't create DMA map for TX\n", 635 sc->vge_dev.dv_xname); 636 return (ENOMEM); 637 } 638 } 639 640 /* Allocate DMA'able memory for the RX ring */ 641 642 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 643 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 644 &sc->vge_ldata.vge_rx_list_map); 645 if (error) 646 return (ENOMEM); 647 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 648 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 649 if (error) { 650 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 651 return (ENOMEM); 652 } 653 654 /* Load the map for the RX ring. */ 655 656 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 657 1, VGE_RX_LIST_SZ, 658 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 659 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 660 if (error) { 661 printf("%s: can't map RX dma buffers\n", 662 sc->vge_dev.dv_xname); 663 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 664 return (ENOMEM); 665 } 666 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 667 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 668 if (error) { 669 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 670 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 671 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 672 VGE_RX_LIST_SZ); 673 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 674 return (ENOMEM); 675 } 676 677 /* Create DMA maps for RX buffers */ 678 679 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 680 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 681 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 682 &sc->vge_ldata.vge_rx_dmamap[i]); 683 if (error) { 684 printf("%s: can't create DMA map for RX\n", 685 sc->vge_dev.dv_xname); 686 return (ENOMEM); 687 } 688 } 689 690 return (0); 691} 692 693void 694vge_freemem(struct vge_softc *sc) 695{ 696 int i; 697 698 for (i = 0; i < VGE_RX_DESC_CNT; i++) 699 bus_dmamap_destroy(sc->sc_dmat, 700 sc->vge_ldata.vge_rx_dmamap[i]); 701 702 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 703 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 704 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 705 VGE_RX_LIST_SZ); 706 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 1); 707 708 for (i = 0; i < VGE_TX_DESC_CNT; i++) 709 bus_dmamap_destroy(sc->sc_dmat, 710 sc->vge_ldata.vge_tx_dmamap[i]); 711 712 bus_dmamap_unload(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 713 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 714 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 715 VGE_TX_LIST_SZ); 716 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 1); 717} 718 719/* 720 * Attach the interface. Allocate softc structures, do ifmedia 721 * setup and ethernet/BPF attach. 722 */ 723void 724vge_attach(struct device *parent, struct device *self, void *aux) 725{ 726 u_char eaddr[ETHER_ADDR_LEN]; 727 struct vge_softc *sc = (struct vge_softc *)self; 728 struct pci_attach_args *pa = aux; 729 pci_chipset_tag_t pc = pa->pa_pc; 730 pci_intr_handle_t ih; 731 const char *intrstr = NULL; 732 struct ifnet *ifp; 733 int error = 0; 734 735 /* 736 * Map control/status registers. 737 */ 738 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 739 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 740 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 741 &sc->vge_btag, &sc->vge_bhandle, NULL, &sc->vge_bsize, 0)) { 742 printf(": can't map mem or i/o space\n"); 743 return; 744 } 745 } 746 747 /* Allocate interrupt */ 748 if (pci_intr_map(pa, &ih)) { 749 printf(": couldn't map interrupt\n"); 750 return; 751 } 752 intrstr = pci_intr_string(pc, ih); 753 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 754 sc->vge_dev.dv_xname); 755 if (sc->vge_intrhand == NULL) { 756 printf(": couldn't establish interrupt"); 757 if (intrstr != NULL) 758 printf(" at %s", intrstr); 759 return; 760 } 761 printf(": %s", intrstr); 762 763 sc->sc_dmat = pa->pa_dmat; 764 sc->sc_pc = pa->pa_pc; 765 766 /* Reset the adapter. */ 767 vge_reset(sc); 768 769 /* 770 * Get station address from the EEPROM. 771 */ 772 vge_read_eeprom(sc, eaddr, VGE_EE_EADDR, 3, 1); 773 774 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 775 776 printf(", address %s\n", 777 ether_sprintf(sc->arpcom.ac_enaddr)); 778 779 error = vge_allocmem(sc); 780 781 if (error) 782 return; 783 784 ifp = &sc->arpcom.ac_if; 785 ifp->if_softc = sc; 786 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 787 ifp->if_ioctl = vge_ioctl; 788 ifp->if_start = vge_start; 789 ifp->if_watchdog = vge_watchdog; 790 ifp->if_init = vge_init; 791 ifp->if_baudrate = 1000000000; 792#ifdef VGE_JUMBO 793 ifp->if_hardmtu = VGE_JUMBO_MTU; 794#endif 795 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 796 IFQ_SET_READY(&ifp->if_snd); 797 798 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 799 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 800 801#if NVLAN > 0 802 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 803#endif 804 805 /* Set interface name */ 806 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 807 808 /* Do MII setup */ 809 sc->sc_mii.mii_ifp = ifp; 810 sc->sc_mii.mii_readreg = vge_miibus_readreg; 811 sc->sc_mii.mii_writereg = vge_miibus_writereg; 812 sc->sc_mii.mii_statchg = vge_miibus_statchg; 813 ifmedia_init(&sc->sc_mii.mii_media, 0, 814 vge_ifmedia_upd, vge_ifmedia_sts); 815 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 816 MII_OFFSET_ANY, 0); 817 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 818 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 819 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 820 0, NULL); 821 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 822 } else 823 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 824 825 timeout_set(&sc->timer_handle, vge_tick, sc); 826 827 /* 828 * Call MI attach routine. 829 */ 830 if_attach(ifp); 831 ether_ifattach(ifp); 832} 833 834int 835vge_detach(struct device *self, int flags) 836{ 837 struct vge_softc *sc = (void *)self; 838 struct ifnet *ifp = &sc->arpcom.ac_if; 839 840 pci_intr_disestablish(sc->sc_pc, sc->vge_intrhand); 841 842 vge_stop(sc); 843 844 /* Detach all PHYs */ 845 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 846 847 /* Delete any remaining media. */ 848 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 849 850 ether_ifdetach(ifp); 851 if_detach(ifp); 852 853 vge_freemem(sc); 854 855 bus_space_unmap(sc->vge_btag, sc->vge_bhandle, sc->vge_bsize); 856 return (0); 857} 858 859int 860vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 861{ 862 struct mbuf *m_new = NULL; 863 struct vge_rx_desc *r; 864 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 865 int i; 866 867 if (m == NULL) { 868 /* Allocate a new mbuf */ 869 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 870 if (m_new == NULL) 871 return (ENOBUFS); 872 873 /* Allocate a cluster */ 874 MCLGET(m_new, M_DONTWAIT); 875 if (!(m_new->m_flags & M_EXT)) { 876 m_freem(m_new); 877 return (ENOBUFS); 878 } 879 880 m = m_new; 881 } else 882 m->m_data = m->m_ext.ext_buf; 883 884 m->m_len = m->m_pkthdr.len = MCLBYTES; 885 /* Fix-up alignment so payload is doubleword-aligned */ 886 /* XXX m_adj(m, ETHER_ALIGN); */ 887 888 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m, BUS_DMA_NOWAIT)) 889 return (ENOBUFS); 890 891 if (rxmap->dm_nsegs > 1) 892 goto out; 893 894 /* Map the segments into RX descriptors */ 895 r = &sc->vge_ldata.vge_rx_list[idx]; 896 897 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 898 printf("%s: tried to map a busy RX descriptor\n", 899 sc->vge_dev.dv_xname); 900 goto out; 901 } 902 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 903 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 904 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 905 r->vge_sts = htole32(0); 906 r->vge_ctl = htole32(0); 907 908 /* 909 * Note: the manual fails to document the fact that for 910 * proper operation, the driver needs to replenish the RX 911 * DMA ring 4 descriptors at a time (rather than one at a 912 * time, like most chips). We can allocate the new buffers 913 * but we should not set the OWN bits until we're ready 914 * to hand back 4 of them in one shot. 915 */ 916#define VGE_RXCHUNK 4 917 sc->vge_rx_consumed++; 918 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 919 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 920 sc->vge_ldata.vge_rx_list[i].vge_sts |= 921 htole32(VGE_RDSTS_OWN); 922 sc->vge_rx_consumed = 0; 923 } 924 925 sc->vge_ldata.vge_rx_mbuf[idx] = m; 926 927 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 928 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 929 930 return (0); 931out: 932 DPRINTF(("vge_newbuf: out of memory\n")); 933 if (m_new != NULL) 934 m_freem(m_new); 935 return (ENOMEM); 936} 937 938int 939vge_tx_list_init(struct vge_softc *sc) 940{ 941 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 942 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 943 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 944 945 bus_dmamap_sync(sc->sc_dmat, 946 sc->vge_ldata.vge_tx_list_map, 0, 947 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 948 BUS_DMASYNC_PREWRITE); 949 sc->vge_ldata.vge_tx_prodidx = 0; 950 sc->vge_ldata.vge_tx_considx = 0; 951 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 952 953 return (0); 954} 955 956/* Init RX descriptors and allocate mbufs with vge_newbuf() 957 * A ring is used, and last descriptor points to first. */ 958int 959vge_rx_list_init(struct vge_softc *sc) 960{ 961 int i; 962 963 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 964 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 965 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 966 967 sc->vge_rx_consumed = 0; 968 969 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 970 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 971 return (ENOBUFS); 972 } 973 974 /* Flush the RX descriptors */ 975 976 bus_dmamap_sync(sc->sc_dmat, 977 sc->vge_ldata.vge_rx_list_map, 978 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 979 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 980 981 sc->vge_ldata.vge_rx_prodidx = 0; 982 sc->vge_rx_consumed = 0; 983 sc->vge_head = sc->vge_tail = NULL; 984 985 return (0); 986} 987 988/* 989 * RX handler. We support the reception of jumbo frames that have 990 * been fragmented across multiple 2K mbuf cluster buffers. 991 */ 992void 993vge_rxeof(struct vge_softc *sc) 994{ 995 struct mbuf *m; 996 struct ifnet *ifp; 997 int i, total_len; 998 int lim = 0; 999 struct vge_rx_desc *cur_rx; 1000 u_int32_t rxstat, rxctl; 1001 1002 ifp = &sc->arpcom.ac_if; 1003 i = sc->vge_ldata.vge_rx_prodidx; 1004 1005 /* Invalidate the descriptor memory */ 1006 1007 bus_dmamap_sync(sc->sc_dmat, 1008 sc->vge_ldata.vge_rx_list_map, 1009 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1010 BUS_DMASYNC_POSTREAD); 1011 1012 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1013 struct mbuf *m0 = NULL; 1014 1015 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1016 m = sc->vge_ldata.vge_rx_mbuf[i]; 1017 total_len = VGE_RXBYTES(cur_rx); 1018 rxstat = letoh32(cur_rx->vge_sts); 1019 rxctl = letoh32(cur_rx->vge_ctl); 1020 1021 /* Invalidate the RX mbuf and unload its map */ 1022 1023 bus_dmamap_sync(sc->sc_dmat, 1024 sc->vge_ldata.vge_rx_dmamap[i], 1025 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1026 BUS_DMASYNC_POSTWRITE); 1027 bus_dmamap_unload(sc->sc_dmat, 1028 sc->vge_ldata.vge_rx_dmamap[i]); 1029 1030 /* 1031 * If the 'start of frame' bit is set, this indicates 1032 * either the first fragment in a multi-fragment receive, 1033 * or an intermediate fragment. Either way, we want to 1034 * accumulate the buffers. 1035 */ 1036 if (rxstat & VGE_RXPKT_SOF) { 1037 DPRINTF(("vge_rxeof: SOF\n")); 1038 m->m_len = MCLBYTES; 1039 if (sc->vge_head == NULL) 1040 sc->vge_head = sc->vge_tail = m; 1041 else { 1042 m->m_flags &= ~M_PKTHDR; 1043 sc->vge_tail->m_next = m; 1044 sc->vge_tail = m; 1045 } 1046 vge_newbuf(sc, i, NULL); 1047 VGE_RX_DESC_INC(i); 1048 continue; 1049 } 1050 1051 /* 1052 * Bad/error frames will have the RXOK bit cleared. 1053 * However, there's one error case we want to allow: 1054 * if a VLAN tagged frame arrives and the chip can't 1055 * match it against the CAM filter, it considers this 1056 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1057 * We don't want to drop the frame though: our VLAN 1058 * filtering is done in software. 1059 */ 1060 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1061 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1062 ifp->if_ierrors++; 1063 /* 1064 * If this is part of a multi-fragment packet, 1065 * discard all the pieces. 1066 */ 1067 if (sc->vge_head != NULL) { 1068 m_freem(sc->vge_head); 1069 sc->vge_head = sc->vge_tail = NULL; 1070 } 1071 vge_newbuf(sc, i, m); 1072 VGE_RX_DESC_INC(i); 1073 continue; 1074 } 1075 1076 /* 1077 * If allocating a replacement mbuf fails, 1078 * reload the current one. 1079 */ 1080 1081 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1082 if (sc->vge_head != NULL) { 1083 m_freem(sc->vge_head); 1084 sc->vge_head = sc->vge_tail = NULL; 1085 } 1086 1087 m0 = m_devget(mtod(m, char *), 1088 total_len - ETHER_CRC_LEN, ETHER_ALIGN, ifp, NULL); 1089 vge_newbuf(sc, i, m); 1090 if (m0 == NULL) { 1091 ifp->if_ierrors++; 1092 continue; 1093 } 1094 m = m0; 1095 1096 VGE_RX_DESC_INC(i); 1097 continue; 1098 } 1099 1100 VGE_RX_DESC_INC(i); 1101 1102 if (sc->vge_head != NULL) { 1103 m->m_len = total_len % MCLBYTES; 1104 /* 1105 * Special case: if there's 4 bytes or less 1106 * in this buffer, the mbuf can be discarded: 1107 * the last 4 bytes is the CRC, which we don't 1108 * care about anyway. 1109 */ 1110 if (m->m_len <= ETHER_CRC_LEN) { 1111 sc->vge_tail->m_len -= 1112 (ETHER_CRC_LEN - m->m_len); 1113 m_freem(m); 1114 } else { 1115 m->m_len -= ETHER_CRC_LEN; 1116 m->m_flags &= ~M_PKTHDR; 1117 sc->vge_tail->m_next = m; 1118 } 1119 m = sc->vge_head; 1120 sc->vge_head = sc->vge_tail = NULL; 1121 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1122 } else 1123 m->m_pkthdr.len = m->m_len = 1124 (total_len - ETHER_CRC_LEN); 1125 1126#ifdef __STRICT_ALIGNMENT 1127 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1128 total_len); 1129 m->m_data += ETHER_ALIGN; 1130#endif 1131 ifp->if_ipackets++; 1132 m->m_pkthdr.rcvif = ifp; 1133 1134 /* Do RX checksumming */ 1135 1136 /* Check IP header checksum */ 1137 if ((rxctl & VGE_RDCTL_IPPKT) && 1138 (rxctl & VGE_RDCTL_IPCSUMOK)) 1139 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1140 1141 /* Check TCP/UDP checksum */ 1142 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1143 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1144 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1145 1146#if NVLAN > 0 1147 if (rxstat & VGE_RDSTS_VTAG) { 1148 m->m_pkthdr.ether_vtag = swap16(rxctl & VGE_RDCTL_VLANID); 1149 m->m_flags |= M_VLANTAG; 1150 } 1151#endif 1152 1153#if NBPFILTER > 0 1154 if (ifp->if_bpf) 1155 bpf_mtap_ether(ifp->if_bpf, m, BPF_DIRECTION_IN); 1156#endif 1157 ether_input_mbuf(ifp, m); 1158 1159 lim++; 1160 if (lim == VGE_RX_DESC_CNT) 1161 break; 1162 } 1163 1164 /* Flush the RX DMA ring */ 1165 bus_dmamap_sync(sc->sc_dmat, 1166 sc->vge_ldata.vge_rx_list_map, 1167 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1168 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1169 1170 sc->vge_ldata.vge_rx_prodidx = i; 1171 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1172} 1173 1174void 1175vge_txeof(struct vge_softc *sc) 1176{ 1177 struct ifnet *ifp; 1178 u_int32_t txstat; 1179 int idx; 1180 1181 ifp = &sc->arpcom.ac_if; 1182 idx = sc->vge_ldata.vge_tx_considx; 1183 1184 /* Invalidate the TX descriptor list */ 1185 1186 bus_dmamap_sync(sc->sc_dmat, 1187 sc->vge_ldata.vge_tx_list_map, 1188 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1189 BUS_DMASYNC_POSTREAD); 1190 1191 /* Transmitted frames can be now free'd from the TX list */ 1192 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1193 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1194 if (txstat & VGE_TDSTS_OWN) 1195 break; 1196 1197 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1198 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1199 bus_dmamap_unload(sc->sc_dmat, 1200 sc->vge_ldata.vge_tx_dmamap[idx]); 1201 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1202 ifp->if_collisions++; 1203 if (txstat & VGE_TDSTS_TXERR) 1204 ifp->if_oerrors++; 1205 else 1206 ifp->if_opackets++; 1207 1208 sc->vge_ldata.vge_tx_free++; 1209 VGE_TX_DESC_INC(idx); 1210 } 1211 1212 /* No changes made to the TX ring, so no flush needed */ 1213 1214 if (idx != sc->vge_ldata.vge_tx_considx) { 1215 sc->vge_ldata.vge_tx_considx = idx; 1216 ifp->if_flags &= ~IFF_OACTIVE; 1217 ifp->if_timer = 0; 1218 } 1219 1220 /* 1221 * If not all descriptors have been released reaped yet, 1222 * reload the timer so that we will eventually get another 1223 * interrupt that will cause us to re-enter this routine. 1224 * This is done in case the transmitter has gone idle. 1225 */ 1226 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1227 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1228} 1229 1230void 1231vge_tick(void *xsc) 1232{ 1233 struct vge_softc *sc = xsc; 1234 struct ifnet *ifp = &sc->arpcom.ac_if; 1235 struct mii_data *mii = &sc->sc_mii; 1236 int s; 1237 1238 s = splnet(); 1239 1240 mii_tick(mii); 1241 1242 if (sc->vge_link) { 1243 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1244 sc->vge_link = 0; 1245 ifp->if_link_state = LINK_STATE_DOWN; 1246 if_link_state_change(ifp); 1247 } 1248 } else { 1249 if (mii->mii_media_status & IFM_ACTIVE && 1250 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1251 sc->vge_link = 1; 1252 if (mii->mii_media_status & IFM_FDX) 1253 ifp->if_link_state = LINK_STATE_FULL_DUPLEX; 1254 else 1255 ifp->if_link_state = LINK_STATE_HALF_DUPLEX; 1256 if_link_state_change(ifp); 1257 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1258 vge_start(ifp); 1259 } 1260 } 1261 timeout_add_sec(&sc->timer_handle, 1); 1262 splx(s); 1263} 1264 1265int 1266vge_intr(void *arg) 1267{ 1268 struct vge_softc *sc = arg; 1269 struct ifnet *ifp; 1270 u_int32_t status; 1271 int claimed = 0; 1272 1273 ifp = &sc->arpcom.ac_if; 1274 1275 if (!(ifp->if_flags & IFF_UP)) 1276 return 0; 1277 1278 /* Disable interrupts */ 1279 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1280 1281 for (;;) { 1282 status = CSR_READ_4(sc, VGE_ISR); 1283 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1284 1285 /* If the card has gone away the read returns 0xffffffff. */ 1286 if (status == 0xFFFFFFFF) 1287 break; 1288 1289 if (status) { 1290 CSR_WRITE_4(sc, VGE_ISR, status); 1291 } 1292 1293 if ((status & VGE_INTRS) == 0) 1294 break; 1295 1296 claimed = 1; 1297 1298 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1299 vge_rxeof(sc); 1300 1301 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1302 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1303 vge_rxeof(sc); 1304 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1305 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1306 } 1307 1308 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1309 vge_txeof(sc); 1310 1311 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1312 DPRINTFN(2, ("DMA_STALL\n")); 1313 vge_init(ifp); 1314 } 1315 1316 if (status & VGE_ISR_LINKSTS) { 1317 timeout_del(&sc->timer_handle); 1318 vge_tick(sc); 1319 } 1320 } 1321 1322 /* Re-enable interrupts */ 1323 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1324 1325 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1326 vge_start(ifp); 1327 1328 return (claimed); 1329} 1330 1331/* 1332 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1333 * the descriptors. 1334 */ 1335int 1336vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1337{ 1338 struct ifnet *ifp = &sc->arpcom.ac_if; 1339 bus_dmamap_t txmap; 1340 struct vge_tx_desc *d = NULL; 1341 struct vge_tx_frag *f; 1342 struct mbuf *mnew = NULL; 1343 int error, frag; 1344 u_int32_t vge_flags; 1345 1346 vge_flags = 0; 1347 1348 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1349 vge_flags |= VGE_TDCTL_IPCSUM; 1350 if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1351 vge_flags |= VGE_TDCTL_TCPCSUM; 1352 if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1353 vge_flags |= VGE_TDCTL_UDPCSUM; 1354 1355 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1356repack: 1357 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1358 m_head, BUS_DMA_NOWAIT); 1359 if (error) { 1360 printf("%s: can't map mbuf (error %d)\n", 1361 sc->vge_dev.dv_xname, error); 1362 return (ENOBUFS); 1363 } 1364 1365 d = &sc->vge_ldata.vge_tx_list[idx]; 1366 /* If owned by chip, fail */ 1367 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1368 return (ENOBUFS); 1369 1370 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1371 /* Check if we have used all 7 fragments. */ 1372 if (frag == VGE_TX_FRAGS) 1373 break; 1374 f = &d->vge_frag[frag]; 1375 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1376 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1377 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1378 } 1379 1380 /* 1381 * We used up all 7 fragments! Now what we have to do is 1382 * copy the data into a mbuf cluster and map that. 1383 */ 1384 if (frag == VGE_TX_FRAGS) { 1385 MGETHDR(mnew, M_DONTWAIT, MT_DATA); 1386 if (mnew == NULL) 1387 return (ENOBUFS); 1388 1389 if (m_head->m_pkthdr.len > MHLEN) { 1390 MCLGET(mnew, M_DONTWAIT); 1391 if (!(mnew->m_flags & M_EXT)) { 1392 m_freem(mnew); 1393 return (ENOBUFS); 1394 } 1395 } 1396 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1397 mtod(mnew, caddr_t)); 1398 mnew->m_pkthdr.len = mnew->m_len = m_head->m_pkthdr.len; 1399 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1400 m_freem(m_head); 1401 m_head = mnew; 1402 goto repack; 1403 } 1404 1405 /* This chip does not do auto-padding */ 1406 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1407 f = &d->vge_frag[frag]; 1408 1409 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1410 m_head->m_pkthdr.len)); 1411 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1412 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1413 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1414 frag++; 1415 } 1416 /* For some reason, we need to tell the card fragment + 1 */ 1417 frag++; 1418 1419 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1420 BUS_DMASYNC_PREWRITE); 1421 1422 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1423 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1424 1425 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1426 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1427 1428#if NVLAN > 0 1429 /* Set up hardware VLAN tagging. */ 1430 if (m_head->m_flags & M_VLANTAG) { 1431 d->vge_ctl |= htole32(m_head->m_pkthdr.ether_vtag | 1432 VGE_TDCTL_VTAG); 1433 } 1434#endif 1435 1436 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1437 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1438 sc->vge_ldata.vge_tx_free--; 1439 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1440 1441 idx++; 1442 if (mnew == NULL) { 1443 /* if mbuf is coalesced, it is already dequeued */ 1444 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1445 } 1446 return (0); 1447} 1448 1449/* 1450 * Main transmit routine. 1451 */ 1452void 1453vge_start(struct ifnet *ifp) 1454{ 1455 struct vge_softc *sc; 1456 struct mbuf *m_head = NULL; 1457 int idx, pidx = 0; 1458 1459 sc = ifp->if_softc; 1460 1461 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1462 return; 1463 1464 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1465 return; 1466 1467 idx = sc->vge_ldata.vge_tx_prodidx; 1468 1469 pidx = idx - 1; 1470 if (pidx < 0) 1471 pidx = VGE_TX_DESC_CNT - 1; 1472 1473 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1474 IFQ_POLL(&ifp->if_snd, m_head); 1475 if (m_head == NULL) 1476 break; 1477 1478 /* 1479 * If there's a BPF listener, bounce a copy of this frame 1480 * to him. 1481 */ 1482#if NBPFILTER > 0 1483 if (ifp->if_bpf) 1484 bpf_mtap_ether(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1485#endif 1486 1487 if (vge_encap(sc, m_head, idx)) { 1488 ifp->if_flags |= IFF_OACTIVE; 1489 break; 1490 } 1491 1492 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1493 htole16(VGE_TXDESC_Q); 1494 1495 pidx = idx; 1496 VGE_TX_DESC_INC(idx); 1497 } 1498 1499 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1500 return; 1501 } 1502 1503 /* Flush the TX descriptors */ 1504 1505 bus_dmamap_sync(sc->sc_dmat, 1506 sc->vge_ldata.vge_tx_list_map, 1507 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1508 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1509 1510 /* Issue a transmit command. */ 1511 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1512 1513 sc->vge_ldata.vge_tx_prodidx = idx; 1514 1515 /* 1516 * Use the countdown timer for interrupt moderation. 1517 * 'TX done' interrupts are disabled. Instead, we reset the 1518 * countdown timer, which will begin counting until it hits 1519 * the value in the SSTIMER register, and then trigger an 1520 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1521 * the timer count is reloaded. Only when the transmitter 1522 * is idle will the timer hit 0 and an interrupt fire. 1523 */ 1524 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1525 1526 /* 1527 * Set a timeout in case the chip goes out to lunch. 1528 */ 1529 ifp->if_timer = 5; 1530} 1531 1532int 1533vge_init(struct ifnet *ifp) 1534{ 1535 struct vge_softc *sc = ifp->if_softc; 1536 int i; 1537 1538 /* 1539 * Cancel pending I/O and free all RX/TX buffers. 1540 */ 1541 vge_stop(sc); 1542 vge_reset(sc); 1543 1544 /* Initialize RX descriptors list */ 1545 if (vge_rx_list_init(sc) == ENOBUFS) { 1546 printf("%s: init failed: no memory for RX buffers\n", 1547 sc->vge_dev.dv_xname); 1548 vge_stop(sc); 1549 return (ENOBUFS); 1550 } 1551 /* Initialize TX descriptors */ 1552 if (vge_tx_list_init(sc) == ENOBUFS) { 1553 printf("%s: init failed: no memory for TX buffers\n", 1554 sc->vge_dev.dv_xname); 1555 vge_stop(sc); 1556 return (ENOBUFS); 1557 } 1558 1559 /* Set our station address */ 1560 for (i = 0; i < ETHER_ADDR_LEN; i++) 1561 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1562 1563 /* Set receive FIFO threshold */ 1564 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR); 1565 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES); 1566 1567 if (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) { 1568 /* 1569 * Allow transmission and reception of VLAN tagged 1570 * frames. 1571 */ 1572 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_VTAGOPT); 1573 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_VTAG_OPT2); 1574 } 1575 1576 /* Set DMA burst length */ 1577 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1578 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1579 1580 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1581 1582 /* Set collision backoff algorithm */ 1583 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1584 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1585 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1586 1587 /* Disable LPSEL field in priority resolution */ 1588 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1589 1590 /* 1591 * Load the addresses of the DMA queues into the chip. 1592 * Note that we only use one transmit queue. 1593 */ 1594 1595 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1596 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1597 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1598 1599 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1600 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1601 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1602 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1603 1604 /* Enable and wake up the RX descriptor queue */ 1605 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1606 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1607 1608 /* Enable the TX descriptor queue */ 1609 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1610 1611 /* Set up the receive filter -- allow large frames for VLANs. */ 1612 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1613 1614 /* If we want promiscuous mode, set the allframes bit. */ 1615 if (ifp->if_flags & IFF_PROMISC) { 1616 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1617 } 1618 1619 /* Set capture broadcast bit to capture broadcast frames. */ 1620 if (ifp->if_flags & IFF_BROADCAST) { 1621 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1622 } 1623 1624 /* Set multicast bit to capture multicast frames. */ 1625 if (ifp->if_flags & IFF_MULTICAST) { 1626 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1627 } 1628 1629 /* Init the cam filter. */ 1630 vge_cam_clear(sc); 1631 1632 /* Init the multicast filter. */ 1633 vge_setmulti(sc); 1634 1635 /* Enable flow control */ 1636 1637 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1638 1639 /* Enable jumbo frame reception (if desired) */ 1640 1641 /* Start the MAC. */ 1642 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1643 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1644 CSR_WRITE_1(sc, VGE_CRS0, 1645 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1646 1647 /* 1648 * Configure one-shot timer for microsecond 1649 * resulution and load it for 500 usecs. 1650 */ 1651 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1652 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1653 1654 /* 1655 * Configure interrupt moderation for receive. Enable 1656 * the holdoff counter and load it, and set the RX 1657 * suppression count to the number of descriptors we 1658 * want to allow before triggering an interrupt. 1659 * The holdoff timer is in units of 20 usecs. 1660 */ 1661 1662#ifdef notyet 1663 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1664 /* Select the interrupt holdoff timer page. */ 1665 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1666 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1667 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1668 1669 /* Enable use of the holdoff timer. */ 1670 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1671 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1672 1673 /* Select the RX suppression threshold page. */ 1674 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1675 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1676 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1677 1678 /* Restore the page select bits. */ 1679 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1680 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1681#endif 1682 1683 /* 1684 * Enable interrupts. 1685 */ 1686 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1687 CSR_WRITE_4(sc, VGE_ISR, 0); 1688 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1689 1690 /* Restore BMCR state */ 1691 mii_mediachg(&sc->sc_mii); 1692 1693 ifp->if_flags |= IFF_RUNNING; 1694 ifp->if_flags &= ~IFF_OACTIVE; 1695 1696 sc->vge_if_flags = 0; 1697 sc->vge_link = 0; 1698 1699 if (!timeout_pending(&sc->timer_handle)) 1700 timeout_add_sec(&sc->timer_handle, 1); 1701 1702 return (0); 1703} 1704 1705/* 1706 * Set media options. 1707 */ 1708int 1709vge_ifmedia_upd(struct ifnet *ifp) 1710{ 1711 struct vge_softc *sc = ifp->if_softc; 1712 1713 return (mii_mediachg(&sc->sc_mii)); 1714} 1715 1716/* 1717 * Report current media status. 1718 */ 1719void 1720vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1721{ 1722 struct vge_softc *sc = ifp->if_softc; 1723 1724 mii_pollstat(&sc->sc_mii); 1725 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1726 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1727} 1728 1729void 1730vge_miibus_statchg(struct device *dev) 1731{ 1732 struct vge_softc *sc = (struct vge_softc *)dev; 1733 struct mii_data *mii; 1734 struct ifmedia_entry *ife; 1735 1736 mii = &sc->sc_mii; 1737 ife = mii->mii_media.ifm_cur; 1738 1739 /* 1740 * If the user manually selects a media mode, we need to turn 1741 * on the forced MAC mode bit in the DIAGCTL register. If the 1742 * user happens to choose a full duplex mode, we also need to 1743 * set the 'force full duplex' bit. This applies only to 1744 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1745 * mode is disabled, and in 1000baseT mode, full duplex is 1746 * always implied, so we turn on the forced mode bit but leave 1747 * the FDX bit cleared. 1748 */ 1749 1750 switch (IFM_SUBTYPE(ife->ifm_media)) { 1751 case IFM_AUTO: 1752 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1753 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1754 break; 1755 case IFM_1000_T: 1756 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1757 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1758 break; 1759 case IFM_100_TX: 1760 case IFM_10_T: 1761 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1762 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1763 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1764 } else { 1765 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1766 } 1767 break; 1768 default: 1769 printf("%s: unknown media type: %x\n", 1770 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1771 break; 1772 } 1773} 1774 1775int 1776vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1777{ 1778 struct vge_softc *sc = ifp->if_softc; 1779 struct ifaddr *ifa = (struct ifaddr *) data; 1780 struct ifreq *ifr = (struct ifreq *) data; 1781 int s, error = 0; 1782 1783 s = splnet(); 1784 1785 switch (command) { 1786 case SIOCSIFADDR: 1787 ifp->if_flags |= IFF_UP; 1788 switch (ifa->ifa_addr->sa_family) { 1789#ifdef INET 1790 case AF_INET: 1791 vge_init(ifp); 1792 arp_ifinit(&sc->arpcom, ifa); 1793 break; 1794#endif 1795 default: 1796 vge_init(ifp); 1797 break; 1798 } 1799 break; 1800 1801 case SIOCSIFFLAGS: 1802 if (ifp->if_flags & IFF_UP) { 1803 if (ifp->if_flags & IFF_RUNNING && 1804 ifp->if_flags & IFF_PROMISC && 1805 !(sc->vge_if_flags & IFF_PROMISC)) { 1806 CSR_SETBIT_1(sc, VGE_RXCTL, 1807 VGE_RXCTL_RX_PROMISC); 1808 vge_setmulti(sc); 1809 } else if (ifp->if_flags & IFF_RUNNING && 1810 !(ifp->if_flags & IFF_PROMISC) && 1811 sc->vge_if_flags & IFF_PROMISC) { 1812 CSR_CLRBIT_1(sc, VGE_RXCTL, 1813 VGE_RXCTL_RX_PROMISC); 1814 vge_setmulti(sc); 1815 } else 1816 vge_init(ifp); 1817 } else { 1818 if (ifp->if_flags & IFF_RUNNING) 1819 vge_stop(sc); 1820 } 1821 sc->vge_if_flags = ifp->if_flags; 1822 break; 1823 1824 case SIOCGIFMEDIA: 1825 case SIOCSIFMEDIA: 1826 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1827 break; 1828 1829 default: 1830 error = ether_ioctl(ifp, &sc->arpcom, command, data); 1831 } 1832 1833 if (error == ENETRESET) { 1834 if (ifp->if_flags & IFF_RUNNING) 1835 vge_setmulti(sc); 1836 error = 0; 1837 } 1838 1839 splx(s); 1840 return (error); 1841} 1842 1843void 1844vge_watchdog(struct ifnet *ifp) 1845{ 1846 struct vge_softc *sc = ifp->if_softc; 1847 int s; 1848 1849 s = splnet(); 1850 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1851 ifp->if_oerrors++; 1852 1853 vge_txeof(sc); 1854 vge_rxeof(sc); 1855 1856 vge_init(ifp); 1857 1858 splx(s); 1859} 1860 1861/* 1862 * Stop the adapter and free any mbufs allocated to the 1863 * RX and TX lists. 1864 */ 1865void 1866vge_stop(struct vge_softc *sc) 1867{ 1868 int i; 1869 struct ifnet *ifp; 1870 1871 ifp = &sc->arpcom.ac_if; 1872 ifp->if_timer = 0; 1873 1874 timeout_del(&sc->timer_handle); 1875 1876 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1877 1878 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1879 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1880 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1881 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1882 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1883 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1884 1885 if (sc->vge_head != NULL) { 1886 m_freem(sc->vge_head); 1887 sc->vge_head = sc->vge_tail = NULL; 1888 } 1889 1890 /* Free the TX list buffers. */ 1891 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1892 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1893 bus_dmamap_unload(sc->sc_dmat, 1894 sc->vge_ldata.vge_tx_dmamap[i]); 1895 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1896 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1897 } 1898 } 1899 1900 /* Free the RX list buffers. */ 1901 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1902 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1903 bus_dmamap_unload(sc->sc_dmat, 1904 sc->vge_ldata.vge_rx_dmamap[i]); 1905 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1906 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1907 } 1908 } 1909} 1910