if_vge.c revision 1.28
1/* $OpenBSD: if_vge.c,v 1.28 2006/10/03 19:46:08 damien Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/timeout.h> 96#include <sys/socket.h> 97 98#include <net/if.h> 99#include <net/if_dl.h> 100#include <net/if_media.h> 101 102#ifdef INET 103#include <netinet/in.h> 104#include <netinet/in_systm.h> 105#include <netinet/in_var.h> 106#include <netinet/ip.h> 107#include <netinet/if_ether.h> 108#endif 109 110#if NVLAN > 0 111#include <net/if_types.h> 112#include <net/if_vlan_var.h> 113#endif 114 115#if NBPFILTER > 0 116#include <net/bpf.h> 117#endif 118 119#include <dev/mii/mii.h> 120#include <dev/mii/miivar.h> 121 122#include <dev/pci/pcireg.h> 123#include <dev/pci/pcivar.h> 124#include <dev/pci/pcidevs.h> 125 126#include <dev/pci/if_vgereg.h> 127#include <dev/pci/if_vgevar.h> 128 129int vge_probe (struct device *, void *, void *); 130void vge_attach (struct device *, struct device *, void *); 131 132int vge_encap (struct vge_softc *, struct mbuf *, int); 133 134int vge_allocmem (struct vge_softc *); 135int vge_newbuf (struct vge_softc *, int, struct mbuf *); 136int vge_rx_list_init (struct vge_softc *); 137int vge_tx_list_init (struct vge_softc *); 138void vge_rxeof (struct vge_softc *); 139void vge_txeof (struct vge_softc *); 140int vge_intr (void *); 141void vge_tick (void *); 142void vge_start (struct ifnet *); 143int vge_ioctl (struct ifnet *, u_long, caddr_t); 144int vge_init (struct ifnet *); 145void vge_stop (struct vge_softc *); 146void vge_watchdog (struct ifnet *); 147int vge_ifmedia_upd (struct ifnet *); 148void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 149 150#ifdef VGE_EEPROM 151void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 152#endif 153void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 154 155void vge_miipoll_start (struct vge_softc *); 156void vge_miipoll_stop (struct vge_softc *); 157int vge_miibus_readreg (struct device *, int, int); 158void vge_miibus_writereg (struct device *, int, int, int); 159void vge_miibus_statchg (struct device *); 160 161void vge_cam_clear (struct vge_softc *); 162int vge_cam_set (struct vge_softc *, uint8_t *); 163void vge_setmulti (struct vge_softc *); 164void vge_reset (struct vge_softc *); 165 166struct cfattach vge_ca = { 167 sizeof(struct vge_softc), vge_probe, vge_attach 168}; 169 170struct cfdriver vge_cd = { 171 0, "vge", DV_IFNET 172}; 173 174#define VGE_PCI_LOIO 0x10 175#define VGE_PCI_LOMEM 0x14 176 177int vge_debug = 0; 178#define DPRINTF(x) if (vge_debug) printf x 179#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 180 181const struct pci_matchid vge_devices[] = { 182 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 183}; 184 185#ifdef VGE_EEPROM 186/* 187 * Read a word of data stored in the EEPROM at address 'addr.' 188 */ 189void 190vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 191{ 192 int i; 193 u_int16_t word = 0; 194 195 /* 196 * Enter EEPROM embedded programming mode. In order to 197 * access the EEPROM at all, we first have to set the 198 * EELOAD bit in the CHIPCFG2 register. 199 */ 200 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 201 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 202 203 /* Select the address of the word we want to read */ 204 CSR_WRITE_1(sc, VGE_EEADDR, addr); 205 206 /* Issue read command */ 207 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 208 209 /* Wait for the done bit to be set. */ 210 for (i = 0; i < VGE_TIMEOUT; i++) { 211 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 212 break; 213 } 214 215 if (i == VGE_TIMEOUT) { 216 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 217 *dest = 0; 218 return; 219 } 220 221 /* Read the result */ 222 word = CSR_READ_2(sc, VGE_EERDDAT); 223 224 /* Turn off EEPROM access mode. */ 225 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 226 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 227 228 *dest = word; 229} 230#endif 231 232/* 233 * Read a sequence of words from the EEPROM. 234 */ 235void 236vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 237 int swap) 238{ 239 int i; 240#ifdef VGE_EEPROM 241 u_int16_t word = 0, *ptr; 242 243 for (i = 0; i < cnt; i++) { 244 vge_eeprom_getword(sc, off + i, &word); 245 ptr = (u_int16_t *)(dest + (i * 2)); 246 if (swap) 247 *ptr = ntohs(word); 248 else 249 *ptr = word; 250 } 251#else 252 for (i = 0; i < ETHER_ADDR_LEN; i++) 253 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 254#endif 255} 256 257void 258vge_miipoll_stop(struct vge_softc *sc) 259{ 260 int i; 261 262 CSR_WRITE_1(sc, VGE_MIICMD, 0); 263 264 for (i = 0; i < VGE_TIMEOUT; i++) { 265 DELAY(1); 266 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 267 break; 268 } 269 270 if (i == VGE_TIMEOUT) 271 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 272} 273 274void 275vge_miipoll_start(struct vge_softc *sc) 276{ 277 int i; 278 279 /* First, make sure we're idle. */ 280 281 CSR_WRITE_1(sc, VGE_MIICMD, 0); 282 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 283 284 for (i = 0; i < VGE_TIMEOUT; i++) { 285 DELAY(1); 286 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 287 break; 288 } 289 290 if (i == VGE_TIMEOUT) { 291 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 292 return; 293 } 294 295 /* Now enable auto poll mode. */ 296 297 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 298 299 /* And make sure it started. */ 300 301 for (i = 0; i < VGE_TIMEOUT; i++) { 302 DELAY(1); 303 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 304 break; 305 } 306 307 if (i == VGE_TIMEOUT) 308 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 309} 310 311int 312vge_miibus_readreg(struct device *dev, int phy, int reg) 313{ 314 struct vge_softc *sc = (struct vge_softc *)dev; 315 int i, s; 316 u_int16_t rval = 0; 317 318 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 319 return(0); 320 321 s = splnet(); 322 323 vge_miipoll_stop(sc); 324 325 /* Specify the register we want to read. */ 326 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 327 328 /* Issue read command. */ 329 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 330 331 /* Wait for the read command bit to self-clear. */ 332 for (i = 0; i < VGE_TIMEOUT; i++) { 333 DELAY(1); 334 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 335 break; 336 } 337 338 if (i == VGE_TIMEOUT) 339 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 340 else 341 rval = CSR_READ_2(sc, VGE_MIIDATA); 342 343 vge_miipoll_start(sc); 344 splx(s); 345 346 return (rval); 347} 348 349void 350vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 351{ 352 struct vge_softc *sc = (struct vge_softc *)dev; 353 int i, s; 354 355 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 356 return; 357 358 s = splnet(); 359 vge_miipoll_stop(sc); 360 361 /* Specify the register we want to write. */ 362 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 363 364 /* Specify the data we want to write. */ 365 CSR_WRITE_2(sc, VGE_MIIDATA, data); 366 367 /* Issue write command. */ 368 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 369 370 /* Wait for the write command bit to self-clear. */ 371 for (i = 0; i < VGE_TIMEOUT; i++) { 372 DELAY(1); 373 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 374 break; 375 } 376 377 if (i == VGE_TIMEOUT) { 378 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 379 } 380 381 vge_miipoll_start(sc); 382 splx(s); 383} 384 385void 386vge_cam_clear(struct vge_softc *sc) 387{ 388 int i; 389 390 /* 391 * Turn off all the mask bits. This tells the chip 392 * that none of the entries in the CAM filter are valid. 393 * desired entries will be enabled as we fill the filter in. 394 */ 395 396 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 397 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 398 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 399 for (i = 0; i < 8; i++) 400 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 401 402 /* Clear the VLAN filter too. */ 403 404 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 405 for (i = 0; i < 8; i++) 406 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 407 408 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 409 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 410 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 411 412 sc->vge_camidx = 0; 413} 414 415int 416vge_cam_set(struct vge_softc *sc, uint8_t *addr) 417{ 418 int i, error = 0; 419 420 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 421 return(ENOSPC); 422 423 /* Select the CAM data page. */ 424 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 426 427 /* Set the filter entry we want to update and enable writing. */ 428 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 429 430 /* Write the address to the CAM registers */ 431 for (i = 0; i < ETHER_ADDR_LEN; i++) 432 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 433 434 /* Issue a write command. */ 435 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 436 437 /* Wake for it to clear. */ 438 for (i = 0; i < VGE_TIMEOUT; i++) { 439 DELAY(1); 440 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 441 break; 442 } 443 444 if (i == VGE_TIMEOUT) { 445 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 446 error = EIO; 447 goto fail; 448 } 449 450 /* Select the CAM mask page. */ 451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 453 454 /* Set the mask bit that enables this filter. */ 455 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 456 1<<(sc->vge_camidx & 7)); 457 458 sc->vge_camidx++; 459 460fail: 461 /* Turn off access to CAM. */ 462 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 463 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 464 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 465 466 return (error); 467} 468 469/* 470 * Program the multicast filter. We use the 64-entry CAM filter 471 * for perfect filtering. If there's more than 64 multicast addresses, 472 * we use the hash filter instead. 473 */ 474void 475vge_setmulti(struct vge_softc *sc) 476{ 477 struct arpcom *ac = &sc->arpcom; 478 struct ifnet *ifp = &ac->ac_if; 479 struct ether_multi *enm; 480 struct ether_multistep step; 481 int error; 482 u_int32_t h = 0, hashes[2] = { 0, 0 }; 483 484 /* First, zot all the multicast entries. */ 485 vge_cam_clear(sc); 486 CSR_WRITE_4(sc, VGE_MAR0, 0); 487 CSR_WRITE_4(sc, VGE_MAR1, 0); 488 ifp->if_flags &= ~IFF_ALLMULTI; 489 490 /* 491 * If the user wants allmulti or promisc mode, enable reception 492 * of all multicast frames. 493 */ 494 if (ifp->if_flags & IFF_PROMISC) { 495allmulti: 496 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 497 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 498 ifp->if_flags |= IFF_ALLMULTI; 499 return; 500 } 501 502 /* Now program new ones */ 503 ETHER_FIRST_MULTI(step, ac, enm); 504 while (enm != NULL) { 505 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 506 goto allmulti; 507 508 error = vge_cam_set(sc, enm->enm_addrlo); 509 if (error) 510 break; 511 512 ETHER_NEXT_MULTI(step, enm); 513 } 514 515 /* If there were too many addresses, use the hash filter. */ 516 if (error) { 517 vge_cam_clear(sc); 518 519 ETHER_FIRST_MULTI(step, ac, enm); 520 while (enm != NULL) { 521 h = ether_crc32_be(enm->enm_addrlo, 522 ETHER_ADDR_LEN) >> 26; 523 hashes[h >> 5] |= 1 << (h & 0x1f); 524 525 ETHER_NEXT_MULTI(step, enm); 526 } 527 528 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 529 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 530 } 531} 532 533void 534vge_reset(struct vge_softc *sc) 535{ 536 int i; 537 538 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 539 540 for (i = 0; i < VGE_TIMEOUT; i++) { 541 DELAY(5); 542 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 543 break; 544 } 545 546 if (i == VGE_TIMEOUT) { 547 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 548 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 549 DELAY(2000); 550 } 551 552 DELAY(5000); 553 554 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 555 556 for (i = 0; i < VGE_TIMEOUT; i++) { 557 DELAY(5); 558 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 559 break; 560 } 561 562 if (i == VGE_TIMEOUT) { 563 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 564 return; 565 } 566 567 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 568} 569 570/* 571 * Probe for a VIA gigabit chip. Check the PCI vendor and device 572 * IDs against our list and return a device name if we find a match. 573 */ 574int 575vge_probe(struct device *dev, void *match, void *aux) 576{ 577 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 578 sizeof(vge_devices)/sizeof(vge_devices[0]))); 579} 580 581/* 582 * Allocate memory for RX/TX rings 583 */ 584int 585vge_allocmem(struct vge_softc *sc) 586{ 587 int nseg, rseg; 588 int i, error; 589 590 nseg = 32; 591 592 /* Allocate DMA'able memory for the TX ring */ 593 594 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 595 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 596 &sc->vge_ldata.vge_tx_list_map); 597 if (error) 598 return (ENOMEM); 599 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 600 ETHER_ALIGN, 0, 601 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 602 if (error) { 603 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 604 return (ENOMEM); 605 } 606 607 /* Load the map for the TX ring. */ 608 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 609 1, VGE_TX_LIST_SZ, 610 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 611 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 612 if (error) { 613 printf("%s: can't map TX dma buffers\n", 614 sc->vge_dev.dv_xname); 615 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 616 return (ENOMEM); 617 } 618 619 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 620 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 621 if (error) { 622 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 623 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 624 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 625 VGE_TX_LIST_SZ); 626 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 627 return (ENOMEM); 628 } 629 630 /* Create DMA maps for TX buffers */ 631 632 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 633 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 634 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 635 &sc->vge_ldata.vge_tx_dmamap[i]); 636 if (error) { 637 printf("%s: can't create DMA map for TX\n", 638 sc->vge_dev.dv_xname); 639 return (ENOMEM); 640 } 641 } 642 643 /* Allocate DMA'able memory for the RX ring */ 644 645 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 646 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 647 &sc->vge_ldata.vge_rx_list_map); 648 if (error) 649 return (ENOMEM); 650 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 651 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 652 if (error) { 653 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 654 return (ENOMEM); 655 } 656 657 /* Load the map for the RX ring. */ 658 659 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 660 1, VGE_RX_LIST_SZ, 661 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 662 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 663 if (error) { 664 printf("%s: can't map RX dma buffers\n", 665 sc->vge_dev.dv_xname); 666 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 667 return (ENOMEM); 668 } 669 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 670 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 671 if (error) { 672 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 673 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 674 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 675 VGE_RX_LIST_SZ); 676 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 677 return (ENOMEM); 678 } 679 680 /* Create DMA maps for RX buffers */ 681 682 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 683 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 684 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 685 &sc->vge_ldata.vge_rx_dmamap[i]); 686 if (error) { 687 printf("%s: can't create DMA map for RX\n", 688 sc->vge_dev.dv_xname); 689 return (ENOMEM); 690 } 691 } 692 693 return (0); 694} 695 696/* 697 * Attach the interface. Allocate softc structures, do ifmedia 698 * setup and ethernet/BPF attach. 699 */ 700void 701vge_attach(struct device *parent, struct device *self, void *aux) 702{ 703 u_char eaddr[ETHER_ADDR_LEN]; 704 u_int16_t as[3]; 705 struct vge_softc *sc = (struct vge_softc *)self; 706 struct pci_attach_args *pa = aux; 707 pci_chipset_tag_t pc = pa->pa_pc; 708 pci_intr_handle_t ih; 709 const char *intrstr = NULL; 710 struct ifnet *ifp; 711 int error = 0, i; 712 bus_size_t iosize; 713 714 /* 715 * Map control/status registers. 716 */ 717 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 718 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 719 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 720 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 721 printf(": can't map mem or i/o space\n"); 722 return; 723 } 724 } 725 726 /* Allocate interrupt */ 727 if (pci_intr_map(pa, &ih)) { 728 printf(": couldn't map interrupt\n"); 729 return; 730 } 731 intrstr = pci_intr_string(pc, ih); 732 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 733 sc->vge_dev.dv_xname); 734 if (sc->vge_intrhand == NULL) { 735 printf(": couldn't establish interrupt"); 736 if (intrstr != NULL) 737 printf(" at %s", intrstr); 738 return; 739 } 740 printf(": %s", intrstr); 741 742 sc->sc_dmat = pa->pa_dmat; 743 744 /* Reset the adapter. */ 745 vge_reset(sc); 746 747 /* 748 * Get station address from the EEPROM. 749 */ 750 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 751 for (i = 0; i < 3; i++) { 752 eaddr[(i * 2) + 0] = as[i] & 0xff; 753 eaddr[(i * 2) + 1] = as[i] >> 8; 754 } 755 756 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 757 758 printf(", address %s\n", 759 ether_sprintf(sc->arpcom.ac_enaddr)); 760 761 error = vge_allocmem(sc); 762 763 if (error) 764 return; 765 766 ifp = &sc->arpcom.ac_if; 767 ifp->if_softc = sc; 768 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 769 ifp->if_ioctl = vge_ioctl; 770 ifp->if_start = vge_start; 771 ifp->if_watchdog = vge_watchdog; 772 ifp->if_init = vge_init; 773 ifp->if_baudrate = 1000000000; 774#ifdef VGE_JUMBO 775 ifp->if_hardmtu = VGE_JUMBO_MTU; 776#endif 777 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 778 IFQ_SET_READY(&ifp->if_snd); 779 780 ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_CSUM_IPv4 | 781 IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 782 783#ifdef VGE_VLAN 784 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 785#endif 786 787 /* Set interface name */ 788 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 789 790 /* Do MII setup */ 791 sc->sc_mii.mii_ifp = ifp; 792 sc->sc_mii.mii_readreg = vge_miibus_readreg; 793 sc->sc_mii.mii_writereg = vge_miibus_writereg; 794 sc->sc_mii.mii_statchg = vge_miibus_statchg; 795 ifmedia_init(&sc->sc_mii.mii_media, 0, 796 vge_ifmedia_upd, vge_ifmedia_sts); 797 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 798 MII_OFFSET_ANY, 0); 799 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 800 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 801 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 802 0, NULL); 803 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 804 } else 805 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 806 807 timeout_set(&sc->timer_handle, vge_tick, sc); 808 809 /* 810 * Call MI attach routine. 811 */ 812 if_attach(ifp); 813 ether_ifattach(ifp); 814} 815 816int 817vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 818{ 819 struct mbuf *m_new = NULL; 820 struct vge_rx_desc *r; 821 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 822 int i; 823 824 if (m == NULL) { 825 /* Allocate a new mbuf */ 826 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 827 if (m_new == NULL) 828 return (ENOBUFS); 829 830 /* Allocate a cluster */ 831 MCLGET(m_new, M_DONTWAIT); 832 if (!(m_new->m_flags & M_EXT)) { 833 m_freem(m_new); 834 return (ENOBUFS); 835 } 836 } else 837 m_new->m_data = m_new->m_ext.ext_buf; 838 839 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 840 /* Fix-up alignment so payload is doubleword-aligned */ 841 /* XXX m_adj(m_new, ETHER_ALIGN); */ 842 843 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT)) 844 return (ENOBUFS); 845 846 if (rxmap->dm_nsegs > 1) 847 goto out; 848 849 /* Map the segments into RX descriptors */ 850 r = &sc->vge_ldata.vge_rx_list[idx]; 851 852 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 853 printf("%s: tried to map a busy RX descriptor\n", 854 sc->vge_dev.dv_xname); 855 goto out; 856 } 857 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 858 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 859 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 860 r->vge_sts = htole32(0); 861 r->vge_ctl = htole32(0); 862 863 /* 864 * Note: the manual fails to document the fact that for 865 * proper operation, the driver needs to replenish the RX 866 * DMA ring 4 descriptors at a time (rather than one at a 867 * time, like most chips). We can allocate the new buffers 868 * but we should not set the OWN bits until we're ready 869 * to hand back 4 of them in one shot. 870 */ 871#define VGE_RXCHUNK 4 872 sc->vge_rx_consumed++; 873 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 874 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 875 sc->vge_ldata.vge_rx_list[i].vge_sts |= 876 htole32(VGE_RDSTS_OWN); 877 sc->vge_rx_consumed = 0; 878 } 879 880 sc->vge_ldata.vge_rx_mbuf[idx] = m_new; 881 882 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 883 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 884 885 return (0); 886out: 887 DPRINTF(("vge_newbuf: out of memory\n")); 888 if (m_new != NULL) 889 m_freem(m_new); 890 return (ENOMEM); 891} 892 893int 894vge_tx_list_init(struct vge_softc *sc) 895{ 896 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 897 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 898 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 899 900 bus_dmamap_sync(sc->sc_dmat, 901 sc->vge_ldata.vge_tx_list_map, 0, 902 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 903 BUS_DMASYNC_PREWRITE); 904 sc->vge_ldata.vge_tx_prodidx = 0; 905 sc->vge_ldata.vge_tx_considx = 0; 906 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 907 908 return (0); 909} 910 911/* Init RX descriptors and allocate mbufs with vge_newbuf() 912 * A ring is used, and last descriptor points to first. */ 913int 914vge_rx_list_init(struct vge_softc *sc) 915{ 916 int i; 917 918 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 919 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 920 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 921 922 sc->vge_rx_consumed = 0; 923 924 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 925 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 926 return (ENOBUFS); 927 } 928 929 /* Flush the RX descriptors */ 930 931 bus_dmamap_sync(sc->sc_dmat, 932 sc->vge_ldata.vge_rx_list_map, 933 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 934 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 935 936 sc->vge_ldata.vge_rx_prodidx = 0; 937 sc->vge_rx_consumed = 0; 938 sc->vge_head = sc->vge_tail = NULL; 939 940 return (0); 941} 942 943/* 944 * RX handler. We support the reception of jumbo frames that have 945 * been fragmented across multiple 2K mbuf cluster buffers. 946 */ 947void 948vge_rxeof(struct vge_softc *sc) 949{ 950 struct mbuf *m; 951 struct ifnet *ifp; 952 int i, total_len; 953 int lim = 0; 954 struct vge_rx_desc *cur_rx; 955 u_int32_t rxstat, rxctl; 956 957 ifp = &sc->arpcom.ac_if; 958 i = sc->vge_ldata.vge_rx_prodidx; 959 960 /* Invalidate the descriptor memory */ 961 962 bus_dmamap_sync(sc->sc_dmat, 963 sc->vge_ldata.vge_rx_list_map, 964 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 965 BUS_DMASYNC_POSTREAD); 966 967 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 968 struct mbuf *m0 = NULL; 969 970 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 971 m = sc->vge_ldata.vge_rx_mbuf[i]; 972 total_len = VGE_RXBYTES(cur_rx); 973 rxstat = letoh32(cur_rx->vge_sts); 974 rxctl = letoh32(cur_rx->vge_ctl); 975 976 /* Invalidate the RX mbuf and unload its map */ 977 978 bus_dmamap_sync(sc->sc_dmat, 979 sc->vge_ldata.vge_rx_dmamap[i], 980 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 981 BUS_DMASYNC_POSTWRITE); 982 bus_dmamap_unload(sc->sc_dmat, 983 sc->vge_ldata.vge_rx_dmamap[i]); 984 985 /* 986 * If the 'start of frame' bit is set, this indicates 987 * either the first fragment in a multi-fragment receive, 988 * or an intermediate fragment. Either way, we want to 989 * accumulate the buffers. 990 */ 991 if (rxstat & VGE_RXPKT_SOF) { 992 DPRINTF(("vge_rxeof: SOF\n")); 993 m->m_len = MCLBYTES; 994 if (sc->vge_head == NULL) 995 sc->vge_head = sc->vge_tail = m; 996 else { 997 m->m_flags &= ~M_PKTHDR; 998 sc->vge_tail->m_next = m; 999 sc->vge_tail = m; 1000 } 1001 vge_newbuf(sc, i, NULL); 1002 VGE_RX_DESC_INC(i); 1003 continue; 1004 } 1005 1006 /* 1007 * Bad/error frames will have the RXOK bit cleared. 1008 * However, there's one error case we want to allow: 1009 * if a VLAN tagged frame arrives and the chip can't 1010 * match it against the CAM filter, it considers this 1011 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1012 * We don't want to drop the frame though: our VLAN 1013 * filtering is done in software. 1014 */ 1015 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1016 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1017 ifp->if_ierrors++; 1018 /* 1019 * If this is part of a multi-fragment packet, 1020 * discard all the pieces. 1021 */ 1022 if (sc->vge_head != NULL) { 1023 m_freem(sc->vge_head); 1024 sc->vge_head = sc->vge_tail = NULL; 1025 } 1026 vge_newbuf(sc, i, m); 1027 VGE_RX_DESC_INC(i); 1028 continue; 1029 } 1030 1031 /* 1032 * If allocating a replacement mbuf fails, 1033 * reload the current one. 1034 */ 1035 1036 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1037 if (sc->vge_head != NULL) { 1038 m_freem(sc->vge_head); 1039 sc->vge_head = sc->vge_tail = NULL; 1040 } 1041 1042 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1043 total_len - ETHER_CRC_LEN + ETHER_ALIGN, 1044 0, ifp, NULL); 1045 vge_newbuf(sc, i, m); 1046 if (m0 == NULL) { 1047 ifp->if_ierrors++; 1048 continue; 1049 } 1050 m_adj(m0, ETHER_ALIGN); 1051 m = m0; 1052 1053 VGE_RX_DESC_INC(i); 1054 continue; 1055 } 1056 1057 VGE_RX_DESC_INC(i); 1058 1059 if (sc->vge_head != NULL) { 1060 m->m_len = total_len % MCLBYTES; 1061 /* 1062 * Special case: if there's 4 bytes or less 1063 * in this buffer, the mbuf can be discarded: 1064 * the last 4 bytes is the CRC, which we don't 1065 * care about anyway. 1066 */ 1067 if (m->m_len <= ETHER_CRC_LEN) { 1068 sc->vge_tail->m_len -= 1069 (ETHER_CRC_LEN - m->m_len); 1070 m_freem(m); 1071 } else { 1072 m->m_len -= ETHER_CRC_LEN; 1073 m->m_flags &= ~M_PKTHDR; 1074 sc->vge_tail->m_next = m; 1075 } 1076 m = sc->vge_head; 1077 sc->vge_head = sc->vge_tail = NULL; 1078 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1079 } else 1080 m->m_pkthdr.len = m->m_len = 1081 (total_len - ETHER_CRC_LEN); 1082 1083#ifdef __STRICT_ALIGNMENT 1084 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1085 total_len); 1086 m->m_data += ETHER_ALIGN; 1087#endif 1088 ifp->if_ipackets++; 1089 m->m_pkthdr.rcvif = ifp; 1090 1091 /* Do RX checksumming */ 1092 1093 /* Check IP header checksum */ 1094 if ((rxctl & VGE_RDCTL_IPPKT) && 1095 (rxctl & VGE_RDCTL_IPCSUMOK)) 1096 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1097 1098 /* Check TCP/UDP checksum */ 1099 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1100 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1101 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1102 1103#if NBPFILTER > 0 1104 if (ifp->if_bpf) 1105 bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); 1106#endif 1107 ether_input_mbuf(ifp, m); 1108 1109 lim++; 1110 if (lim == VGE_RX_DESC_CNT) 1111 break; 1112 } 1113 1114 /* Flush the RX DMA ring */ 1115 bus_dmamap_sync(sc->sc_dmat, 1116 sc->vge_ldata.vge_rx_list_map, 1117 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1118 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1119 1120 sc->vge_ldata.vge_rx_prodidx = i; 1121 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1122} 1123 1124void 1125vge_txeof(struct vge_softc *sc) 1126{ 1127 struct ifnet *ifp; 1128 u_int32_t txstat; 1129 int idx; 1130 1131 ifp = &sc->arpcom.ac_if; 1132 idx = sc->vge_ldata.vge_tx_considx; 1133 1134 /* Invalidate the TX descriptor list */ 1135 1136 bus_dmamap_sync(sc->sc_dmat, 1137 sc->vge_ldata.vge_tx_list_map, 1138 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1139 BUS_DMASYNC_POSTREAD); 1140 1141 /* Transmitted frames can be now free'd from the TX list */ 1142 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1143 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1144 if (txstat & VGE_TDSTS_OWN) 1145 break; 1146 1147 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1148 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1149 bus_dmamap_unload(sc->sc_dmat, 1150 sc->vge_ldata.vge_tx_dmamap[idx]); 1151 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1152 ifp->if_collisions++; 1153 if (txstat & VGE_TDSTS_TXERR) 1154 ifp->if_oerrors++; 1155 else 1156 ifp->if_opackets++; 1157 1158 sc->vge_ldata.vge_tx_free++; 1159 VGE_TX_DESC_INC(idx); 1160 } 1161 1162 /* No changes made to the TX ring, so no flush needed */ 1163 1164 if (idx != sc->vge_ldata.vge_tx_considx) { 1165 sc->vge_ldata.vge_tx_considx = idx; 1166 ifp->if_flags &= ~IFF_OACTIVE; 1167 ifp->if_timer = 0; 1168 } 1169 1170 /* 1171 * If not all descriptors have been released reaped yet, 1172 * reload the timer so that we will eventually get another 1173 * interrupt that will cause us to re-enter this routine. 1174 * This is done in case the transmitter has gone idle. 1175 */ 1176 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1177 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1178} 1179 1180void 1181vge_tick(void *xsc) 1182{ 1183 struct vge_softc *sc = xsc; 1184 struct ifnet *ifp = &sc->arpcom.ac_if; 1185 struct mii_data *mii = &sc->sc_mii; 1186 int s; 1187 1188 s = splnet(); 1189 1190 mii_tick(mii); 1191 1192 if (sc->vge_link) { 1193 if (!(mii->mii_media_status & IFM_ACTIVE)) 1194 sc->vge_link = 0; 1195 ifp->if_link_state = LINK_STATE_DOWN; 1196 if_link_state_change(ifp); 1197 } else { 1198 if (mii->mii_media_status & IFM_ACTIVE && 1199 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1200 sc->vge_link = 1; 1201 ifp->if_link_state = LINK_STATE_UP; 1202 if_link_state_change(ifp); 1203 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1204 vge_start(ifp); 1205 } 1206 } 1207 timeout_add(&sc->timer_handle, hz); 1208 splx(s); 1209} 1210 1211int 1212vge_intr(void *arg) 1213{ 1214 struct vge_softc *sc = arg; 1215 struct ifnet *ifp; 1216 u_int32_t status; 1217 int claimed = 0; 1218 1219 ifp = &sc->arpcom.ac_if; 1220 1221 if (!(ifp->if_flags & IFF_UP)) 1222 return 0; 1223 1224 /* Disable interrupts */ 1225 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1226 1227 for (;;) { 1228 status = CSR_READ_4(sc, VGE_ISR); 1229 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1230 1231 /* If the card has gone away the read returns 0xffffffff. */ 1232 if (status == 0xFFFFFFFF) 1233 break; 1234 1235 if (status) { 1236 CSR_WRITE_4(sc, VGE_ISR, status); 1237 } 1238 1239 if ((status & VGE_INTRS) == 0) 1240 break; 1241 1242 claimed = 1; 1243 1244 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1245 vge_rxeof(sc); 1246 1247 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1248 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1249 vge_rxeof(sc); 1250 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1251 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1252 } 1253 1254 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1255 vge_txeof(sc); 1256 1257 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1258 DPRINTFN(2, ("DMA_STALL\n")); 1259 vge_init(ifp); 1260 } 1261 1262 if (status & VGE_ISR_LINKSTS) { 1263 timeout_del(&sc->timer_handle); 1264 vge_tick(sc); 1265 } 1266 } 1267 1268 /* Re-enable interrupts */ 1269 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1270 1271 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1272 vge_start(ifp); 1273 1274 return (claimed); 1275} 1276 1277/* 1278 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1279 * the descriptors. 1280 */ 1281int 1282vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1283{ 1284 bus_dmamap_t txmap; 1285 struct vge_tx_desc *d = NULL; 1286 struct vge_tx_frag *f; 1287 int error, frag; 1288 u_int32_t vge_flags; 1289 1290 vge_flags = 0; 1291 1292 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1293 vge_flags |= VGE_TDCTL_IPCSUM; 1294 if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1295 vge_flags |= VGE_TDCTL_TCPCSUM; 1296 if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1297 vge_flags |= VGE_TDCTL_UDPCSUM; 1298 1299 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1300repack: 1301 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1302 m_head, BUS_DMA_NOWAIT); 1303 if (error) { 1304 printf("%s: can't map mbuf (error %d)\n", 1305 sc->vge_dev.dv_xname, error); 1306 return (ENOBUFS); 1307 } 1308 1309 d = &sc->vge_ldata.vge_tx_list[idx]; 1310 /* If owned by chip, fail */ 1311 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1312 return (ENOBUFS); 1313 1314 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1315 /* Check if we have used all 7 fragments. */ 1316 if (frag == VGE_TX_FRAGS) 1317 break; 1318 f = &d->vge_frag[frag]; 1319 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1320 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1321 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1322 } 1323 1324 /* 1325 * We used up all 7 fragments! Now what we have to do is 1326 * copy the data into a mbuf cluster and map that. 1327 */ 1328 if (frag == VGE_TX_FRAGS) { 1329 struct mbuf *m = NULL; 1330 1331 MGETHDR(m, M_DONTWAIT, MT_DATA); 1332 if (m == NULL) { 1333 m_freem(m_head); 1334 return (ENOBUFS); 1335 } 1336 if (m_head->m_pkthdr.len > MHLEN) { 1337 MCLGET(m, M_DONTWAIT); 1338 if (!(m->m_flags & M_EXT)) { 1339 m_freem(m); 1340 m_freem(m_head); 1341 return (ENOBUFS); 1342 } 1343 } 1344 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1345 mtod(m, caddr_t)); 1346 m->m_pkthdr.len = m->m_len = m_head->m_pkthdr.len; 1347 m_freem(m_head); 1348 m_head = m; 1349 goto repack; 1350 } 1351 1352 /* This chip does not do auto-padding */ 1353 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1354 f = &d->vge_frag[frag]; 1355 1356 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1357 m_head->m_pkthdr.len)); 1358 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1359 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1360 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1361 frag++; 1362 } 1363 /* For some reason, we need to tell the card fragment + 1 */ 1364 frag++; 1365 1366 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1367 BUS_DMASYNC_PREWRITE); 1368 1369 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1370 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1371 1372 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1373 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1374 1375 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1376 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1377 sc->vge_ldata.vge_tx_free--; 1378 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1379 1380 /* 1381 * Set up hardware VLAN tagging. 1382 */ 1383#ifdef VGE_VLAN 1384 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1385 if (mtag != NULL) 1386 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1387 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1388#endif 1389 1390 idx++; 1391 1392 return (0); 1393} 1394 1395/* 1396 * Main transmit routine. 1397 */ 1398void 1399vge_start(struct ifnet *ifp) 1400{ 1401 struct vge_softc *sc; 1402 struct mbuf *m_head = NULL; 1403 int idx, pidx = 0; 1404 1405 sc = ifp->if_softc; 1406 1407 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1408 return; 1409 1410 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1411 return; 1412 1413 idx = sc->vge_ldata.vge_tx_prodidx; 1414 1415 pidx = idx - 1; 1416 if (pidx < 0) 1417 pidx = VGE_TX_DESC_CNT - 1; 1418 1419 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1420 IFQ_POLL(&ifp->if_snd, m_head); 1421 if (m_head == NULL) 1422 break; 1423 1424 /* 1425 * If there's a BPF listener, bounce a copy of this frame 1426 * to him. 1427 */ 1428#if NBPFILTER > 0 1429 if (ifp->if_bpf) 1430 bpf_mtap(ifp->if_bpf, m_head, BPF_DIRECTION_OUT); 1431#endif 1432 1433 if (vge_encap(sc, m_head, idx)) { 1434 ifp->if_flags |= IFF_OACTIVE; 1435 break; 1436 } 1437 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1438 1439 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1440 htole16(VGE_TXDESC_Q); 1441 1442 pidx = idx; 1443 VGE_TX_DESC_INC(idx); 1444 } 1445 1446 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1447 return; 1448 } 1449 1450 /* Flush the TX descriptors */ 1451 1452 bus_dmamap_sync(sc->sc_dmat, 1453 sc->vge_ldata.vge_tx_list_map, 1454 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1455 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1456 1457 /* Issue a transmit command. */ 1458 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1459 1460 sc->vge_ldata.vge_tx_prodidx = idx; 1461 1462 /* 1463 * Use the countdown timer for interrupt moderation. 1464 * 'TX done' interrupts are disabled. Instead, we reset the 1465 * countdown timer, which will begin counting until it hits 1466 * the value in the SSTIMER register, and then trigger an 1467 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1468 * the timer count is reloaded. Only when the transmitter 1469 * is idle will the timer hit 0 and an interrupt fire. 1470 */ 1471 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1472 1473 /* 1474 * Set a timeout in case the chip goes out to lunch. 1475 */ 1476 ifp->if_timer = 5; 1477} 1478 1479int 1480vge_init(struct ifnet *ifp) 1481{ 1482 struct vge_softc *sc = ifp->if_softc; 1483 int i; 1484 1485 /* 1486 * Cancel pending I/O and free all RX/TX buffers. 1487 */ 1488 vge_stop(sc); 1489 vge_reset(sc); 1490 1491 /* Initialize RX descriptors list */ 1492 if (vge_rx_list_init(sc) == ENOBUFS) { 1493 printf("%s: init failed: no memory for RX buffers\n", 1494 sc->vge_dev.dv_xname); 1495 vge_stop(sc); 1496 return (ENOBUFS); 1497 } 1498 /* Initialize TX descriptors */ 1499 if (vge_tx_list_init(sc) == ENOBUFS) { 1500 printf("%s: init failed: no memory for TX buffers\n", 1501 sc->vge_dev.dv_xname); 1502 vge_stop(sc); 1503 return (ENOBUFS); 1504 } 1505 1506 /* Set our station address */ 1507 for (i = 0; i < ETHER_ADDR_LEN; i++) 1508 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1509 1510 /* 1511 * Set receive FIFO threshold. Also allow transmission and 1512 * reception of VLAN tagged frames. 1513 */ 1514 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1515 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1516 1517 /* Set DMA burst length */ 1518 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1519 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1520 1521 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1522 1523 /* Set collision backoff algorithm */ 1524 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1525 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1526 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1527 1528 /* Disable LPSEL field in priority resolution */ 1529 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1530 1531 /* 1532 * Load the addresses of the DMA queues into the chip. 1533 * Note that we only use one transmit queue. 1534 */ 1535 1536 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1537 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1538 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1539 1540 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1541 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1542 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1543 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1544 1545 /* Enable and wake up the RX descriptor queue */ 1546 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1547 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1548 1549 /* Enable the TX descriptor queue */ 1550 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1551 1552 /* Set up the receive filter -- allow large frames for VLANs. */ 1553 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1554 1555 /* If we want promiscuous mode, set the allframes bit. */ 1556 if (ifp->if_flags & IFF_PROMISC) { 1557 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1558 } 1559 1560 /* Set capture broadcast bit to capture broadcast frames. */ 1561 if (ifp->if_flags & IFF_BROADCAST) { 1562 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1563 } 1564 1565 /* Set multicast bit to capture multicast frames. */ 1566 if (ifp->if_flags & IFF_MULTICAST) { 1567 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1568 } 1569 1570 /* Init the cam filter. */ 1571 vge_cam_clear(sc); 1572 1573 /* Init the multicast filter. */ 1574 vge_setmulti(sc); 1575 1576 /* Enable flow control */ 1577 1578 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1579 1580 /* Enable jumbo frame reception (if desired) */ 1581 1582 /* Start the MAC. */ 1583 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1584 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1585 CSR_WRITE_1(sc, VGE_CRS0, 1586 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1587 1588 /* 1589 * Configure one-shot timer for microsecond 1590 * resulution and load it for 500 usecs. 1591 */ 1592 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1593 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1594 1595 /* 1596 * Configure interrupt moderation for receive. Enable 1597 * the holdoff counter and load it, and set the RX 1598 * suppression count to the number of descriptors we 1599 * want to allow before triggering an interrupt. 1600 * The holdoff timer is in units of 20 usecs. 1601 */ 1602 1603#ifdef notyet 1604 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1605 /* Select the interrupt holdoff timer page. */ 1606 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1607 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1608 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1609 1610 /* Enable use of the holdoff timer. */ 1611 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1612 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1613 1614 /* Select the RX suppression threshold page. */ 1615 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1616 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1617 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1618 1619 /* Restore the page select bits. */ 1620 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1621 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1622#endif 1623 1624 /* 1625 * Enable interrupts. 1626 */ 1627 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1628 CSR_WRITE_4(sc, VGE_ISR, 0); 1629 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1630 1631 /* Restore BMCR state */ 1632 mii_mediachg(&sc->sc_mii); 1633 1634 ifp->if_flags |= IFF_RUNNING; 1635 ifp->if_flags &= ~IFF_OACTIVE; 1636 1637 sc->vge_if_flags = 0; 1638 sc->vge_link = 0; 1639 1640 if (!timeout_pending(&sc->timer_handle)) 1641 timeout_add(&sc->timer_handle, hz); 1642 1643 return (0); 1644} 1645 1646/* 1647 * Set media options. 1648 */ 1649int 1650vge_ifmedia_upd(struct ifnet *ifp) 1651{ 1652 struct vge_softc *sc = ifp->if_softc; 1653 1654 return (mii_mediachg(&sc->sc_mii)); 1655} 1656 1657/* 1658 * Report current media status. 1659 */ 1660void 1661vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1662{ 1663 struct vge_softc *sc = ifp->if_softc; 1664 1665 mii_pollstat(&sc->sc_mii); 1666 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1667 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1668} 1669 1670void 1671vge_miibus_statchg(struct device *dev) 1672{ 1673 struct vge_softc *sc = (struct vge_softc *)dev; 1674 struct mii_data *mii; 1675 struct ifmedia_entry *ife; 1676 1677 mii = &sc->sc_mii; 1678 ife = mii->mii_media.ifm_cur; 1679 1680 /* 1681 * If the user manually selects a media mode, we need to turn 1682 * on the forced MAC mode bit in the DIAGCTL register. If the 1683 * user happens to choose a full duplex mode, we also need to 1684 * set the 'force full duplex' bit. This applies only to 1685 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1686 * mode is disabled, and in 1000baseT mode, full duplex is 1687 * always implied, so we turn on the forced mode bit but leave 1688 * the FDX bit cleared. 1689 */ 1690 1691 switch (IFM_SUBTYPE(ife->ifm_media)) { 1692 case IFM_AUTO: 1693 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1694 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1695 break; 1696 case IFM_1000_T: 1697 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1698 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1699 break; 1700 case IFM_100_TX: 1701 case IFM_10_T: 1702 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1703 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1704 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1705 } else { 1706 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1707 } 1708 break; 1709 default: 1710 printf("%s: unknown media type: %x\n", 1711 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1712 break; 1713 } 1714} 1715 1716int 1717vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1718{ 1719 struct vge_softc *sc = ifp->if_softc; 1720 struct ifreq *ifr = (struct ifreq *) data; 1721 struct ifaddr *ifa = (struct ifaddr *) data; 1722 int s, error = 0; 1723 1724 s = splnet(); 1725 1726 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1727 splx(s); 1728 return (error); 1729 } 1730 1731 switch (command) { 1732 case SIOCSIFADDR: 1733 ifp->if_flags |= IFF_UP; 1734 switch (ifa->ifa_addr->sa_family) { 1735#ifdef INET 1736 case AF_INET: 1737 vge_init(ifp); 1738 arp_ifinit(&sc->arpcom, ifa); 1739 break; 1740#endif 1741 default: 1742 vge_init(ifp); 1743 break; 1744 } 1745 break; 1746 case SIOCSIFMTU: 1747 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ifp->if_hardmtu) 1748 error = EINVAL; 1749 else if (ifp->if_mtu != ifr->ifr_mtu) 1750 ifp->if_mtu = ifr->ifr_mtu; 1751 break; 1752 case SIOCSIFFLAGS: 1753 if (ifp->if_flags & IFF_UP) { 1754 if (ifp->if_flags & IFF_RUNNING && 1755 ifp->if_flags & IFF_PROMISC && 1756 !(sc->vge_if_flags & IFF_PROMISC)) { 1757 CSR_SETBIT_1(sc, VGE_RXCTL, 1758 VGE_RXCTL_RX_PROMISC); 1759 vge_setmulti(sc); 1760 } else if (ifp->if_flags & IFF_RUNNING && 1761 !(ifp->if_flags & IFF_PROMISC) && 1762 sc->vge_if_flags & IFF_PROMISC) { 1763 CSR_CLRBIT_1(sc, VGE_RXCTL, 1764 VGE_RXCTL_RX_PROMISC); 1765 vge_setmulti(sc); 1766 } else 1767 vge_init(ifp); 1768 } else { 1769 if (ifp->if_flags & IFF_RUNNING) 1770 vge_stop(sc); 1771 } 1772 sc->vge_if_flags = ifp->if_flags; 1773 break; 1774 case SIOCADDMULTI: 1775 case SIOCDELMULTI: 1776 error = (command == SIOCADDMULTI) ? 1777 ether_addmulti(ifr, &sc->arpcom) : 1778 ether_delmulti(ifr, &sc->arpcom); 1779 1780 if (error == ENETRESET) { 1781 if (ifp->if_flags & IFF_RUNNING) 1782 vge_setmulti(sc); 1783 error = 0; 1784 } 1785 break; 1786 case SIOCGIFMEDIA: 1787 case SIOCSIFMEDIA: 1788 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1789 break; 1790 default: 1791 error = ENOTTY; 1792 break; 1793 } 1794 1795 splx(s); 1796 return (error); 1797} 1798 1799void 1800vge_watchdog(struct ifnet *ifp) 1801{ 1802 struct vge_softc *sc = ifp->if_softc; 1803 int s; 1804 1805 s = splnet(); 1806 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1807 ifp->if_oerrors++; 1808 1809 vge_txeof(sc); 1810 vge_rxeof(sc); 1811 1812 vge_init(ifp); 1813 1814 splx(s); 1815} 1816 1817/* 1818 * Stop the adapter and free any mbufs allocated to the 1819 * RX and TX lists. 1820 */ 1821void 1822vge_stop(struct vge_softc *sc) 1823{ 1824 int i; 1825 struct ifnet *ifp; 1826 1827 ifp = &sc->arpcom.ac_if; 1828 ifp->if_timer = 0; 1829 if (timeout_pending(&sc->timer_handle)) 1830 timeout_del(&sc->timer_handle); 1831 1832 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1833 1834 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1835 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1836 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1837 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1838 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1839 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1840 1841 if (sc->vge_head != NULL) { 1842 m_freem(sc->vge_head); 1843 sc->vge_head = sc->vge_tail = NULL; 1844 } 1845 1846 /* Free the TX list buffers. */ 1847 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1848 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1849 bus_dmamap_unload(sc->sc_dmat, 1850 sc->vge_ldata.vge_tx_dmamap[i]); 1851 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1852 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1853 } 1854 } 1855 1856 /* Free the RX list buffers. */ 1857 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1858 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1859 bus_dmamap_unload(sc->sc_dmat, 1860 sc->vge_ldata.vge_rx_dmamap[i]); 1861 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1862 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1863 } 1864 } 1865} 1866