if_vge.c revision 1.18
1/* $OpenBSD: if_vge.c,v 1.18 2005/11/07 02:57:45 brad Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#ifdef INET 102#include <netinet/in.h> 103#include <netinet/in_systm.h> 104#include <netinet/in_var.h> 105#include <netinet/ip.h> 106#include <netinet/if_ether.h> 107#endif 108 109#if NVLAN > 0 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112#endif 113 114#if NBPFILTER > 0 115#include <net/bpf.h> 116#endif 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123#include <dev/pci/pcidevs.h> 124 125#include <dev/pci/if_vgereg.h> 126#include <dev/pci/if_vgevar.h> 127 128int vge_probe (struct device *, void *, void *); 129void vge_attach (struct device *, struct device *, void *); 130 131int vge_encap (struct vge_softc *, struct mbuf *, int); 132 133int vge_allocmem (struct vge_softc *); 134int vge_newbuf (struct vge_softc *, int, struct mbuf *); 135int vge_rx_list_init (struct vge_softc *); 136int vge_tx_list_init (struct vge_softc *); 137void vge_rxeof (struct vge_softc *); 138void vge_txeof (struct vge_softc *); 139int vge_intr (void *); 140void vge_tick (void *); 141void vge_start (struct ifnet *); 142int vge_ioctl (struct ifnet *, u_long, caddr_t); 143int vge_init (struct ifnet *); 144void vge_stop (struct vge_softc *); 145void vge_watchdog (struct ifnet *); 146int vge_ifmedia_upd (struct ifnet *); 147void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 149#ifdef VGE_EEPROM 150void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 151#endif 152void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 153 154void vge_miipoll_start (struct vge_softc *); 155void vge_miipoll_stop (struct vge_softc *); 156int vge_miibus_readreg (struct device *, int, int); 157void vge_miibus_writereg (struct device *, int, int, int); 158void vge_miibus_statchg (struct device *); 159 160void vge_cam_clear (struct vge_softc *); 161int vge_cam_set (struct vge_softc *, uint8_t *); 162void vge_setmulti (struct vge_softc *); 163void vge_reset (struct vge_softc *); 164 165struct cfattach vge_ca = { 166 sizeof(struct vge_softc), vge_probe, vge_attach 167}; 168 169struct cfdriver vge_cd = { 170 0, "vge", DV_IFNET 171}; 172 173#define VGE_PCI_LOIO 0x10 174#define VGE_PCI_LOMEM 0x14 175 176int vge_debug = 0; 177#define DPRINTF(x) if (vge_debug) printf x 178#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 179 180const struct pci_matchid vge_devices[] = { 181 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 182}; 183 184#ifdef VGE_EEPROM 185/* 186 * Read a word of data stored in the EEPROM at address 'addr.' 187 */ 188void 189vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 190{ 191 register int i; 192 u_int16_t word = 0; 193 194 /* 195 * Enter EEPROM embedded programming mode. In order to 196 * access the EEPROM at all, we first have to set the 197 * EELOAD bit in the CHIPCFG2 register. 198 */ 199 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 200 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 201 202 /* Select the address of the word we want to read */ 203 CSR_WRITE_1(sc, VGE_EEADDR, addr); 204 205 /* Issue read command */ 206 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 207 208 /* Wait for the done bit to be set. */ 209 for (i = 0; i < VGE_TIMEOUT; i++) { 210 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 211 break; 212 } 213 214 if (i == VGE_TIMEOUT) { 215 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 216 *dest = 0; 217 return; 218 } 219 220 /* Read the result */ 221 word = CSR_READ_2(sc, VGE_EERDDAT); 222 223 /* Turn off EEPROM access mode. */ 224 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 225 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 226 227 *dest = word; 228} 229#endif 230 231/* 232 * Read a sequence of words from the EEPROM. 233 */ 234void 235vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 236 int swap) 237{ 238 int i; 239#ifdef VGE_EEPROM 240 u_int16_t word = 0, *ptr; 241 242 for (i = 0; i < cnt; i++) { 243 vge_eeprom_getword(sc, off + i, &word); 244 ptr = (u_int16_t *)(dest + (i * 2)); 245 if (swap) 246 *ptr = ntohs(word); 247 else 248 *ptr = word; 249 } 250#else 251 for (i = 0; i < ETHER_ADDR_LEN; i++) 252 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 253#endif 254} 255 256void 257vge_miipoll_stop(struct vge_softc *sc) 258{ 259 int i; 260 261 CSR_WRITE_1(sc, VGE_MIICMD, 0); 262 263 for (i = 0; i < VGE_TIMEOUT; i++) { 264 DELAY(1); 265 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 266 break; 267 } 268 269 if (i == VGE_TIMEOUT) 270 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 271} 272 273void 274vge_miipoll_start(struct vge_softc *sc) 275{ 276 int i; 277 278 /* First, make sure we're idle. */ 279 280 CSR_WRITE_1(sc, VGE_MIICMD, 0); 281 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 282 283 for (i = 0; i < VGE_TIMEOUT; i++) { 284 DELAY(1); 285 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 286 break; 287 } 288 289 if (i == VGE_TIMEOUT) { 290 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 291 return; 292 } 293 294 /* Now enable auto poll mode. */ 295 296 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 297 298 /* And make sure it started. */ 299 300 for (i = 0; i < VGE_TIMEOUT; i++) { 301 DELAY(1); 302 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 303 break; 304 } 305 306 if (i == VGE_TIMEOUT) 307 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 308} 309 310int 311vge_miibus_readreg(struct device *dev, int phy, int reg) 312{ 313 struct vge_softc *sc = (struct vge_softc *)dev; 314 int i, s; 315 u_int16_t rval = 0; 316 317 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 318 return(0); 319 320 s = splnet(); 321 322 vge_miipoll_stop(sc); 323 324 /* Specify the register we want to read. */ 325 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 326 327 /* Issue read command. */ 328 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 329 330 /* Wait for the read command bit to self-clear. */ 331 for (i = 0; i < VGE_TIMEOUT; i++) { 332 DELAY(1); 333 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 334 break; 335 } 336 337 if (i == VGE_TIMEOUT) 338 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 339 else 340 rval = CSR_READ_2(sc, VGE_MIIDATA); 341 342 vge_miipoll_start(sc); 343 splx(s); 344 345 return (rval); 346} 347 348void 349vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 350{ 351 struct vge_softc *sc = (struct vge_softc *)dev; 352 int i, s; 353 354 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 355 return; 356 357 s = splnet(); 358 vge_miipoll_stop(sc); 359 360 /* Specify the register we want to write. */ 361 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 362 363 /* Specify the data we want to write. */ 364 CSR_WRITE_2(sc, VGE_MIIDATA, data); 365 366 /* Issue write command. */ 367 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 368 369 /* Wait for the write command bit to self-clear. */ 370 for (i = 0; i < VGE_TIMEOUT; i++) { 371 DELAY(1); 372 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 373 break; 374 } 375 376 if (i == VGE_TIMEOUT) { 377 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 378 } 379 380 vge_miipoll_start(sc); 381 splx(s); 382} 383 384void 385vge_cam_clear(struct vge_softc *sc) 386{ 387 int i; 388 389 /* 390 * Turn off all the mask bits. This tells the chip 391 * that none of the entries in the CAM filter are valid. 392 * desired entries will be enabled as we fill the filter in. 393 */ 394 395 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 396 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 397 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 398 for (i = 0; i < 8; i++) 399 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 400 401 /* Clear the VLAN filter too. */ 402 403 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 404 for (i = 0; i < 8; i++) 405 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 406 407 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 408 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 409 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 410 411 sc->vge_camidx = 0; 412} 413 414int 415vge_cam_set(struct vge_softc *sc, uint8_t *addr) 416{ 417 int i, error = 0; 418 419 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 420 return(ENOSPC); 421 422 /* Select the CAM data page. */ 423 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 424 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 425 426 /* Set the filter entry we want to update and enable writing. */ 427 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 428 429 /* Write the address to the CAM registers */ 430 for (i = 0; i < ETHER_ADDR_LEN; i++) 431 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 432 433 /* Issue a write command. */ 434 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 435 436 /* Wake for it to clear. */ 437 for (i = 0; i < VGE_TIMEOUT; i++) { 438 DELAY(1); 439 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 440 break; 441 } 442 443 if (i == VGE_TIMEOUT) { 444 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 445 error = EIO; 446 goto fail; 447 } 448 449 /* Select the CAM mask page. */ 450 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 451 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 452 453 /* Set the mask bit that enables this filter. */ 454 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 455 1<<(sc->vge_camidx & 7)); 456 457 sc->vge_camidx++; 458 459fail: 460 /* Turn off access to CAM. */ 461 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 462 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 463 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 464 465 return (error); 466} 467 468/* 469 * Program the multicast filter. We use the 64-entry CAM filter 470 * for perfect filtering. If there's more than 64 multicast addresses, 471 * we use the hash filter instead. 472 */ 473void 474vge_setmulti(struct vge_softc *sc) 475{ 476 struct arpcom *ac = &sc->arpcom; 477 struct ifnet *ifp = &ac->ac_if; 478 struct ether_multi *enm; 479 struct ether_multistep step; 480 int error; 481 u_int32_t h = 0, hashes[2] = { 0, 0 }; 482 483 /* First, zot all the multicast entries. */ 484 vge_cam_clear(sc); 485 CSR_WRITE_4(sc, VGE_MAR0, 0); 486 CSR_WRITE_4(sc, VGE_MAR1, 0); 487 ifp->if_flags &= ~IFF_ALLMULTI; 488 489 /* 490 * If the user wants allmulti or promisc mode, enable reception 491 * of all multicast frames. 492 */ 493 if (ifp->if_flags & IFF_PROMISC) { 494allmulti: 495 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 496 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 497 ifp->if_flags |= IFF_ALLMULTI; 498 return; 499 } 500 501 /* Now program new ones */ 502 ETHER_FIRST_MULTI(step, ac, enm); 503 while (enm != NULL) { 504 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 505 goto allmulti; 506 507 error = vge_cam_set(sc, enm->enm_addrlo); 508 if (error) 509 break; 510 511 ETHER_NEXT_MULTI(step, enm); 512 } 513 514 /* If there were too many addresses, use the hash filter. */ 515 if (error) { 516 vge_cam_clear(sc); 517 518 ETHER_FIRST_MULTI(step, ac, enm); 519 while (enm != NULL) { 520 h = ether_crc32_be(enm->enm_addrlo, 521 ETHER_ADDR_LEN) >> 26; 522 hashes[h >> 5] |= 1 << (h & 0x1f); 523 524 ETHER_NEXT_MULTI(step, enm); 525 } 526 527 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 528 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 529 } 530} 531 532void 533vge_reset(struct vge_softc *sc) 534{ 535 register int i; 536 537 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 538 539 for (i = 0; i < VGE_TIMEOUT; i++) { 540 DELAY(5); 541 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 542 break; 543 } 544 545 if (i == VGE_TIMEOUT) { 546 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 547 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 548 DELAY(2000); 549 } 550 551 DELAY(5000); 552 553 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 554 555 for (i = 0; i < VGE_TIMEOUT; i++) { 556 DELAY(5); 557 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 558 break; 559 } 560 561 if (i == VGE_TIMEOUT) { 562 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 563 return; 564 } 565 566 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 567} 568 569/* 570 * Probe for a VIA gigabit chip. Check the PCI vendor and device 571 * IDs against our list and return a device name if we find a match. 572 */ 573int 574vge_probe(struct device *dev, void *match, void *aux) 575{ 576 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 577 sizeof(vge_devices)/sizeof(vge_devices[0]))); 578} 579 580/* 581 * Allocate memory for RX/TX rings 582 */ 583int 584vge_allocmem(struct vge_softc *sc) 585{ 586 int nseg, rseg; 587 int i, error; 588 589 nseg = 32; 590 591 /* Allocate DMA'able memory for the TX ring */ 592 593 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 594 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 595 &sc->vge_ldata.vge_tx_list_map); 596 if (error) 597 return (ENOMEM); 598 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 599 ETHER_ALIGN, 0, 600 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 601 if (error) { 602 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 603 return (ENOMEM); 604 } 605 606 /* Load the map for the TX ring. */ 607 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 608 1, VGE_TX_LIST_SZ, 609 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 610 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 611 if (error) { 612 printf("%s: can't map TX dma buffers\n", 613 sc->vge_dev.dv_xname); 614 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 615 return (ENOMEM); 616 } 617 618 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 619 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 620 if (error) { 621 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 622 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 623 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 624 VGE_TX_LIST_SZ); 625 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 626 return (ENOMEM); 627 } 628 629 /* Create DMA maps for TX buffers */ 630 631 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 632 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 633 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 634 &sc->vge_ldata.vge_tx_dmamap[i]); 635 if (error) { 636 printf("%s: can't create DMA map for TX\n", 637 sc->vge_dev.dv_xname); 638 return (ENOMEM); 639 } 640 } 641 642 /* Allocate DMA'able memory for the RX ring */ 643 644 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 645 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 646 &sc->vge_ldata.vge_rx_list_map); 647 if (error) 648 return (ENOMEM); 649 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 650 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 651 if (error) { 652 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 653 return (ENOMEM); 654 } 655 656 /* Load the map for the RX ring. */ 657 658 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 659 1, VGE_RX_LIST_SZ, 660 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 661 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 662 if (error) { 663 printf("%s: can't map RX dma buffers\n", 664 sc->vge_dev.dv_xname); 665 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 666 return (ENOMEM); 667 } 668 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 669 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 670 if (error) { 671 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 672 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 673 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 674 VGE_RX_LIST_SZ); 675 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 676 return (ENOMEM); 677 } 678 679 /* Create DMA maps for RX buffers */ 680 681 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 682 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 683 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 684 &sc->vge_ldata.vge_rx_dmamap[i]); 685 if (error) { 686 printf("%s: can't create DMA map for RX\n", 687 sc->vge_dev.dv_xname); 688 return (ENOMEM); 689 } 690 } 691 692 return (0); 693} 694 695/* 696 * Attach the interface. Allocate softc structures, do ifmedia 697 * setup and ethernet/BPF attach. 698 */ 699void 700vge_attach(struct device *parent, struct device *self, void *aux) 701{ 702 u_char eaddr[ETHER_ADDR_LEN]; 703 u_int16_t as[3]; 704 struct vge_softc *sc = (struct vge_softc *)self; 705 struct pci_attach_args *pa = aux; 706 pci_chipset_tag_t pc = pa->pa_pc; 707 pci_intr_handle_t ih; 708 const char *intrstr = NULL; 709 struct ifnet *ifp; 710 int error = 0, i; 711 bus_size_t iosize; 712 pcireg_t command; 713 714 /* 715 * Map control/status registers. 716 */ 717 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 718 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) == 0) { 719 printf(": neither i/o nor mem enabled\n"); 720 return; 721 } 722 723 if (command & PCI_COMMAND_MEM_ENABLE) { 724 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 725 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 726 printf(": can't map mem space\n"); 727 return; 728 } 729 } else { 730 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 731 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 732 printf(": can't map i/o space\n"); 733 return; 734 } 735 } 736 737 /* Allocate interrupt */ 738 if (pci_intr_map(pa, &ih)) { 739 printf(": couldn't map interrupt\n"); 740 return; 741 } 742 intrstr = pci_intr_string(pc, ih); 743 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 744 sc->vge_dev.dv_xname); 745 if (sc->vge_intrhand == NULL) { 746 printf(": couldn't establish interrupt"); 747 if (intrstr != NULL) 748 printf(" at %s", intrstr); 749 return; 750 } 751 printf(": %s", intrstr); 752 753 sc->sc_dmat = pa->pa_dmat; 754 755 /* Reset the adapter. */ 756 vge_reset(sc); 757 758 /* 759 * Get station address from the EEPROM. 760 */ 761 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 762 for (i = 0; i < 3; i++) { 763 eaddr[(i * 2) + 0] = as[i] & 0xff; 764 eaddr[(i * 2) + 1] = as[i] >> 8; 765 } 766 767 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 768 769 printf(", address %s\n", 770 ether_sprintf(sc->arpcom.ac_enaddr)); 771 772 error = vge_allocmem(sc); 773 774 if (error) 775 return; 776 777 ifp = &sc->arpcom.ac_if; 778 ifp->if_softc = sc; 779 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 780 ifp->if_ioctl = vge_ioctl; 781 ifp->if_start = vge_start; 782 ifp->if_watchdog = vge_watchdog; 783 ifp->if_init = vge_init; 784 ifp->if_baudrate = 1000000000; 785 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 786 IFQ_SET_READY(&ifp->if_snd); 787 788 ifp->if_capabilities = IFCAP_VLAN_MTU|IFCAP_CSUM_IPv4| 789 IFCAP_CSUM_TCPv4|IFCAP_CSUM_UDPv4; 790 791#ifdef VGE_VLAN 792 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 793#endif 794 795 /* Set interface name */ 796 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 797 798 /* Do MII setup */ 799 sc->sc_mii.mii_ifp = ifp; 800 sc->sc_mii.mii_readreg = vge_miibus_readreg; 801 sc->sc_mii.mii_writereg = vge_miibus_writereg; 802 sc->sc_mii.mii_statchg = vge_miibus_statchg; 803 ifmedia_init(&sc->sc_mii.mii_media, 0, 804 vge_ifmedia_upd, vge_ifmedia_sts); 805 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 806 MII_OFFSET_ANY, 0); 807 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 808 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 809 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 810 0, NULL); 811 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 812 } else 813 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 814 815 timeout_set(&sc->timer_handle, vge_tick, sc); 816 817 /* 818 * Call MI attach routine. 819 */ 820 if_attach(ifp); 821 ether_ifattach(ifp); 822} 823 824int 825vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 826{ 827 struct mbuf *m_new = NULL; 828 struct vge_rx_desc *r; 829 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 830 int i; 831 832 if (m == NULL) { 833 /* Allocate a new mbuf */ 834 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 835 if (m_new == NULL) 836 return (ENOBUFS); 837 838 /* Allocate a cluster */ 839 MCLGET(m_new, M_DONTWAIT); 840 if (!(m_new->m_flags & M_EXT)) { 841 m_freem(m_new); 842 return (ENOBUFS); 843 } 844 } else 845 m_new->m_data = m_new->m_ext.ext_buf; 846 847 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 848 /* Fix-up alignment so payload is doubleword-aligned */ 849 /* XXX m_adj(m_new, ETHER_ALIGN); */ 850 851 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT)) 852 return (ENOBUFS); 853 854 if (rxmap->dm_nsegs > 1) 855 goto out; 856 857 /* Map the segments into RX descriptors */ 858 r = &sc->vge_ldata.vge_rx_list[idx]; 859 860 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 861 printf("%s: tried to map a busy RX descriptor\n", 862 sc->vge_dev.dv_xname); 863 goto out; 864 } 865 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 866 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 867 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 868 r->vge_sts = htole32(0); 869 r->vge_ctl = htole32(0); 870 871 /* 872 * Note: the manual fails to document the fact that for 873 * proper operation, the driver needs to replenish the RX 874 * DMA ring 4 descriptors at a time (rather than one at a 875 * time, like most chips). We can allocate the new buffers 876 * but we should not set the OWN bits until we're ready 877 * to hand back 4 of them in one shot. 878 */ 879#define VGE_RXCHUNK 4 880 sc->vge_rx_consumed++; 881 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 882 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 883 sc->vge_ldata.vge_rx_list[i].vge_sts |= 884 htole32(VGE_RDSTS_OWN); 885 sc->vge_rx_consumed = 0; 886 } 887 888 sc->vge_ldata.vge_rx_mbuf[idx] = m_new; 889 890 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 891 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 892 893 return (0); 894out: 895 DPRINTF(("vge_newbuf: out of memory\n")); 896 if (m_new != NULL) 897 m_freem(m_new); 898 return (ENOMEM); 899} 900 901int 902vge_tx_list_init(struct vge_softc *sc) 903{ 904 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 905 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 906 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 907 908 bus_dmamap_sync(sc->sc_dmat, 909 sc->vge_ldata.vge_tx_list_map, 0, 910 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 911 BUS_DMASYNC_PREWRITE); 912 sc->vge_ldata.vge_tx_prodidx = 0; 913 sc->vge_ldata.vge_tx_considx = 0; 914 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 915 916 return (0); 917} 918 919/* Init RX descriptors and allocate mbufs with vge_newbuf() 920 * A ring is used, and last descriptor points to first. */ 921int 922vge_rx_list_init(struct vge_softc *sc) 923{ 924 int i; 925 926 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 927 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 928 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 929 930 sc->vge_rx_consumed = 0; 931 932 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 933 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 934 return (ENOBUFS); 935 } 936 937 /* Flush the RX descriptors */ 938 939 bus_dmamap_sync(sc->sc_dmat, 940 sc->vge_ldata.vge_rx_list_map, 941 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 942 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 943 944 sc->vge_ldata.vge_rx_prodidx = 0; 945 sc->vge_rx_consumed = 0; 946 sc->vge_head = sc->vge_tail = NULL; 947 948 return (0); 949} 950 951/* 952 * RX handler. We support the reception of jumbo frames that have 953 * been fragmented across multiple 2K mbuf cluster buffers. 954 */ 955void 956vge_rxeof(struct vge_softc *sc) 957{ 958 struct mbuf *m; 959 struct ifnet *ifp; 960 int i, total_len; 961 int lim = 0; 962 struct vge_rx_desc *cur_rx; 963 u_int32_t rxstat, rxctl; 964 965 ifp = &sc->arpcom.ac_if; 966 i = sc->vge_ldata.vge_rx_prodidx; 967 968 /* Invalidate the descriptor memory */ 969 970 bus_dmamap_sync(sc->sc_dmat, 971 sc->vge_ldata.vge_rx_list_map, 972 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 973 BUS_DMASYNC_POSTREAD); 974 975 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 976 struct mbuf *m0 = NULL; 977 978 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 979 m = sc->vge_ldata.vge_rx_mbuf[i]; 980 total_len = VGE_RXBYTES(cur_rx); 981 rxstat = letoh32(cur_rx->vge_sts); 982 rxctl = letoh32(cur_rx->vge_ctl); 983 984 /* Invalidate the RX mbuf and unload its map */ 985 986 bus_dmamap_sync(sc->sc_dmat, 987 sc->vge_ldata.vge_rx_dmamap[i], 988 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 989 BUS_DMASYNC_POSTWRITE); 990 bus_dmamap_unload(sc->sc_dmat, 991 sc->vge_ldata.vge_rx_dmamap[i]); 992 993 /* 994 * If the 'start of frame' bit is set, this indicates 995 * either the first fragment in a multi-fragment receive, 996 * or an intermediate fragment. Either way, we want to 997 * accumulate the buffers. 998 */ 999 if (rxstat & VGE_RXPKT_SOF) { 1000 DPRINTF(("vge_rxeof: SOF\n")); 1001 m->m_len = MCLBYTES; 1002 if (sc->vge_head == NULL) 1003 sc->vge_head = sc->vge_tail = m; 1004 else { 1005 m->m_flags &= ~M_PKTHDR; 1006 sc->vge_tail->m_next = m; 1007 sc->vge_tail = m; 1008 } 1009 vge_newbuf(sc, i, NULL); 1010 VGE_RX_DESC_INC(i); 1011 continue; 1012 } 1013 1014 /* 1015 * Bad/error frames will have the RXOK bit cleared. 1016 * However, there's one error case we want to allow: 1017 * if a VLAN tagged frame arrives and the chip can't 1018 * match it against the CAM filter, it considers this 1019 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1020 * We don't want to drop the frame though: our VLAN 1021 * filtering is done in software. 1022 */ 1023 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1024 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1025 ifp->if_ierrors++; 1026 /* 1027 * If this is part of a multi-fragment packet, 1028 * discard all the pieces. 1029 */ 1030 if (sc->vge_head != NULL) { 1031 m_freem(sc->vge_head); 1032 sc->vge_head = sc->vge_tail = NULL; 1033 } 1034 vge_newbuf(sc, i, m); 1035 VGE_RX_DESC_INC(i); 1036 continue; 1037 } 1038 1039 /* 1040 * If allocating a replacement mbuf fails, 1041 * reload the current one. 1042 */ 1043 1044 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1045 if (sc->vge_head != NULL) { 1046 m_freem(sc->vge_head); 1047 sc->vge_head = sc->vge_tail = NULL; 1048 } 1049 1050 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1051 total_len - ETHER_CRC_LEN + ETHER_ALIGN, 1052 0, ifp, NULL); 1053 vge_newbuf(sc, i, m); 1054 if (m0 == NULL) { 1055 ifp->if_ierrors++; 1056 continue; 1057 } 1058 m_adj(m0, ETHER_ALIGN); 1059 m = m0; 1060 1061 VGE_RX_DESC_INC(i); 1062 continue; 1063 } 1064 1065 VGE_RX_DESC_INC(i); 1066 1067 if (sc->vge_head != NULL) { 1068 m->m_len = total_len % MCLBYTES; 1069 /* 1070 * Special case: if there's 4 bytes or less 1071 * in this buffer, the mbuf can be discarded: 1072 * the last 4 bytes is the CRC, which we don't 1073 * care about anyway. 1074 */ 1075 if (m->m_len <= ETHER_CRC_LEN) { 1076 sc->vge_tail->m_len -= 1077 (ETHER_CRC_LEN - m->m_len); 1078 m_freem(m); 1079 } else { 1080 m->m_len -= ETHER_CRC_LEN; 1081 m->m_flags &= ~M_PKTHDR; 1082 sc->vge_tail->m_next = m; 1083 } 1084 m = sc->vge_head; 1085 sc->vge_head = sc->vge_tail = NULL; 1086 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1087 } else 1088 m->m_pkthdr.len = m->m_len = 1089 (total_len - ETHER_CRC_LEN); 1090 1091#ifdef __STRICT_ALIGNMENT 1092 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1093 total_len); 1094 m->m_data += ETHER_ALIGN; 1095#endif 1096 ifp->if_ipackets++; 1097 m->m_pkthdr.rcvif = ifp; 1098 1099 /* Do RX checksumming */ 1100 1101 /* Check IP header checksum */ 1102 if ((rxctl & VGE_RDCTL_IPPKT) && 1103 (rxctl & VGE_RDCTL_IPCSUMOK)) 1104 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1105 1106 /* Check TCP/UDP checksum */ 1107 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1108 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1109 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1110 1111#if NBPFILTER > 0 1112 if (ifp->if_bpf) 1113 bpf_mtap(ifp->if_bpf, m); 1114#endif 1115 ether_input_mbuf(ifp, m); 1116 1117 lim++; 1118 if (lim == VGE_RX_DESC_CNT) 1119 break; 1120 } 1121 1122 /* Flush the RX DMA ring */ 1123 bus_dmamap_sync(sc->sc_dmat, 1124 sc->vge_ldata.vge_rx_list_map, 1125 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1126 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1127 1128 sc->vge_ldata.vge_rx_prodidx = i; 1129 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1130} 1131 1132void 1133vge_txeof(struct vge_softc *sc) 1134{ 1135 struct ifnet *ifp; 1136 u_int32_t txstat; 1137 int idx; 1138 1139 ifp = &sc->arpcom.ac_if; 1140 idx = sc->vge_ldata.vge_tx_considx; 1141 1142 /* Invalidate the TX descriptor list */ 1143 1144 bus_dmamap_sync(sc->sc_dmat, 1145 sc->vge_ldata.vge_tx_list_map, 1146 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1147 BUS_DMASYNC_POSTREAD); 1148 1149 /* Transmitted frames can be now free'd from the TX list */ 1150 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1151 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1152 if (txstat & VGE_TDSTS_OWN) 1153 break; 1154 1155 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1156 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1157 bus_dmamap_unload(sc->sc_dmat, 1158 sc->vge_ldata.vge_tx_dmamap[idx]); 1159 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1160 ifp->if_collisions++; 1161 if (txstat & VGE_TDSTS_TXERR) 1162 ifp->if_oerrors++; 1163 else 1164 ifp->if_opackets++; 1165 1166 sc->vge_ldata.vge_tx_free++; 1167 VGE_TX_DESC_INC(idx); 1168 } 1169 1170 /* No changes made to the TX ring, so no flush needed */ 1171 1172 if (idx != sc->vge_ldata.vge_tx_considx) { 1173 sc->vge_ldata.vge_tx_considx = idx; 1174 ifp->if_flags &= ~IFF_OACTIVE; 1175 ifp->if_timer = 0; 1176 } 1177 1178 /* 1179 * If not all descriptors have been released reaped yet, 1180 * reload the timer so that we will eventually get another 1181 * interrupt that will cause us to re-enter this routine. 1182 * This is done in case the transmitter has gone idle. 1183 */ 1184 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1185 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1186} 1187 1188void 1189vge_tick(void *xsc) 1190{ 1191 struct vge_softc *sc = xsc; 1192 struct ifnet *ifp = &sc->arpcom.ac_if; 1193 struct mii_data *mii = &sc->sc_mii; 1194 int s; 1195 1196 s = splnet(); 1197 1198 mii_tick(mii); 1199 1200 if (sc->vge_link) { 1201 if (!(mii->mii_media_status & IFM_ACTIVE)) 1202 sc->vge_link = 0; 1203 ifp->if_link_state = LINK_STATE_DOWN; 1204 if_link_state_change(ifp); 1205 } else { 1206 if (mii->mii_media_status & IFM_ACTIVE && 1207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1208 sc->vge_link = 1; 1209 ifp->if_link_state = LINK_STATE_UP; 1210 if_link_state_change(ifp); 1211 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1212 vge_start(ifp); 1213 } 1214 } 1215 timeout_add(&sc->timer_handle, hz); 1216 splx(s); 1217} 1218 1219int 1220vge_intr(void *arg) 1221{ 1222 struct vge_softc *sc = arg; 1223 struct ifnet *ifp; 1224 u_int32_t status; 1225 int claimed = 0; 1226 1227 ifp = &sc->arpcom.ac_if; 1228 1229 if (!(ifp->if_flags & IFF_UP)) 1230 return 0; 1231 1232 /* Disable interrupts */ 1233 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1234 1235 for (;;) { 1236 status = CSR_READ_4(sc, VGE_ISR); 1237 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1238 1239 /* If the card has gone away the read returns 0xffffffff. */ 1240 if (status == 0xFFFFFFFF) 1241 break; 1242 1243 if (status) { 1244 CSR_WRITE_4(sc, VGE_ISR, status); 1245 } 1246 1247 if ((status & VGE_INTRS) == 0) 1248 break; 1249 1250 claimed = 1; 1251 1252 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1253 vge_rxeof(sc); 1254 1255 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1256 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1257 vge_rxeof(sc); 1258 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1259 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1260 } 1261 1262 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1263 vge_txeof(sc); 1264 1265 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1266 DPRINTFN(2, ("DMA_STALL\n")); 1267 vge_init(ifp); 1268 } 1269 1270 if (status & VGE_ISR_LINKSTS) { 1271 timeout_del(&sc->timer_handle); 1272 vge_tick(sc); 1273 } 1274 } 1275 1276 /* Re-enable interrupts */ 1277 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1278 1279 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1280 vge_start(ifp); 1281 1282 return (claimed); 1283} 1284 1285/* 1286 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1287 * the descriptors. 1288 */ 1289int 1290vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1291{ 1292 bus_dmamap_t txmap; 1293 struct vge_tx_desc *d = NULL; 1294 struct vge_tx_frag *f; 1295 int error, frag; 1296 u_int32_t vge_flags; 1297 1298 vge_flags = 0; 1299 1300 if (m_head->m_pkthdr.csum_flags & M_IPV4_CSUM_OUT) 1301 vge_flags |= VGE_TDCTL_IPCSUM; 1302 if (m_head->m_pkthdr.csum_flags & M_TCPV4_CSUM_OUT) 1303 vge_flags |= VGE_TDCTL_TCPCSUM; 1304 if (m_head->m_pkthdr.csum_flags & M_UDPV4_CSUM_OUT) 1305 vge_flags |= VGE_TDCTL_UDPCSUM; 1306 1307 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1308repack: 1309 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1310 m_head, BUS_DMA_NOWAIT); 1311 if (error) { 1312 printf("%s: can't map mbuf (error %d)\n", 1313 sc->vge_dev.dv_xname, error); 1314 return (ENOBUFS); 1315 } 1316 1317 d = &sc->vge_ldata.vge_tx_list[idx]; 1318 /* If owned by chip, fail */ 1319 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1320 return (ENOBUFS); 1321 1322 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1323 /* Check if we have used all 7 fragments. */ 1324 if (frag == VGE_TX_FRAGS) 1325 break; 1326 f = &d->vge_frag[frag]; 1327 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1328 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1329 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1330 } 1331 1332 /* 1333 * We used up all 7 fragments! Now what we have to do is 1334 * copy the data into a mbuf cluster and map that. 1335 */ 1336 if (frag == VGE_TX_FRAGS) { 1337 struct mbuf *m = NULL; 1338 1339 MGETHDR(m, M_DONTWAIT, MT_DATA); 1340 if (m == NULL) { 1341 m_freem(m_head); 1342 return (ENOBUFS); 1343 } 1344 if (m_head->m_pkthdr.len > MHLEN) { 1345 MCLGET(m, M_DONTWAIT); 1346 if (!(m->m_flags & M_EXT)) { 1347 m_freem(m); 1348 m_freem(m_head); 1349 return (ENOBUFS); 1350 } 1351 } 1352 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1353 mtod(m, caddr_t)); 1354 m->m_pkthdr.len = m->m_len = m_head->m_pkthdr.len; 1355 m_freem(m_head); 1356 m_head = m; 1357 goto repack; 1358 } 1359 1360 /* This chip does not do auto-padding */ 1361 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1362 f = &d->vge_frag[frag]; 1363 1364 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1365 m_head->m_pkthdr.len)); 1366 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1367 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1368 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1369 frag++; 1370 } 1371 /* For some reason, we need to tell the card fragment + 1 */ 1372 frag++; 1373 1374 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1375 BUS_DMASYNC_PREWRITE); 1376 1377 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1378 d->vge_ctl = htole32(vge_flags|(frag << 28) | VGE_TD_LS_NORM); 1379 1380 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1381 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1382 1383 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1384 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1385 sc->vge_ldata.vge_tx_free--; 1386 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1387 1388 /* 1389 * Set up hardware VLAN tagging. 1390 */ 1391#ifdef VGE_VLAN 1392 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1393 if (mtag != NULL) 1394 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1395 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1396#endif 1397 1398 idx++; 1399 1400 return (0); 1401} 1402 1403/* 1404 * Main transmit routine. 1405 */ 1406void 1407vge_start(struct ifnet *ifp) 1408{ 1409 struct vge_softc *sc; 1410 struct mbuf *m_head = NULL; 1411 int idx, pidx = 0; 1412 1413 sc = ifp->if_softc; 1414 1415 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1416 return; 1417 1418 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1419 return; 1420 1421 idx = sc->vge_ldata.vge_tx_prodidx; 1422 1423 pidx = idx - 1; 1424 if (pidx < 0) 1425 pidx = VGE_TX_DESC_CNT - 1; 1426 1427 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1428 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1429 if (m_head == NULL) 1430 break; 1431 1432 /* 1433 * If there's a BPF listener, bounce a copy of this frame 1434 * to him. 1435 */ 1436#if NBPFILTER > 0 1437 if (ifp->if_bpf) 1438 bpf_mtap(ifp->if_bpf, m_head); 1439#endif 1440 1441 if (vge_encap(sc, m_head, idx)) { 1442 IF_PREPEND(&ifp->if_snd, m_head); 1443 ifp->if_flags |= IFF_OACTIVE; 1444 break; 1445 } 1446 1447 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1448 htole16(VGE_TXDESC_Q); 1449 1450 pidx = idx; 1451 VGE_TX_DESC_INC(idx); 1452 } 1453 1454 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1455 return; 1456 } 1457 1458 /* Flush the TX descriptors */ 1459 1460 bus_dmamap_sync(sc->sc_dmat, 1461 sc->vge_ldata.vge_tx_list_map, 1462 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1463 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1464 1465 /* Issue a transmit command. */ 1466 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1467 1468 sc->vge_ldata.vge_tx_prodidx = idx; 1469 1470 /* 1471 * Use the countdown timer for interrupt moderation. 1472 * 'TX done' interrupts are disabled. Instead, we reset the 1473 * countdown timer, which will begin counting until it hits 1474 * the value in the SSTIMER register, and then trigger an 1475 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1476 * the timer count is reloaded. Only when the transmitter 1477 * is idle will the timer hit 0 and an interrupt fire. 1478 */ 1479 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1480 1481 /* 1482 * Set a timeout in case the chip goes out to lunch. 1483 */ 1484 ifp->if_timer = 5; 1485} 1486 1487int 1488vge_init(struct ifnet *ifp) 1489{ 1490 struct vge_softc *sc = ifp->if_softc; 1491 int i; 1492 1493 /* 1494 * Cancel pending I/O and free all RX/TX buffers. 1495 */ 1496 vge_stop(sc); 1497 vge_reset(sc); 1498 1499 /* Initialize RX descriptors list */ 1500 if (vge_rx_list_init(sc) == ENOBUFS) { 1501 printf("%s: init failed: no memory for RX buffers\n", 1502 sc->vge_dev.dv_xname); 1503 vge_stop(sc); 1504 return (ENOBUFS); 1505 } 1506 /* Initialize TX descriptors */ 1507 if (vge_tx_list_init(sc) == ENOBUFS) { 1508 printf("%s: init failed: no memory for TX buffers\n", 1509 sc->vge_dev.dv_xname); 1510 vge_stop(sc); 1511 return (ENOBUFS); 1512 } 1513 1514 /* Set our station address */ 1515 for (i = 0; i < ETHER_ADDR_LEN; i++) 1516 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1517 1518 /* 1519 * Set receive FIFO threshold. Also allow transmission and 1520 * reception of VLAN tagged frames. 1521 */ 1522 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1523 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1524 1525 /* Set DMA burst length */ 1526 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1527 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1528 1529 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1530 1531 /* Set collision backoff algorithm */ 1532 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1533 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1534 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1535 1536 /* Disable LPSEL field in priority resolution */ 1537 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1538 1539 /* 1540 * Load the addresses of the DMA queues into the chip. 1541 * Note that we only use one transmit queue. 1542 */ 1543 1544 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1545 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1546 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1547 1548 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1549 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1550 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1551 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1552 1553 /* Enable and wake up the RX descriptor queue */ 1554 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1555 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1556 1557 /* Enable the TX descriptor queue */ 1558 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1559 1560 /* Set up the receive filter -- allow large frames for VLANs. */ 1561 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1562 1563 /* If we want promiscuous mode, set the allframes bit. */ 1564 if (ifp->if_flags & IFF_PROMISC) { 1565 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1566 } 1567 1568 /* Set capture broadcast bit to capture broadcast frames. */ 1569 if (ifp->if_flags & IFF_BROADCAST) { 1570 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1571 } 1572 1573 /* Set multicast bit to capture multicast frames. */ 1574 if (ifp->if_flags & IFF_MULTICAST) { 1575 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1576 } 1577 1578 /* Init the cam filter. */ 1579 vge_cam_clear(sc); 1580 1581 /* Init the multicast filter. */ 1582 vge_setmulti(sc); 1583 1584 /* Enable flow control */ 1585 1586 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1587 1588 /* Enable jumbo frame reception (if desired) */ 1589 1590 /* Start the MAC. */ 1591 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1592 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1593 CSR_WRITE_1(sc, VGE_CRS0, 1594 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1595 1596 /* 1597 * Configure one-shot timer for microsecond 1598 * resulution and load it for 500 usecs. 1599 */ 1600 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1601 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1602 1603 /* 1604 * Configure interrupt moderation for receive. Enable 1605 * the holdoff counter and load it, and set the RX 1606 * suppression count to the number of descriptors we 1607 * want to allow before triggering an interrupt. 1608 * The holdoff timer is in units of 20 usecs. 1609 */ 1610 1611#ifdef notyet 1612 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1613 /* Select the interrupt holdoff timer page. */ 1614 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1615 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1616 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1617 1618 /* Enable use of the holdoff timer. */ 1619 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1620 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1621 1622 /* Select the RX suppression threshold page. */ 1623 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1624 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1625 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1626 1627 /* Restore the page select bits. */ 1628 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1629 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1630#endif 1631 1632 /* 1633 * Enable interrupts. 1634 */ 1635 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1636 CSR_WRITE_4(sc, VGE_ISR, 0); 1637 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1638 1639 /* Restore BMCR state */ 1640 mii_mediachg(&sc->sc_mii); 1641 1642 ifp->if_flags |= IFF_RUNNING; 1643 ifp->if_flags &= ~IFF_OACTIVE; 1644 1645 sc->vge_if_flags = 0; 1646 sc->vge_link = 0; 1647 1648 if (!timeout_pending(&sc->timer_handle)) 1649 timeout_add(&sc->timer_handle, hz); 1650 1651 return (0); 1652} 1653 1654/* 1655 * Set media options. 1656 */ 1657int 1658vge_ifmedia_upd(struct ifnet *ifp) 1659{ 1660 struct vge_softc *sc = ifp->if_softc; 1661 1662 return (mii_mediachg(&sc->sc_mii)); 1663} 1664 1665/* 1666 * Report current media status. 1667 */ 1668void 1669vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1670{ 1671 struct vge_softc *sc = ifp->if_softc; 1672 1673 mii_pollstat(&sc->sc_mii); 1674 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1675 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1676} 1677 1678void 1679vge_miibus_statchg(struct device *dev) 1680{ 1681 struct vge_softc *sc = (struct vge_softc *)dev; 1682 struct mii_data *mii; 1683 struct ifmedia_entry *ife; 1684 1685 mii = &sc->sc_mii; 1686 ife = mii->mii_media.ifm_cur; 1687 1688 /* 1689 * If the user manually selects a media mode, we need to turn 1690 * on the forced MAC mode bit in the DIAGCTL register. If the 1691 * user happens to choose a full duplex mode, we also need to 1692 * set the 'force full duplex' bit. This applies only to 1693 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1694 * mode is disabled, and in 1000baseT mode, full duplex is 1695 * always implied, so we turn on the forced mode bit but leave 1696 * the FDX bit cleared. 1697 */ 1698 1699 switch (IFM_SUBTYPE(ife->ifm_media)) { 1700 case IFM_AUTO: 1701 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1702 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1703 break; 1704 case IFM_1000_T: 1705 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1706 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1707 break; 1708 case IFM_100_TX: 1709 case IFM_10_T: 1710 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1711 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1712 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1713 } else { 1714 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1715 } 1716 break; 1717 default: 1718 printf("%s: unknown media type: %x\n", 1719 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1720 break; 1721 } 1722} 1723 1724int 1725vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1726{ 1727 struct vge_softc *sc = ifp->if_softc; 1728 struct ifreq *ifr = (struct ifreq *) data; 1729 struct ifaddr *ifa = (struct ifaddr *) data; 1730 int s, error = 0; 1731 1732 s = splnet(); 1733 1734 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1735 splx(s); 1736 return (error); 1737 } 1738 1739 switch (command) { 1740 case SIOCSIFADDR: 1741 ifp->if_flags |= IFF_UP; 1742 switch (ifa->ifa_addr->sa_family) { 1743#ifdef INET 1744 case AF_INET: 1745 vge_init(ifp); 1746 arp_ifinit(&sc->arpcom, ifa); 1747 break; 1748#endif 1749 default: 1750 vge_init(ifp); 1751 break; 1752 } 1753 break; 1754 case SIOCSIFMTU: 1755 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1756 error = EINVAL; 1757 else if (ifp->if_mtu != ifr->ifr_mtu) 1758 ifp->if_mtu = ifr->ifr_mtu; 1759 break; 1760 case SIOCSIFFLAGS: 1761 if (ifp->if_flags & IFF_UP) { 1762 if (ifp->if_flags & IFF_RUNNING && 1763 ifp->if_flags & IFF_PROMISC && 1764 !(sc->vge_if_flags & IFF_PROMISC)) { 1765 CSR_SETBIT_1(sc, VGE_RXCTL, 1766 VGE_RXCTL_RX_PROMISC); 1767 vge_setmulti(sc); 1768 } else if (ifp->if_flags & IFF_RUNNING && 1769 !(ifp->if_flags & IFF_PROMISC) && 1770 sc->vge_if_flags & IFF_PROMISC) { 1771 CSR_CLRBIT_1(sc, VGE_RXCTL, 1772 VGE_RXCTL_RX_PROMISC); 1773 vge_setmulti(sc); 1774 } else 1775 vge_init(ifp); 1776 } else { 1777 if (ifp->if_flags & IFF_RUNNING) 1778 vge_stop(sc); 1779 } 1780 sc->vge_if_flags = ifp->if_flags; 1781 break; 1782 case SIOCADDMULTI: 1783 case SIOCDELMULTI: 1784 error = (command == SIOCADDMULTI) ? 1785 ether_addmulti(ifr, &sc->arpcom) : 1786 ether_delmulti(ifr, &sc->arpcom); 1787 1788 if (error == ENETRESET) { 1789 if (ifp->if_flags & IFF_RUNNING) 1790 vge_setmulti(sc); 1791 error = 0; 1792 } 1793 break; 1794 case SIOCGIFMEDIA: 1795 case SIOCSIFMEDIA: 1796 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1797 break; 1798 default: 1799 error = EINVAL; 1800 break; 1801 } 1802 1803 splx(s); 1804 return (error); 1805} 1806 1807void 1808vge_watchdog(struct ifnet *ifp) 1809{ 1810 struct vge_softc *sc = ifp->if_softc; 1811 int s; 1812 1813 s = splnet(); 1814 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1815 ifp->if_oerrors++; 1816 1817 vge_txeof(sc); 1818 vge_rxeof(sc); 1819 1820 vge_init(ifp); 1821 1822 splx(s); 1823} 1824 1825/* 1826 * Stop the adapter and free any mbufs allocated to the 1827 * RX and TX lists. 1828 */ 1829void 1830vge_stop(struct vge_softc *sc) 1831{ 1832 register int i; 1833 struct ifnet *ifp; 1834 1835 ifp = &sc->arpcom.ac_if; 1836 ifp->if_timer = 0; 1837 if (timeout_pending(&sc->timer_handle)) 1838 timeout_del(&sc->timer_handle); 1839 1840 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1841 1842 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1843 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1844 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1845 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1846 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1847 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1848 1849 if (sc->vge_head != NULL) { 1850 m_freem(sc->vge_head); 1851 sc->vge_head = sc->vge_tail = NULL; 1852 } 1853 1854 /* Free the TX list buffers. */ 1855 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1856 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1857 bus_dmamap_unload(sc->sc_dmat, 1858 sc->vge_ldata.vge_tx_dmamap[i]); 1859 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1860 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1861 } 1862 } 1863 1864 /* Free the RX list buffers. */ 1865 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1866 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1867 bus_dmamap_unload(sc->sc_dmat, 1868 sc->vge_ldata.vge_rx_dmamap[i]); 1869 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1870 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1871 } 1872 } 1873} 1874