if_vge.c revision 1.11
1/* $OpenBSD: if_vge.c,v 1.11 2005/04/25 17:55:51 brad Exp $ */ 2/* $FreeBSD: if_vge.c,v 1.3 2004/09/11 22:13:25 wpaul Exp $ */ 3/* 4 * Copyright (c) 2004 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35/* 36 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 37 * 38 * Written by Bill Paul <wpaul@windriver.com> 39 * Senior Networking Software Engineer 40 * Wind River Systems 41 * 42 * Ported to OpenBSD by Peter Valchev <pvalchev@openbsd.org> 43 */ 44 45/* 46 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 47 * combines a tri-speed ethernet MAC and PHY, with the following 48 * features: 49 * 50 * o Jumbo frame support up to 16K 51 * o Transmit and receive flow control 52 * o IPv4 checksum offload 53 * o VLAN tag insertion and stripping 54 * o TCP large send 55 * o 64-bit multicast hash table filter 56 * o 64 entry CAM filter 57 * o 16K RX FIFO and 48K TX FIFO memory 58 * o Interrupt moderation 59 * 60 * The VT6122 supports up to four transmit DMA queues. The descriptors 61 * in the transmit ring can address up to 7 data fragments; frames which 62 * span more than 7 data buffers must be coalesced, but in general the 63 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 64 * long. The receive descriptors address only a single buffer. 65 * 66 * There are two peculiar design issues with the VT6122. One is that 67 * receive data buffers must be aligned on a 32-bit boundary. This is 68 * not a problem where the VT6122 is used as a LOM device in x86-based 69 * systems, but on architectures that generate unaligned access traps, we 70 * have to do some copying. 71 * 72 * The other issue has to do with the way 64-bit addresses are handled. 73 * The DMA descriptors only allow you to specify 48 bits of addressing 74 * information. The remaining 16 bits are specified using one of the 75 * I/O registers. If you only have a 32-bit system, then this isn't 76 * an issue, but if you have a 64-bit system and more than 4GB of 77 * memory, you must have to make sure your network data buffers reside 78 * in the same 48-bit 'segment.' 79 * 80 * Special thanks to Ryan Fu at VIA Networking for providing documentation 81 * and sample NICs for testing. 82 */ 83 84#include "bpfilter.h" 85#include "vlan.h" 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/device.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_dl.h> 99#include <net/if_media.h> 100 101#ifdef INET 102#include <netinet/in.h> 103#include <netinet/in_systm.h> 104#include <netinet/in_var.h> 105#include <netinet/ip.h> 106#include <netinet/if_ether.h> 107#endif 108 109#if NVLAN > 0 110#include <net/if_types.h> 111#include <net/if_vlan_var.h> 112#endif 113 114#if NBPFILTER > 0 115#include <net/bpf.h> 116#endif 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121#include <dev/pci/pcireg.h> 122#include <dev/pci/pcivar.h> 123#include <dev/pci/pcidevs.h> 124 125#include <dev/pci/if_vgereg.h> 126#include <dev/pci/if_vgevar.h> 127 128int vge_probe (struct device *, void *, void *); 129void vge_attach (struct device *, struct device *, void *); 130 131int vge_encap (struct vge_softc *, struct mbuf *, int); 132 133int vge_allocmem (struct vge_softc *); 134int vge_newbuf (struct vge_softc *, int, struct mbuf *); 135int vge_rx_list_init (struct vge_softc *); 136int vge_tx_list_init (struct vge_softc *); 137void vge_rxeof (struct vge_softc *); 138void vge_txeof (struct vge_softc *); 139int vge_intr (void *); 140void vge_tick (void *); 141void vge_start (struct ifnet *); 142int vge_ioctl (struct ifnet *, u_long, caddr_t); 143int vge_init (struct ifnet *); 144void vge_stop (struct vge_softc *); 145void vge_watchdog (struct ifnet *); 146int vge_ifmedia_upd (struct ifnet *); 147void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 148 149void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 150void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 151 152void vge_miipoll_start (struct vge_softc *); 153void vge_miipoll_stop (struct vge_softc *); 154int vge_miibus_readreg (struct device *, int, int); 155void vge_miibus_writereg (struct device *, int, int, int); 156void vge_miibus_statchg (struct device *); 157 158void vge_cam_clear (struct vge_softc *); 159int vge_cam_set (struct vge_softc *, uint8_t *); 160void vge_setmulti (struct vge_softc *); 161void vge_reset (struct vge_softc *); 162 163struct cfattach vge_ca = { 164 sizeof(struct vge_softc), vge_probe, vge_attach 165}; 166 167struct cfdriver vge_cd = { 168 0, "vge", DV_IFNET 169}; 170 171#define VGE_PCI_LOIO 0x10 172#define VGE_PCI_LOMEM 0x14 173 174int vge_debug = 0; 175#define DPRINTF(x) if (vge_debug) printf x 176#define DPRINTFN(n, x) if (vge_debug >= (n)) printf x 177 178const struct pci_matchid vge_devices[] = { 179 { PCI_VENDOR_VIATECH, PCI_PRODUCT_VIATECH_VT612x }, 180}; 181 182/* 183 * Read a word of data stored in the EEPROM at address 'addr.' 184 */ 185void 186vge_eeprom_getword(struct vge_softc *sc, int addr, u_int16_t *dest) 187{ 188 register int i; 189 u_int16_t word = 0; 190 191 /* 192 * Enter EEPROM embedded programming mode. In order to 193 * access the EEPROM at all, we first have to set the 194 * EELOAD bit in the CHIPCFG2 register. 195 */ 196 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 197 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 198 199 /* Select the address of the word we want to read */ 200 CSR_WRITE_1(sc, VGE_EEADDR, addr); 201 202 /* Issue read command */ 203 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 204 205 /* Wait for the done bit to be set. */ 206 for (i = 0; i < VGE_TIMEOUT; i++) { 207 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 208 break; 209 } 210 211 if (i == VGE_TIMEOUT) { 212 printf("%s: EEPROM read timed out\n", sc->vge_dev.dv_xname); 213 *dest = 0; 214 return; 215 } 216 217 /* Read the result */ 218 word = CSR_READ_2(sc, VGE_EERDDAT); 219 220 /* Turn off EEPROM access mode. */ 221 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 222 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 223 224 *dest = word; 225} 226 227/* 228 * Read a sequence of words from the EEPROM. 229 */ 230void 231vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, 232 int swap) 233{ 234 int i; 235 u_int16_t word = 0, *ptr; 236 237 for (i = 0; i < cnt; i++) { 238 vge_eeprom_getword(sc, off + i, &word); 239 ptr = (u_int16_t *)(dest + (i * 2)); 240 if (swap) 241 *ptr = ntohs(word); 242 else 243 *ptr = word; 244 } 245} 246 247void 248vge_miipoll_stop(struct vge_softc *sc) 249{ 250 int i; 251 252 CSR_WRITE_1(sc, VGE_MIICMD, 0); 253 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 DELAY(1); 256 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 257 break; 258 } 259 260 if (i == VGE_TIMEOUT) 261 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 262} 263 264void 265vge_miipoll_start(struct vge_softc *sc) 266{ 267 int i; 268 269 /* First, make sure we're idle. */ 270 271 CSR_WRITE_1(sc, VGE_MIICMD, 0); 272 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 273 274 for (i = 0; i < VGE_TIMEOUT; i++) { 275 DELAY(1); 276 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 277 break; 278 } 279 280 if (i == VGE_TIMEOUT) { 281 printf("%s: failed to idle MII autopoll\n", sc->vge_dev.dv_xname); 282 return; 283 } 284 285 /* Now enable auto poll mode. */ 286 287 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 288 289 /* And make sure it started. */ 290 291 for (i = 0; i < VGE_TIMEOUT; i++) { 292 DELAY(1); 293 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 294 break; 295 } 296 297 if (i == VGE_TIMEOUT) 298 printf("%s: failed to start MII autopoll\n", sc->vge_dev.dv_xname); 299} 300 301int 302vge_miibus_readreg(struct device *dev, int phy, int reg) 303{ 304 struct vge_softc *sc = (struct vge_softc *)dev; 305 int i, s; 306 u_int16_t rval = 0; 307 308 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 309 return(0); 310 311 s = splimp(); 312 313 vge_miipoll_stop(sc); 314 315 /* Specify the register we want to read. */ 316 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 317 318 /* Issue read command. */ 319 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 320 321 /* Wait for the read command bit to self-clear. */ 322 for (i = 0; i < VGE_TIMEOUT; i++) { 323 DELAY(1); 324 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 325 break; 326 } 327 328 if (i == VGE_TIMEOUT) 329 printf("%s: MII read timed out\n", sc->vge_dev.dv_xname); 330 else 331 rval = CSR_READ_2(sc, VGE_MIIDATA); 332 333 vge_miipoll_start(sc); 334 splx(s); 335 336 return (rval); 337} 338 339void 340vge_miibus_writereg(struct device *dev, int phy, int reg, int data) 341{ 342 struct vge_softc *sc = (struct vge_softc *)dev; 343 int i, s; 344 345 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 346 return; 347 348 s = splimp(); 349 vge_miipoll_stop(sc); 350 351 /* Specify the register we want to write. */ 352 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 353 354 /* Specify the data we want to write. */ 355 CSR_WRITE_2(sc, VGE_MIIDATA, data); 356 357 /* Issue write command. */ 358 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 359 360 /* Wait for the write command bit to self-clear. */ 361 for (i = 0; i < VGE_TIMEOUT; i++) { 362 DELAY(1); 363 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 364 break; 365 } 366 367 if (i == VGE_TIMEOUT) { 368 printf("%s: MII write timed out\n", sc->vge_dev.dv_xname); 369 } 370 371 vge_miipoll_start(sc); 372 splx(s); 373} 374 375void 376vge_cam_clear(struct vge_softc *sc) 377{ 378 int i; 379 380 /* 381 * Turn off all the mask bits. This tells the chip 382 * that none of the entries in the CAM filter are valid. 383 * desired entries will be enabled as we fill the filter in. 384 */ 385 386 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 387 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 388 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 389 for (i = 0; i < 8; i++) 390 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 391 392 /* Clear the VLAN filter too. */ 393 394 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 395 for (i = 0; i < 8; i++) 396 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 397 398 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 399 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 400 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 401 402 sc->vge_camidx = 0; 403} 404 405int 406vge_cam_set(struct vge_softc *sc, uint8_t *addr) 407{ 408 int i, error = 0; 409 410 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 411 return(ENOSPC); 412 413 /* Select the CAM data page. */ 414 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 415 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 416 417 /* Set the filter entry we want to update and enable writing. */ 418 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 419 420 /* Write the address to the CAM registers */ 421 for (i = 0; i < ETHER_ADDR_LEN; i++) 422 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 423 424 /* Issue a write command. */ 425 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 426 427 /* Wake for it to clear. */ 428 for (i = 0; i < VGE_TIMEOUT; i++) { 429 DELAY(1); 430 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 431 break; 432 } 433 434 if (i == VGE_TIMEOUT) { 435 printf("%s: setting CAM filter failed\n", sc->vge_dev.dv_xname); 436 error = EIO; 437 goto fail; 438 } 439 440 /* Select the CAM mask page. */ 441 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 442 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 443 444 /* Set the mask bit that enables this filter. */ 445 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 446 1<<(sc->vge_camidx & 7)); 447 448 sc->vge_camidx++; 449 450fail: 451 /* Turn off access to CAM. */ 452 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 453 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 454 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 455 456 return (error); 457} 458 459/* 460 * Program the multicast filter. We use the 64-entry CAM filter 461 * for perfect filtering. If there's more than 64 multicast addresses, 462 * we use the hash filter instead. 463 */ 464void 465vge_setmulti(struct vge_softc *sc) 466{ 467 struct arpcom *ac = &sc->arpcom; 468 struct ifnet *ifp = &ac->ac_if; 469 struct ether_multi *enm; 470 struct ether_multistep step; 471 u_int32_t h = 0, hashes[2] = { 0, 0 }; 472 473 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 474 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 475 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 476 return; 477 } 478 /* reset existing hash bits */ 479 CSR_WRITE_4(sc, VGE_MAR0, 0); 480 CSR_WRITE_4(sc, VGE_MAR1, 0); 481 482 /* program new ones */ 483 ETHER_FIRST_MULTI(step, ac, enm); 484 while (enm != NULL) { 485 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) 486 ifp->if_flags |= IFF_ALLMULTI; 487 h = (ether_crc32_be(enm->enm_addrlo, 488 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 489 if (h < 32) 490 hashes[0] |= (1 << h); 491 else 492 hashes[1] |= (1 << (h - 32)); 493 ETHER_NEXT_MULTI(step, enm); 494 } 495 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 496 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 497 498#ifdef CAM_FILTERING 499 struct ifnet *ifp; 500 u_int32_t h, hashes[2] = { 0, 0 }; 501 int mcnt = 0; 502 struct arpcom *ac = &sc->arpcom; 503 struct ether_multi *enm; 504 struct ether_multistep step; 505 506 ifp = &sc->arpcom.ac_if; 507 508 /* First, zot all the multicast entries. */ 509 vge_cam_clear(sc); 510 CSR_WRITE_4(sc, VGE_MAR0, 0); 511 CSR_WRITE_4(sc, VGE_MAR1, 0); 512 513 /* 514 * If the user wants allmulti or promisc mode, enable reception 515 * of all multicast frames. 516 */ 517 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 518 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 519 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 520 return; 521 } 522 523 ETHER_FIRST_MULTI(step, ac, enm); 524 while (enm != NULL) { 525 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 526 ifp->if_flags |= IFF_ALLMULTI; 527 mcnt = MAX_NUM_MULTICAST_ADDRESSES; 528 } 529 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES) 530 break; 531 532 h = (ether_crc32_be(enm->enm_addrlo, 533 ETHER_ADDR_LEN) >> 26) & 0x0000003F; 534 if (h < 32) 535 hashes[0] |= (1 << h); 536 else 537 hashes[1] |= (1 << (h - 32)); 538 mcnt++; 539 ETHER_NEXT_MULTI(step, enm); 540 } 541 542 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 543 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 544#endif 545} 546 547void 548vge_reset(struct vge_softc *sc) 549{ 550 register int i; 551 552 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 553 554 for (i = 0; i < VGE_TIMEOUT; i++) { 555 DELAY(5); 556 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 557 break; 558 } 559 560 if (i == VGE_TIMEOUT) { 561 printf("%s: soft reset timed out", sc->vge_dev.dv_xname); 562 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 563 DELAY(2000); 564 } 565 566 DELAY(5000); 567 568 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 569 570 for (i = 0; i < VGE_TIMEOUT; i++) { 571 DELAY(5); 572 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 573 break; 574 } 575 576 if (i == VGE_TIMEOUT) { 577 printf("%s: EEPROM reload timed out\n", sc->vge_dev.dv_xname); 578 return; 579 } 580 581 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 582} 583 584/* 585 * Probe for a VIA gigabit chip. Check the PCI vendor and device 586 * IDs against our list and return a device name if we find a match. 587 */ 588int 589vge_probe(struct device *dev, void *match, void *aux) 590{ 591 return (pci_matchbyid((struct pci_attach_args *)aux, vge_devices, 592 sizeof(vge_devices)/sizeof(vge_devices[0]))); 593} 594 595/* 596 * Allocate memory for RX/TX rings 597 */ 598int 599vge_allocmem(struct vge_softc *sc) 600{ 601 int nseg, rseg; 602 int i, error; 603 604 nseg = 32; 605 606 /* Allocate DMA'able memory for the TX ring */ 607 608 error = bus_dmamap_create(sc->sc_dmat, VGE_TX_LIST_SZ, 1, 609 VGE_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 610 &sc->vge_ldata.vge_tx_list_map); 611 if (error) 612 return (ENOMEM); 613 error = bus_dmamem_alloc(sc->sc_dmat, VGE_TX_LIST_SZ, 614 ETHER_ALIGN, 0, 615 &sc->vge_ldata.vge_tx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 616 if (error) { 617 printf("%s: can't alloc TX list\n", sc->vge_dev.dv_xname); 618 return (ENOMEM); 619 } 620 621 /* Load the map for the TX ring. */ 622 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, 623 1, VGE_TX_LIST_SZ, 624 (caddr_t *)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT); 625 memset(sc->vge_ldata.vge_tx_list, 0, VGE_TX_LIST_SZ); 626 if (error) { 627 printf("%s: can't map TX dma buffers\n", 628 sc->vge_dev.dv_xname); 629 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 630 return (ENOMEM); 631 } 632 633 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map, 634 sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 635 if (error) { 636 printf("%s: can't load TX dma map\n", sc->vge_dev.dv_xname); 637 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_tx_list_map); 638 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_tx_list, 639 VGE_TX_LIST_SZ); 640 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_tx_listseg, rseg); 641 return (ENOMEM); 642 } 643 644 /* Create DMA maps for TX buffers */ 645 646 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 647 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 648 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 649 &sc->vge_ldata.vge_tx_dmamap[i]); 650 if (error) { 651 printf("%s: can't create DMA map for TX\n", 652 sc->vge_dev.dv_xname); 653 return (ENOMEM); 654 } 655 } 656 657 /* Allocate DMA'able memory for the RX ring */ 658 659 error = bus_dmamap_create(sc->sc_dmat, VGE_RX_LIST_SZ, 1, 660 VGE_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 661 &sc->vge_ldata.vge_rx_list_map); 662 if (error) 663 return (ENOMEM); 664 error = bus_dmamem_alloc(sc->sc_dmat, VGE_RX_LIST_SZ, VGE_RING_ALIGN, 665 0, &sc->vge_ldata.vge_rx_listseg, 1, &rseg, BUS_DMA_NOWAIT); 666 if (error) { 667 printf("%s: can't alloc RX list\n", sc->vge_dev.dv_xname); 668 return (ENOMEM); 669 } 670 671 /* Load the map for the RX ring. */ 672 673 error = bus_dmamem_map(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, 674 1, VGE_RX_LIST_SZ, 675 (caddr_t *)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT); 676 memset(sc->vge_ldata.vge_rx_list, 0, VGE_RX_LIST_SZ); 677 if (error) { 678 printf("%s: can't map RX dma buffers\n", 679 sc->vge_dev.dv_xname); 680 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 681 return (ENOMEM); 682 } 683 error = bus_dmamap_load(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map, 684 sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT); 685 if (error) { 686 printf("%s: can't load RX dma map\n", sc->vge_dev.dv_xname); 687 bus_dmamap_destroy(sc->sc_dmat, sc->vge_ldata.vge_rx_list_map); 688 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->vge_ldata.vge_rx_list, 689 VGE_RX_LIST_SZ); 690 bus_dmamem_free(sc->sc_dmat, &sc->vge_ldata.vge_rx_listseg, rseg); 691 return (ENOMEM); 692 } 693 694 /* Create DMA maps for RX buffers */ 695 696 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 697 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * nseg, nseg, 698 MCLBYTES, 0, BUS_DMA_ALLOCNOW, 699 &sc->vge_ldata.vge_rx_dmamap[i]); 700 if (error) { 701 printf("%s: can't create DMA map for RX\n", 702 sc->vge_dev.dv_xname); 703 return (ENOMEM); 704 } 705 } 706 707 return (0); 708} 709 710/* 711 * Attach the interface. Allocate softc structures, do ifmedia 712 * setup and ethernet/BPF attach. 713 */ 714void 715vge_attach(struct device *parent, struct device *self, void *aux) 716{ 717 u_char eaddr[ETHER_ADDR_LEN]; 718 u_int16_t as[3]; 719 struct vge_softc *sc = (struct vge_softc *)self; 720 struct pci_attach_args *pa = aux; 721 pci_chipset_tag_t pc = pa->pa_pc; 722 pci_intr_handle_t ih; 723 const char *intrstr = NULL; 724 struct ifnet *ifp; 725 int error = 0, i; 726 bus_size_t iosize; 727 pcireg_t command; 728 729 /* 730 * Map control/status registers. 731 */ 732 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 733 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 734 PCI_COMMAND_MASTER_ENABLE; 735 pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, command); 736 command = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 737 738 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE)) == 0) { 739 printf(": neither i/o nor mem enabled\n"); 740 return; 741 } 742 743 if (command & PCI_COMMAND_MEM_ENABLE) { 744 if (pci_mapreg_map(pa, VGE_PCI_LOMEM, PCI_MAPREG_TYPE_MEM, 0, 745 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 746 printf(": can't map mem space\n"); 747 return; 748 } 749 } else { 750 if (pci_mapreg_map(pa, VGE_PCI_LOIO, PCI_MAPREG_TYPE_IO, 0, 751 &sc->vge_btag, &sc->vge_bhandle, NULL, &iosize, 0)) { 752 printf(": can't map i/o space\n"); 753 return; 754 } 755 } 756 757 /* Allocate interrupt */ 758 if (pci_intr_map(pa, &ih)) { 759 printf(": couldn't map interrupt\n"); 760 return; 761 } 762 intrstr = pci_intr_string(pc, ih); 763 sc->vge_intrhand = pci_intr_establish(pc, ih, IPL_NET, vge_intr, sc, 764 sc->vge_dev.dv_xname); 765 if (sc->vge_intrhand == NULL) { 766 printf(": couldn't establish interrupt"); 767 if (intrstr != NULL) 768 printf(" at %s", intrstr); 769 return; 770 } 771 printf(": %s", intrstr); 772 773 sc->sc_dmat = pa->pa_dmat; 774 775 /* Reset the adapter. */ 776 vge_reset(sc); 777 778 /* 779 * Get station address from the EEPROM. 780 */ 781 vge_read_eeprom(sc, (caddr_t)as, VGE_EE_EADDR, 3, 0); 782 for (i = 0; i < 3; i++) { 783 eaddr[(i * 2) + 0] = as[i] & 0xff; 784 eaddr[(i * 2) + 1] = as[i] >> 8; 785 } 786 787 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 788 789 printf(", address %s\n", 790 ether_sprintf(sc->arpcom.ac_enaddr)); 791 792 error = vge_allocmem(sc); 793 794 if (error) 795 return; 796 797 ifp = &sc->arpcom.ac_if; 798 ifp->if_softc = sc; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = vge_ioctl; 801 ifp->if_start = vge_start; 802 ifp->if_watchdog = vge_watchdog; 803 ifp->if_init = vge_init; 804 ifp->if_baudrate = 1000000000; 805 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 806 IFQ_SET_READY(&ifp->if_snd); 807 808 ifp->if_capabilities = IFCAP_VLAN_MTU; 809 810#ifdef VGE_VLAN 811 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 812#endif 813#ifdef VGE_CSUM_OFFLOAD 814 ifp->if_capabilities |= IFCAP_CSUM_IPv4|IFCAP_CSUM_TCPv4| 815 IFCAP_CSUM_UDPv4; 816#endif 817 818 /* Set interface name */ 819 strlcpy(ifp->if_xname, sc->vge_dev.dv_xname, IFNAMSIZ); 820 821 /* Do MII setup */ 822 sc->sc_mii.mii_ifp = ifp; 823 sc->sc_mii.mii_readreg = vge_miibus_readreg; 824 sc->sc_mii.mii_writereg = vge_miibus_writereg; 825 sc->sc_mii.mii_statchg = vge_miibus_statchg; 826 ifmedia_init(&sc->sc_mii.mii_media, 0, 827 vge_ifmedia_upd, vge_ifmedia_sts); 828 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 829 MII_OFFSET_ANY, 0); 830 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 831 printf("%s: no PHY found!\n", sc->vge_dev.dv_xname); 832 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL, 833 0, NULL); 834 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL); 835 } else 836 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 837 838 timeout_set(&sc->timer_handle, vge_tick, sc); 839 840 /* 841 * Call MI attach routine. 842 */ 843 if_attach(ifp); 844 ether_ifattach(ifp); 845} 846 847int 848vge_newbuf(struct vge_softc *sc, int idx, struct mbuf *m) 849{ 850 struct mbuf *m_new = NULL; 851 struct vge_rx_desc *r; 852 bus_dmamap_t rxmap = sc->vge_ldata.vge_rx_dmamap[idx]; 853 int i; 854 855 if (m == NULL) { 856 /* Allocate a new mbuf */ 857 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 858 if (m_new == NULL) 859 return (ENOBUFS); 860 861 /* Allocate a cluster */ 862 MCLGET(m_new, M_DONTWAIT); 863 if (!(m_new->m_flags & M_EXT)) { 864 m_freem(m_new); 865 return (ENOBUFS); 866 } 867 } else 868 m_new->m_data = m_new->m_ext.ext_buf; 869 870 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 871 /* Fix-up alignment so payload is doubleword-aligned */ 872 /* XXX m_adj(m_new, ETHER_ALIGN); */ 873 874 if (bus_dmamap_load_mbuf(sc->sc_dmat, rxmap, m_new, BUS_DMA_NOWAIT)) 875 return (ENOBUFS); 876 877 if (rxmap->dm_nsegs > 1) 878 goto out; 879 880 /* Map the segments into RX descriptors */ 881 r = &sc->vge_ldata.vge_rx_list[idx]; 882 883 if (letoh32(r->vge_sts) & VGE_RDSTS_OWN) { 884 printf("%s: tried to map a busy RX descriptor\n", 885 sc->vge_dev.dv_xname); 886 goto out; 887 } 888 r->vge_buflen = htole16(VGE_BUFLEN(rxmap->dm_segs[0].ds_len) | VGE_RXDESC_I); 889 r->vge_addrlo = htole32(VGE_ADDR_LO(rxmap->dm_segs[0].ds_addr)); 890 r->vge_addrhi = htole16(VGE_ADDR_HI(rxmap->dm_segs[0].ds_addr) & 0xFFFF); 891 r->vge_sts = htole32(0); 892 r->vge_ctl = htole32(0); 893 894 /* 895 * Note: the manual fails to document the fact that for 896 * proper operation, the driver needs to replenish the RX 897 * DMA ring 4 descriptors at a time (rather than one at a 898 * time, like most chips). We can allocate the new buffers 899 * but we should not set the OWN bits until we're ready 900 * to hand back 4 of them in one shot. 901 */ 902#define VGE_RXCHUNK 4 903 sc->vge_rx_consumed++; 904 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 905 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 906 sc->vge_ldata.vge_rx_list[i].vge_sts |= 907 htole32(VGE_RDSTS_OWN); 908 sc->vge_rx_consumed = 0; 909 } 910 911 sc->vge_ldata.vge_rx_mbuf[idx] = m_new; 912 913 bus_dmamap_sync(sc->sc_dmat, rxmap, 0, 914 rxmap->dm_mapsize, BUS_DMASYNC_PREREAD); 915 916 return (0); 917out: 918 DPRINTF(("vge_newbuf: out of memory\n")); 919 if (m_new != NULL) 920 m_freem(m_new); 921 return (ENOMEM); 922} 923 924int 925vge_tx_list_init(struct vge_softc *sc) 926{ 927 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 928 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 929 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 930 931 bus_dmamap_sync(sc->sc_dmat, 932 sc->vge_ldata.vge_tx_list_map, 0, 933 sc->vge_ldata.vge_tx_list_map->dm_mapsize, 934 BUS_DMASYNC_PREWRITE); 935 sc->vge_ldata.vge_tx_prodidx = 0; 936 sc->vge_ldata.vge_tx_considx = 0; 937 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 938 939 return (0); 940} 941 942/* Init RX descriptors and allocate mbufs with vge_newbuf() 943 * A ring is used, and last descriptor points to first. */ 944int 945vge_rx_list_init(struct vge_softc *sc) 946{ 947 int i; 948 949 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 950 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 951 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 952 953 sc->vge_rx_consumed = 0; 954 955 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 956 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 957 return (ENOBUFS); 958 } 959 960 /* Flush the RX descriptors */ 961 962 bus_dmamap_sync(sc->sc_dmat, 963 sc->vge_ldata.vge_rx_list_map, 964 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 965 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 966 967 sc->vge_ldata.vge_rx_prodidx = 0; 968 sc->vge_rx_consumed = 0; 969 sc->vge_head = sc->vge_tail = NULL; 970 971 return (0); 972} 973 974/* 975 * RX handler. We support the reception of jumbo frames that have 976 * been fragmented across multiple 2K mbuf cluster buffers. 977 */ 978void 979vge_rxeof(struct vge_softc *sc) 980{ 981 struct mbuf *m; 982 struct ifnet *ifp; 983 int i, total_len; 984 int lim = 0; 985 struct vge_rx_desc *cur_rx; 986 u_int32_t rxstat, rxctl; 987 988 ifp = &sc->arpcom.ac_if; 989 i = sc->vge_ldata.vge_rx_prodidx; 990 991 /* Invalidate the descriptor memory */ 992 993 bus_dmamap_sync(sc->sc_dmat, 994 sc->vge_ldata.vge_rx_list_map, 995 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 996 BUS_DMASYNC_POSTREAD); 997 998 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 999 struct mbuf *m0 = NULL; 1000 1001 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1002 m = sc->vge_ldata.vge_rx_mbuf[i]; 1003 total_len = VGE_RXBYTES(cur_rx); 1004 rxstat = letoh32(cur_rx->vge_sts); 1005 rxctl = letoh32(cur_rx->vge_ctl); 1006 1007 /* Invalidate the RX mbuf and unload its map */ 1008 1009 bus_dmamap_sync(sc->sc_dmat, 1010 sc->vge_ldata.vge_rx_dmamap[i], 1011 0, sc->vge_ldata.vge_rx_dmamap[i]->dm_mapsize, 1012 BUS_DMASYNC_POSTWRITE); 1013 bus_dmamap_unload(sc->sc_dmat, 1014 sc->vge_ldata.vge_rx_dmamap[i]); 1015 1016 /* 1017 * If the 'start of frame' bit is set, this indicates 1018 * either the first fragment in a multi-fragment receive, 1019 * or an intermediate fragment. Either way, we want to 1020 * accumulate the buffers. 1021 */ 1022 if (rxstat & VGE_RXPKT_SOF) { 1023 DPRINTF(("vge_rxeof: SOF\n")); 1024 m->m_len = MCLBYTES; 1025 if (sc->vge_head == NULL) 1026 sc->vge_head = sc->vge_tail = m; 1027 else { 1028 m->m_flags &= ~M_PKTHDR; 1029 sc->vge_tail->m_next = m; 1030 sc->vge_tail = m; 1031 } 1032 vge_newbuf(sc, i, NULL); 1033 VGE_RX_DESC_INC(i); 1034 continue; 1035 } 1036 1037 /* 1038 * Bad/error frames will have the RXOK bit cleared. 1039 * However, there's one error case we want to allow: 1040 * if a VLAN tagged frame arrives and the chip can't 1041 * match it against the CAM filter, it considers this 1042 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1043 * We don't want to drop the frame though: our VLAN 1044 * filtering is done in software. 1045 */ 1046 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1047 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1048 ifp->if_ierrors++; 1049 /* 1050 * If this is part of a multi-fragment packet, 1051 * discard all the pieces. 1052 */ 1053 if (sc->vge_head != NULL) { 1054 m_freem(sc->vge_head); 1055 sc->vge_head = sc->vge_tail = NULL; 1056 } 1057 vge_newbuf(sc, i, m); 1058 VGE_RX_DESC_INC(i); 1059 continue; 1060 } 1061 1062 /* 1063 * If allocating a replacement mbuf fails, 1064 * reload the current one. 1065 */ 1066 1067 if (vge_newbuf(sc, i, NULL) == ENOBUFS) { 1068 if (sc->vge_head != NULL) { 1069 m_freem(sc->vge_head); 1070 sc->vge_head = sc->vge_tail = NULL; 1071 } 1072 1073 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1074 total_len - ETHER_CRC_LEN + ETHER_ALIGN, 1075 0, ifp, NULL); 1076 vge_newbuf(sc, i, m); 1077 if (m0 == NULL) { 1078 ifp->if_ierrors++; 1079 continue; 1080 } 1081 m_adj(m0, ETHER_ALIGN); 1082 m = m0; 1083 1084 VGE_RX_DESC_INC(i); 1085 continue; 1086 } 1087 1088 VGE_RX_DESC_INC(i); 1089 1090 if (sc->vge_head != NULL) { 1091 m->m_len = total_len % MCLBYTES; 1092 /* 1093 * Special case: if there's 4 bytes or less 1094 * in this buffer, the mbuf can be discarded: 1095 * the last 4 bytes is the CRC, which we don't 1096 * care about anyway. 1097 */ 1098 if (m->m_len <= ETHER_CRC_LEN) { 1099 sc->vge_tail->m_len -= 1100 (ETHER_CRC_LEN - m->m_len); 1101 m_freem(m); 1102 } else { 1103 m->m_len -= ETHER_CRC_LEN; 1104 m->m_flags &= ~M_PKTHDR; 1105 sc->vge_tail->m_next = m; 1106 } 1107 m = sc->vge_head; 1108 sc->vge_head = sc->vge_tail = NULL; 1109 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1110 } else 1111 m->m_pkthdr.len = m->m_len = 1112 (total_len - ETHER_CRC_LEN); 1113 1114#ifdef __STRICT_ALIGNMENT 1115 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1116 total_len); 1117 m->m_data += ETHER_ALIGN; 1118#endif 1119 ifp->if_ipackets++; 1120 m->m_pkthdr.rcvif = ifp; 1121 1122 /* Do RX checksumming */ 1123 1124 /* Check IP header checksum */ 1125 if ((rxctl & VGE_RDCTL_IPPKT) && 1126 (rxctl & VGE_RDCTL_IPCSUMOK)) 1127 m->m_pkthdr.csum_flags |= M_IPV4_CSUM_IN_OK; 1128 1129 /* Check TCP/UDP checksum */ 1130 if ((rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT)) && 1131 (rxctl & VGE_RDCTL_PROTOCSUMOK)) 1132 m->m_pkthdr.csum_flags |= M_TCP_CSUM_IN_OK | M_UDP_CSUM_IN_OK; 1133 1134#ifdef VGE_VLAN 1135 if (rxstat & VGE_RDSTS_VTAG) 1136 VLAN_INPUT_TAG(ifp, m, 1137 ntohs((rxctl & VGE_RDCTL_VLANID)), continue); 1138#endif 1139 1140#if NBPFILTER > 0 1141 if (ifp->if_bpf) 1142 bpf_mtap(ifp->if_bpf, m); 1143#endif 1144 ether_input_mbuf(ifp, m); 1145 1146 lim++; 1147 if (lim == VGE_RX_DESC_CNT) 1148 break; 1149 } 1150 1151 /* Flush the RX DMA ring */ 1152 bus_dmamap_sync(sc->sc_dmat, 1153 sc->vge_ldata.vge_rx_list_map, 1154 0, sc->vge_ldata.vge_rx_list_map->dm_mapsize, 1155 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1156 1157 sc->vge_ldata.vge_rx_prodidx = i; 1158 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1159} 1160 1161void 1162vge_txeof(struct vge_softc *sc) 1163{ 1164 struct ifnet *ifp; 1165 u_int32_t txstat; 1166 int idx; 1167 1168 ifp = &sc->arpcom.ac_if; 1169 idx = sc->vge_ldata.vge_tx_considx; 1170 1171 /* Invalidate the TX descriptor list */ 1172 1173 bus_dmamap_sync(sc->sc_dmat, 1174 sc->vge_ldata.vge_tx_list_map, 1175 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1176 BUS_DMASYNC_POSTREAD); 1177 1178 /* Transmitted frames can be now free'd from the TX list */ 1179 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1180 txstat = letoh32(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1181 if (txstat & VGE_TDSTS_OWN) 1182 break; 1183 1184 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1185 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1186 bus_dmamap_unload(sc->sc_dmat, 1187 sc->vge_ldata.vge_tx_dmamap[idx]); 1188 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1189 ifp->if_collisions++; 1190 if (txstat & VGE_TDSTS_TXERR) 1191 ifp->if_oerrors++; 1192 else 1193 ifp->if_opackets++; 1194 1195 sc->vge_ldata.vge_tx_free++; 1196 VGE_TX_DESC_INC(idx); 1197 } 1198 1199 /* No changes made to the TX ring, so no flush needed */ 1200 1201 if (idx != sc->vge_ldata.vge_tx_considx) { 1202 sc->vge_ldata.vge_tx_considx = idx; 1203 ifp->if_flags &= ~IFF_OACTIVE; 1204 ifp->if_timer = 0; 1205 } 1206 1207 /* 1208 * If not all descriptors have been released reaped yet, 1209 * reload the timer so that we will eventually get another 1210 * interrupt that will cause us to re-enter this routine. 1211 * This is done in case the transmitter has gone idle. 1212 */ 1213 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) 1214 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1215} 1216 1217void 1218vge_tick(void *xsc) 1219{ 1220 struct vge_softc *sc = xsc; 1221 struct ifnet *ifp = &sc->arpcom.ac_if; 1222 struct mii_data *mii = &sc->sc_mii; 1223 int s; 1224 1225 s = splimp(); 1226 1227 mii_tick(mii); 1228 1229 if (sc->vge_link) { 1230 if (!(mii->mii_media_status & IFM_ACTIVE)) 1231 sc->vge_link = 0; 1232 ifp->if_link_state = LINK_STATE_UP; 1233 if_link_state_change(ifp); 1234 } else { 1235 if (mii->mii_media_status & IFM_ACTIVE && 1236 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1237 sc->vge_link = 1; 1238 ifp->if_link_state = LINK_STATE_DOWN; 1239 if_link_state_change(ifp); 1240 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1241 vge_start(ifp); 1242 } 1243 } 1244 timeout_add(&sc->timer_handle, hz); 1245 splx(s); 1246} 1247 1248int 1249vge_intr(void *arg) 1250{ 1251 struct vge_softc *sc = arg; 1252 struct ifnet *ifp; 1253 u_int32_t status; 1254 int claimed = 0; 1255 1256 ifp = &sc->arpcom.ac_if; 1257 1258 if (!(ifp->if_flags & IFF_UP)) 1259 return 0; 1260 1261 /* Disable interrupts */ 1262 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1263 1264 for (;;) { 1265 status = CSR_READ_4(sc, VGE_ISR); 1266 DPRINTFN(3, ("vge_intr: status=%#x\n", status)); 1267 1268 /* If the card has gone away the read returns 0xffffffff. */ 1269 if (status == 0xFFFFFFFF) 1270 break; 1271 1272 if (status) { 1273 CSR_WRITE_4(sc, VGE_ISR, status); 1274 } 1275 1276 if ((status & VGE_INTRS) == 0) 1277 break; 1278 1279 claimed = 1; 1280 1281 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1282 vge_rxeof(sc); 1283 1284 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1285 DPRINTFN(2, ("vge_intr: RX error, recovering\n")); 1286 vge_rxeof(sc); 1287 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1288 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1289 } 1290 1291 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1292 vge_txeof(sc); 1293 1294 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1295 DPRINTFN(2, ("DMA_STALL\n")); 1296 vge_init(ifp); 1297 } 1298 1299 if (status & VGE_ISR_LINKSTS) { 1300 timeout_del(&sc->timer_handle); 1301 vge_tick(sc); 1302 } 1303 } 1304 1305 /* Re-enable interrupts */ 1306 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1307 1308 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1309 vge_start(ifp); 1310 1311 return (claimed); 1312} 1313 1314/* 1315 * Encapsulate an mbuf chain into the TX ring by combining it w/ 1316 * the descriptors. 1317 */ 1318int 1319vge_encap(struct vge_softc *sc, struct mbuf *m_head, int idx) 1320{ 1321 bus_dmamap_t txmap; 1322 struct vge_tx_desc *d = NULL; 1323 struct vge_tx_frag *f; 1324 int error, frag; 1325 1326 txmap = sc->vge_ldata.vge_tx_dmamap[idx]; 1327repack: 1328 error = bus_dmamap_load_mbuf(sc->sc_dmat, txmap, 1329 m_head, BUS_DMA_NOWAIT); 1330 if (error) { 1331 printf("%s: can't map mbuf (error %d)\n", 1332 sc->vge_dev.dv_xname, error); 1333 return (ENOBUFS); 1334 } 1335 1336 d = &sc->vge_ldata.vge_tx_list[idx]; 1337 /* If owned by chip, fail */ 1338 if (letoh32(d->vge_sts) & VGE_TDSTS_OWN) 1339 return (ENOBUFS); 1340 1341 for (frag = 0; frag < txmap->dm_nsegs; frag++) { 1342 /* Check if we have used all 7 fragments. */ 1343 if (frag == VGE_TX_FRAGS) 1344 break; 1345 f = &d->vge_frag[frag]; 1346 f->vge_buflen = htole16(VGE_BUFLEN(txmap->dm_segs[frag].ds_len)); 1347 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[frag].ds_addr)); 1348 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[frag].ds_addr) & 0xFFFF); 1349 } 1350 1351 /* 1352 * We used up all 7 fragments! Now what we have to do is 1353 * copy the data into a mbuf cluster and map that. 1354 */ 1355 if (frag == VGE_TX_FRAGS) { 1356 struct mbuf *m = NULL; 1357 1358 MGETHDR(m, M_DONTWAIT, MT_DATA); 1359 if (m == NULL) { 1360 m_freem(m_head); 1361 return (ENOBUFS); 1362 } 1363 if (m_head->m_pkthdr.len > MHLEN) { 1364 MCLGET(m, M_DONTWAIT); 1365 if (!(m->m_flags & M_EXT)) { 1366 m_freem(m); 1367 m_freem(m_head); 1368 return (ENOBUFS); 1369 } 1370 } 1371 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1372 mtod(m, caddr_t)); 1373 m->m_pkthdr.len = m->m_len = m_head->m_pkthdr.len; 1374 m_freem(m_head); 1375 m_head = m; 1376 goto repack; 1377 } 1378 1379 /* This chip does not do auto-padding */ 1380 if (m_head->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1381 f = &d->vge_frag[frag]; 1382 1383 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 1384 m_head->m_pkthdr.len)); 1385 f->vge_addrlo = htole32(VGE_ADDR_LO(txmap->dm_segs[0].ds_addr)); 1386 f->vge_addrhi = htole16(VGE_ADDR_HI(txmap->dm_segs[0].ds_addr) & 0xFFFF); 1387 m_head->m_pkthdr.len = VGE_MIN_FRAMELEN; 1388 frag++; 1389 } 1390 /* For some reason, we need to tell the card fragment + 1 */ 1391 frag++; 1392 1393 bus_dmamap_sync(sc->sc_dmat, txmap, 0, txmap->dm_mapsize, 1394 BUS_DMASYNC_PREWRITE); 1395 1396 d->vge_sts = htole32(m_head->m_pkthdr.len << 16); 1397 d->vge_ctl = htole32((frag << 28) | VGE_TD_LS_NORM); 1398 1399 if (m_head->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 1400 d->vge_ctl |= htole32(VGE_TDCTL_JUMBO); 1401 1402 sc->vge_ldata.vge_tx_dmamap[idx] = txmap; 1403 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1404 sc->vge_ldata.vge_tx_free--; 1405 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1406 1407 /* 1408 * Set up hardware VLAN tagging. 1409 */ 1410#ifdef VGE_VLAN 1411 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 1412 if (mtag != NULL) 1413 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1414 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1415#endif 1416 1417 idx++; 1418 1419 return (0); 1420} 1421 1422/* 1423 * Main transmit routine. 1424 */ 1425void 1426vge_start(struct ifnet *ifp) 1427{ 1428 struct vge_softc *sc; 1429 struct mbuf *m_head = NULL; 1430 int idx, pidx = 0; 1431 1432 sc = ifp->if_softc; 1433 1434 if (!sc->vge_link || ifp->if_flags & IFF_OACTIVE) 1435 return; 1436 1437 if (IFQ_IS_EMPTY(&ifp->if_snd)) 1438 return; 1439 1440 idx = sc->vge_ldata.vge_tx_prodidx; 1441 1442 pidx = idx - 1; 1443 if (pidx < 0) 1444 pidx = VGE_TX_DESC_CNT - 1; 1445 1446 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1447 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1448 if (m_head == NULL) 1449 break; 1450 1451 /* 1452 * If there's a BPF listener, bounce a copy of this frame 1453 * to him. 1454 */ 1455#if NBPFILTER > 0 1456 if (ifp->if_bpf) 1457 bpf_mtap(ifp->if_bpf, m_head); 1458#endif 1459 1460 if (vge_encap(sc, m_head, idx)) { 1461 IF_PREPEND(&ifp->if_snd, m_head); 1462 ifp->if_flags |= IFF_OACTIVE; 1463 break; 1464 } 1465 1466 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1467 htole16(VGE_TXDESC_Q); 1468 1469 pidx = idx; 1470 VGE_TX_DESC_INC(idx); 1471 } 1472 1473 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1474 return; 1475 } 1476 1477 /* Flush the TX descriptors */ 1478 1479 bus_dmamap_sync(sc->sc_dmat, 1480 sc->vge_ldata.vge_tx_list_map, 1481 0, sc->vge_ldata.vge_tx_list_map->dm_mapsize, 1482 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1483 1484 /* Issue a transmit command. */ 1485 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1486 1487 sc->vge_ldata.vge_tx_prodidx = idx; 1488 1489 /* 1490 * Use the countdown timer for interrupt moderation. 1491 * 'TX done' interrupts are disabled. Instead, we reset the 1492 * countdown timer, which will begin counting until it hits 1493 * the value in the SSTIMER register, and then trigger an 1494 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1495 * the timer count is reloaded. Only when the transmitter 1496 * is idle will the timer hit 0 and an interrupt fire. 1497 */ 1498 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1499 1500 /* 1501 * Set a timeout in case the chip goes out to lunch. 1502 */ 1503 ifp->if_timer = 5; 1504} 1505 1506int 1507vge_init(struct ifnet *ifp) 1508{ 1509 struct vge_softc *sc = ifp->if_softc; 1510 int i; 1511 1512 /* 1513 * Cancel pending I/O and free all RX/TX buffers. 1514 */ 1515 vge_stop(sc); 1516 vge_reset(sc); 1517 1518 /* Initialize RX descriptors list */ 1519 if (vge_rx_list_init(sc) == ENOBUFS) { 1520 printf("%s: init failed: no memory for RX buffers\n", 1521 sc->vge_dev.dv_xname); 1522 vge_stop(sc); 1523 return (ENOBUFS); 1524 } 1525 /* Initialize TX descriptors */ 1526 if (vge_tx_list_init(sc) == ENOBUFS) { 1527 printf("%s: init failed: no memory for TX buffers\n", 1528 sc->vge_dev.dv_xname); 1529 vge_stop(sc); 1530 return (ENOBUFS); 1531 } 1532 1533 /* Set our station address */ 1534 for (i = 0; i < ETHER_ADDR_LEN; i++) 1535 CSR_WRITE_1(sc, VGE_PAR0 + i, sc->arpcom.ac_enaddr[i]); 1536 1537 /* 1538 * Set receive FIFO threshold. Also allow transmission and 1539 * reception of VLAN tagged frames. 1540 */ 1541 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1542 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1543 1544 /* Set DMA burst length */ 1545 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1546 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1547 1548 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1549 1550 /* Set collision backoff algorithm */ 1551 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1552 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1553 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1554 1555 /* Disable LPSEL field in priority resolution */ 1556 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1557 1558 /* 1559 * Load the addresses of the DMA queues into the chip. 1560 * Note that we only use one transmit queue. 1561 */ 1562 1563 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1564 VGE_ADDR_LO(sc->vge_ldata.vge_tx_listseg.ds_addr)); 1565 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1566 1567 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1568 VGE_ADDR_LO(sc->vge_ldata.vge_rx_listseg.ds_addr)); 1569 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1570 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1571 1572 /* Enable and wake up the RX descriptor queue */ 1573 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1574 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1575 1576 /* Enable the TX descriptor queue */ 1577 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1578 1579 /* Set up the receive filter -- allow large frames for VLANs. */ 1580 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1581 1582 /* If we want promiscuous mode, set the allframes bit. */ 1583 if (ifp->if_flags & IFF_PROMISC) { 1584 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1585 } 1586 1587 /* Set capture broadcast bit to capture broadcast frames. */ 1588 if (ifp->if_flags & IFF_BROADCAST) { 1589 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1590 } 1591 1592 /* Set multicast bit to capture multicast frames. */ 1593 if (ifp->if_flags & IFF_MULTICAST) { 1594 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1595 } 1596 1597 /* Init the cam filter. */ 1598#ifdef CAM_FILTERING 1599 vge_cam_clear(sc); 1600#endif 1601 1602 /* Init the multicast filter. */ 1603 vge_setmulti(sc); 1604 1605 /* Enable flow control */ 1606 1607 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1608 1609 /* Enable jumbo frame reception (if desired) */ 1610 1611 /* Start the MAC. */ 1612 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1613 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1614 CSR_WRITE_1(sc, VGE_CRS0, 1615 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1616 1617 /* 1618 * Configure one-shot timer for microsecond 1619 * resulution and load it for 500 usecs. 1620 */ 1621 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1622 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1623 1624 /* 1625 * Configure interrupt moderation for receive. Enable 1626 * the holdoff counter and load it, and set the RX 1627 * suppression count to the number of descriptors we 1628 * want to allow before triggering an interrupt. 1629 * The holdoff timer is in units of 20 usecs. 1630 */ 1631 1632#ifdef notyet 1633 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1634 /* Select the interrupt holdoff timer page. */ 1635 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1636 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1637 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1638 1639 /* Enable use of the holdoff timer. */ 1640 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1641 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1642 1643 /* Select the RX suppression threshold page. */ 1644 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1645 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 1646 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 1647 1648 /* Restore the page select bits. */ 1649 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1650 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 1651#endif 1652 1653 /* 1654 * Enable interrupts. 1655 */ 1656 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 1657 CSR_WRITE_4(sc, VGE_ISR, 0); 1658 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1659 1660 /* Restore BMCR state */ 1661 mii_mediachg(&sc->sc_mii); 1662 1663 ifp->if_flags |= IFF_RUNNING; 1664 ifp->if_flags &= ~IFF_OACTIVE; 1665 1666 sc->vge_if_flags = 0; 1667 sc->vge_link = 0; 1668 1669 if (!timeout_pending(&sc->timer_handle)) 1670 timeout_add(&sc->timer_handle, hz); 1671 1672 return (0); 1673} 1674 1675/* 1676 * Set media options. 1677 */ 1678int 1679vge_ifmedia_upd(struct ifnet *ifp) 1680{ 1681 struct vge_softc *sc = ifp->if_softc; 1682 1683 return (mii_mediachg(&sc->sc_mii)); 1684} 1685 1686/* 1687 * Report current media status. 1688 */ 1689void 1690vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1691{ 1692 struct vge_softc *sc = ifp->if_softc; 1693 1694 mii_pollstat(&sc->sc_mii); 1695 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1696 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1697} 1698 1699void 1700vge_miibus_statchg(struct device *dev) 1701{ 1702 struct vge_softc *sc = (struct vge_softc *)dev; 1703 struct mii_data *mii; 1704 struct ifmedia_entry *ife; 1705 1706 mii = &sc->sc_mii; 1707 ife = mii->mii_media.ifm_cur; 1708 1709 /* 1710 * If the user manually selects a media mode, we need to turn 1711 * on the forced MAC mode bit in the DIAGCTL register. If the 1712 * user happens to choose a full duplex mode, we also need to 1713 * set the 'force full duplex' bit. This applies only to 1714 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 1715 * mode is disabled, and in 1000baseT mode, full duplex is 1716 * always implied, so we turn on the forced mode bit but leave 1717 * the FDX bit cleared. 1718 */ 1719 1720 switch (IFM_SUBTYPE(ife->ifm_media)) { 1721 case IFM_AUTO: 1722 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1723 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1724 break; 1725 case IFM_1000_T: 1726 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1727 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1728 break; 1729 case IFM_100_TX: 1730 case IFM_10_T: 1731 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 1732 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 1733 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1734 } else { 1735 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 1736 } 1737 break; 1738 default: 1739 printf("%s: unknown media type: %x\n", 1740 sc->vge_dev.dv_xname, IFM_SUBTYPE(ife->ifm_media)); 1741 break; 1742 } 1743} 1744 1745int 1746vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1747{ 1748 struct vge_softc *sc = ifp->if_softc; 1749 struct ifreq *ifr = (struct ifreq *) data; 1750 struct ifaddr *ifa = (struct ifaddr *) data; 1751 int s, error = 0; 1752 1753 s = splimp(); 1754 1755 if ((error = ether_ioctl(ifp, &sc->arpcom, command, data)) > 0) { 1756 splx(s); 1757 return (error); 1758 } 1759 1760 switch (command) { 1761 case SIOCSIFADDR: 1762 ifp->if_flags |= IFF_UP; 1763 switch (ifa->ifa_addr->sa_family) { 1764#ifdef INET 1765 case AF_INET: 1766 vge_init(ifp); 1767 arp_ifinit(&sc->arpcom, ifa); 1768 break; 1769#endif 1770 default: 1771 vge_init(ifp); 1772 break; 1773 } 1774#if 0 /* XXX mtu gets reset to 0 at ifconfig up for some reason with this */ 1775 case SIOCSIFMTU: 1776 if (ifr->ifr_mtu > ETHERMTU_JUMBO) 1777 error = EINVAL; 1778 else 1779 ifp->if_mtu = ifr->ifr_mtu; 1780 break; 1781#endif 1782 case SIOCSIFFLAGS: 1783 if (ifp->if_flags & IFF_UP) { 1784 if (ifp->if_flags & IFF_RUNNING && 1785 ifp->if_flags & IFF_PROMISC && 1786 !(sc->vge_if_flags & IFF_PROMISC)) { 1787 CSR_SETBIT_1(sc, VGE_RXCTL, 1788 VGE_RXCTL_RX_PROMISC); 1789 vge_setmulti(sc); 1790 } else if (ifp->if_flags & IFF_RUNNING && 1791 !(ifp->if_flags & IFF_PROMISC) && 1792 sc->vge_if_flags & IFF_PROMISC) { 1793 CSR_CLRBIT_1(sc, VGE_RXCTL, 1794 VGE_RXCTL_RX_PROMISC); 1795 vge_setmulti(sc); 1796 } else 1797 vge_init(ifp); 1798 } else { 1799 if (ifp->if_flags & IFF_RUNNING) 1800 vge_stop(sc); 1801 } 1802 sc->vge_if_flags = ifp->if_flags; 1803 break; 1804 case SIOCADDMULTI: 1805 case SIOCDELMULTI: 1806 error = (command == SIOCADDMULTI) ? 1807 ether_addmulti(ifr, &sc->arpcom) : 1808 ether_delmulti(ifr, &sc->arpcom); 1809 1810 if (error == ENETRESET) { 1811 if (ifp->if_flags & IFF_RUNNING) 1812 vge_setmulti(sc); 1813 error = 0; 1814 } 1815 break; 1816 case SIOCGIFMEDIA: 1817 case SIOCSIFMEDIA: 1818 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1819 break; 1820 default: 1821 error = EINVAL; 1822 break; 1823 } 1824 1825 splx(s); 1826 return (error); 1827} 1828 1829void 1830vge_watchdog(struct ifnet *ifp) 1831{ 1832 struct vge_softc *sc = ifp->if_softc; 1833 int s; 1834 1835 s = splnet(); 1836 printf("%s: watchdog timeout\n", sc->vge_dev.dv_xname); 1837 ifp->if_oerrors++; 1838 1839 vge_txeof(sc); 1840 vge_rxeof(sc); 1841 1842 vge_init(ifp); 1843 1844 splx(s); 1845} 1846 1847/* 1848 * Stop the adapter and free any mbufs allocated to the 1849 * RX and TX lists. 1850 */ 1851void 1852vge_stop(struct vge_softc *sc) 1853{ 1854 register int i; 1855 struct ifnet *ifp; 1856 1857 ifp = &sc->arpcom.ac_if; 1858 ifp->if_timer = 0; 1859 if (timeout_pending(&sc->timer_handle)) 1860 timeout_del(&sc->timer_handle); 1861 1862 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1863 1864 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1865 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 1866 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 1867 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 1868 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 1869 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 1870 1871 if (sc->vge_head != NULL) { 1872 m_freem(sc->vge_head); 1873 sc->vge_head = sc->vge_tail = NULL; 1874 } 1875 1876 /* Free the TX list buffers. */ 1877 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1878 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 1879 bus_dmamap_unload(sc->sc_dmat, 1880 sc->vge_ldata.vge_tx_dmamap[i]); 1881 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 1882 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 1883 } 1884 } 1885 1886 /* Free the RX list buffers. */ 1887 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1888 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 1889 bus_dmamap_unload(sc->sc_dmat, 1890 sc->vge_ldata.vge_rx_dmamap[i]); 1891 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 1892 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 1893 } 1894 } 1895} 1896